1//=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AArch64 Instruction definitions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM Instruction Predicate Definitions. 15// 16def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 17 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 18def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 19 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 20def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 21 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 22def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 23 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 24def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, 25 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; 26def HasVH : Predicate<"Subtarget->hasVH()">, 27 AssemblerPredicate<"FeatureVH", "vh">; 28 29def HasLOR : Predicate<"Subtarget->hasLOR()">, 30 AssemblerPredicate<"FeatureLOR", "lor">; 31 32def HasPA : Predicate<"Subtarget->hasPA()">, 33 AssemblerPredicate<"FeaturePA", "pa">; 34 35def HasJS : Predicate<"Subtarget->hasJS()">, 36 AssemblerPredicate<"FeatureJS", "jsconv">; 37 38def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">, 39 AssemblerPredicate<"FeatureCCIDX", "ccidx">; 40 41def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">, 42 AssemblerPredicate<"FeatureComplxNum", "complxnum">; 43 44def HasNV : Predicate<"Subtarget->hasNV()">, 45 AssemblerPredicate<"FeatureNV", "nv">; 46 47def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">, 48 AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">; 49 50def HasMPAM : Predicate<"Subtarget->hasMPAM()">, 51 AssemblerPredicate<"FeatureMPAM", "mpam">; 52 53def HasDIT : Predicate<"Subtarget->hasDIT()">, 54 AssemblerPredicate<"FeatureDIT", "dit">; 55 56def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">, 57 AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">; 58 59def HasAM : Predicate<"Subtarget->hasAM()">, 60 AssemblerPredicate<"FeatureAM", "am">; 61 62def HasSEL2 : Predicate<"Subtarget->hasSEL2()">, 63 AssemblerPredicate<"FeatureSEL2", "sel2">; 64 65def HasPMU : Predicate<"Subtarget->hasPMU()">, 66 AssemblerPredicate<"FeaturePMU", "pmu">; 67 68def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">, 69 AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">; 70 71def HasFMI : Predicate<"Subtarget->hasFMI()">, 72 AssemblerPredicate<"FeatureFMI", "fmi">; 73 74def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">, 75 AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">; 76 77def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 78 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; 79def HasNEON : Predicate<"Subtarget->hasNEON()">, 80 AssemblerPredicate<"FeatureNEON", "neon">; 81def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 82 AssemblerPredicate<"FeatureCrypto", "crypto">; 83def HasSM4 : Predicate<"Subtarget->hasSM4()">, 84 AssemblerPredicate<"FeatureSM4", "sm4">; 85def HasSHA3 : Predicate<"Subtarget->hasSHA3()">, 86 AssemblerPredicate<"FeatureSHA3", "sha3">; 87def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 88 AssemblerPredicate<"FeatureSHA2", "sha2">; 89def HasAES : Predicate<"Subtarget->hasAES()">, 90 AssemblerPredicate<"FeatureAES", "aes">; 91def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 92 AssemblerPredicate<"FeatureDotProd", "dotprod">; 93def HasCRC : Predicate<"Subtarget->hasCRC()">, 94 AssemblerPredicate<"FeatureCRC", "crc">; 95def HasLSE : Predicate<"Subtarget->hasLSE()">, 96 AssemblerPredicate<"FeatureLSE", "lse">; 97def HasRAS : Predicate<"Subtarget->hasRAS()">, 98 AssemblerPredicate<"FeatureRAS", "ras">; 99def HasRDM : Predicate<"Subtarget->hasRDM()">, 100 AssemblerPredicate<"FeatureRDM", "rdm">; 101def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">; 102def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 103 AssemblerPredicate<"FeatureFullFP16", "fullfp16">; 104def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, 105 AssemblerPredicate<"FeatureFP16FML", "fp16fml">; 106def HasSPE : Predicate<"Subtarget->hasSPE()">, 107 AssemblerPredicate<"FeatureSPE", "spe">; 108def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, 109 AssemblerPredicate<"FeatureFuseAES", 110 "fuse-aes">; 111def HasSVE : Predicate<"Subtarget->hasSVE()">, 112 AssemblerPredicate<"FeatureSVE", "sve">; 113def HasSVE2 : Predicate<"Subtarget->hasSVE2()">, 114 AssemblerPredicate<"FeatureSVE2", "sve2">; 115def HasSVE2AES : Predicate<"Subtarget->hasSVE2AES()">, 116 AssemblerPredicate<"FeatureSVE2AES", "sve2-aes">; 117def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">, 118 AssemblerPredicate<"FeatureSVE2SM4", "sve2-sm4">; 119def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">, 120 AssemblerPredicate<"FeatureSVE2SHA3", "sve2-sha3">; 121def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">, 122 AssemblerPredicate<"FeatureSVE2BitPerm", "sve2-bitperm">; 123def HasRCPC : Predicate<"Subtarget->hasRCPC()">, 124 AssemblerPredicate<"FeatureRCPC", "rcpc">; 125def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, 126 AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">; 127def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">, 128 AssemblerPredicate<"FeatureFRInt3264", "frint3264">; 129def HasSB : Predicate<"Subtarget->hasSB()">, 130 AssemblerPredicate<"FeatureSB", "sb">; 131def HasPredRes : Predicate<"Subtarget->hasPredRes()">, 132 AssemblerPredicate<"FeaturePredRes", "predres">; 133def HasCCDP : Predicate<"Subtarget->hasCCDP()">, 134 AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">; 135def HasBTI : Predicate<"Subtarget->hasBTI()">, 136 AssemblerPredicate<"FeatureBranchTargetId", "bti">; 137def HasMTE : Predicate<"Subtarget->hasMTE()">, 138 AssemblerPredicate<"FeatureMTE", "mte">; 139def HasTME : Predicate<"Subtarget->hasTME()">, 140 AssemblerPredicate<"FeatureTME", "tme">; 141def HasETE : Predicate<"Subtarget->hasETE()">, 142 AssemblerPredicate<"FeatureETE", "ete">; 143def HasTRBE : Predicate<"Subtarget->hasTRBE()">, 144 AssemblerPredicate<"FeatureTRBE", "trbe">; 145def IsLE : Predicate<"Subtarget->isLittleEndian()">; 146def IsBE : Predicate<"!Subtarget->isLittleEndian()">; 147def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 148def UseAlternateSExtLoadCVTF32 149 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">; 150 151def UseNegativeImmediates 152 : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", 153 "NegativeImmediates">; 154 155def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER", 156 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 157 SDTCisInt<1>]>>; 158 159 160//===----------------------------------------------------------------------===// 161// AArch64-specific DAG Nodes. 162// 163 164// SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS 165def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2, 166 [SDTCisSameAs<0, 2>, 167 SDTCisSameAs<0, 3>, 168 SDTCisInt<0>, SDTCisVT<1, i32>]>; 169 170// SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS 171def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3, 172 [SDTCisSameAs<0, 1>, 173 SDTCisSameAs<0, 2>, 174 SDTCisInt<0>, 175 SDTCisVT<3, i32>]>; 176 177// SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS 178def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 179 [SDTCisSameAs<0, 2>, 180 SDTCisSameAs<0, 3>, 181 SDTCisInt<0>, 182 SDTCisVT<1, i32>, 183 SDTCisVT<4, i32>]>; 184 185def SDT_AArch64Brcond : SDTypeProfile<0, 3, 186 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, 187 SDTCisVT<2, i32>]>; 188def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>; 189def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, 190 SDTCisVT<2, OtherVT>]>; 191 192 193def SDT_AArch64CSel : SDTypeProfile<1, 4, 194 [SDTCisSameAs<0, 1>, 195 SDTCisSameAs<0, 2>, 196 SDTCisInt<3>, 197 SDTCisVT<4, i32>]>; 198def SDT_AArch64CCMP : SDTypeProfile<1, 5, 199 [SDTCisVT<0, i32>, 200 SDTCisInt<1>, 201 SDTCisSameAs<1, 2>, 202 SDTCisInt<3>, 203 SDTCisInt<4>, 204 SDTCisVT<5, i32>]>; 205def SDT_AArch64FCCMP : SDTypeProfile<1, 5, 206 [SDTCisVT<0, i32>, 207 SDTCisFP<1>, 208 SDTCisSameAs<1, 2>, 209 SDTCisInt<3>, 210 SDTCisInt<4>, 211 SDTCisVT<5, i32>]>; 212def SDT_AArch64FCmp : SDTypeProfile<0, 2, 213 [SDTCisFP<0>, 214 SDTCisSameAs<0, 1>]>; 215def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 216def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>; 217def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>, 218 SDTCisSameAs<0, 1>, 219 SDTCisSameAs<0, 2>]>; 220def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 221def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>; 222def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 223 SDTCisInt<2>, SDTCisInt<3>]>; 224def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 225def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 226 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 227def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>; 228 229def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 230def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>; 231def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>; 232def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 233 SDTCisSameAs<0,2>]>; 234def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 235 SDTCisSameAs<0,2>, 236 SDTCisSameAs<0,3>]>; 237def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; 238def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; 239 240def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>; 241 242def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, 243 SDTCisPtrTy<1>]>; 244 245// Generates the general dynamic sequences, i.e. 246// adrp x0, :tlsdesc:var 247// ldr x1, [x0, #:tlsdesc_lo12:var] 248// add x0, x0, #:tlsdesc_lo12:var 249// .tlsdesccall var 250// blr x1 251 252// (the TPIDR_EL0 offset is put directly in X0, hence no "result" here) 253// number of operands (the variable) 254def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1, 255 [SDTCisPtrTy<0>]>; 256 257def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4, 258 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, 259 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, 260 SDTCisSameAs<1, 4>]>; 261 262 263// Node definitions. 264def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>; 265def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>; 266def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>; 267def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>; 268def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", 269 SDCallSeqStart<[ SDTCisVT<0, i32>, 270 SDTCisVT<1, i32> ]>, 271 [SDNPHasChain, SDNPOutGlue]>; 272def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", 273 SDCallSeqEnd<[ SDTCisVT<0, i32>, 274 SDTCisVT<1, i32> ]>, 275 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 276def AArch64call : SDNode<"AArch64ISD::CALL", 277 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 278 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 279 SDNPVariadic]>; 280def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond, 281 [SDNPHasChain]>; 282def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz, 283 [SDNPHasChain]>; 284def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz, 285 [SDNPHasChain]>; 286def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz, 287 [SDNPHasChain]>; 288def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz, 289 [SDNPHasChain]>; 290 291 292def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>; 293def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>; 294def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>; 295def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>; 296def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone, 297 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 298def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >; 299def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>; 300def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut, 301 [SDNPCommutative]>; 302def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>; 303def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut, 304 [SDNPCommutative]>; 305def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>; 306def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>; 307 308def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>; 309def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>; 310def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>; 311 312def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 313 314def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>; 315 316def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>; 317def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>; 318def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>; 319def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>; 320def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>; 321 322def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>; 323def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>; 324def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>; 325def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>; 326def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>; 327def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>; 328 329def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>; 330def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>; 331def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>; 332def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>; 333def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>; 334def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>; 335def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>; 336 337def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>; 338def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>; 339def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>; 340def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>; 341 342def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>; 343def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>; 344def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>; 345def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>; 346def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>; 347def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>; 348def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>; 349def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>; 350 351def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>; 352def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>; 353def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>; 354 355def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>; 356def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>; 357def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>; 358def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>; 359def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>; 360 361def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>; 362def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>; 363def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>; 364 365def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>; 366def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>; 367def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>; 368def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>; 369def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>; 370def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS), 371 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>; 372 373def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>; 374def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>; 375def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>; 376def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>; 377def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>; 378 379def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>; 380def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>; 381 382def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>; 383 384def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET, 385 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 386 387def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH, 388 [SDNPHasChain, SDNPSideEffect]>; 389 390def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>; 391def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>; 392 393def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ", 394 SDT_AArch64TLSDescCallSeq, 395 [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 396 SDNPVariadic]>; 397 398 399def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge", 400 SDT_AArch64WrapperLarge>; 401 402def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>; 403 404def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 405 SDTCisSameAs<1, 2>]>; 406def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>; 407def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>; 408 409def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>; 410def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>; 411def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>; 412def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>; 413 414def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>; 415def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>; 416def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>; 417def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; 418def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>; 419def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>; 420 421def SDT_AArch64SETTAG : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 422def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 423def AArch64stzg : SDNode<"AArch64ISD::STZG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 424def AArch64st2g : SDNode<"AArch64ISD::ST2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 425def AArch64stz2g : SDNode<"AArch64ISD::STZ2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 426 427def SDT_AArch64unpk : SDTypeProfile<1, 1, [ 428 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 429]>; 430def AArch64sunpkhi : SDNode<"AArch64ISD::SUNPKHI", SDT_AArch64unpk>; 431def AArch64sunpklo : SDNode<"AArch64ISD::SUNPKLO", SDT_AArch64unpk>; 432def AArch64uunpkhi : SDNode<"AArch64ISD::UUNPKHI", SDT_AArch64unpk>; 433def AArch64uunpklo : SDNode<"AArch64ISD::UUNPKLO", SDT_AArch64unpk>; 434 435//===----------------------------------------------------------------------===// 436 437//===----------------------------------------------------------------------===// 438 439// AArch64 Instruction Predicate Definitions. 440// We could compute these on a per-module basis but doing so requires accessing 441// the Function object through the <Target>Subtarget and objections were raised 442// to that (see post-commit review comments for r301750). 443let RecomputePerFunction = 1 in { 444 def ForCodeSize : Predicate<"MF->getFunction().hasOptSize()">; 445 def NotForCodeSize : Predicate<"!MF->getFunction().hasOptSize()">; 446 // Avoid generating STRQro if it is slow, unless we're optimizing for code size. 447 def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction().hasOptSize()">; 448 449 def UseBTI : Predicate<[{ MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>; 450 def NotUseBTI : Predicate<[{ !MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>; 451 452 // Toggles patterns which aren't beneficial in GlobalISel when we aren't 453 // optimizing. This allows us to selectively use patterns without impacting 454 // SelectionDAG's behaviour. 455 // FIXME: One day there will probably be a nicer way to check for this, but 456 // today is not that day. 457 def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">; 458} 459 460include "AArch64InstrFormats.td" 461include "SVEInstrFormats.td" 462 463//===----------------------------------------------------------------------===// 464 465//===----------------------------------------------------------------------===// 466// Miscellaneous instructions. 467//===----------------------------------------------------------------------===// 468 469let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in { 470// We set Sched to empty list because we expect these instructions to simply get 471// removed in most cases. 472def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 473 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>, 474 Sched<[]>; 475def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 476 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>, 477 Sched<[]>; 478} // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 479 480let isReMaterializable = 1, isCodeGenOnly = 1 in { 481// FIXME: The following pseudo instructions are only needed because remat 482// cannot handle multiple instructions. When that changes, they can be 483// removed, along with the AArch64Wrapper node. 484 485let AddedComplexity = 10 in 486def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), 487 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, 488 Sched<[WriteLDAdr]>; 489 490// The MOVaddr instruction should match only when the add is not folded 491// into a load or store address. 492def MOVaddr 493 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 494 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), 495 tglobaladdr:$low))]>, 496 Sched<[WriteAdrAdr]>; 497def MOVaddrJT 498 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 499 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), 500 tjumptable:$low))]>, 501 Sched<[WriteAdrAdr]>; 502def MOVaddrCP 503 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 504 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), 505 tconstpool:$low))]>, 506 Sched<[WriteAdrAdr]>; 507def MOVaddrBA 508 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 509 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), 510 tblockaddress:$low))]>, 511 Sched<[WriteAdrAdr]>; 512def MOVaddrTLS 513 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 514 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), 515 tglobaltlsaddr:$low))]>, 516 Sched<[WriteAdrAdr]>; 517def MOVaddrEXT 518 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 519 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), 520 texternalsym:$low))]>, 521 Sched<[WriteAdrAdr]>; 522// Normally AArch64addlow either gets folded into a following ldr/str, 523// or together with an adrp into MOVaddr above. For cases with TLS, it 524// might appear without either of them, so allow lowering it into a plain 525// add. 526def ADDlowTLS 527 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low), 528 [(set GPR64:$dst, (AArch64addlow GPR64:$src, 529 tglobaltlsaddr:$low))]>, 530 Sched<[WriteAdr]>; 531 532} // isReMaterializable, isCodeGenOnly 533 534def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr), 535 (LOADgot tglobaltlsaddr:$addr)>; 536 537def : Pat<(AArch64LOADgot texternalsym:$addr), 538 (LOADgot texternalsym:$addr)>; 539 540def : Pat<(AArch64LOADgot tconstpool:$addr), 541 (LOADgot tconstpool:$addr)>; 542 543// 32-bit jump table destination is actually only 2 instructions since we can 544// use the table itself as a PC-relative base. But optimization occurs after 545// branch relaxation so be pessimistic. 546let Size = 12, Constraints = "@earlyclobber $dst,@earlyclobber $scratch" in { 547def JumpTableDest32 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 548 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 549 Sched<[]>; 550def JumpTableDest16 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 551 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 552 Sched<[]>; 553def JumpTableDest8 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 554 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 555 Sched<[]>; 556} 557 558// Space-consuming pseudo to aid testing of placement and reachability 559// algorithms. Immediate operand is the number of bytes this "instruction" 560// occupies; register operands can be used to enforce dependency and constrain 561// the scheduler. 562let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in 563def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn), 564 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>, 565 Sched<[]>; 566 567let hasSideEffects = 1, isCodeGenOnly = 1 in { 568 def SpeculationSafeValueX 569 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src), []>, Sched<[]>; 570 def SpeculationSafeValueW 571 : Pseudo<(outs GPR32:$dst), (ins GPR32:$src), []>, Sched<[]>; 572} 573 574 575//===----------------------------------------------------------------------===// 576// System instructions. 577//===----------------------------------------------------------------------===// 578 579def HINT : HintI<"hint">; 580def : InstAlias<"nop", (HINT 0b000)>; 581def : InstAlias<"yield",(HINT 0b001)>; 582def : InstAlias<"wfe", (HINT 0b010)>; 583def : InstAlias<"wfi", (HINT 0b011)>; 584def : InstAlias<"sev", (HINT 0b100)>; 585def : InstAlias<"sevl", (HINT 0b101)>; 586def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; 587def : InstAlias<"csdb", (HINT 20)>; 588def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>; 589def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>; 590 591// v8.2a Statistical Profiling extension 592def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; 593 594// As far as LLVM is concerned this writes to the system's exclusive monitors. 595let mayLoad = 1, mayStore = 1 in 596def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">; 597 598// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot 599// model patterns with sufficiently fine granularity. 600let mayLoad = ?, mayStore = ? in { 601def DMB : CRmSystemI<barrier_op, 0b101, "dmb", 602 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>; 603 604def DSB : CRmSystemI<barrier_op, 0b100, "dsb", 605 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>; 606 607def ISB : CRmSystemI<barrier_op, 0b110, "isb", 608 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>; 609 610def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> { 611 let CRm = 0b0010; 612 let Inst{12} = 0; 613 let Predicates = [HasTRACEV8_4]; 614} 615} 616 617// ARMv8.2-A Dot Product 618let Predicates = [HasDotProd] in { 619defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>; 620defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>; 621defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>; 622defm UDOTlane : SIMDThreeSameVectorDotIndex<1, "udot", int_aarch64_neon_udot>; 623} 624 625// ARMv8.2-A FP16 Fused Multiply-Add Long 626let Predicates = [HasNEON, HasFP16FML] in { 627defm FMLAL : SIMDThreeSameVectorFML<0, 1, 0b001, "fmlal", int_aarch64_neon_fmlal>; 628defm FMLSL : SIMDThreeSameVectorFML<0, 1, 0b101, "fmlsl", int_aarch64_neon_fmlsl>; 629defm FMLAL2 : SIMDThreeSameVectorFML<1, 0, 0b001, "fmlal2", int_aarch64_neon_fmlal2>; 630defm FMLSL2 : SIMDThreeSameVectorFML<1, 0, 0b101, "fmlsl2", int_aarch64_neon_fmlsl2>; 631defm FMLALlane : SIMDThreeSameVectorFMLIndex<0, 0b0000, "fmlal", int_aarch64_neon_fmlal>; 632defm FMLSLlane : SIMDThreeSameVectorFMLIndex<0, 0b0100, "fmlsl", int_aarch64_neon_fmlsl>; 633defm FMLAL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1000, "fmlal2", int_aarch64_neon_fmlal2>; 634defm FMLSL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1100, "fmlsl2", int_aarch64_neon_fmlsl2>; 635} 636 637// Armv8.2-A Crypto extensions 638let Predicates = [HasSHA3] in { 639def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">; 640def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">; 641def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">; 642def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">; 643def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">; 644def EOR3 : CryptoRRRR_16B<0b00, "eor3">; 645def BCAX : CryptoRRRR_16B<0b01, "bcax">; 646def XAR : CryptoRRRi6<"xar">; 647} // HasSHA3 648 649let Predicates = [HasSM4] in { 650def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">; 651def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">; 652def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">; 653def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">; 654def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">; 655def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">; 656def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">; 657def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">; 658def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">; 659} // HasSM4 660 661let Predicates = [HasRCPC] in { 662 // v8.3 Release Consistent Processor Consistent support, optional in v8.2. 663 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>; 664 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>; 665 def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>; 666 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>; 667} 668 669// v8.3a complex add and multiply-accumulate. No predicate here, that is done 670// inside the multiclass as the FP16 versions need different predicates. 671defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop, 672 "fcmla", null_frag>; 673defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd, 674 "fcadd", null_frag>; 675defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla", 676 null_frag>; 677 678// v8.3a Pointer Authentication 679// These instructions inhabit part of the hint space and so can be used for 680// armv8 targets 681let Uses = [LR], Defs = [LR] in { 682 def PACIAZ : SystemNoOperands<0b000, "paciaz">; 683 def PACIBZ : SystemNoOperands<0b010, "pacibz">; 684 def AUTIAZ : SystemNoOperands<0b100, "autiaz">; 685 def AUTIBZ : SystemNoOperands<0b110, "autibz">; 686} 687let Uses = [LR, SP], Defs = [LR] in { 688 def PACIASP : SystemNoOperands<0b001, "paciasp">; 689 def PACIBSP : SystemNoOperands<0b011, "pacibsp">; 690 def AUTIASP : SystemNoOperands<0b101, "autiasp">; 691 def AUTIBSP : SystemNoOperands<0b111, "autibsp">; 692} 693let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in { 694 def PACIA1716 : SystemNoOperands<0b000, "pacia1716">; 695 def PACIB1716 : SystemNoOperands<0b010, "pacib1716">; 696 def AUTIA1716 : SystemNoOperands<0b100, "autia1716">; 697 def AUTIB1716 : SystemNoOperands<0b110, "autib1716">; 698} 699 700let Uses = [LR], Defs = [LR], CRm = 0b0000 in { 701 def XPACLRI : SystemNoOperands<0b111, "xpaclri">; 702} 703 704// These pointer authentication isntructions require armv8.3a 705let Predicates = [HasPA] in { 706 multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> { 707 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>; 708 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>; 709 def DA : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>; 710 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>; 711 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>; 712 def DZA : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>; 713 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>; 714 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb")>; 715 } 716 717 defm PAC : SignAuth<0b000, 0b010, "pac">; 718 defm AUT : SignAuth<0b001, 0b011, "aut">; 719 720 def XPACI : SignAuthZero<0b100, 0b00, "xpaci">; 721 def XPACD : SignAuthZero<0b100, 0b01, "xpacd">; 722 def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>; 723 724 // Combined Instructions 725 def BRAA : AuthBranchTwoOperands<0, 0, "braa">; 726 def BRAB : AuthBranchTwoOperands<0, 1, "brab">; 727 def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">; 728 def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">; 729 730 def BRAAZ : AuthOneOperand<0b000, 0, "braaz">; 731 def BRABZ : AuthOneOperand<0b000, 1, "brabz">; 732 def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">; 733 def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">; 734 735 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 736 def RETAA : AuthReturn<0b010, 0, "retaa">; 737 def RETAB : AuthReturn<0b010, 1, "retab">; 738 def ERETAA : AuthReturn<0b100, 0, "eretaa">; 739 def ERETAB : AuthReturn<0b100, 1, "eretab">; 740 } 741 742 defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; 743 defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; 744 745} 746 747// v8.3a floating point conversion for javascript 748let Predicates = [HasJS, HasFPARMv8] in 749def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, 750 "fjcvtzs", 751 [(set GPR32:$Rd, 752 (int_aarch64_fjcvtzs FPR64:$Rn))]> { 753 let Inst{31} = 0; 754} // HasJS, HasFPARMv8 755 756// v8.4 Flag manipulation instructions 757let Predicates = [HasFMI] in { 758def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> { 759 let Inst{20-5} = 0b0000001000000000; 760} 761def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">; 762def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">; 763def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif", 764 "{\t$Rn, $imm, $mask}">; 765} // HasFMI 766 767// v8.5 flag manipulation instructions 768let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in { 769 770def XAFLAG : PstateWriteSimple<(ins), "xaflag", "">, Sched<[WriteSys]> { 771 let Inst{18-16} = 0b000; 772 let Inst{11-8} = 0b0000; 773 let Unpredictable{11-8} = 0b1111; 774 let Inst{7-5} = 0b001; 775} 776 777def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> { 778 let Inst{18-16} = 0b000; 779 let Inst{11-8} = 0b0000; 780 let Unpredictable{11-8} = 0b1111; 781 let Inst{7-5} = 0b010; 782} 783} // HasAltNZCV 784 785 786// Armv8.5-A speculation barrier 787def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> { 788 let Inst{20-5} = 0b0001100110000111; 789 let Unpredictable{11-8} = 0b1111; 790 let Predicates = [HasSB]; 791 let hasSideEffects = 1; 792} 793 794def : InstAlias<"clrex", (CLREX 0xf)>; 795def : InstAlias<"isb", (ISB 0xf)>; 796def : InstAlias<"ssbb", (DSB 0)>; 797def : InstAlias<"pssbb", (DSB 4)>; 798 799def MRS : MRSI; 800def MSR : MSRI; 801def MSRpstateImm1 : MSRpstateImm0_1; 802def MSRpstateImm4 : MSRpstateImm0_15; 803 804// The thread pointer (on Linux, at least, where this has been implemented) is 805// TPIDR_EL0. 806def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins), 807 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>; 808 809let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in { 810def HWASAN_CHECK_MEMACCESS : Pseudo< 811 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo), 812 [(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>, 813 Sched<[]>; 814def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo< 815 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo), 816 [(int_hwasan_check_memaccess_shortgranules X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>, 817 Sched<[]>; 818} 819 820// The cycle counter PMC register is PMCCNTR_EL0. 821let Predicates = [HasPerfMon] in 822def : Pat<(readcyclecounter), (MRS 0xdce8)>; 823 824// FPCR register 825def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>; 826 827// Generic system instructions 828def SYSxt : SystemXtI<0, "sys">; 829def SYSLxt : SystemLXtI<1, "sysl">; 830 831def : InstAlias<"sys $op1, $Cn, $Cm, $op2", 832 (SYSxt imm0_7:$op1, sys_cr_op:$Cn, 833 sys_cr_op:$Cm, imm0_7:$op2, XZR)>; 834 835 836let Predicates = [HasTME] in { 837 838def TSTART : TMSystemI<0b0000, "tstart", 839 [(set GPR64:$Rt, (int_aarch64_tstart))]>; 840 841def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>; 842 843def TCANCEL : TMSystemException<0b011, "tcancel", 844 [(int_aarch64_tcancel i64_imm0_65535:$imm)]>; 845 846def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> { 847 let mayLoad = 0; 848 let mayStore = 0; 849} 850} // HasTME 851 852//===----------------------------------------------------------------------===// 853// Move immediate instructions. 854//===----------------------------------------------------------------------===// 855 856defm MOVK : InsertImmediate<0b11, "movk">; 857defm MOVN : MoveImmediate<0b00, "movn">; 858 859let PostEncoderMethod = "fixMOVZ" in 860defm MOVZ : MoveImmediate<0b10, "movz">; 861 862// First group of aliases covers an implicit "lsl #0". 863def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>; 864def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>; 865def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; 866def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; 867def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; 868def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; 869 870// Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. 871def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>; 872def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>; 873def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>; 874def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>; 875 876def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>; 877def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>; 878def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>; 879def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>; 880 881def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g3:$sym, 48), 0>; 882def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g2:$sym, 32), 0>; 883def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g1:$sym, 16), 0>; 884def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g0:$sym, 0), 0>; 885 886def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>; 887def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>; 888 889def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>; 890def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>; 891 892def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g1:$sym, 16), 0>; 893def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g0:$sym, 0), 0>; 894 895// Final group of aliases covers true "mov $Rd, $imm" cases. 896multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR, 897 int width, int shift> { 898 def _asmoperand : AsmOperandClass { 899 let Name = basename # width # "_lsl" # shift # "MovAlias"; 900 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", " 901 # shift # ">"; 902 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">"; 903 } 904 905 def _movimm : Operand<i32> { 906 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand"); 907 } 908 909 def : InstAlias<"mov $Rd, $imm", 910 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>; 911} 912 913defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; 914defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; 915 916defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; 917defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; 918defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; 919defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; 920 921defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>; 922defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>; 923 924defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>; 925defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>; 926defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>; 927defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>; 928 929let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1, 930 isAsCheapAsAMove = 1 in { 931// FIXME: The following pseudo instructions are only needed because remat 932// cannot handle multiple instructions. When that changes, we can select 933// directly to the real instructions and get rid of these pseudos. 934 935def MOVi32imm 936 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src), 937 [(set GPR32:$dst, imm:$src)]>, 938 Sched<[WriteImm]>; 939def MOVi64imm 940 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src), 941 [(set GPR64:$dst, imm:$src)]>, 942 Sched<[WriteImm]>; 943} // isReMaterializable, isCodeGenOnly 944 945// If possible, we want to use MOVi32imm even for 64-bit moves. This gives the 946// eventual expansion code fewer bits to worry about getting right. Marshalling 947// the types is a little tricky though: 948def i64imm_32bit : ImmLeaf<i64, [{ 949 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); 950}]>; 951 952def s64imm_32bit : ImmLeaf<i64, [{ 953 int64_t Imm64 = static_cast<int64_t>(Imm); 954 return Imm64 >= std::numeric_limits<int32_t>::min() && 955 Imm64 <= std::numeric_limits<int32_t>::max(); 956}]>; 957 958def trunc_imm : SDNodeXForm<imm, [{ 959 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32); 960}]>; 961 962def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">, 963 GISDNodeXFormEquiv<trunc_imm>; 964 965let Predicates = [OptimizedGISelOrOtherSelector] in { 966// The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless 967// copies. 968def : Pat<(i64 i64imm_32bit:$src), 969 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; 970} 971 972// Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). 973def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ 974return CurDAG->getTargetConstant( 975 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); 976}]>; 977 978def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ 979return CurDAG->getTargetConstant( 980 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); 981}]>; 982 983 984def : Pat<(f32 fpimm:$in), 985 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>; 986def : Pat<(f64 fpimm:$in), 987 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>; 988 989 990// Deal with the various forms of (ELF) large addressing with MOVZ/MOVK 991// sequences. 992def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2, 993 tglobaladdr:$g1, tglobaladdr:$g0), 994 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0), 995 tglobaladdr:$g1, 16), 996 tglobaladdr:$g2, 32), 997 tglobaladdr:$g3, 48)>; 998 999def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2, 1000 tblockaddress:$g1, tblockaddress:$g0), 1001 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0), 1002 tblockaddress:$g1, 16), 1003 tblockaddress:$g2, 32), 1004 tblockaddress:$g3, 48)>; 1005 1006def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2, 1007 tconstpool:$g1, tconstpool:$g0), 1008 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0), 1009 tconstpool:$g1, 16), 1010 tconstpool:$g2, 32), 1011 tconstpool:$g3, 48)>; 1012 1013def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2, 1014 tjumptable:$g1, tjumptable:$g0), 1015 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0), 1016 tjumptable:$g1, 16), 1017 tjumptable:$g2, 32), 1018 tjumptable:$g3, 48)>; 1019 1020 1021//===----------------------------------------------------------------------===// 1022// Arithmetic instructions. 1023//===----------------------------------------------------------------------===// 1024 1025// Add/subtract with carry. 1026defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>; 1027defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>; 1028 1029def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>; 1030def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>; 1031def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>; 1032def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>; 1033 1034// Add/subtract 1035defm ADD : AddSub<0, "add", "sub", add>; 1036defm SUB : AddSub<1, "sub", "add">; 1037 1038def : InstAlias<"mov $dst, $src", 1039 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>; 1040def : InstAlias<"mov $dst, $src", 1041 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>; 1042def : InstAlias<"mov $dst, $src", 1043 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>; 1044def : InstAlias<"mov $dst, $src", 1045 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>; 1046 1047defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">; 1048defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">; 1049 1050// Use SUBS instead of SUB to enable CSE between SUBS and SUB. 1051def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm), 1052 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>; 1053def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm), 1054 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>; 1055def : Pat<(sub GPR32:$Rn, GPR32:$Rm), 1056 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>; 1057def : Pat<(sub GPR64:$Rn, GPR64:$Rm), 1058 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>; 1059def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm), 1060 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>; 1061def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm), 1062 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>; 1063let AddedComplexity = 1 in { 1064def : Pat<(sub GPR32sp:$R2, arith_extended_reg32_i32:$R3), 1065 (SUBSWrx GPR32sp:$R2, arith_extended_reg32_i32:$R3)>; 1066def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64_i64:$R3), 1067 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64_i64:$R3)>; 1068} 1069 1070// Because of the immediate format for add/sub-imm instructions, the 1071// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 1072// These patterns capture that transformation. 1073let AddedComplexity = 1 in { 1074def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1075 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1076def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1077 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1078def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1079 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1080def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1081 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1082} 1083 1084// Because of the immediate format for add/sub-imm instructions, the 1085// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 1086// These patterns capture that transformation. 1087let AddedComplexity = 1 in { 1088def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1089 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1090def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1091 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1092def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1093 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1094def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1095 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1096} 1097 1098def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 1099def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 1100def : InstAlias<"neg $dst, $src$shift", 1101 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 1102def : InstAlias<"neg $dst, $src$shift", 1103 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 1104 1105def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 1106def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 1107def : InstAlias<"negs $dst, $src$shift", 1108 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 1109def : InstAlias<"negs $dst, $src$shift", 1110 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 1111 1112 1113// Unsigned/Signed divide 1114defm UDIV : Div<0, "udiv", udiv>; 1115defm SDIV : Div<1, "sdiv", sdiv>; 1116 1117def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>; 1118def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>; 1119def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>; 1120def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>; 1121 1122// Variable shift 1123defm ASRV : Shift<0b10, "asr", sra>; 1124defm LSLV : Shift<0b00, "lsl", shl>; 1125defm LSRV : Shift<0b01, "lsr", srl>; 1126defm RORV : Shift<0b11, "ror", rotr>; 1127 1128def : ShiftAlias<"asrv", ASRVWr, GPR32>; 1129def : ShiftAlias<"asrv", ASRVXr, GPR64>; 1130def : ShiftAlias<"lslv", LSLVWr, GPR32>; 1131def : ShiftAlias<"lslv", LSLVXr, GPR64>; 1132def : ShiftAlias<"lsrv", LSRVWr, GPR32>; 1133def : ShiftAlias<"lsrv", LSRVXr, GPR64>; 1134def : ShiftAlias<"rorv", RORVWr, GPR32>; 1135def : ShiftAlias<"rorv", RORVXr, GPR64>; 1136 1137// Multiply-add 1138let AddedComplexity = 5 in { 1139defm MADD : MulAccum<0, "madd", add>; 1140defm MSUB : MulAccum<1, "msub", sub>; 1141 1142def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)), 1143 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1144def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)), 1145 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1146 1147def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))), 1148 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1149def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))), 1150 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1151def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)), 1152 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1153def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)), 1154 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1155} // AddedComplexity = 5 1156 1157let AddedComplexity = 5 in { 1158def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>; 1159def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>; 1160def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>; 1161def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>; 1162 1163def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))), 1164 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1165def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))), 1166 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1167 1168def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))), 1169 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1170def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))), 1171 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1172 1173def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))), 1174 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1175def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))), 1176 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1177def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))), 1178 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1179 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1180 1181def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 1182 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1183def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 1184 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1185def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))), 1186 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1187 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1188 1189def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)), 1190 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1191def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)), 1192 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1193def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)), 1194 GPR64:$Ra)), 1195 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1196 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1197 1198def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 1199 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1200def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 1201 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1202def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32), 1203 (s64imm_32bit:$C)))), 1204 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1205 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1206} // AddedComplexity = 5 1207 1208def : MulAccumWAlias<"mul", MADDWrrr>; 1209def : MulAccumXAlias<"mul", MADDXrrr>; 1210def : MulAccumWAlias<"mneg", MSUBWrrr>; 1211def : MulAccumXAlias<"mneg", MSUBXrrr>; 1212def : WideMulAccumAlias<"smull", SMADDLrrr>; 1213def : WideMulAccumAlias<"smnegl", SMSUBLrrr>; 1214def : WideMulAccumAlias<"umull", UMADDLrrr>; 1215def : WideMulAccumAlias<"umnegl", UMSUBLrrr>; 1216 1217// Multiply-high 1218def SMULHrr : MulHi<0b010, "smulh", mulhs>; 1219def UMULHrr : MulHi<0b110, "umulh", mulhu>; 1220 1221// CRC32 1222def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">; 1223def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">; 1224def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">; 1225def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">; 1226 1227def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">; 1228def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">; 1229def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">; 1230def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">; 1231 1232// v8.1 atomic CAS 1233defm CAS : CompareAndSwap<0, 0, "">; 1234defm CASA : CompareAndSwap<1, 0, "a">; 1235defm CASL : CompareAndSwap<0, 1, "l">; 1236defm CASAL : CompareAndSwap<1, 1, "al">; 1237 1238// v8.1 atomic CASP 1239defm CASP : CompareAndSwapPair<0, 0, "">; 1240defm CASPA : CompareAndSwapPair<1, 0, "a">; 1241defm CASPL : CompareAndSwapPair<0, 1, "l">; 1242defm CASPAL : CompareAndSwapPair<1, 1, "al">; 1243 1244// v8.1 atomic SWP 1245defm SWP : Swap<0, 0, "">; 1246defm SWPA : Swap<1, 0, "a">; 1247defm SWPL : Swap<0, 1, "l">; 1248defm SWPAL : Swap<1, 1, "al">; 1249 1250// v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register) 1251defm LDADD : LDOPregister<0b000, "add", 0, 0, "">; 1252defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">; 1253defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">; 1254defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">; 1255 1256defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">; 1257defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">; 1258defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">; 1259defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">; 1260 1261defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">; 1262defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">; 1263defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">; 1264defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">; 1265 1266defm LDSET : LDOPregister<0b011, "set", 0, 0, "">; 1267defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">; 1268defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">; 1269defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">; 1270 1271defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">; 1272defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">; 1273defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">; 1274defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">; 1275 1276defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">; 1277defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">; 1278defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">; 1279defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">; 1280 1281defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">; 1282defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">; 1283defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">; 1284defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">; 1285 1286defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">; 1287defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">; 1288defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">; 1289defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">; 1290 1291// v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR" 1292defm : STOPregister<"stadd","LDADD">; // STADDx 1293defm : STOPregister<"stclr","LDCLR">; // STCLRx 1294defm : STOPregister<"steor","LDEOR">; // STEORx 1295defm : STOPregister<"stset","LDSET">; // STSETx 1296defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx 1297defm : STOPregister<"stsmin","LDSMIN">;// STSMINx 1298defm : STOPregister<"stumax","LDUMAX">;// STUMAXx 1299defm : STOPregister<"stumin","LDUMIN">;// STUMINx 1300 1301// v8.5 Memory Tagging Extension 1302let Predicates = [HasMTE] in { 1303 1304def IRG : BaseTwoOperand<0b0100, GPR64sp, "irg", int_aarch64_irg, GPR64sp, GPR64>, 1305 Sched<[]>{ 1306 let Inst{31} = 1; 1307} 1308def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", int_aarch64_gmi, GPR64sp>, Sched<[]>{ 1309 let Inst{31} = 1; 1310 let isNotDuplicable = 1; 1311} 1312def ADDG : AddSubG<0, "addg", null_frag>; 1313def SUBG : AddSubG<1, "subg", null_frag>; 1314 1315def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>; 1316 1317def SUBP : SUBP<0, "subp", int_aarch64_subp>, Sched<[]>; 1318def SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{ 1319 let Defs = [NZCV]; 1320} 1321 1322def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>; 1323 1324def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">; 1325 1326def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4), 1327 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>; 1328def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)), 1329 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>; 1330 1331def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>; 1332 1333def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]", 1334 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>; 1335def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]", 1336 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>; 1337def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]", 1338 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> { 1339 let Inst{23} = 0; 1340} 1341 1342defm STG : MemTagStore<0b00, "stg">; 1343defm STZG : MemTagStore<0b01, "stzg">; 1344defm ST2G : MemTagStore<0b10, "st2g">; 1345defm STZ2G : MemTagStore<0b11, "stz2g">; 1346 1347def : Pat<(AArch64stg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1348 (STGOffset $Rn, $Rm, $imm)>; 1349def : Pat<(AArch64stzg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1350 (STZGOffset $Rn, $Rm, $imm)>; 1351def : Pat<(AArch64st2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1352 (ST2GOffset $Rn, $Rm, $imm)>; 1353def : Pat<(AArch64stz2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1354 (STZ2GOffset $Rn, $Rm, $imm)>; 1355 1356defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">; 1357def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">; 1358def STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">; 1359 1360def : Pat<(int_aarch64_stg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)), 1361 (STGOffset GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>; 1362 1363def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2), 1364 (STGPi $Rt, $Rt2, $Rn, $imm)>; 1365 1366def IRGstack 1367 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rsp, GPR64:$Rm), []>, 1368 Sched<[]>; 1369def TAGPstack 1370 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>, 1371 Sched<[]>; 1372 1373// Explicit SP in the first operand prevents ShrinkWrap optimization 1374// from leaving this instruction out of the stack frame. When IRGstack 1375// is transformed into IRG, this operand is replaced with the actual 1376// register / expression for the tagged base pointer of the current function. 1377def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>; 1378 1379// Large STG to be expanded into a loop. $Rm is the size, $Rn is start address. 1380// $Rn_wback is one past the end of the range. 1381let isCodeGenOnly=1, mayStore=1 in { 1382def STGloop 1383 : Pseudo<(outs GPR64common:$Rm_wback, GPR64sp:$Rn_wback), (ins GPR64common:$Rm, GPR64sp:$Rn), 1384 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,$Rm = $Rm_wback,@earlyclobber $Rm_wback" >, 1385 Sched<[WriteAdr, WriteST]>; 1386 1387def STZGloop 1388 : Pseudo<(outs GPR64common:$Rm_wback, GPR64sp:$Rn_wback), (ins GPR64common:$Rm, GPR64sp:$Rn), 1389 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,$Rm = $Rm_wback,@earlyclobber $Rm_wback" >, 1390 Sched<[WriteAdr, WriteST]>; 1391} 1392 1393} // Predicates = [HasMTE] 1394 1395//===----------------------------------------------------------------------===// 1396// Logical instructions. 1397//===----------------------------------------------------------------------===// 1398 1399// (immediate) 1400defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">; 1401defm AND : LogicalImm<0b00, "and", and, "bic">; 1402defm EOR : LogicalImm<0b10, "eor", xor, "eon">; 1403defm ORR : LogicalImm<0b01, "orr", or, "orn">; 1404 1405// FIXME: these aliases *are* canonical sometimes (when movz can't be 1406// used). Actually, it seems to be working right now, but putting logical_immXX 1407// here is a bit dodgy on the AsmParser side too. 1408def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR, 1409 logical_imm32:$imm), 0>; 1410def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR, 1411 logical_imm64:$imm), 0>; 1412 1413 1414// (register) 1415defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>; 1416defm BICS : LogicalRegS<0b11, 1, "bics", 1417 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>; 1418defm AND : LogicalReg<0b00, 0, "and", and>; 1419defm BIC : LogicalReg<0b00, 1, "bic", 1420 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1421defm EON : LogicalReg<0b10, 1, "eon", 1422 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>; 1423defm EOR : LogicalReg<0b10, 0, "eor", xor>; 1424defm ORN : LogicalReg<0b01, 1, "orn", 1425 BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 1426defm ORR : LogicalReg<0b01, 0, "orr", or>; 1427 1428def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>; 1429def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>; 1430 1431def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>; 1432def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>; 1433 1434def : InstAlias<"mvn $Wd, $Wm$sh", 1435 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>; 1436def : InstAlias<"mvn $Xd, $Xm$sh", 1437 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>; 1438 1439def : InstAlias<"tst $src1, $src2", 1440 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>; 1441def : InstAlias<"tst $src1, $src2", 1442 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>; 1443 1444def : InstAlias<"tst $src1, $src2", 1445 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>; 1446def : InstAlias<"tst $src1, $src2", 1447 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>; 1448 1449def : InstAlias<"tst $src1, $src2$sh", 1450 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>; 1451def : InstAlias<"tst $src1, $src2$sh", 1452 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>; 1453 1454 1455def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>; 1456def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>; 1457 1458 1459//===----------------------------------------------------------------------===// 1460// One operand data processing instructions. 1461//===----------------------------------------------------------------------===// 1462 1463defm CLS : OneOperandData<0b101, "cls">; 1464defm CLZ : OneOperandData<0b100, "clz", ctlz>; 1465defm RBIT : OneOperandData<0b000, "rbit", bitreverse>; 1466 1467def REV16Wr : OneWRegData<0b001, "rev16", 1468 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>; 1469def REV16Xr : OneXRegData<0b001, "rev16", null_frag>; 1470 1471def : Pat<(cttz GPR32:$Rn), 1472 (CLZWr (RBITWr GPR32:$Rn))>; 1473def : Pat<(cttz GPR64:$Rn), 1474 (CLZXr (RBITXr GPR64:$Rn))>; 1475def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)), 1476 (i32 1))), 1477 (CLSWr GPR32:$Rn)>; 1478def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)), 1479 (i64 1))), 1480 (CLSXr GPR64:$Rn)>; 1481 1482// Unlike the other one operand instructions, the instructions with the "rev" 1483// mnemonic do *not* just different in the size bit, but actually use different 1484// opcode bits for the different sizes. 1485def REVWr : OneWRegData<0b010, "rev", bswap>; 1486def REVXr : OneXRegData<0b011, "rev", bswap>; 1487def REV32Xr : OneXRegData<0b010, "rev32", 1488 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>; 1489 1490def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>; 1491 1492// The bswap commutes with the rotr so we want a pattern for both possible 1493// orders. 1494def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>; 1495def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>; 1496 1497//===----------------------------------------------------------------------===// 1498// Bitfield immediate extraction instruction. 1499//===----------------------------------------------------------------------===// 1500let hasSideEffects = 0 in 1501defm EXTR : ExtractImm<"extr">; 1502def : InstAlias<"ror $dst, $src, $shift", 1503 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>; 1504def : InstAlias<"ror $dst, $src, $shift", 1505 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>; 1506 1507def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), 1508 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>; 1509def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), 1510 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; 1511 1512//===----------------------------------------------------------------------===// 1513// Other bitfield immediate instructions. 1514//===----------------------------------------------------------------------===// 1515let hasSideEffects = 0 in { 1516defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">; 1517defm SBFM : BitfieldImm<0b00, "sbfm">; 1518defm UBFM : BitfieldImm<0b10, "ubfm">; 1519} 1520 1521def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{ 1522 uint64_t enc = (32 - N->getZExtValue()) & 0x1f; 1523 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1524}]>; 1525 1526def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{ 1527 uint64_t enc = 31 - N->getZExtValue(); 1528 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1529}]>; 1530 1531// min(7, 31 - shift_amt) 1532def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 1533 uint64_t enc = 31 - N->getZExtValue(); 1534 enc = enc > 7 ? 7 : enc; 1535 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1536}]>; 1537 1538// min(15, 31 - shift_amt) 1539def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 1540 uint64_t enc = 31 - N->getZExtValue(); 1541 enc = enc > 15 ? 15 : enc; 1542 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1543}]>; 1544 1545def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{ 1546 uint64_t enc = (64 - N->getZExtValue()) & 0x3f; 1547 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1548}]>; 1549 1550def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{ 1551 uint64_t enc = 63 - N->getZExtValue(); 1552 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1553}]>; 1554 1555// min(7, 63 - shift_amt) 1556def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 1557 uint64_t enc = 63 - N->getZExtValue(); 1558 enc = enc > 7 ? 7 : enc; 1559 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1560}]>; 1561 1562// min(15, 63 - shift_amt) 1563def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 1564 uint64_t enc = 63 - N->getZExtValue(); 1565 enc = enc > 15 ? 15 : enc; 1566 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1567}]>; 1568 1569// min(31, 63 - shift_amt) 1570def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{ 1571 uint64_t enc = 63 - N->getZExtValue(); 1572 enc = enc > 31 ? 31 : enc; 1573 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1574}]>; 1575 1576def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)), 1577 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 1578 (i64 (i32shift_b imm0_31:$imm)))>; 1579def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)), 1580 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 1581 (i64 (i64shift_b imm0_63:$imm)))>; 1582 1583let AddedComplexity = 10 in { 1584def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)), 1585 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 1586def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)), 1587 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 1588} 1589 1590def : InstAlias<"asr $dst, $src, $shift", 1591 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 1592def : InstAlias<"asr $dst, $src, $shift", 1593 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 1594def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 1595def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 1596def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 1597def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 1598def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 1599 1600def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)), 1601 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 1602def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)), 1603 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 1604 1605def : InstAlias<"lsr $dst, $src, $shift", 1606 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 1607def : InstAlias<"lsr $dst, $src, $shift", 1608 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 1609def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 1610def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 1611def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 1612def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 1613def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 1614 1615//===----------------------------------------------------------------------===// 1616// Conditional comparison instructions. 1617//===----------------------------------------------------------------------===// 1618defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>; 1619defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>; 1620 1621//===----------------------------------------------------------------------===// 1622// Conditional select instructions. 1623//===----------------------------------------------------------------------===// 1624defm CSEL : CondSelect<0, 0b00, "csel">; 1625 1626def inc : PatFrag<(ops node:$in), (add node:$in, 1)>; 1627defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>; 1628defm CSINV : CondSelectOp<1, 0b00, "csinv", not>; 1629defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>; 1630 1631def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1632 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1633def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1634 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1635def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1636 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1637def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1638 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1639def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1640 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1641def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1642 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1643 1644def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV), 1645 (CSINCWr WZR, WZR, (i32 imm:$cc))>; 1646def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV), 1647 (CSINCXr XZR, XZR, (i32 imm:$cc))>; 1648def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV), 1649 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>; 1650def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV), 1651 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>; 1652def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV), 1653 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1654def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV), 1655 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1656def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV), 1657 (CSINVWr WZR, WZR, (i32 imm:$cc))>; 1658def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV), 1659 (CSINVXr XZR, XZR, (i32 imm:$cc))>; 1660def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV), 1661 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>; 1662def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV), 1663 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>; 1664def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV), 1665 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1666def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV), 1667 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1668 1669// The inverse of the condition code from the alias instruction is what is used 1670// in the aliased instruction. The parser all ready inverts the condition code 1671// for these aliases. 1672def : InstAlias<"cset $dst, $cc", 1673 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 1674def : InstAlias<"cset $dst, $cc", 1675 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 1676 1677def : InstAlias<"csetm $dst, $cc", 1678 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 1679def : InstAlias<"csetm $dst, $cc", 1680 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 1681 1682def : InstAlias<"cinc $dst, $src, $cc", 1683 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1684def : InstAlias<"cinc $dst, $src, $cc", 1685 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1686 1687def : InstAlias<"cinv $dst, $src, $cc", 1688 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1689def : InstAlias<"cinv $dst, $src, $cc", 1690 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1691 1692def : InstAlias<"cneg $dst, $src, $cc", 1693 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1694def : InstAlias<"cneg $dst, $src, $cc", 1695 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1696 1697//===----------------------------------------------------------------------===// 1698// PC-relative instructions. 1699//===----------------------------------------------------------------------===// 1700let isReMaterializable = 1 in { 1701let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 1702def ADR : ADRI<0, "adr", adrlabel, 1703 [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>; 1704} // hasSideEffects = 0 1705 1706def ADRP : ADRI<1, "adrp", adrplabel, 1707 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>; 1708} // isReMaterializable = 1 1709 1710// page address of a constant pool entry, block address 1711def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>; 1712def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>; 1713def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>; 1714def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>; 1715def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>; 1716def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>; 1717def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>; 1718 1719//===----------------------------------------------------------------------===// 1720// Unconditional branch (register) instructions. 1721//===----------------------------------------------------------------------===// 1722 1723let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1724def RET : BranchReg<0b0010, "ret", []>; 1725def DRPS : SpecialReturn<0b0101, "drps">; 1726def ERET : SpecialReturn<0b0100, "eret">; 1727} // isReturn = 1, isTerminator = 1, isBarrier = 1 1728 1729// Default to the LR register. 1730def : InstAlias<"ret", (RET LR)>; 1731 1732let isCall = 1, Defs = [LR], Uses = [SP] in { 1733def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>; 1734} // isCall 1735 1736let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1737def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>; 1738} // isBranch, isTerminator, isBarrier, isIndirectBranch 1739 1740// Create a separate pseudo-instruction for codegen to use so that we don't 1741// flag lr as used in every function. It'll be restored before the RET by the 1742// epilogue if it's legitimately used. 1743def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>, 1744 Sched<[WriteBrReg]> { 1745 let isTerminator = 1; 1746 let isBarrier = 1; 1747 let isReturn = 1; 1748} 1749 1750// This is a directive-like pseudo-instruction. The purpose is to insert an 1751// R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction 1752// (which in the usual case is a BLR). 1753let hasSideEffects = 1 in 1754def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> { 1755 let AsmString = ".tlsdesccall $sym"; 1756} 1757 1758// Pseudo instruction to tell the streamer to emit a 'B' character into the 1759// augmentation string. 1760def EMITBKEY : Pseudo<(outs), (ins), []>, Sched<[]> {} 1761 1762// FIXME: maybe the scratch register used shouldn't be fixed to X1? 1763// FIXME: can "hasSideEffects be dropped? 1764let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, 1765 isCodeGenOnly = 1 in 1766def TLSDESC_CALLSEQ 1767 : Pseudo<(outs), (ins i64imm:$sym), 1768 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>, 1769 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>; 1770def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym), 1771 (TLSDESC_CALLSEQ texternalsym:$sym)>; 1772 1773//===----------------------------------------------------------------------===// 1774// Conditional branch (immediate) instruction. 1775//===----------------------------------------------------------------------===// 1776def Bcc : BranchCond; 1777 1778//===----------------------------------------------------------------------===// 1779// Compare-and-branch instructions. 1780//===----------------------------------------------------------------------===// 1781defm CBZ : CmpBranch<0, "cbz", AArch64cbz>; 1782defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>; 1783 1784//===----------------------------------------------------------------------===// 1785// Test-bit-and-branch instructions. 1786//===----------------------------------------------------------------------===// 1787defm TBZ : TestBranch<0, "tbz", AArch64tbz>; 1788defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>; 1789 1790//===----------------------------------------------------------------------===// 1791// Unconditional branch (immediate) instructions. 1792//===----------------------------------------------------------------------===// 1793let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1794def B : BranchImm<0, "b", [(br bb:$addr)]>; 1795} // isBranch, isTerminator, isBarrier 1796 1797let isCall = 1, Defs = [LR], Uses = [SP] in { 1798def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>; 1799} // isCall 1800def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>; 1801 1802//===----------------------------------------------------------------------===// 1803// Exception generation instructions. 1804//===----------------------------------------------------------------------===// 1805let isTrap = 1 in { 1806def BRK : ExceptionGeneration<0b001, 0b00, "brk">; 1807} 1808def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">; 1809def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; 1810def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">; 1811def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; 1812def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; 1813def SMC : ExceptionGeneration<0b000, 0b11, "smc">; 1814def SVC : ExceptionGeneration<0b000, 0b01, "svc">; 1815 1816// DCPSn defaults to an immediate operand of zero if unspecified. 1817def : InstAlias<"dcps1", (DCPS1 0)>; 1818def : InstAlias<"dcps2", (DCPS2 0)>; 1819def : InstAlias<"dcps3", (DCPS3 0)>; 1820 1821def UDF : UDFType<0, "udf">; 1822 1823//===----------------------------------------------------------------------===// 1824// Load instructions. 1825//===----------------------------------------------------------------------===// 1826 1827// Pair (indexed, offset) 1828defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; 1829defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; 1830defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; 1831defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; 1832defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; 1833 1834defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1835 1836// Pair (pre-indexed) 1837def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 1838def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 1839def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 1840def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 1841def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 1842 1843def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1844 1845// Pair (post-indexed) 1846def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 1847def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 1848def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 1849def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 1850def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 1851 1852def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1853 1854 1855// Pair (no allocate) 1856defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; 1857defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; 1858defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; 1859defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; 1860defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; 1861 1862//--- 1863// (register offset) 1864//--- 1865 1866// Integer 1867defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>; 1868defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>; 1869defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; 1870defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; 1871 1872// Floating-point 1873defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>; 1874defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; 1875defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; 1876defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; 1877defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; 1878 1879// Load sign-extended half-word 1880defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; 1881defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>; 1882 1883// Load sign-extended byte 1884defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>; 1885defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>; 1886 1887// Load sign-extended word 1888defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>; 1889 1890// Pre-fetch. 1891defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">; 1892 1893// For regular load, we do not have any alignment requirement. 1894// Thus, it is safe to directly map the vector loads with interesting 1895// addressing modes. 1896// FIXME: We could do the same for bitconvert to floating point vectors. 1897multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop, 1898 ValueType ScalTy, ValueType VecTy, 1899 Instruction LOADW, Instruction LOADX, 1900 SubRegIndex sub> { 1901 def : Pat<(VecTy (scalar_to_vector (ScalTy 1902 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))), 1903 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 1904 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset), 1905 sub)>; 1906 1907 def : Pat<(VecTy (scalar_to_vector (ScalTy 1908 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))), 1909 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 1910 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset), 1911 sub)>; 1912} 1913 1914let AddedComplexity = 10 in { 1915defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>; 1916defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>; 1917 1918defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>; 1919defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>; 1920 1921defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>; 1922defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>; 1923 1924defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>; 1925defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>; 1926 1927defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>; 1928defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>; 1929 1930defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>; 1931 1932defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>; 1933 1934 1935def : Pat <(v1i64 (scalar_to_vector (i64 1936 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, 1937 ro_Wextend64:$extend))))), 1938 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; 1939 1940def : Pat <(v1i64 (scalar_to_vector (i64 1941 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, 1942 ro_Xextend64:$extend))))), 1943 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; 1944} 1945 1946// Match all load 64 bits width whose type is compatible with FPR64 1947multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy, 1948 Instruction LOADW, Instruction LOADX> { 1949 1950 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 1951 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 1952 1953 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 1954 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 1955} 1956 1957let AddedComplexity = 10 in { 1958let Predicates = [IsLE] in { 1959 // We must do vector loads with LD1 in big-endian. 1960 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>; 1961 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>; 1962 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>; 1963 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>; 1964 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>; 1965} 1966 1967defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>; 1968defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 1969 1970// Match all load 128 bits width whose type is compatible with FPR128 1971let Predicates = [IsLE] in { 1972 // We must do vector loads with LD1 in big-endian. 1973 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>; 1974 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>; 1975 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>; 1976 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>; 1977 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>; 1978 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>; 1979 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>; 1980} 1981} // AddedComplexity = 10 1982 1983// zextload -> i64 1984multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop, 1985 Instruction INSTW, Instruction INSTX> { 1986 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 1987 (SUBREG_TO_REG (i64 0), 1988 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 1989 sub_32)>; 1990 1991 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 1992 (SUBREG_TO_REG (i64 0), 1993 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 1994 sub_32)>; 1995} 1996 1997let AddedComplexity = 10 in { 1998 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>; 1999 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>; 2000 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>; 2001 2002 // zextloadi1 -> zextloadi8 2003 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 2004 2005 // extload -> zextload 2006 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 2007 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 2008 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 2009 2010 // extloadi1 -> zextloadi8 2011 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>; 2012} 2013 2014 2015// zextload -> i64 2016multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop, 2017 Instruction INSTW, Instruction INSTX> { 2018 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 2019 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2020 2021 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 2022 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2023 2024} 2025 2026let AddedComplexity = 10 in { 2027 // extload -> zextload 2028 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 2029 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 2030 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 2031 2032 // zextloadi1 -> zextloadi8 2033 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 2034} 2035 2036//--- 2037// (unsigned immediate) 2038//--- 2039defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", 2040 [(set GPR64z:$Rt, 2041 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 2042defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", 2043 [(set GPR32z:$Rt, 2044 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 2045defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", 2046 [(set FPR8Op:$Rt, 2047 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; 2048defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr", 2049 [(set (f16 FPR16Op:$Rt), 2050 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; 2051defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr", 2052 [(set (f32 FPR32Op:$Rt), 2053 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 2054defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", 2055 [(set (f64 FPR64Op:$Rt), 2056 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 2057defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", 2058 [(set (f128 FPR128Op:$Rt), 2059 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; 2060 2061// For regular load, we do not have any alignment requirement. 2062// Thus, it is safe to directly map the vector loads with interesting 2063// addressing modes. 2064// FIXME: We could do the same for bitconvert to floating point vectors. 2065def : Pat <(v8i8 (scalar_to_vector (i32 2066 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 2067 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 2068 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 2069def : Pat <(v16i8 (scalar_to_vector (i32 2070 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 2071 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 2072 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 2073def : Pat <(v4i16 (scalar_to_vector (i32 2074 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 2075 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 2076 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 2077def : Pat <(v8i16 (scalar_to_vector (i32 2078 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 2079 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 2080 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 2081def : Pat <(v2i32 (scalar_to_vector (i32 2082 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 2083 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 2084 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 2085def : Pat <(v4i32 (scalar_to_vector (i32 2086 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 2087 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 2088 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 2089def : Pat <(v1i64 (scalar_to_vector (i64 2090 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 2091 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2092def : Pat <(v2i64 (scalar_to_vector (i64 2093 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 2094 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 2095 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>; 2096 2097// Match all load 64 bits width whose type is compatible with FPR64 2098let Predicates = [IsLE] in { 2099 // We must use LD1 to perform vector loads in big-endian. 2100 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2101 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2102 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2103 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2104 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2105 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2106 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2107 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2108 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2109 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2110} 2111def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2112 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2113def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2114 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2115 2116// Match all load 128 bits width whose type is compatible with FPR128 2117let Predicates = [IsLE] in { 2118 // We must use LD1 to perform vector loads in big-endian. 2119 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2120 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2121 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2122 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2123 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2124 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2125 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2126 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2127 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2128 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2129 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2130 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2131 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2132 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2133} 2134def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2135 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2136 2137defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh", 2138 [(set GPR32:$Rt, 2139 (zextloadi16 (am_indexed16 GPR64sp:$Rn, 2140 uimm12s2:$offset)))]>; 2141defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", 2142 [(set GPR32:$Rt, 2143 (zextloadi8 (am_indexed8 GPR64sp:$Rn, 2144 uimm12s1:$offset)))]>; 2145// zextload -> i64 2146def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2147 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2148def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2149 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 2150 2151// zextloadi1 -> zextloadi8 2152def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2153 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2154def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2155 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2156 2157// extload -> zextload 2158def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2159 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>; 2160def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2161 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2162def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2163 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2164def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 2165 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 2166def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2167 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 2168def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2169 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2170def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2171 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2172 2173// load sign-extended half-word 2174defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", 2175 [(set GPR32:$Rt, 2176 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 2177 uimm12s2:$offset)))]>; 2178defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh", 2179 [(set GPR64:$Rt, 2180 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 2181 uimm12s2:$offset)))]>; 2182 2183// load sign-extended byte 2184defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb", 2185 [(set GPR32:$Rt, 2186 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 2187 uimm12s1:$offset)))]>; 2188defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb", 2189 [(set GPR64:$Rt, 2190 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 2191 uimm12s1:$offset)))]>; 2192 2193// load sign-extended word 2194defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", 2195 [(set GPR64:$Rt, 2196 (sextloadi32 (am_indexed32 GPR64sp:$Rn, 2197 uimm12s4:$offset)))]>; 2198 2199// load zero-extended word 2200def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 2201 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 2202 2203// Pre-fetch. 2204def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", 2205 [(AArch64Prefetch imm:$Rt, 2206 (am_indexed64 GPR64sp:$Rn, 2207 uimm12s8:$offset))]>; 2208 2209def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>; 2210 2211//--- 2212// (literal) 2213 2214def alignedglobal : PatLeaf<(iPTR iPTR:$label), [{ 2215 if (auto *G = dyn_cast<GlobalAddressSDNode>(N)) { 2216 const DataLayout &DL = MF->getDataLayout(); 2217 MaybeAlign Align = G->getGlobal()->getPointerAlignment(DL); 2218 return Align && *Align >= 4 && G->getOffset() % 4 == 0; 2219 } 2220 if (auto *C = dyn_cast<ConstantPoolSDNode>(N)) 2221 return C->getAlignment() >= 4 && C->getOffset() % 4 == 0; 2222 return false; 2223}]>; 2224 2225def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr", 2226 [(set GPR32z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; 2227def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr", 2228 [(set GPR64z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; 2229def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr", 2230 [(set (f32 FPR32Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2231def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr", 2232 [(set (f64 FPR64Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2233def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr", 2234 [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2235 2236// load sign-extended word 2237def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw", 2238 [(set GPR64z:$Rt, (sextloadi32 (AArch64adr alignedglobal:$label)))]>; 2239 2240let AddedComplexity = 20 in { 2241def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))), 2242 (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>; 2243} 2244 2245// prefetch 2246def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; 2247// [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>; 2248 2249//--- 2250// (unscaled immediate) 2251defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", 2252 [(set GPR64z:$Rt, 2253 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 2254defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", 2255 [(set GPR32z:$Rt, 2256 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2257defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", 2258 [(set FPR8Op:$Rt, 2259 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2260defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur", 2261 [(set FPR16Op:$Rt, 2262 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2263defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur", 2264 [(set (f32 FPR32Op:$Rt), 2265 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2266defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", 2267 [(set (f64 FPR64Op:$Rt), 2268 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 2269defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", 2270 [(set (f128 FPR128Op:$Rt), 2271 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; 2272 2273defm LDURHH 2274 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh", 2275 [(set GPR32:$Rt, 2276 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2277defm LDURBB 2278 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb", 2279 [(set GPR32:$Rt, 2280 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2281 2282// Match all load 64 bits width whose type is compatible with FPR64 2283let Predicates = [IsLE] in { 2284 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2285 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2286 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2287 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2288 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2289 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2290 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2291 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2292 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2293 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2294} 2295def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2296 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2297def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2298 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2299 2300// Match all load 128 bits width whose type is compatible with FPR128 2301let Predicates = [IsLE] in { 2302 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2303 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2304 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2305 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2306 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2307 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2308 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2309 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2310 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2311 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2312 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2313 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2314 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2315 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2316} 2317 2318// anyext -> zext 2319def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2320 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 2321def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2322 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2323def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2324 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2325def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 2326 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2327def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2328 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2329def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2330 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2331def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2332 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2333// unscaled zext 2334def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2335 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 2336def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2337 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2338def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2339 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2340def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 2341 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2342def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2343 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2344def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2345 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2346def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2347 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2348 2349 2350//--- 2351// LDR mnemonics fall back to LDUR for negative or unaligned offsets. 2352 2353// Define new assembler match classes as we want to only match these when 2354// the don't otherwise match the scaled addressing mode for LDR/STR. Don't 2355// associate a DiagnosticType either, as we want the diagnostic for the 2356// canonical form (the scaled operand) to take precedence. 2357class SImm9OffsetOperand<int Width> : AsmOperandClass { 2358 let Name = "SImm9OffsetFB" # Width; 2359 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">"; 2360 let RenderMethod = "addImmOperands"; 2361} 2362 2363def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>; 2364def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>; 2365def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>; 2366def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>; 2367def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>; 2368 2369def simm9_offset_fb8 : Operand<i64> { 2370 let ParserMatchClass = SImm9OffsetFB8Operand; 2371} 2372def simm9_offset_fb16 : Operand<i64> { 2373 let ParserMatchClass = SImm9OffsetFB16Operand; 2374} 2375def simm9_offset_fb32 : Operand<i64> { 2376 let ParserMatchClass = SImm9OffsetFB32Operand; 2377} 2378def simm9_offset_fb64 : Operand<i64> { 2379 let ParserMatchClass = SImm9OffsetFB64Operand; 2380} 2381def simm9_offset_fb128 : Operand<i64> { 2382 let ParserMatchClass = SImm9OffsetFB128Operand; 2383} 2384 2385def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2386 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2387def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2388 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2389def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2390 (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2391def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2392 (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2393def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2394 (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2395def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2396 (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2397def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2398 (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 2399 2400// zextload -> i64 2401def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2402 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2403def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2404 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2405 2406// load sign-extended half-word 2407defm LDURSHW 2408 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh", 2409 [(set GPR32:$Rt, 2410 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2411defm LDURSHX 2412 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh", 2413 [(set GPR64:$Rt, 2414 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2415 2416// load sign-extended byte 2417defm LDURSBW 2418 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb", 2419 [(set GPR32:$Rt, 2420 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2421defm LDURSBX 2422 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb", 2423 [(set GPR64:$Rt, 2424 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2425 2426// load sign-extended word 2427defm LDURSW 2428 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw", 2429 [(set GPR64:$Rt, 2430 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2431 2432// zero and sign extending aliases from generic LDR* mnemonics to LDUR*. 2433def : InstAlias<"ldrb $Rt, [$Rn, $offset]", 2434 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2435def : InstAlias<"ldrh $Rt, [$Rn, $offset]", 2436 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2437def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2438 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2439def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2440 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2441def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2442 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2443def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2444 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2445def : InstAlias<"ldrsw $Rt, [$Rn, $offset]", 2446 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2447 2448// Pre-fetch. 2449defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum", 2450 [(AArch64Prefetch imm:$Rt, 2451 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2452 2453//--- 2454// (unscaled immediate, unprivileged) 2455defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">; 2456defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">; 2457 2458defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">; 2459defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">; 2460 2461// load sign-extended half-word 2462defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">; 2463defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">; 2464 2465// load sign-extended byte 2466defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">; 2467defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">; 2468 2469// load sign-extended word 2470defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; 2471 2472//--- 2473// (immediate pre-indexed) 2474def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; 2475def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; 2476def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 2477def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 2478def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 2479def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 2480def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 2481 2482// load sign-extended half-word 2483def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 2484def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 2485 2486// load sign-extended byte 2487def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 2488def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 2489 2490// load zero-extended byte 2491def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 2492def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 2493 2494// load sign-extended word 2495def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 2496 2497//--- 2498// (immediate post-indexed) 2499def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; 2500def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; 2501def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 2502def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 2503def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 2504def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 2505def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 2506 2507// load sign-extended half-word 2508def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 2509def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 2510 2511// load sign-extended byte 2512def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 2513def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 2514 2515// load zero-extended byte 2516def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 2517def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 2518 2519// load sign-extended word 2520def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 2521 2522//===----------------------------------------------------------------------===// 2523// Store instructions. 2524//===----------------------------------------------------------------------===// 2525 2526// Pair (indexed, offset) 2527// FIXME: Use dedicated range-checked addressing mode operand here. 2528defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; 2529defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; 2530defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; 2531defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; 2532defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; 2533 2534// Pair (pre-indexed) 2535def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; 2536def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; 2537def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 2538def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 2539def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 2540 2541// Pair (pre-indexed) 2542def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; 2543def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; 2544def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 2545def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 2546def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 2547 2548// Pair (no allocate) 2549defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; 2550defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; 2551defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; 2552defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; 2553defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; 2554 2555//--- 2556// (Register offset) 2557 2558// Integer 2559defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>; 2560defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>; 2561defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>; 2562defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; 2563 2564 2565// Floating-point 2566defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>; 2567defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; 2568defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; 2569defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; 2570defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>; 2571 2572let Predicates = [UseSTRQro], AddedComplexity = 10 in { 2573 def : Pat<(store (f128 FPR128:$Rt), 2574 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm, 2575 ro_Wextend128:$extend)), 2576 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>; 2577 def : Pat<(store (f128 FPR128:$Rt), 2578 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm, 2579 ro_Xextend128:$extend)), 2580 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>; 2581} 2582 2583multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop, 2584 Instruction STRW, Instruction STRX> { 2585 2586 def : Pat<(storeop GPR64:$Rt, 2587 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2588 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32), 2589 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2590 2591 def : Pat<(storeop GPR64:$Rt, 2592 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2593 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32), 2594 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2595} 2596 2597let AddedComplexity = 10 in { 2598 // truncstore i64 2599 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>; 2600 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>; 2601 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>; 2602} 2603 2604multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR, 2605 Instruction STRW, Instruction STRX> { 2606 def : Pat<(store (VecTy FPR:$Rt), 2607 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2608 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2609 2610 def : Pat<(store (VecTy FPR:$Rt), 2611 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2612 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2613} 2614 2615let AddedComplexity = 10 in { 2616// Match all store 64 bits width whose type is compatible with FPR64 2617let Predicates = [IsLE] in { 2618 // We must use ST1 to store vectors in big-endian. 2619 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>; 2620 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>; 2621 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>; 2622 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>; 2623 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>; 2624} 2625 2626defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>; 2627defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 2628 2629// Match all store 128 bits width whose type is compatible with FPR128 2630let Predicates = [IsLE, UseSTRQro] in { 2631 // We must use ST1 to store vectors in big-endian. 2632 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>; 2633 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>; 2634 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>; 2635 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>; 2636 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>; 2637 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>; 2638 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>; 2639} 2640} // AddedComplexity = 10 2641 2642// Match stores from lane 0 to the appropriate subreg's store. 2643multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop, 2644 ValueType VecTy, ValueType STy, 2645 SubRegIndex SubRegIdx, 2646 Instruction STRW, Instruction STRX> { 2647 2648 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 2649 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2650 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2651 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2652 2653 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 2654 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2655 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2656 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2657} 2658 2659let AddedComplexity = 19 in { 2660 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>; 2661 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>; 2662 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>; 2663 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>; 2664 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>; 2665 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>; 2666} 2667 2668//--- 2669// (unsigned immediate) 2670defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", 2671 [(store GPR64z:$Rt, 2672 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 2673defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", 2674 [(store GPR32z:$Rt, 2675 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 2676defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", 2677 [(store FPR8Op:$Rt, 2678 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; 2679defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str", 2680 [(store (f16 FPR16Op:$Rt), 2681 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; 2682defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str", 2683 [(store (f32 FPR32Op:$Rt), 2684 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 2685defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", 2686 [(store (f64 FPR64Op:$Rt), 2687 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 2688defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; 2689 2690defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", 2691 [(truncstorei16 GPR32z:$Rt, 2692 (am_indexed16 GPR64sp:$Rn, 2693 uimm12s2:$offset))]>; 2694defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb", 2695 [(truncstorei8 GPR32z:$Rt, 2696 (am_indexed8 GPR64sp:$Rn, 2697 uimm12s1:$offset))]>; 2698 2699let AddedComplexity = 10 in { 2700 2701// Match all store 64 bits width whose type is compatible with FPR64 2702def : Pat<(store (v1i64 FPR64:$Rt), 2703 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2704 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2705def : Pat<(store (v1f64 FPR64:$Rt), 2706 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2707 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2708 2709let Predicates = [IsLE] in { 2710 // We must use ST1 to store vectors in big-endian. 2711 def : Pat<(store (v2f32 FPR64:$Rt), 2712 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2713 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2714 def : Pat<(store (v8i8 FPR64:$Rt), 2715 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2716 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2717 def : Pat<(store (v4i16 FPR64:$Rt), 2718 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2719 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2720 def : Pat<(store (v2i32 FPR64:$Rt), 2721 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2722 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2723 def : Pat<(store (v4f16 FPR64:$Rt), 2724 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2725 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2726} 2727 2728// Match all store 128 bits width whose type is compatible with FPR128 2729def : Pat<(store (f128 FPR128:$Rt), 2730 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2731 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2732 2733let Predicates = [IsLE] in { 2734 // We must use ST1 to store vectors in big-endian. 2735 def : Pat<(store (v4f32 FPR128:$Rt), 2736 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2737 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2738 def : Pat<(store (v2f64 FPR128:$Rt), 2739 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2740 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2741 def : Pat<(store (v16i8 FPR128:$Rt), 2742 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2743 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2744 def : Pat<(store (v8i16 FPR128:$Rt), 2745 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2746 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2747 def : Pat<(store (v4i32 FPR128:$Rt), 2748 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2749 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2750 def : Pat<(store (v2i64 FPR128:$Rt), 2751 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2752 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2753 def : Pat<(store (v8f16 FPR128:$Rt), 2754 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2755 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2756} 2757 2758// truncstore i64 2759def : Pat<(truncstorei32 GPR64:$Rt, 2760 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)), 2761 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>; 2762def : Pat<(truncstorei16 GPR64:$Rt, 2763 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), 2764 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>; 2765def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), 2766 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>; 2767 2768} // AddedComplexity = 10 2769 2770// Match stores from lane 0 to the appropriate subreg's store. 2771multiclass VecStoreLane0Pat<Operand UIAddrMode, SDPatternOperator storeop, 2772 ValueType VTy, ValueType STy, 2773 SubRegIndex SubRegIdx, Operand IndexType, 2774 Instruction STR> { 2775 def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)), 2776 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)), 2777 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2778 GPR64sp:$Rn, IndexType:$offset)>; 2779} 2780 2781let AddedComplexity = 19 in { 2782 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>; 2783 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>; 2784 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>; 2785 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>; 2786 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>; 2787 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>; 2788} 2789 2790//--- 2791// (unscaled immediate) 2792defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", 2793 [(store GPR64z:$Rt, 2794 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2795defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", 2796 [(store GPR32z:$Rt, 2797 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 2798defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", 2799 [(store FPR8Op:$Rt, 2800 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 2801defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur", 2802 [(store (f16 FPR16Op:$Rt), 2803 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 2804defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur", 2805 [(store (f32 FPR32Op:$Rt), 2806 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 2807defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", 2808 [(store (f64 FPR64Op:$Rt), 2809 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2810defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", 2811 [(store (f128 FPR128Op:$Rt), 2812 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; 2813defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", 2814 [(truncstorei16 GPR32z:$Rt, 2815 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 2816defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", 2817 [(truncstorei8 GPR32z:$Rt, 2818 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 2819 2820// Armv8.4 Weaker Release Consistency enhancements 2821// LDAPR & STLR with Immediate Offset instructions 2822let Predicates = [HasRCPC_IMMO] in { 2823defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>; 2824defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>; 2825defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>; 2826defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>; 2827defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>; 2828defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>; 2829defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>; 2830defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>; 2831defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>; 2832defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>; 2833defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>; 2834defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>; 2835defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>; 2836} 2837 2838// Match all store 64 bits width whose type is compatible with FPR64 2839def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2840 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2841def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2842 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2843 2844let AddedComplexity = 10 in { 2845 2846let Predicates = [IsLE] in { 2847 // We must use ST1 to store vectors in big-endian. 2848 def : Pat<(store (v2f32 FPR64:$Rt), 2849 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2850 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2851 def : Pat<(store (v8i8 FPR64:$Rt), 2852 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2853 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2854 def : Pat<(store (v4i16 FPR64:$Rt), 2855 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2856 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2857 def : Pat<(store (v2i32 FPR64:$Rt), 2858 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2859 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2860 def : Pat<(store (v4f16 FPR64:$Rt), 2861 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2862 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2863} 2864 2865// Match all store 128 bits width whose type is compatible with FPR128 2866def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2867 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2868 2869let Predicates = [IsLE] in { 2870 // We must use ST1 to store vectors in big-endian. 2871 def : Pat<(store (v4f32 FPR128:$Rt), 2872 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2873 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2874 def : Pat<(store (v2f64 FPR128:$Rt), 2875 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2876 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2877 def : Pat<(store (v16i8 FPR128:$Rt), 2878 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2879 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2880 def : Pat<(store (v8i16 FPR128:$Rt), 2881 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2882 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2883 def : Pat<(store (v4i32 FPR128:$Rt), 2884 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2885 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2886 def : Pat<(store (v2i64 FPR128:$Rt), 2887 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2888 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2889 def : Pat<(store (v2f64 FPR128:$Rt), 2890 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2891 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2892 def : Pat<(store (v8f16 FPR128:$Rt), 2893 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2894 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2895} 2896 2897} // AddedComplexity = 10 2898 2899// unscaled i64 truncating stores 2900def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), 2901 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2902def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), 2903 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2904def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), 2905 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2906 2907// Match stores from lane 0 to the appropriate subreg's store. 2908multiclass VecStoreULane0Pat<SDPatternOperator StoreOp, 2909 ValueType VTy, ValueType STy, 2910 SubRegIndex SubRegIdx, Instruction STR> { 2911 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegIdx, simm9, STR>; 2912} 2913 2914let AddedComplexity = 19 in { 2915 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, hsub, STURHi>; 2916 defm : VecStoreULane0Pat<store, v8f16, f16, hsub, STURHi>; 2917 defm : VecStoreULane0Pat<store, v4i32, i32, ssub, STURSi>; 2918 defm : VecStoreULane0Pat<store, v4f32, f32, ssub, STURSi>; 2919 defm : VecStoreULane0Pat<store, v2i64, i64, dsub, STURDi>; 2920 defm : VecStoreULane0Pat<store, v2f64, f64, dsub, STURDi>; 2921} 2922 2923//--- 2924// STR mnemonics fall back to STUR for negative or unaligned offsets. 2925def : InstAlias<"str $Rt, [$Rn, $offset]", 2926 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2927def : InstAlias<"str $Rt, [$Rn, $offset]", 2928 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2929def : InstAlias<"str $Rt, [$Rn, $offset]", 2930 (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2931def : InstAlias<"str $Rt, [$Rn, $offset]", 2932 (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2933def : InstAlias<"str $Rt, [$Rn, $offset]", 2934 (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2935def : InstAlias<"str $Rt, [$Rn, $offset]", 2936 (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2937def : InstAlias<"str $Rt, [$Rn, $offset]", 2938 (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 2939 2940def : InstAlias<"strb $Rt, [$Rn, $offset]", 2941 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2942def : InstAlias<"strh $Rt, [$Rn, $offset]", 2943 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2944 2945//--- 2946// (unscaled immediate, unprivileged) 2947defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">; 2948defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">; 2949 2950defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">; 2951defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; 2952 2953//--- 2954// (immediate pre-indexed) 2955def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; 2956def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; 2957def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>; 2958def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; 2959def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; 2960def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; 2961def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; 2962 2963def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; 2964def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; 2965 2966// truncstore i64 2967def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2968 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2969 simm9:$off)>; 2970def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2971 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2972 simm9:$off)>; 2973def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2974 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2975 simm9:$off)>; 2976 2977def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2978 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2979def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2980 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2981def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2982 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2983def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2984 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2985def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2986 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2987def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2988 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2989def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2990 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2991 2992def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2993 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2994def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2995 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2996def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2997 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2998def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2999 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3000def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3001 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3002def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3003 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3004def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3005 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3006 3007//--- 3008// (immediate post-indexed) 3009def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; 3010def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; 3011def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>; 3012def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; 3013def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; 3014def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; 3015def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; 3016 3017def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; 3018def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; 3019 3020// truncstore i64 3021def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3022 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3023 simm9:$off)>; 3024def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3025 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3026 simm9:$off)>; 3027def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3028 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3029 simm9:$off)>; 3030 3031def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3032 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3033def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3034 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3035def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3036 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3037def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3038 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3039def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3040 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3041def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3042 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3043def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3044 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3045 3046def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3047 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3048def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3049 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3050def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3051 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3052def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3053 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3054def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3055 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3056def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3057 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3058def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3059 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3060 3061//===----------------------------------------------------------------------===// 3062// Load/store exclusive instructions. 3063//===----------------------------------------------------------------------===// 3064 3065def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">; 3066def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">; 3067def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">; 3068def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">; 3069 3070def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">; 3071def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">; 3072def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">; 3073def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">; 3074 3075def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">; 3076def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">; 3077def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">; 3078def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">; 3079 3080def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">; 3081def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">; 3082def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">; 3083def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">; 3084 3085def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">; 3086def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">; 3087def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">; 3088def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">; 3089 3090def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">; 3091def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">; 3092def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">; 3093def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">; 3094 3095def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">; 3096def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">; 3097 3098def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">; 3099def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">; 3100 3101def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">; 3102def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">; 3103 3104def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">; 3105def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">; 3106 3107let Predicates = [HasLOR] in { 3108 // v8.1a "Limited Order Region" extension load-acquire instructions 3109 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">; 3110 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">; 3111 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">; 3112 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">; 3113 3114 // v8.1a "Limited Order Region" extension store-release instructions 3115 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">; 3116 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">; 3117 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">; 3118 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">; 3119} 3120 3121//===----------------------------------------------------------------------===// 3122// Scaled floating point to integer conversion instructions. 3123//===----------------------------------------------------------------------===// 3124 3125defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>; 3126defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>; 3127defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>; 3128defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>; 3129defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>; 3130defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>; 3131defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>; 3132defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>; 3133defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>; 3134defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>; 3135defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>; 3136defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>; 3137 3138multiclass FPToIntegerIntPats<Intrinsic round, string INST> { 3139 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>; 3140 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>; 3141 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>; 3142 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>; 3143 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>; 3144 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>; 3145 3146 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))), 3147 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>; 3148 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))), 3149 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>; 3150 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))), 3151 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>; 3152 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))), 3153 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>; 3154 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))), 3155 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>; 3156 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))), 3157 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>; 3158} 3159 3160defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">; 3161defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">; 3162 3163multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> { 3164 def : Pat<(i32 (to_int (round f32:$Rn))), 3165 (!cast<Instruction>(INST # UWSr) f32:$Rn)>; 3166 def : Pat<(i64 (to_int (round f32:$Rn))), 3167 (!cast<Instruction>(INST # UXSr) f32:$Rn)>; 3168 def : Pat<(i32 (to_int (round f64:$Rn))), 3169 (!cast<Instruction>(INST # UWDr) f64:$Rn)>; 3170 def : Pat<(i64 (to_int (round f64:$Rn))), 3171 (!cast<Instruction>(INST # UXDr) f64:$Rn)>; 3172} 3173 3174defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">; 3175defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">; 3176defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">; 3177defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">; 3178defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">; 3179defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">; 3180defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">; 3181defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">; 3182 3183let Predicates = [HasFullFP16] in { 3184 def : Pat<(i32 (lround f16:$Rn)), 3185 (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>; 3186 def : Pat<(i64 (lround f16:$Rn)), 3187 (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>; 3188 def : Pat<(i64 (llround f16:$Rn)), 3189 (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>; 3190} 3191def : Pat<(i32 (lround f32:$Rn)), 3192 (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>; 3193def : Pat<(i32 (lround f64:$Rn)), 3194 (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>; 3195def : Pat<(i64 (lround f32:$Rn)), 3196 (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>; 3197def : Pat<(i64 (lround f64:$Rn)), 3198 (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>; 3199def : Pat<(i64 (llround f32:$Rn)), 3200 (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>; 3201def : Pat<(i64 (llround f64:$Rn)), 3202 (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>; 3203 3204//===----------------------------------------------------------------------===// 3205// Scaled integer to floating point conversion instructions. 3206//===----------------------------------------------------------------------===// 3207 3208defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>; 3209defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>; 3210 3211//===----------------------------------------------------------------------===// 3212// Unscaled integer to floating point conversion instruction. 3213//===----------------------------------------------------------------------===// 3214 3215defm FMOV : UnscaledConversion<"fmov">; 3216 3217// Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable 3218let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { 3219def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, 3220 Sched<[WriteF]>, Requires<[HasFullFP16]>; 3221def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, 3222 Sched<[WriteF]>; 3223def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, 3224 Sched<[WriteF]>; 3225} 3226// Similarly add aliases 3227def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, 3228 Requires<[HasFullFP16]>; 3229def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; 3230def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; 3231 3232//===----------------------------------------------------------------------===// 3233// Floating point conversion instruction. 3234//===----------------------------------------------------------------------===// 3235 3236defm FCVT : FPConversion<"fcvt">; 3237 3238//===----------------------------------------------------------------------===// 3239// Floating point single operand instructions. 3240//===----------------------------------------------------------------------===// 3241 3242defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>; 3243defm FMOV : SingleOperandFPData<0b0000, "fmov">; 3244defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>; 3245defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>; 3246defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>; 3247defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>; 3248defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>; 3249defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>; 3250 3251def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), 3252 (FRINTNDr FPR64:$Rn)>; 3253 3254defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>; 3255defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>; 3256 3257let SchedRW = [WriteFDiv] in { 3258defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>; 3259} 3260 3261let Predicates = [HasFRInt3264] in { 3262 defm FRINT32Z : FRIntNNT<0b00, "frint32z">; 3263 defm FRINT64Z : FRIntNNT<0b10, "frint64z">; 3264 defm FRINT32X : FRIntNNT<0b01, "frint32x">; 3265 defm FRINT64X : FRIntNNT<0b11, "frint64x">; 3266} // HasFRInt3264 3267 3268let Predicates = [HasFullFP16] in { 3269 def : Pat<(i32 (lrint f16:$Rn)), 3270 (FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3271 def : Pat<(i64 (lrint f16:$Rn)), 3272 (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3273 def : Pat<(i64 (llrint f16:$Rn)), 3274 (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3275} 3276def : Pat<(i32 (lrint f32:$Rn)), 3277 (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3278def : Pat<(i32 (lrint f64:$Rn)), 3279 (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3280def : Pat<(i64 (lrint f32:$Rn)), 3281 (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3282def : Pat<(i64 (lrint f64:$Rn)), 3283 (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3284def : Pat<(i64 (llrint f32:$Rn)), 3285 (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3286def : Pat<(i64 (llrint f64:$Rn)), 3287 (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3288 3289//===----------------------------------------------------------------------===// 3290// Floating point two operand instructions. 3291//===----------------------------------------------------------------------===// 3292 3293defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>; 3294let SchedRW = [WriteFDiv] in { 3295defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>; 3296} 3297defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>; 3298defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>; 3299defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>; 3300defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>; 3301let SchedRW = [WriteFMul] in { 3302defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>; 3303defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>; 3304} 3305defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>; 3306 3307def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3308 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>; 3309def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3310 (FMINDrr FPR64:$Rn, FPR64:$Rm)>; 3311def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3312 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>; 3313def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3314 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>; 3315 3316//===----------------------------------------------------------------------===// 3317// Floating point three operand instructions. 3318//===----------------------------------------------------------------------===// 3319 3320defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>; 3321defm FMSUB : ThreeOperandFPData<0, 1, "fmsub", 3322 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >; 3323defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd", 3324 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >; 3325defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub", 3326 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >; 3327 3328// The following def pats catch the case where the LHS of an FMA is negated. 3329// The TriOpFrag above catches the case where the middle operand is negated. 3330 3331// N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike 3332// the NEON variant. 3333 3334// Here we handle first -(a + b*c) for FNMADD: 3335 3336let Predicates = [HasNEON, HasFullFP16] in 3337def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)), 3338 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3339 3340def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)), 3341 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3342 3343def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)), 3344 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3345 3346// Now it's time for "(-a) + (-b)*c" 3347 3348let Predicates = [HasNEON, HasFullFP16] in 3349def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, (fneg FPR16:$Ra))), 3350 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3351 3352def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), 3353 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3354 3355def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), 3356 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3357 3358// And here "(-a) + b*(-c)" 3359 3360let Predicates = [HasNEON, HasFullFP16] in 3361def : Pat<(f16 (fma FPR16:$Rn, (fneg FPR16:$Rm), (fneg FPR16:$Ra))), 3362 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3363 3364def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))), 3365 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3366 3367def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))), 3368 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3369 3370//===----------------------------------------------------------------------===// 3371// Floating point comparison instructions. 3372//===----------------------------------------------------------------------===// 3373 3374defm FCMPE : FPComparison<1, "fcmpe">; 3375defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>; 3376 3377//===----------------------------------------------------------------------===// 3378// Floating point conditional comparison instructions. 3379//===----------------------------------------------------------------------===// 3380 3381defm FCCMPE : FPCondComparison<1, "fccmpe">; 3382defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>; 3383 3384//===----------------------------------------------------------------------===// 3385// Floating point conditional select instruction. 3386//===----------------------------------------------------------------------===// 3387 3388defm FCSEL : FPCondSelect<"fcsel">; 3389 3390// CSEL instructions providing f128 types need to be handled by a 3391// pseudo-instruction since the eventual code will need to introduce basic 3392// blocks and control flow. 3393def F128CSEL : Pseudo<(outs FPR128:$Rd), 3394 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond), 3395 [(set (f128 FPR128:$Rd), 3396 (AArch64csel FPR128:$Rn, FPR128:$Rm, 3397 (i32 imm:$cond), NZCV))]> { 3398 let Uses = [NZCV]; 3399 let usesCustomInserter = 1; 3400 let hasNoSchedulingInfo = 1; 3401} 3402 3403//===----------------------------------------------------------------------===// 3404// Instructions used for emitting unwind opcodes on ARM64 Windows. 3405//===----------------------------------------------------------------------===// 3406let isPseudo = 1 in { 3407 def SEH_StackAlloc : Pseudo<(outs), (ins i32imm:$size), []>, Sched<[]>; 3408 def SEH_SaveFPLR : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 3409 def SEH_SaveFPLR_X : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 3410 def SEH_SaveReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 3411 def SEH_SaveReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 3412 def SEH_SaveRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 3413 def SEH_SaveRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 3414 def SEH_SaveFReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 3415 def SEH_SaveFReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 3416 def SEH_SaveFRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 3417 def SEH_SaveFRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 3418 def SEH_SetFP : Pseudo<(outs), (ins), []>, Sched<[]>; 3419 def SEH_AddFP : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 3420 def SEH_Nop : Pseudo<(outs), (ins), []>, Sched<[]>; 3421 def SEH_PrologEnd : Pseudo<(outs), (ins), []>, Sched<[]>; 3422 def SEH_EpilogStart : Pseudo<(outs), (ins), []>, Sched<[]>; 3423 def SEH_EpilogEnd : Pseudo<(outs), (ins), []>, Sched<[]>; 3424} 3425 3426// Pseudo instructions for Windows EH 3427//===----------------------------------------------------------------------===// 3428let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 3429 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1, isPseudo = 1 in { 3430 def CLEANUPRET : Pseudo<(outs), (ins), [(cleanupret)]>, Sched<[]>; 3431 let usesCustomInserter = 1 in 3432 def CATCHRET : Pseudo<(outs), (ins am_brcond:$dst, am_brcond:$src), [(catchret bb:$dst, bb:$src)]>, 3433 Sched<[]>; 3434} 3435 3436let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 3437 usesCustomInserter = 1 in 3438def CATCHPAD : Pseudo<(outs), (ins), [(catchpad)]>, Sched<[]>; 3439 3440//===----------------------------------------------------------------------===// 3441// Floating point immediate move. 3442//===----------------------------------------------------------------------===// 3443 3444let isReMaterializable = 1 in { 3445defm FMOV : FPMoveImmediate<"fmov">; 3446} 3447 3448//===----------------------------------------------------------------------===// 3449// Advanced SIMD two vector instructions. 3450//===----------------------------------------------------------------------===// 3451 3452defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", 3453 int_aarch64_neon_uabd>; 3454// Match UABDL in log2-shuffle patterns. 3455def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)), 3456 (zext (v8i8 V64:$opB))))), 3457 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 3458def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 3459 (v8i16 (add (sub (zext (v8i8 V64:$opA)), 3460 (zext (v8i8 V64:$opB))), 3461 (AArch64vashr v8i16:$src, (i32 15))))), 3462 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 3463def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)), 3464 (zext (extract_high_v16i8 V128:$opB))))), 3465 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 3466def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 3467 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)), 3468 (zext (extract_high_v16i8 V128:$opB))), 3469 (AArch64vashr v8i16:$src, (i32 15))))), 3470 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 3471def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)), 3472 (zext (v4i16 V64:$opB))))), 3473 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>; 3474def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 V128:$opA)), 3475 (zext (extract_high_v8i16 V128:$opB))))), 3476 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>; 3477def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)), 3478 (zext (v2i32 V64:$opB))))), 3479 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>; 3480def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 V128:$opA)), 3481 (zext (extract_high_v4i32 V128:$opB))))), 3482 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>; 3483 3484defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>; 3485defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>; 3486defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>; 3487defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>; 3488defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>; 3489defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>; 3490defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>; 3491defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>; 3492defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>; 3493defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>; 3494 3495defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 3496defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 3497defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 3498defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 3499defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 3500defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>; 3501defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>; 3502defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">; 3503def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))), 3504 (FCVTLv4i16 V64:$Rn)>; 3505def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn), 3506 (i64 4)))), 3507 (FCVTLv8i16 V128:$Rn)>; 3508def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>; 3509def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn), 3510 (i64 2))))), 3511 (FCVTLv4i32 V128:$Rn)>; 3512 3513def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>; 3514def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn), 3515 (i64 4))))), 3516 (FCVTLv8i16 V128:$Rn)>; 3517 3518defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>; 3519defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>; 3520defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>; 3521defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>; 3522defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">; 3523def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))), 3524 (FCVTNv4i16 V128:$Rn)>; 3525def : Pat<(concat_vectors V64:$Rd, 3526 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))), 3527 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 3528def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>; 3529def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>; 3530def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))), 3531 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 3532defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>; 3533defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>; 3534defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn", 3535 int_aarch64_neon_fcvtxn>; 3536defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>; 3537defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>; 3538 3539def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>; 3540def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>; 3541def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>; 3542def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>; 3543def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>; 3544 3545def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>; 3546def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>; 3547def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>; 3548def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>; 3549def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>; 3550 3551defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>; 3552defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>; 3553defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>; 3554defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>; 3555defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>; 3556defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>; 3557defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>; 3558defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>; 3559defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>; 3560 3561let Predicates = [HasFRInt3264] in { 3562 defm FRINT32Z : FRIntNNTVector<0, 0, "frint32z">; 3563 defm FRINT64Z : FRIntNNTVector<0, 1, "frint64z">; 3564 defm FRINT32X : FRIntNNTVector<1, 0, "frint32x">; 3565 defm FRINT64X : FRIntNNTVector<1, 1, "frint64x">; 3566} // HasFRInt3264 3567 3568defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>; 3569defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>; 3570defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", 3571 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 3572defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; 3573// Aliases for MVN -> NOT. 3574def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", 3575 (NOTv8i8 V64:$Vd, V64:$Vn)>; 3576def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", 3577 (NOTv16i8 V128:$Vd, V128:$Vn)>; 3578 3579def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>; 3580def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>; 3581def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>; 3582def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>; 3583def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>; 3584def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>; 3585def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>; 3586 3587def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3588def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3589def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3590def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3591def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3592def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3593def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3594def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3595 3596def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3597def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3598def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3599def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3600def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3601 3602defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>; 3603defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>; 3604defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>; 3605defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>; 3606defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp", 3607 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >; 3608defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>; 3609defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; 3610defm SHLL : SIMDVectorLShiftLongBySizeBHS; 3611defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 3612defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 3613defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>; 3614defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>; 3615defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>; 3616defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp", 3617 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >; 3618defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", 3619 int_aarch64_neon_uaddlp>; 3620defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>; 3621defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>; 3622defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>; 3623defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>; 3624defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>; 3625defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>; 3626 3627def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>; 3628def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>; 3629def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>; 3630def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>; 3631def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>; 3632def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>; 3633 3634// Patterns for vector long shift (by element width). These need to match all 3635// three of zext, sext and anyext so it's easier to pull the patterns out of the 3636// definition. 3637multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> { 3638 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)), 3639 (SHLLv8i8 V64:$Rn)>; 3640 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)), 3641 (SHLLv16i8 V128:$Rn)>; 3642 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)), 3643 (SHLLv4i16 V64:$Rn)>; 3644 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)), 3645 (SHLLv8i16 V128:$Rn)>; 3646 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)), 3647 (SHLLv2i32 V64:$Rn)>; 3648 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)), 3649 (SHLLv4i32 V128:$Rn)>; 3650} 3651 3652defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>; 3653defm : SIMDVectorLShiftLongBySizeBHSPats<zext>; 3654defm : SIMDVectorLShiftLongBySizeBHSPats<sext>; 3655 3656//===----------------------------------------------------------------------===// 3657// Advanced SIMD three vector instructions. 3658//===----------------------------------------------------------------------===// 3659 3660defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>; 3661defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>; 3662defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>; 3663defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>; 3664defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>; 3665defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>; 3666defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>; 3667defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>; 3668defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>; 3669let Predicates = [HasNEON] in { 3670foreach VT = [ v2f32, v4f32, v2f64 ] in 3671def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 3672} 3673let Predicates = [HasNEON, HasFullFP16] in { 3674foreach VT = [ v4f16, v8f16 ] in 3675def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 3676} 3677defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>; 3678defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>; 3679defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_faddp>; 3680defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>; 3681defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 3682defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 3683defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 3684defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>; 3685defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>; 3686defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>; 3687defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>; 3688defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>; 3689defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>; 3690defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>; 3691defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>; 3692defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>; 3693 3694// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the 3695// instruction expects the addend first, while the fma intrinsic puts it last. 3696defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", 3697 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 3698defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", 3699 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 3700 3701// The following def pats catch the case where the LHS of an FMA is negated. 3702// The TriOpFrag above catches the case where the middle operand is negated. 3703def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)), 3704 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>; 3705 3706def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), 3707 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>; 3708 3709def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), 3710 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>; 3711 3712defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; 3713defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; 3714defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; 3715defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>; 3716defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>; 3717defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", 3718 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >; 3719defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", 3720 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >; 3721defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>; 3722defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>; 3723defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba", 3724 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >; 3725defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>; 3726defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>; 3727defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>; 3728defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>; 3729defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>; 3730defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>; 3731defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>; 3732defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>; 3733defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>; 3734defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>; 3735defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>; 3736defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>; 3737defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>; 3738defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>; 3739defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>; 3740defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>; 3741defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>; 3742defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba", 3743 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >; 3744defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>; 3745defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>; 3746defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>; 3747defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>; 3748defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>; 3749defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>; 3750defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>; 3751defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>; 3752defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>; 3753defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>; 3754defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>; 3755defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>; 3756defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>; 3757defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>; 3758defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah", 3759 int_aarch64_neon_sqadd>; 3760defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", 3761 int_aarch64_neon_sqsub>; 3762 3763defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; 3764defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", 3765 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; 3766defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">; 3767defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>; 3768defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl", 3769 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>; 3770defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>; 3771defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn", 3772 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >; 3773defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>; 3774 3775 3776def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm), 3777 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3778def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm), 3779 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3780def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm), 3781 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3782def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm), 3783 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3784 3785def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm), 3786 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3787def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm), 3788 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3789def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), 3790 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3791def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), 3792 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3793 3794def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", 3795 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; 3796def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", 3797 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3798def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}", 3799 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3800def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}", 3801 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3802 3803def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}", 3804 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>; 3805def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}", 3806 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3807def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}", 3808 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3809def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}", 3810 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3811 3812def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" # 3813 "|cmls.8b\t$dst, $src1, $src2}", 3814 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3815def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" # 3816 "|cmls.16b\t$dst, $src1, $src2}", 3817 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3818def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" # 3819 "|cmls.4h\t$dst, $src1, $src2}", 3820 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3821def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" # 3822 "|cmls.8h\t$dst, $src1, $src2}", 3823 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3824def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" # 3825 "|cmls.2s\t$dst, $src1, $src2}", 3826 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3827def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" # 3828 "|cmls.4s\t$dst, $src1, $src2}", 3829 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3830def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" # 3831 "|cmls.2d\t$dst, $src1, $src2}", 3832 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3833 3834def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" # 3835 "|cmlo.8b\t$dst, $src1, $src2}", 3836 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3837def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" # 3838 "|cmlo.16b\t$dst, $src1, $src2}", 3839 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3840def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" # 3841 "|cmlo.4h\t$dst, $src1, $src2}", 3842 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3843def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" # 3844 "|cmlo.8h\t$dst, $src1, $src2}", 3845 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3846def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" # 3847 "|cmlo.2s\t$dst, $src1, $src2}", 3848 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3849def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" # 3850 "|cmlo.4s\t$dst, $src1, $src2}", 3851 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3852def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" # 3853 "|cmlo.2d\t$dst, $src1, $src2}", 3854 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3855 3856def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" # 3857 "|cmle.8b\t$dst, $src1, $src2}", 3858 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3859def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" # 3860 "|cmle.16b\t$dst, $src1, $src2}", 3861 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3862def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" # 3863 "|cmle.4h\t$dst, $src1, $src2}", 3864 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3865def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" # 3866 "|cmle.8h\t$dst, $src1, $src2}", 3867 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3868def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" # 3869 "|cmle.2s\t$dst, $src1, $src2}", 3870 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3871def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" # 3872 "|cmle.4s\t$dst, $src1, $src2}", 3873 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3874def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" # 3875 "|cmle.2d\t$dst, $src1, $src2}", 3876 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3877 3878def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" # 3879 "|cmlt.8b\t$dst, $src1, $src2}", 3880 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3881def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" # 3882 "|cmlt.16b\t$dst, $src1, $src2}", 3883 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3884def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" # 3885 "|cmlt.4h\t$dst, $src1, $src2}", 3886 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3887def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" # 3888 "|cmlt.8h\t$dst, $src1, $src2}", 3889 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3890def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" # 3891 "|cmlt.2s\t$dst, $src1, $src2}", 3892 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3893def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" # 3894 "|cmlt.4s\t$dst, $src1, $src2}", 3895 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3896def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" # 3897 "|cmlt.2d\t$dst, $src1, $src2}", 3898 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3899 3900let Predicates = [HasNEON, HasFullFP16] in { 3901def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" # 3902 "|fcmle.4h\t$dst, $src1, $src2}", 3903 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3904def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" # 3905 "|fcmle.8h\t$dst, $src1, $src2}", 3906 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3907} 3908def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" # 3909 "|fcmle.2s\t$dst, $src1, $src2}", 3910 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3911def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" # 3912 "|fcmle.4s\t$dst, $src1, $src2}", 3913 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3914def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" # 3915 "|fcmle.2d\t$dst, $src1, $src2}", 3916 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3917 3918let Predicates = [HasNEON, HasFullFP16] in { 3919def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" # 3920 "|fcmlt.4h\t$dst, $src1, $src2}", 3921 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3922def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" # 3923 "|fcmlt.8h\t$dst, $src1, $src2}", 3924 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3925} 3926def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" # 3927 "|fcmlt.2s\t$dst, $src1, $src2}", 3928 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3929def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" # 3930 "|fcmlt.4s\t$dst, $src1, $src2}", 3931 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3932def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" # 3933 "|fcmlt.2d\t$dst, $src1, $src2}", 3934 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3935 3936let Predicates = [HasNEON, HasFullFP16] in { 3937def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" # 3938 "|facle.4h\t$dst, $src1, $src2}", 3939 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3940def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" # 3941 "|facle.8h\t$dst, $src1, $src2}", 3942 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3943} 3944def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" # 3945 "|facle.2s\t$dst, $src1, $src2}", 3946 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3947def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" # 3948 "|facle.4s\t$dst, $src1, $src2}", 3949 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3950def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" # 3951 "|facle.2d\t$dst, $src1, $src2}", 3952 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3953 3954let Predicates = [HasNEON, HasFullFP16] in { 3955def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" # 3956 "|faclt.4h\t$dst, $src1, $src2}", 3957 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3958def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" # 3959 "|faclt.8h\t$dst, $src1, $src2}", 3960 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3961} 3962def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" # 3963 "|faclt.2s\t$dst, $src1, $src2}", 3964 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3965def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # 3966 "|faclt.4s\t$dst, $src1, $src2}", 3967 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3968def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # 3969 "|faclt.2d\t$dst, $src1, $src2}", 3970 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3971 3972//===----------------------------------------------------------------------===// 3973// Advanced SIMD three scalar instructions. 3974//===----------------------------------------------------------------------===// 3975 3976defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>; 3977defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>; 3978defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>; 3979defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>; 3980defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>; 3981defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>; 3982defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>; 3983defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>; 3984def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3985 (FABD64 FPR64:$Rn, FPR64:$Rm)>; 3986let Predicates = [HasFullFP16] in { 3987def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>; 3988} 3989def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>; 3990def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>; 3991defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge", 3992 int_aarch64_neon_facge>; 3993defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt", 3994 int_aarch64_neon_facgt>; 3995defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 3996defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 3997defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 3998defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>; 3999defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>; 4000defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>; 4001defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>; 4002defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>; 4003defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 4004defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>; 4005defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>; 4006defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>; 4007defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>; 4008defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>; 4009defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>; 4010defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>; 4011defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>; 4012defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>; 4013defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>; 4014defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>; 4015defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>; 4016let Predicates = [HasRDM] in { 4017 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">; 4018 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">; 4019 def : Pat<(i32 (int_aarch64_neon_sqadd 4020 (i32 FPR32:$Rd), 4021 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 4022 (i32 FPR32:$Rm))))), 4023 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4024 def : Pat<(i32 (int_aarch64_neon_sqsub 4025 (i32 FPR32:$Rd), 4026 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 4027 (i32 FPR32:$Rm))))), 4028 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4029} 4030 4031def : InstAlias<"cmls $dst, $src1, $src2", 4032 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4033def : InstAlias<"cmle $dst, $src1, $src2", 4034 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4035def : InstAlias<"cmlo $dst, $src1, $src2", 4036 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4037def : InstAlias<"cmlt $dst, $src1, $src2", 4038 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4039def : InstAlias<"fcmle $dst, $src1, $src2", 4040 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4041def : InstAlias<"fcmle $dst, $src1, $src2", 4042 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4043def : InstAlias<"fcmlt $dst, $src1, $src2", 4044 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4045def : InstAlias<"fcmlt $dst, $src1, $src2", 4046 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4047def : InstAlias<"facle $dst, $src1, $src2", 4048 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4049def : InstAlias<"facle $dst, $src1, $src2", 4050 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4051def : InstAlias<"faclt $dst, $src1, $src2", 4052 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4053def : InstAlias<"faclt $dst, $src1, $src2", 4054 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4055 4056//===----------------------------------------------------------------------===// 4057// Advanced SIMD three scalar instructions (mixed operands). 4058//===----------------------------------------------------------------------===// 4059defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull", 4060 int_aarch64_neon_sqdmulls_scalar>; 4061defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">; 4062defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">; 4063 4064def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd), 4065 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 4066 (i32 FPR32:$Rm))))), 4067 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4068def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd), 4069 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 4070 (i32 FPR32:$Rm))))), 4071 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4072 4073//===----------------------------------------------------------------------===// 4074// Advanced SIMD two scalar instructions. 4075//===----------------------------------------------------------------------===// 4076 4077defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>; 4078defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>; 4079defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>; 4080defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>; 4081defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>; 4082defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>; 4083defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 4084defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 4085defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 4086defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 4087defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 4088defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">; 4089defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">; 4090defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">; 4091defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">; 4092defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">; 4093defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">; 4094defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">; 4095defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">; 4096def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">; 4097defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">; 4098defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">; 4099defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">; 4100defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">; 4101defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">; 4102defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg", 4103 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 4104defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; 4105defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 4106defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 4107defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>; 4108defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>; 4109defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd", 4110 int_aarch64_neon_suqadd>; 4111defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>; 4112defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>; 4113defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd", 4114 int_aarch64_neon_usqadd>; 4115 4116def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>; 4117 4118def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))), 4119 (FCVTASv1i64 FPR64:$Rn)>; 4120def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))), 4121 (FCVTAUv1i64 FPR64:$Rn)>; 4122def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))), 4123 (FCVTMSv1i64 FPR64:$Rn)>; 4124def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))), 4125 (FCVTMUv1i64 FPR64:$Rn)>; 4126def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))), 4127 (FCVTNSv1i64 FPR64:$Rn)>; 4128def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))), 4129 (FCVTNUv1i64 FPR64:$Rn)>; 4130def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))), 4131 (FCVTPSv1i64 FPR64:$Rn)>; 4132def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))), 4133 (FCVTPUv1i64 FPR64:$Rn)>; 4134 4135def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))), 4136 (FRECPEv1f16 FPR16:$Rn)>; 4137def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))), 4138 (FRECPEv1i32 FPR32:$Rn)>; 4139def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))), 4140 (FRECPEv1i64 FPR64:$Rn)>; 4141def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))), 4142 (FRECPEv1i64 FPR64:$Rn)>; 4143 4144def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))), 4145 (FRECPEv1i32 FPR32:$Rn)>; 4146def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))), 4147 (FRECPEv2f32 V64:$Rn)>; 4148def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))), 4149 (FRECPEv4f32 FPR128:$Rn)>; 4150def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))), 4151 (FRECPEv1i64 FPR64:$Rn)>; 4152def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))), 4153 (FRECPEv1i64 FPR64:$Rn)>; 4154def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))), 4155 (FRECPEv2f64 FPR128:$Rn)>; 4156 4157def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 4158 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>; 4159def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 4160 (FRECPSv2f32 V64:$Rn, V64:$Rm)>; 4161def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 4162 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>; 4163def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 4164 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>; 4165def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 4166 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>; 4167 4168def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))), 4169 (FRECPXv1f16 FPR16:$Rn)>; 4170def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))), 4171 (FRECPXv1i32 FPR32:$Rn)>; 4172def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))), 4173 (FRECPXv1i64 FPR64:$Rn)>; 4174 4175def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))), 4176 (FRSQRTEv1f16 FPR16:$Rn)>; 4177def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))), 4178 (FRSQRTEv1i32 FPR32:$Rn)>; 4179def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))), 4180 (FRSQRTEv1i64 FPR64:$Rn)>; 4181def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))), 4182 (FRSQRTEv1i64 FPR64:$Rn)>; 4183 4184def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))), 4185 (FRSQRTEv1i32 FPR32:$Rn)>; 4186def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))), 4187 (FRSQRTEv2f32 V64:$Rn)>; 4188def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))), 4189 (FRSQRTEv4f32 FPR128:$Rn)>; 4190def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))), 4191 (FRSQRTEv1i64 FPR64:$Rn)>; 4192def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))), 4193 (FRSQRTEv1i64 FPR64:$Rn)>; 4194def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))), 4195 (FRSQRTEv2f64 FPR128:$Rn)>; 4196 4197def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 4198 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>; 4199def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 4200 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>; 4201def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 4202 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>; 4203def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 4204 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>; 4205def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 4206 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>; 4207 4208// If an integer is about to be converted to a floating point value, 4209// just load it on the floating point unit. 4210// Here are the patterns for 8 and 16-bits to float. 4211// 8-bits -> float. 4212multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy, 4213 SDPatternOperator loadop, Instruction UCVTF, 4214 ROAddrMode ro, Instruction LDRW, Instruction LDRX, 4215 SubRegIndex sub> { 4216 def : Pat<(DstTy (uint_to_fp (SrcTy 4217 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, 4218 ro.Wext:$extend))))), 4219 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 4220 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 4221 sub))>; 4222 4223 def : Pat<(DstTy (uint_to_fp (SrcTy 4224 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, 4225 ro.Wext:$extend))))), 4226 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 4227 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 4228 sub))>; 4229} 4230 4231defm : UIntToFPROLoadPat<f32, i32, zextloadi8, 4232 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>; 4233def : Pat <(f32 (uint_to_fp (i32 4234 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 4235 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4236 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 4237def : Pat <(f32 (uint_to_fp (i32 4238 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 4239 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4240 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 4241// 16-bits -> float. 4242defm : UIntToFPROLoadPat<f32, i32, zextloadi16, 4243 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>; 4244def : Pat <(f32 (uint_to_fp (i32 4245 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 4246 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4247 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 4248def : Pat <(f32 (uint_to_fp (i32 4249 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 4250 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4251 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 4252// 32-bits are handled in target specific dag combine: 4253// performIntToFpCombine. 4254// 64-bits integer to 32-bits floating point, not possible with 4255// UCVTF on floating point registers (both source and destination 4256// must have the same size). 4257 4258// Here are the patterns for 8, 16, 32, and 64-bits to double. 4259// 8-bits -> double. 4260defm : UIntToFPROLoadPat<f64, i32, zextloadi8, 4261 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>; 4262def : Pat <(f64 (uint_to_fp (i32 4263 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 4264 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4265 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 4266def : Pat <(f64 (uint_to_fp (i32 4267 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 4268 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4269 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 4270// 16-bits -> double. 4271defm : UIntToFPROLoadPat<f64, i32, zextloadi16, 4272 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>; 4273def : Pat <(f64 (uint_to_fp (i32 4274 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 4275 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4276 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 4277def : Pat <(f64 (uint_to_fp (i32 4278 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 4279 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4280 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 4281// 32-bits -> double. 4282defm : UIntToFPROLoadPat<f64, i32, load, 4283 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>; 4284def : Pat <(f64 (uint_to_fp (i32 4285 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 4286 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4287 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>; 4288def : Pat <(f64 (uint_to_fp (i32 4289 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), 4290 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4291 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>; 4292// 64-bits -> double are handled in target specific dag combine: 4293// performIntToFpCombine. 4294 4295//===----------------------------------------------------------------------===// 4296// Advanced SIMD three different-sized vector instructions. 4297//===----------------------------------------------------------------------===// 4298 4299defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>; 4300defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>; 4301defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>; 4302defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>; 4303defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>; 4304defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", 4305 int_aarch64_neon_sabd>; 4306defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", 4307 int_aarch64_neon_sabd>; 4308defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl", 4309 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>; 4310defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw", 4311 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>; 4312defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal", 4313 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4314defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl", 4315 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4316defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>; 4317defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", 4318 int_aarch64_neon_sqadd>; 4319defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", 4320 int_aarch64_neon_sqsub>; 4321defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", 4322 int_aarch64_neon_sqdmull>; 4323defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl", 4324 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>; 4325defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw", 4326 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>; 4327defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", 4328 int_aarch64_neon_uabd>; 4329defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl", 4330 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>; 4331defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw", 4332 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>; 4333defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal", 4334 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 4335defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl", 4336 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 4337defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>; 4338defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl", 4339 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>; 4340defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw", 4341 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>; 4342 4343// Additional patterns for SMULL and UMULL 4344multiclass Neon_mul_widen_patterns<SDPatternOperator opnode, 4345 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 4346 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 4347 (INST8B V64:$Rn, V64:$Rm)>; 4348 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 4349 (INST4H V64:$Rn, V64:$Rm)>; 4350 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 4351 (INST2S V64:$Rn, V64:$Rm)>; 4352} 4353 4354defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16, 4355 SMULLv4i16_v4i32, SMULLv2i32_v2i64>; 4356defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16, 4357 UMULLv4i16_v4i32, UMULLv2i32_v2i64>; 4358 4359// Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL 4360multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode, 4361 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 4362 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 4363 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>; 4364 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 4365 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>; 4366 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 4367 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>; 4368} 4369 4370defm : Neon_mulacc_widen_patterns< 4371 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 4372 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>; 4373defm : Neon_mulacc_widen_patterns< 4374 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 4375 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>; 4376defm : Neon_mulacc_widen_patterns< 4377 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 4378 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>; 4379defm : Neon_mulacc_widen_patterns< 4380 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 4381 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>; 4382 4383// Patterns for 64-bit pmull 4384def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm), 4385 (PMULLv1i64 V64:$Rn, V64:$Rm)>; 4386def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)), 4387 (extractelt (v2i64 V128:$Rm), (i64 1))), 4388 (PMULLv2i64 V128:$Rn, V128:$Rm)>; 4389 4390// CodeGen patterns for addhn and subhn instructions, which can actually be 4391// written in LLVM IR without too much difficulty. 4392 4393// ADDHN 4394def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))), 4395 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 4396def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 4397 (i32 16))))), 4398 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 4399def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 4400 (i32 32))))), 4401 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 4402def : Pat<(concat_vectors (v8i8 V64:$Rd), 4403 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), 4404 (i32 8))))), 4405 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4406 V128:$Rn, V128:$Rm)>; 4407def : Pat<(concat_vectors (v4i16 V64:$Rd), 4408 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 4409 (i32 16))))), 4410 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4411 V128:$Rn, V128:$Rm)>; 4412def : Pat<(concat_vectors (v2i32 V64:$Rd), 4413 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 4414 (i32 32))))), 4415 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4416 V128:$Rn, V128:$Rm)>; 4417 4418// SUBHN 4419def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))), 4420 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 4421def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 4422 (i32 16))))), 4423 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 4424def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 4425 (i32 32))))), 4426 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 4427def : Pat<(concat_vectors (v8i8 V64:$Rd), 4428 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 4429 (i32 8))))), 4430 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4431 V128:$Rn, V128:$Rm)>; 4432def : Pat<(concat_vectors (v4i16 V64:$Rd), 4433 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 4434 (i32 16))))), 4435 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4436 V128:$Rn, V128:$Rm)>; 4437def : Pat<(concat_vectors (v2i32 V64:$Rd), 4438 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 4439 (i32 32))))), 4440 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 4441 V128:$Rn, V128:$Rm)>; 4442 4443//---------------------------------------------------------------------------- 4444// AdvSIMD bitwise extract from vector instruction. 4445//---------------------------------------------------------------------------- 4446 4447defm EXT : SIMDBitwiseExtract<"ext">; 4448 4449def AdjustExtImm : SDNodeXForm<imm, [{ 4450 return CurDAG->getTargetConstant(8 + N->getZExtValue(), SDLoc(N), MVT::i32); 4451}]>; 4452multiclass ExtPat<ValueType VT64, ValueType VT128, int N> { 4453 def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 4454 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 4455 def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4456 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4457 // We use EXT to handle extract_subvector to copy the upper 64-bits of a 4458 // 128-bit vector. 4459 def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))), 4460 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4461 // A 64-bit EXT of two halves of the same 128-bit register can be done as a 4462 // single 128-bit EXT. 4463 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)), 4464 (extract_subvector V128:$Rn, (i64 N)), 4465 (i32 imm:$imm))), 4466 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, imm:$imm), dsub)>; 4467 // A 64-bit EXT of the high half of a 128-bit register can be done using a 4468 // 128-bit EXT of the whole register with an adjustment to the immediate. The 4469 // top half of the other operand will be unset, but that doesn't matter as it 4470 // will not be used. 4471 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 N)), 4472 V64:$Rm, 4473 (i32 imm:$imm))), 4474 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, 4475 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 4476 (AdjustExtImm imm:$imm)), dsub)>; 4477} 4478 4479defm : ExtPat<v8i8, v16i8, 8>; 4480defm : ExtPat<v4i16, v8i16, 4>; 4481defm : ExtPat<v4f16, v8f16, 4>; 4482defm : ExtPat<v2i32, v4i32, 2>; 4483defm : ExtPat<v2f32, v4f32, 2>; 4484defm : ExtPat<v1i64, v2i64, 1>; 4485defm : ExtPat<v1f64, v2f64, 1>; 4486 4487//---------------------------------------------------------------------------- 4488// AdvSIMD zip vector 4489//---------------------------------------------------------------------------- 4490 4491defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>; 4492defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>; 4493defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>; 4494defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>; 4495defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>; 4496defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>; 4497 4498//---------------------------------------------------------------------------- 4499// AdvSIMD TBL/TBX instructions 4500//---------------------------------------------------------------------------- 4501 4502defm TBL : SIMDTableLookup< 0, "tbl">; 4503defm TBX : SIMDTableLookupTied<1, "tbx">; 4504 4505def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 4506 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>; 4507def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 4508 (TBLv16i8One V128:$Ri, V128:$Rn)>; 4509 4510def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd), 4511 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 4512 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; 4513def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd), 4514 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 4515 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>; 4516 4517 4518//---------------------------------------------------------------------------- 4519// AdvSIMD scalar CPY instruction 4520//---------------------------------------------------------------------------- 4521 4522defm CPY : SIMDScalarCPY<"cpy">; 4523 4524//---------------------------------------------------------------------------- 4525// AdvSIMD scalar pairwise instructions 4526//---------------------------------------------------------------------------- 4527 4528defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">; 4529defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">; 4530defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">; 4531defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">; 4532defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">; 4533defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">; 4534def : Pat<(v2i64 (AArch64saddv V128:$Rn)), 4535 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 4536def : Pat<(v2i64 (AArch64uaddv V128:$Rn)), 4537 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 4538def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))), 4539 (FADDPv2i32p V64:$Rn)>; 4540def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))), 4541 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>; 4542def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))), 4543 (FADDPv2i64p V128:$Rn)>; 4544def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))), 4545 (FMAXNMPv2i32p V64:$Rn)>; 4546def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))), 4547 (FMAXNMPv2i64p V128:$Rn)>; 4548def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))), 4549 (FMAXPv2i32p V64:$Rn)>; 4550def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))), 4551 (FMAXPv2i64p V128:$Rn)>; 4552def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))), 4553 (FMINNMPv2i32p V64:$Rn)>; 4554def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))), 4555 (FMINNMPv2i64p V128:$Rn)>; 4556def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))), 4557 (FMINPv2i32p V64:$Rn)>; 4558def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))), 4559 (FMINPv2i64p V128:$Rn)>; 4560 4561//---------------------------------------------------------------------------- 4562// AdvSIMD INS/DUP instructions 4563//---------------------------------------------------------------------------- 4564 4565def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>; 4566def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>; 4567def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>; 4568def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>; 4569def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>; 4570def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>; 4571def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>; 4572 4573def DUPv2i64lane : SIMDDup64FromElement; 4574def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>; 4575def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>; 4576def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>; 4577def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>; 4578def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>; 4579def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>; 4580 4581// DUP from a 64-bit register to a 64-bit register is just a copy 4582def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))), 4583 (COPY_TO_REGCLASS GPR64:$Rn, FPR64)>; 4584def : Pat<(v1f64 (AArch64dup (f64 FPR64:$Rn))), 4585 (COPY_TO_REGCLASS FPR64:$Rn, FPR64)>; 4586 4587def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))), 4588 (v2f32 (DUPv2i32lane 4589 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 4590 (i64 0)))>; 4591def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))), 4592 (v4f32 (DUPv4i32lane 4593 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 4594 (i64 0)))>; 4595def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))), 4596 (v2f64 (DUPv2i64lane 4597 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub), 4598 (i64 0)))>; 4599def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))), 4600 (v4f16 (DUPv4i16lane 4601 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 4602 (i64 0)))>; 4603def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))), 4604 (v8f16 (DUPv8i16lane 4605 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 4606 (i64 0)))>; 4607 4608def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 4609 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>; 4610def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 4611 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>; 4612 4613def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 4614 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>; 4615def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 4616 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>; 4617def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)), 4618 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>; 4619 4620// If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane 4621// instruction even if the types don't match: we just have to remap the lane 4622// carefully. N.b. this trick only applies to truncations. 4623def VecIndex_x2 : SDNodeXForm<imm, [{ 4624 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64); 4625}]>; 4626def VecIndex_x4 : SDNodeXForm<imm, [{ 4627 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64); 4628}]>; 4629def VecIndex_x8 : SDNodeXForm<imm, [{ 4630 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64); 4631}]>; 4632 4633multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT, 4634 ValueType Src128VT, ValueType ScalVT, 4635 Instruction DUP, SDNodeXForm IdxXFORM> { 4636 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn), 4637 imm:$idx)))), 4638 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 4639 4640 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn), 4641 imm:$idx)))), 4642 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 4643} 4644 4645defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>; 4646defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>; 4647defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>; 4648 4649defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>; 4650defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>; 4651defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>; 4652 4653multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP, 4654 SDNodeXForm IdxXFORM> { 4655 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn), 4656 imm:$idx))))), 4657 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 4658 4659 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn), 4660 imm:$idx))))), 4661 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 4662} 4663 4664defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>; 4665defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>; 4666defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>; 4667 4668defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>; 4669defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>; 4670defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>; 4671 4672// SMOV and UMOV definitions, with some extra patterns for convenience 4673defm SMOV : SMov; 4674defm UMOV : UMov; 4675 4676def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 4677 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; 4678def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 4679 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 4680def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4681 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 4682def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4683 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 4684def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4685 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 4686def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))), 4687 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>; 4688 4689def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), 4690 VectorIndexB:$idx)))), i8), 4691 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 4692def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), 4693 VectorIndexH:$idx)))), i16), 4694 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 4695 4696// Extracting i8 or i16 elements will have the zero-extend transformed to 4697// an 'and' mask by type legalization since neither i8 nor i16 are legal types 4698// for AArch64. Match these patterns here since UMOV already zeroes out the high 4699// bits of the destination register. 4700def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), 4701 (i32 0xff)), 4702 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>; 4703def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), 4704 (i32 0xffff)), 4705 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>; 4706 4707defm INS : SIMDIns; 4708 4709def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), 4710 (SUBREG_TO_REG (i32 0), 4711 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4712def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), 4713 (SUBREG_TO_REG (i32 0), 4714 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4715 4716def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)), 4717 (SUBREG_TO_REG (i32 0), 4718 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4719def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)), 4720 (SUBREG_TO_REG (i32 0), 4721 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4722 4723def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 4724 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4725def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 4726 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4727 4728def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))), 4729 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 4730 (i32 FPR32:$Rn), ssub))>; 4731def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))), 4732 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4733 (i32 FPR32:$Rn), ssub))>; 4734 4735def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))), 4736 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 4737 (i64 FPR64:$Rn), dsub))>; 4738 4739def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 4740 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4741def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 4742 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4743 4744def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), 4745 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 4746def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), 4747 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 4748 4749def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))), 4750 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>; 4751 4752def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn), 4753 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))), 4754 (EXTRACT_SUBREG 4755 (INSvi16lane 4756 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)), 4757 VectorIndexS:$imm, 4758 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 4759 (i64 0)), 4760 dsub)>; 4761 4762def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn), 4763 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))), 4764 (INSvi16lane 4765 V128:$Rn, VectorIndexH:$imm, 4766 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 4767 (i64 0))>; 4768 4769def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn), 4770 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 4771 (EXTRACT_SUBREG 4772 (INSvi32lane 4773 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)), 4774 VectorIndexS:$imm, 4775 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 4776 (i64 0)), 4777 dsub)>; 4778def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn), 4779 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 4780 (INSvi32lane 4781 V128:$Rn, VectorIndexS:$imm, 4782 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 4783 (i64 0))>; 4784def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn), 4785 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))), 4786 (INSvi64lane 4787 V128:$Rn, VectorIndexD:$imm, 4788 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)), 4789 (i64 0))>; 4790 4791// Copy an element at a constant index in one vector into a constant indexed 4792// element of another. 4793// FIXME refactor to a shared class/dev parameterized on vector type, vector 4794// index type and INS extension 4795def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane 4796 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs), 4797 VectorIndexB:$idx2)), 4798 (v16i8 (INSvi8lane 4799 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2) 4800 )>; 4801def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane 4802 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs), 4803 VectorIndexH:$idx2)), 4804 (v8i16 (INSvi16lane 4805 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2) 4806 )>; 4807def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane 4808 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs), 4809 VectorIndexS:$idx2)), 4810 (v4i32 (INSvi32lane 4811 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2) 4812 )>; 4813def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane 4814 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs), 4815 VectorIndexD:$idx2)), 4816 (v2i64 (INSvi64lane 4817 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2) 4818 )>; 4819 4820multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, 4821 ValueType VTScal, Instruction INS> { 4822 def : Pat<(VT128 (vector_insert V128:$src, 4823 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 4824 imm:$Immd)), 4825 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; 4826 4827 def : Pat<(VT128 (vector_insert V128:$src, 4828 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 4829 imm:$Immd)), 4830 (INS V128:$src, imm:$Immd, 4831 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; 4832 4833 def : Pat<(VT64 (vector_insert V64:$src, 4834 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 4835 imm:$Immd)), 4836 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), 4837 imm:$Immd, V128:$Rn, imm:$Immn), 4838 dsub)>; 4839 4840 def : Pat<(VT64 (vector_insert V64:$src, 4841 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 4842 imm:$Immd)), 4843 (EXTRACT_SUBREG 4844 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, 4845 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), 4846 dsub)>; 4847} 4848 4849defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>; 4850defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>; 4851defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>; 4852 4853 4854// Floating point vector extractions are codegen'd as either a sequence of 4855// subregister extractions, or a MOV (aka CPY here, alias for DUP) if 4856// the lane number is anything other than zero. 4857def : Pat<(vector_extract (v2f64 V128:$Rn), 0), 4858 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>; 4859def : Pat<(vector_extract (v4f32 V128:$Rn), 0), 4860 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>; 4861def : Pat<(vector_extract (v8f16 V128:$Rn), 0), 4862 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>; 4863 4864def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx), 4865 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>; 4866def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx), 4867 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>; 4868def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx), 4869 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; 4870 4871// All concat_vectors operations are canonicalised to act on i64 vectors for 4872// AArch64. In the general case we need an instruction, which had just as well be 4873// INS. 4874class ConcatPat<ValueType DstTy, ValueType SrcTy> 4875 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)), 4876 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1, 4877 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>; 4878 4879def : ConcatPat<v2i64, v1i64>; 4880def : ConcatPat<v2f64, v1f64>; 4881def : ConcatPat<v4i32, v2i32>; 4882def : ConcatPat<v4f32, v2f32>; 4883def : ConcatPat<v8i16, v4i16>; 4884def : ConcatPat<v8f16, v4f16>; 4885def : ConcatPat<v16i8, v8i8>; 4886 4887// If the high lanes are undef, though, we can just ignore them: 4888class ConcatUndefPat<ValueType DstTy, ValueType SrcTy> 4889 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), 4890 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>; 4891 4892def : ConcatUndefPat<v2i64, v1i64>; 4893def : ConcatUndefPat<v2f64, v1f64>; 4894def : ConcatUndefPat<v4i32, v2i32>; 4895def : ConcatUndefPat<v4f32, v2f32>; 4896def : ConcatUndefPat<v8i16, v4i16>; 4897def : ConcatUndefPat<v16i8, v8i8>; 4898 4899//---------------------------------------------------------------------------- 4900// AdvSIMD across lanes instructions 4901//---------------------------------------------------------------------------- 4902 4903defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">; 4904defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">; 4905defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">; 4906defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">; 4907defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">; 4908defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">; 4909defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">; 4910defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>; 4911defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>; 4912defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>; 4913defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>; 4914 4915// Patterns for across-vector intrinsics, that have a node equivalent, that 4916// returns a vector (with only the low lane defined) instead of a scalar. 4917// In effect, opNode is the same as (scalar_to_vector (IntNode)). 4918multiclass SIMDAcrossLanesIntrinsic<string baseOpc, 4919 SDPatternOperator opNode> { 4920// If a lane instruction caught the vector_extract around opNode, we can 4921// directly match the latter to the instruction. 4922def : Pat<(v8i8 (opNode V64:$Rn)), 4923 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 4924 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>; 4925def : Pat<(v16i8 (opNode V128:$Rn)), 4926 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4927 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>; 4928def : Pat<(v4i16 (opNode V64:$Rn)), 4929 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 4930 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>; 4931def : Pat<(v8i16 (opNode V128:$Rn)), 4932 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 4933 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>; 4934def : Pat<(v4i32 (opNode V128:$Rn)), 4935 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4936 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>; 4937 4938 4939// If none did, fallback to the explicit patterns, consuming the vector_extract. 4940def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)), 4941 (i32 0)), (i64 0))), 4942 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 4943 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), 4944 bsub), ssub)>; 4945def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))), 4946 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4947 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), 4948 bsub), ssub)>; 4949def : Pat<(i32 (vector_extract (insert_subvector undef, 4950 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))), 4951 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 4952 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), 4953 hsub), ssub)>; 4954def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))), 4955 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 4956 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), 4957 hsub), ssub)>; 4958def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))), 4959 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4960 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), 4961 ssub), ssub)>; 4962 4963} 4964 4965multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, 4966 SDPatternOperator opNode> 4967 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 4968// If there is a sign extension after this intrinsic, consume it as smov already 4969// performed it 4970def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 4971 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)), 4972 (i32 (SMOVvi8to32 4973 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4974 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 4975 (i64 0)))>; 4976def : Pat<(i32 (sext_inreg (i32 (vector_extract 4977 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)), 4978 (i32 (SMOVvi8to32 4979 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4980 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 4981 (i64 0)))>; 4982def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 4983 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)), 4984 (i32 (SMOVvi16to32 4985 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4986 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 4987 (i64 0)))>; 4988def : Pat<(i32 (sext_inreg (i32 (vector_extract 4989 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)), 4990 (i32 (SMOVvi16to32 4991 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4992 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 4993 (i64 0)))>; 4994} 4995 4996multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, 4997 SDPatternOperator opNode> 4998 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 4999// If there is a masking operation keeping only what has been actually 5000// generated, consume it. 5001def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 5002 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)), 5003 (i32 (EXTRACT_SUBREG 5004 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5005 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 5006 ssub))>; 5007def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))), 5008 maski8_or_more)), 5009 (i32 (EXTRACT_SUBREG 5010 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5011 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 5012 ssub))>; 5013def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 5014 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)), 5015 (i32 (EXTRACT_SUBREG 5016 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5017 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 5018 ssub))>; 5019def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))), 5020 maski16_or_more)), 5021 (i32 (EXTRACT_SUBREG 5022 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5023 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 5024 ssub))>; 5025} 5026 5027defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>; 5028// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5029def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))), 5030 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 5031 5032defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>; 5033// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5034def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))), 5035 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 5036 5037defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>; 5038def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))), 5039 (SMAXPv2i32 V64:$Rn, V64:$Rn)>; 5040 5041defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>; 5042def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))), 5043 (SMINPv2i32 V64:$Rn, V64:$Rn)>; 5044 5045defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>; 5046def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))), 5047 (UMAXPv2i32 V64:$Rn, V64:$Rn)>; 5048 5049defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>; 5050def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))), 5051 (UMINPv2i32 V64:$Rn, V64:$Rn)>; 5052 5053multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> { 5054 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 5055 (i32 (SMOVvi16to32 5056 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5057 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 5058 (i64 0)))>; 5059def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 5060 (i32 (SMOVvi16to32 5061 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5062 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 5063 (i64 0)))>; 5064 5065def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 5066 (i32 (EXTRACT_SUBREG 5067 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5068 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 5069 ssub))>; 5070def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 5071 (i32 (EXTRACT_SUBREG 5072 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5073 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 5074 ssub))>; 5075 5076def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 5077 (i64 (EXTRACT_SUBREG 5078 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5079 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 5080 dsub))>; 5081} 5082 5083multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc, 5084 Intrinsic intOp> { 5085 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 5086 (i32 (EXTRACT_SUBREG 5087 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5088 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 5089 ssub))>; 5090def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 5091 (i32 (EXTRACT_SUBREG 5092 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5093 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 5094 ssub))>; 5095 5096def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 5097 (i32 (EXTRACT_SUBREG 5098 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5099 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 5100 ssub))>; 5101def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 5102 (i32 (EXTRACT_SUBREG 5103 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5104 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 5105 ssub))>; 5106 5107def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 5108 (i64 (EXTRACT_SUBREG 5109 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5110 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 5111 dsub))>; 5112} 5113 5114defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>; 5115defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>; 5116 5117// The vaddlv_s32 intrinsic gets mapped to SADDLP. 5118def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))), 5119 (i64 (EXTRACT_SUBREG 5120 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5121 (SADDLPv2i32_v1i64 V64:$Rn), dsub), 5122 dsub))>; 5123// The vaddlv_u32 intrinsic gets mapped to UADDLP. 5124def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))), 5125 (i64 (EXTRACT_SUBREG 5126 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5127 (UADDLPv2i32_v1i64 V64:$Rn), dsub), 5128 dsub))>; 5129 5130//------------------------------------------------------------------------------ 5131// AdvSIMD modified immediate instructions 5132//------------------------------------------------------------------------------ 5133 5134// AdvSIMD BIC 5135defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; 5136// AdvSIMD ORR 5137defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; 5138 5139def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5140def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5141def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5142def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5143 5144def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5145def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5146def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5147def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5148 5149def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5150def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5151def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5152def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5153 5154def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5155def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5156def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5157def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5158 5159// AdvSIMD FMOV 5160def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, 5161 "fmov", ".2d", 5162 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5163def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8, 5164 "fmov", ".2s", 5165 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5166def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8, 5167 "fmov", ".4s", 5168 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5169let Predicates = [HasNEON, HasFullFP16] in { 5170def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8, 5171 "fmov", ".4h", 5172 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5173def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8, 5174 "fmov", ".8h", 5175 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5176} // Predicates = [HasNEON, HasFullFP16] 5177 5178// AdvSIMD MOVI 5179 5180// EDIT byte mask: scalar 5181let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5182def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi", 5183 [(set FPR64:$Rd, simdimmtype10:$imm8)]>; 5184// The movi_edit node has the immediate value already encoded, so we use 5185// a plain imm0_255 here. 5186def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)), 5187 (MOVID imm0_255:$shift)>; 5188 5189// EDIT byte mask: 2d 5190 5191// The movi_edit node has the immediate value already encoded, so we use 5192// a plain imm0_255 in the pattern 5193let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5194def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128, 5195 simdimmtype10, 5196 "movi", ".2d", 5197 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>; 5198 5199def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5200def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5201def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5202def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5203 5204def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; 5205def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>; 5206def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>; 5207def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>; 5208 5209// Set 64-bit vectors to all 0/1 by extracting from a 128-bit register as the 5210// extract is free and this gives better MachineCSE results. 5211def : Pat<(v1i64 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 5212def : Pat<(v2i32 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 5213def : Pat<(v4i16 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 5214def : Pat<(v8i8 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 5215 5216def : Pat<(v1i64 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 5217def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 5218def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 5219def : Pat<(v8i8 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 5220 5221// EDIT per word & halfword: 2s, 4h, 4s, & 8h 5222let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5223defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; 5224 5225def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 5226def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 5227def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 5228def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 5229 5230def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 5231def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 5232def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 5233def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 5234 5235def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 5236 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; 5237def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 5238 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>; 5239def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 5240 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>; 5241def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 5242 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>; 5243 5244let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 5245// EDIT per word: 2s & 4s with MSL shifter 5246def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", 5247 [(set (v2i32 V64:$Rd), 5248 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 5249def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", 5250 [(set (v4i32 V128:$Rd), 5251 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 5252 5253// Per byte: 8b & 16b 5254def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255, 5255 "movi", ".8b", 5256 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>; 5257 5258def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, 5259 "movi", ".16b", 5260 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>; 5261} 5262 5263// AdvSIMD MVNI 5264 5265// EDIT per word & halfword: 2s, 4h, 4s, & 8h 5266let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5267defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; 5268 5269def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 5270def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 5271def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 5272def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 5273 5274def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 5275def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 5276def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 5277def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 5278 5279def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 5280 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; 5281def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 5282 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>; 5283def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 5284 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>; 5285def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 5286 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>; 5287 5288// EDIT per word: 2s & 4s with MSL shifter 5289let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 5290def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", 5291 [(set (v2i32 V64:$Rd), 5292 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 5293def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", 5294 [(set (v4i32 V128:$Rd), 5295 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 5296} 5297 5298//---------------------------------------------------------------------------- 5299// AdvSIMD indexed element 5300//---------------------------------------------------------------------------- 5301 5302let hasSideEffects = 0 in { 5303 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">; 5304 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">; 5305} 5306 5307// NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the 5308// instruction expects the addend first, while the intrinsic expects it last. 5309 5310// On the other hand, there are quite a few valid combinatorial options due to 5311// the commutativity of multiplication and the fact that (-x) * y = x * (-y). 5312defm : SIMDFPIndexedTiedPatterns<"FMLA", 5313 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>; 5314defm : SIMDFPIndexedTiedPatterns<"FMLA", 5315 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>; 5316 5317defm : SIMDFPIndexedTiedPatterns<"FMLS", 5318 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 5319defm : SIMDFPIndexedTiedPatterns<"FMLS", 5320 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >; 5321defm : SIMDFPIndexedTiedPatterns<"FMLS", 5322 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >; 5323defm : SIMDFPIndexedTiedPatterns<"FMLS", 5324 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >; 5325 5326multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> { 5327 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit 5328 // and DUP scalar. 5329 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 5330 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 5331 VectorIndexS:$idx))), 5332 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; 5333 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 5334 (v2f32 (AArch64duplane32 5335 (v4f32 (insert_subvector undef, 5336 (v2f32 (fneg V64:$Rm)), 5337 (i32 0))), 5338 VectorIndexS:$idx)))), 5339 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 5340 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 5341 VectorIndexS:$idx)>; 5342 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 5343 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 5344 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 5345 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 5346 5347 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit 5348 // and DUP scalar. 5349 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 5350 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 5351 VectorIndexS:$idx))), 5352 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm, 5353 VectorIndexS:$idx)>; 5354 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 5355 (v4f32 (AArch64duplane32 5356 (v4f32 (insert_subvector undef, 5357 (v2f32 (fneg V64:$Rm)), 5358 (i32 0))), 5359 VectorIndexS:$idx)))), 5360 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 5361 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 5362 VectorIndexS:$idx)>; 5363 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 5364 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 5365 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 5366 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 5367 5368 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar 5369 // (DUPLANE from 64-bit would be trivial). 5370 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 5371 (AArch64duplane64 (v2f64 (fneg V128:$Rm)), 5372 VectorIndexD:$idx))), 5373 (FMLSv2i64_indexed 5374 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; 5375 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 5376 (AArch64dup (f64 (fneg FPR64Op:$Rm))))), 5377 (FMLSv2i64_indexed V128:$Rd, V128:$Rn, 5378 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; 5379 5380 // 2 variants for 32-bit scalar version: extract from .2s or from .4s 5381 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 5382 (vector_extract (v4f32 (fneg V128:$Rm)), 5383 VectorIndexS:$idx))), 5384 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 5385 V128:$Rm, VectorIndexS:$idx)>; 5386 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 5387 (vector_extract (v4f32 (insert_subvector undef, 5388 (v2f32 (fneg V64:$Rm)), 5389 (i32 0))), 5390 VectorIndexS:$idx))), 5391 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 5392 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; 5393 5394 // 1 variant for 64-bit scalar version: extract from .1d or from .2d 5395 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), 5396 (vector_extract (v2f64 (fneg V128:$Rm)), 5397 VectorIndexS:$idx))), 5398 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn, 5399 V128:$Rm, VectorIndexS:$idx)>; 5400} 5401 5402defm : FMLSIndexedAfterNegPatterns< 5403 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 5404defm : FMLSIndexedAfterNegPatterns< 5405 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >; 5406 5407defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>; 5408defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>; 5409 5410def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 5411 (FMULv2i32_indexed V64:$Rn, 5412 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 5413 (i64 0))>; 5414def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 5415 (FMULv4i32_indexed V128:$Rn, 5416 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 5417 (i64 0))>; 5418def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))), 5419 (FMULv2i64_indexed V128:$Rn, 5420 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub), 5421 (i64 0))>; 5422 5423defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>; 5424defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 5425defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", 5426 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>; 5427defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls", 5428 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>; 5429defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>; 5430defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal", 5431 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 5432defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl", 5433 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 5434defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", 5435 int_aarch64_neon_smull>; 5436defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal", 5437 int_aarch64_neon_sqadd>; 5438defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl", 5439 int_aarch64_neon_sqsub>; 5440defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah", 5441 int_aarch64_neon_sqadd>; 5442defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh", 5443 int_aarch64_neon_sqsub>; 5444defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>; 5445defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal", 5446 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 5447defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl", 5448 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 5449defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull", 5450 int_aarch64_neon_umull>; 5451 5452// A scalar sqdmull with the second operand being a vector lane can be 5453// handled directly with the indexed instruction encoding. 5454def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 5455 (vector_extract (v4i32 V128:$Vm), 5456 VectorIndexS:$idx)), 5457 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>; 5458 5459//---------------------------------------------------------------------------- 5460// AdvSIMD scalar shift instructions 5461//---------------------------------------------------------------------------- 5462defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">; 5463defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">; 5464defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; 5465defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">; 5466// Codegen patterns for the above. We don't put these directly on the 5467// instructions because TableGen's type inference can't handle the truth. 5468// Having the same base pattern for fp <--> int totally freaks it out. 5469def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm), 5470 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>; 5471def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm), 5472 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>; 5473def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)), 5474 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 5475def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)), 5476 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 5477def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn), 5478 vecshiftR64:$imm)), 5479 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 5480def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn), 5481 vecshiftR64:$imm)), 5482 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 5483def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm), 5484 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 5485def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 5486 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5487def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn), 5488 vecshiftR64:$imm)), 5489 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5490def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 5491 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5492def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn), 5493 vecshiftR64:$imm)), 5494 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5495def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm), 5496 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 5497 5498// Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported. 5499 5500def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)), 5501 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5502def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)), 5503 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5504def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), 5505 (SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; 5506def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp 5507 (and FPR32:$Rn, (i32 65535)), 5508 vecshiftR16:$imm)), 5509 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5510def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)), 5511 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5512def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), 5513 (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; 5514def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)), 5515 (i32 (INSERT_SUBREG 5516 (i32 (IMPLICIT_DEF)), 5517 (FCVTZSh FPR16:$Rn, vecshiftR32:$imm), 5518 hsub))>; 5519def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)), 5520 (i64 (INSERT_SUBREG 5521 (i64 (IMPLICIT_DEF)), 5522 (FCVTZSh FPR16:$Rn, vecshiftR64:$imm), 5523 hsub))>; 5524def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)), 5525 (i32 (INSERT_SUBREG 5526 (i32 (IMPLICIT_DEF)), 5527 (FCVTZUh FPR16:$Rn, vecshiftR32:$imm), 5528 hsub))>; 5529def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)), 5530 (i64 (INSERT_SUBREG 5531 (i64 (IMPLICIT_DEF)), 5532 (FCVTZUh FPR16:$Rn, vecshiftR64:$imm), 5533 hsub))>; 5534def : Pat<(i32 (int_aarch64_neon_facge (f16 FPR16:$Rn), (f16 FPR16:$Rm))), 5535 (i32 (INSERT_SUBREG 5536 (i32 (IMPLICIT_DEF)), 5537 (FACGE16 FPR16:$Rn, FPR16:$Rm), 5538 hsub))>; 5539def : Pat<(i32 (int_aarch64_neon_facgt (f16 FPR16:$Rn), (f16 FPR16:$Rm))), 5540 (i32 (INSERT_SUBREG 5541 (i32 (IMPLICIT_DEF)), 5542 (FACGT16 FPR16:$Rn, FPR16:$Rm), 5543 hsub))>; 5544 5545defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>; 5546defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">; 5547defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn", 5548 int_aarch64_neon_sqrshrn>; 5549defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun", 5550 int_aarch64_neon_sqrshrun>; 5551defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 5552defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 5553defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn", 5554 int_aarch64_neon_sqshrn>; 5555defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun", 5556 int_aarch64_neon_sqshrun>; 5557defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">; 5558defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>; 5559defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra", 5560 TriOpFrag<(add node:$LHS, 5561 (AArch64srshri node:$MHS, node:$RHS))>>; 5562defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>; 5563defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra", 5564 TriOpFrag<(add node:$LHS, 5565 (AArch64vashr node:$MHS, node:$RHS))>>; 5566defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn", 5567 int_aarch64_neon_uqrshrn>; 5568defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 5569defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn", 5570 int_aarch64_neon_uqshrn>; 5571defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>; 5572defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra", 5573 TriOpFrag<(add node:$LHS, 5574 (AArch64urshri node:$MHS, node:$RHS))>>; 5575defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>; 5576defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra", 5577 TriOpFrag<(add node:$LHS, 5578 (AArch64vlshr node:$MHS, node:$RHS))>>; 5579 5580//---------------------------------------------------------------------------- 5581// AdvSIMD vector shift instructions 5582//---------------------------------------------------------------------------- 5583defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>; 5584defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>; 5585defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", 5586 int_aarch64_neon_vcvtfxs2fp>; 5587defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", 5588 int_aarch64_neon_rshrn>; 5589defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>; 5590defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn", 5591 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>; 5592defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>; 5593def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 5594 (i32 vecshiftL64:$imm))), 5595 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>; 5596defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn", 5597 int_aarch64_neon_sqrshrn>; 5598defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun", 5599 int_aarch64_neon_sqrshrun>; 5600defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 5601defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 5602defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn", 5603 int_aarch64_neon_sqshrn>; 5604defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun", 5605 int_aarch64_neon_sqshrun>; 5606defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>; 5607def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 5608 (i32 vecshiftR64:$imm))), 5609 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>; 5610defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>; 5611defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra", 5612 TriOpFrag<(add node:$LHS, 5613 (AArch64srshri node:$MHS, node:$RHS))> >; 5614defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll", 5615 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>; 5616 5617defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>; 5618defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra", 5619 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>; 5620defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf", 5621 int_aarch64_neon_vcvtfxu2fp>; 5622defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn", 5623 int_aarch64_neon_uqrshrn>; 5624defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 5625defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn", 5626 int_aarch64_neon_uqshrn>; 5627defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>; 5628defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra", 5629 TriOpFrag<(add node:$LHS, 5630 (AArch64urshri node:$MHS, node:$RHS))> >; 5631defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll", 5632 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>; 5633defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>; 5634defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra", 5635 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >; 5636 5637// SHRN patterns for when a logical right shift was used instead of arithmetic 5638// (the immediate guarantees no sign bits actually end up in the result so it 5639// doesn't matter). 5640def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))), 5641 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>; 5642def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))), 5643 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>; 5644def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))), 5645 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>; 5646 5647def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd), 5648 (trunc (AArch64vlshr (v8i16 V128:$Rn), 5649 vecshiftR16Narrow:$imm)))), 5650 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5651 V128:$Rn, vecshiftR16Narrow:$imm)>; 5652def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd), 5653 (trunc (AArch64vlshr (v4i32 V128:$Rn), 5654 vecshiftR32Narrow:$imm)))), 5655 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5656 V128:$Rn, vecshiftR32Narrow:$imm)>; 5657def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd), 5658 (trunc (AArch64vlshr (v2i64 V128:$Rn), 5659 vecshiftR64Narrow:$imm)))), 5660 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5661 V128:$Rn, vecshiftR32Narrow:$imm)>; 5662 5663// Vector sign and zero extensions are implemented with SSHLL and USSHLL. 5664// Anyexts are implemented as zexts. 5665def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>; 5666def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 5667def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 5668def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>; 5669def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 5670def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 5671def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>; 5672def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 5673def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 5674// Also match an extend from the upper half of a 128 bit source register. 5675def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5676 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 5677def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5678 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 5679def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5680 (SSHLLv16i8_shift V128:$Rn, (i32 0))>; 5681def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5682 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 5683def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5684 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 5685def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5686 (SSHLLv8i16_shift V128:$Rn, (i32 0))>; 5687def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5688 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 5689def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5690 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 5691def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5692 (SSHLLv4i32_shift V128:$Rn, (i32 0))>; 5693 5694// Vector shift sxtl aliases 5695def : InstAlias<"sxtl.8h $dst, $src1", 5696 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5697def : InstAlias<"sxtl $dst.8h, $src1.8b", 5698 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5699def : InstAlias<"sxtl.4s $dst, $src1", 5700 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5701def : InstAlias<"sxtl $dst.4s, $src1.4h", 5702 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5703def : InstAlias<"sxtl.2d $dst, $src1", 5704 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5705def : InstAlias<"sxtl $dst.2d, $src1.2s", 5706 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5707 5708// Vector shift sxtl2 aliases 5709def : InstAlias<"sxtl2.8h $dst, $src1", 5710 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5711def : InstAlias<"sxtl2 $dst.8h, $src1.16b", 5712 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5713def : InstAlias<"sxtl2.4s $dst, $src1", 5714 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5715def : InstAlias<"sxtl2 $dst.4s, $src1.8h", 5716 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5717def : InstAlias<"sxtl2.2d $dst, $src1", 5718 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5719def : InstAlias<"sxtl2 $dst.2d, $src1.4s", 5720 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5721 5722// Vector shift uxtl aliases 5723def : InstAlias<"uxtl.8h $dst, $src1", 5724 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5725def : InstAlias<"uxtl $dst.8h, $src1.8b", 5726 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5727def : InstAlias<"uxtl.4s $dst, $src1", 5728 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5729def : InstAlias<"uxtl $dst.4s, $src1.4h", 5730 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5731def : InstAlias<"uxtl.2d $dst, $src1", 5732 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5733def : InstAlias<"uxtl $dst.2d, $src1.2s", 5734 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5735 5736// Vector shift uxtl2 aliases 5737def : InstAlias<"uxtl2.8h $dst, $src1", 5738 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5739def : InstAlias<"uxtl2 $dst.8h, $src1.16b", 5740 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5741def : InstAlias<"uxtl2.4s $dst, $src1", 5742 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5743def : InstAlias<"uxtl2 $dst.4s, $src1.8h", 5744 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5745def : InstAlias<"uxtl2.2d $dst, $src1", 5746 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5747def : InstAlias<"uxtl2 $dst.2d, $src1.4s", 5748 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5749 5750// If an integer is about to be converted to a floating point value, 5751// just load it on the floating point unit. 5752// These patterns are more complex because floating point loads do not 5753// support sign extension. 5754// The sign extension has to be explicitly added and is only supported for 5755// one step: byte-to-half, half-to-word, word-to-doubleword. 5756// SCVTF GPR -> FPR is 9 cycles. 5757// SCVTF FPR -> FPR is 4 cyclces. 5758// (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles. 5759// Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR 5760// and still being faster. 5761// However, this is not good for code size. 5762// 8-bits -> float. 2 sizes step-up. 5763class SExtLoadi8CVTf32Pat<dag addrmode, dag INST> 5764 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))), 5765 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 5766 (SSHLLv4i16_shift 5767 (f64 5768 (EXTRACT_SUBREG 5769 (SSHLLv8i8_shift 5770 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5771 INST, 5772 bsub), 5773 0), 5774 dsub)), 5775 0), 5776 ssub)))>, 5777 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 5778 5779def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), 5780 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; 5781def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext), 5782 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>; 5783def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), 5784 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>; 5785def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset), 5786 (LDURBi GPR64sp:$Rn, simm9:$offset)>; 5787 5788// 16-bits -> float. 1 size step-up. 5789class SExtLoadi16CVTf32Pat<dag addrmode, dag INST> 5790 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))), 5791 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 5792 (SSHLLv4i16_shift 5793 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5794 INST, 5795 hsub), 5796 0), 5797 ssub)))>, Requires<[NotForCodeSize]>; 5798 5799def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 5800 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 5801def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 5802 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 5803def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 5804 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 5805def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 5806 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 5807 5808// 32-bits to 32-bits are handled in target specific dag combine: 5809// performIntToFpCombine. 5810// 64-bits integer to 32-bits floating point, not possible with 5811// SCVTF on floating point registers (both source and destination 5812// must have the same size). 5813 5814// Here are the patterns for 8, 16, 32, and 64-bits to double. 5815// 8-bits -> double. 3 size step-up: give up. 5816// 16-bits -> double. 2 size step. 5817class SExtLoadi16CVTf64Pat<dag addrmode, dag INST> 5818 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))), 5819 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 5820 (SSHLLv2i32_shift 5821 (f64 5822 (EXTRACT_SUBREG 5823 (SSHLLv4i16_shift 5824 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5825 INST, 5826 hsub), 5827 0), 5828 dsub)), 5829 0), 5830 dsub)))>, 5831 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 5832 5833def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 5834 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 5835def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 5836 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 5837def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 5838 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 5839def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 5840 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 5841// 32-bits -> double. 1 size step-up. 5842class SExtLoadi32CVTf64Pat<dag addrmode, dag INST> 5843 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))), 5844 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 5845 (SSHLLv2i32_shift 5846 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5847 INST, 5848 ssub), 5849 0), 5850 dsub)))>, Requires<[NotForCodeSize]>; 5851 5852def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext), 5853 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>; 5854def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext), 5855 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>; 5856def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), 5857 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>; 5858def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset), 5859 (LDURSi GPR64sp:$Rn, simm9:$offset)>; 5860 5861// 64-bits -> double are handled in target specific dag combine: 5862// performIntToFpCombine. 5863 5864 5865//---------------------------------------------------------------------------- 5866// AdvSIMD Load-Store Structure 5867//---------------------------------------------------------------------------- 5868defm LD1 : SIMDLd1Multiple<"ld1">; 5869defm LD2 : SIMDLd2Multiple<"ld2">; 5870defm LD3 : SIMDLd3Multiple<"ld3">; 5871defm LD4 : SIMDLd4Multiple<"ld4">; 5872 5873defm ST1 : SIMDSt1Multiple<"st1">; 5874defm ST2 : SIMDSt2Multiple<"st2">; 5875defm ST3 : SIMDSt3Multiple<"st3">; 5876defm ST4 : SIMDSt4Multiple<"st4">; 5877 5878class Ld1Pat<ValueType ty, Instruction INST> 5879 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>; 5880 5881def : Ld1Pat<v16i8, LD1Onev16b>; 5882def : Ld1Pat<v8i16, LD1Onev8h>; 5883def : Ld1Pat<v4i32, LD1Onev4s>; 5884def : Ld1Pat<v2i64, LD1Onev2d>; 5885def : Ld1Pat<v8i8, LD1Onev8b>; 5886def : Ld1Pat<v4i16, LD1Onev4h>; 5887def : Ld1Pat<v2i32, LD1Onev2s>; 5888def : Ld1Pat<v1i64, LD1Onev1d>; 5889 5890class St1Pat<ValueType ty, Instruction INST> 5891 : Pat<(store ty:$Vt, GPR64sp:$Rn), 5892 (INST ty:$Vt, GPR64sp:$Rn)>; 5893 5894def : St1Pat<v16i8, ST1Onev16b>; 5895def : St1Pat<v8i16, ST1Onev8h>; 5896def : St1Pat<v4i32, ST1Onev4s>; 5897def : St1Pat<v2i64, ST1Onev2d>; 5898def : St1Pat<v8i8, ST1Onev8b>; 5899def : St1Pat<v4i16, ST1Onev4h>; 5900def : St1Pat<v2i32, ST1Onev2s>; 5901def : St1Pat<v1i64, ST1Onev1d>; 5902 5903//--- 5904// Single-element 5905//--- 5906 5907defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>; 5908defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>; 5909defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>; 5910defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>; 5911let mayLoad = 1, hasSideEffects = 0 in { 5912defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>; 5913defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>; 5914defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>; 5915defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>; 5916defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>; 5917defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>; 5918defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>; 5919defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>; 5920defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>; 5921defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>; 5922defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>; 5923defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>; 5924defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>; 5925defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>; 5926defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>; 5927defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>; 5928} 5929 5930def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 5931 (LD1Rv8b GPR64sp:$Rn)>; 5932def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 5933 (LD1Rv16b GPR64sp:$Rn)>; 5934def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 5935 (LD1Rv4h GPR64sp:$Rn)>; 5936def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 5937 (LD1Rv8h GPR64sp:$Rn)>; 5938def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 5939 (LD1Rv2s GPR64sp:$Rn)>; 5940def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 5941 (LD1Rv4s GPR64sp:$Rn)>; 5942def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 5943 (LD1Rv2d GPR64sp:$Rn)>; 5944def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 5945 (LD1Rv1d GPR64sp:$Rn)>; 5946// Grab the floating point version too 5947def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 5948 (LD1Rv2s GPR64sp:$Rn)>; 5949def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 5950 (LD1Rv4s GPR64sp:$Rn)>; 5951def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 5952 (LD1Rv2d GPR64sp:$Rn)>; 5953def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 5954 (LD1Rv1d GPR64sp:$Rn)>; 5955def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 5956 (LD1Rv4h GPR64sp:$Rn)>; 5957def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 5958 (LD1Rv8h GPR64sp:$Rn)>; 5959 5960class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex, 5961 ValueType VTy, ValueType STy, Instruction LD1> 5962 : Pat<(vector_insert (VTy VecListOne128:$Rd), 5963 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 5964 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; 5965 5966def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>; 5967def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>; 5968def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>; 5969def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>; 5970def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>; 5971def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>; 5972def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>; 5973 5974class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex, 5975 ValueType VTy, ValueType STy, Instruction LD1> 5976 : Pat<(vector_insert (VTy VecListOne64:$Rd), 5977 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 5978 (EXTRACT_SUBREG 5979 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), 5980 VecIndex:$idx, GPR64sp:$Rn), 5981 dsub)>; 5982 5983def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>; 5984def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>; 5985def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>; 5986def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>; 5987def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>; 5988 5989 5990defm LD1 : SIMDLdSt1SingleAliases<"ld1">; 5991defm LD2 : SIMDLdSt2SingleAliases<"ld2">; 5992defm LD3 : SIMDLdSt3SingleAliases<"ld3">; 5993defm LD4 : SIMDLdSt4SingleAliases<"ld4">; 5994 5995// Stores 5996defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>; 5997defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>; 5998defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>; 5999defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>; 6000 6001let AddedComplexity = 19 in 6002class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex, 6003 ValueType VTy, ValueType STy, Instruction ST1> 6004 : Pat<(scalar_store 6005 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6006 GPR64sp:$Rn), 6007 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>; 6008 6009def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>; 6010def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>; 6011def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>; 6012def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>; 6013def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>; 6014def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>; 6015def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>; 6016 6017let AddedComplexity = 19 in 6018class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex, 6019 ValueType VTy, ValueType STy, Instruction ST1> 6020 : Pat<(scalar_store 6021 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6022 GPR64sp:$Rn), 6023 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6024 VecIndex:$idx, GPR64sp:$Rn)>; 6025 6026def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>; 6027def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>; 6028def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>; 6029def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>; 6030def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>; 6031 6032multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex, 6033 ValueType VTy, ValueType STy, Instruction ST1, 6034 int offset> { 6035 def : Pat<(scalar_store 6036 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6037 GPR64sp:$Rn, offset), 6038 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6039 VecIndex:$idx, GPR64sp:$Rn, XZR)>; 6040 6041 def : Pat<(scalar_store 6042 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6043 GPR64sp:$Rn, GPR64:$Rm), 6044 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6045 VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 6046} 6047 6048defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>; 6049defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST, 6050 2>; 6051defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>; 6052defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>; 6053defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>; 6054defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>; 6055defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>; 6056 6057multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex, 6058 ValueType VTy, ValueType STy, Instruction ST1, 6059 int offset> { 6060 def : Pat<(scalar_store 6061 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6062 GPR64sp:$Rn, offset), 6063 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>; 6064 6065 def : Pat<(scalar_store 6066 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6067 GPR64sp:$Rn, GPR64:$Rm), 6068 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 6069} 6070 6071defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST, 6072 1>; 6073defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST, 6074 2>; 6075defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>; 6076defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>; 6077defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>; 6078defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>; 6079defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>; 6080 6081let mayStore = 1, hasSideEffects = 0 in { 6082defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>; 6083defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>; 6084defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>; 6085defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>; 6086defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>; 6087defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>; 6088defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>; 6089defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>; 6090defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>; 6091defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>; 6092defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>; 6093defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>; 6094} 6095 6096defm ST1 : SIMDLdSt1SingleAliases<"st1">; 6097defm ST2 : SIMDLdSt2SingleAliases<"st2">; 6098defm ST3 : SIMDLdSt3SingleAliases<"st3">; 6099defm ST4 : SIMDLdSt4SingleAliases<"st4">; 6100 6101//---------------------------------------------------------------------------- 6102// Crypto extensions 6103//---------------------------------------------------------------------------- 6104 6105let Predicates = [HasAES] in { 6106def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>; 6107def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>; 6108def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>; 6109def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; 6110} 6111 6112// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required 6113// for AES fusion on some CPUs. 6114let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 6115def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 6116 Sched<[WriteV]>; 6117def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 6118 Sched<[WriteV]>; 6119} 6120 6121// Only use constrained versions of AES(I)MC instructions if they are paired with 6122// AESE/AESD. 6123def : Pat<(v16i8 (int_aarch64_crypto_aesmc 6124 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1), 6125 (v16i8 V128:$src2))))), 6126 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1), 6127 (v16i8 V128:$src2)))))>, 6128 Requires<[HasFuseAES]>; 6129 6130def : Pat<(v16i8 (int_aarch64_crypto_aesimc 6131 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1), 6132 (v16i8 V128:$src2))))), 6133 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1), 6134 (v16i8 V128:$src2)))))>, 6135 Requires<[HasFuseAES]>; 6136 6137let Predicates = [HasSHA2] in { 6138def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>; 6139def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>; 6140def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>; 6141def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>; 6142def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>; 6143def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>; 6144def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>; 6145 6146def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>; 6147def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>; 6148def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>; 6149} 6150 6151//---------------------------------------------------------------------------- 6152// Compiler-pseudos 6153//---------------------------------------------------------------------------- 6154// FIXME: Like for X86, these should go in their own separate .td file. 6155 6156def def32 : PatLeaf<(i32 GPR32:$src), [{ 6157 return isDef32(*N); 6158}]>; 6159 6160// In the case of a 32-bit def that is known to implicitly zero-extend, 6161// we can use a SUBREG_TO_REG. 6162def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>; 6163 6164// For an anyext, we don't care what the high bits are, so we can perform an 6165// INSERT_SUBREF into an IMPLICIT_DEF. 6166def : Pat<(i64 (anyext GPR32:$src)), 6167 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 6168 6169// When we need to explicitly zero-extend, we use a 32-bit MOV instruction and 6170// then assert the extension has happened. 6171def : Pat<(i64 (zext GPR32:$src)), 6172 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; 6173 6174// To sign extend, we use a signed bitfield move instruction (SBFM) on the 6175// containing super-reg. 6176def : Pat<(i64 (sext GPR32:$src)), 6177 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>; 6178def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>; 6179def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>; 6180def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>; 6181def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>; 6182def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>; 6183def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>; 6184def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>; 6185 6186def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)), 6187 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 6188 (i64 (i32shift_sext_i8 imm0_31:$imm)))>; 6189def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)), 6190 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 6191 (i64 (i64shift_sext_i8 imm0_63:$imm)))>; 6192 6193def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)), 6194 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 6195 (i64 (i32shift_sext_i16 imm0_31:$imm)))>; 6196def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)), 6197 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 6198 (i64 (i64shift_sext_i16 imm0_63:$imm)))>; 6199 6200def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)), 6201 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 6202 (i64 (i64shift_a imm0_63:$imm)), 6203 (i64 (i64shift_sext_i32 imm0_63:$imm)))>; 6204 6205// sra patterns have an AddedComplexity of 10, so make sure we have a higher 6206// AddedComplexity for the following patterns since we want to match sext + sra 6207// patterns before we attempt to match a single sra node. 6208let AddedComplexity = 20 in { 6209// We support all sext + sra combinations which preserve at least one bit of the 6210// original value which is to be sign extended. E.g. we support shifts up to 6211// bitwidth-1 bits. 6212def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)), 6213 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>; 6214def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)), 6215 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>; 6216 6217def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)), 6218 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>; 6219def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)), 6220 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>; 6221 6222def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)), 6223 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 6224 (i64 imm0_31:$imm), 31)>; 6225} // AddedComplexity = 20 6226 6227// To truncate, we can simply extract from a subregister. 6228def : Pat<(i32 (trunc GPR64sp:$src)), 6229 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>; 6230 6231// __builtin_trap() uses the BRK instruction on AArch64. 6232def : Pat<(trap), (BRK 1)>; 6233def : Pat<(debugtrap), (BRK 0xF000)>, Requires<[IsWindows]>; 6234 6235// Multiply high patterns which multiply the lower subvector using smull/umull 6236// and the upper subvector with smull2/umull2. Then shuffle the high the high 6237// part of both results together. 6238def : Pat<(v16i8 (mulhs V128:$Rn, V128:$Rm)), 6239 (UZP2v16i8 6240 (SMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub), 6241 (EXTRACT_SUBREG V128:$Rm, dsub)), 6242 (SMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>; 6243def : Pat<(v8i16 (mulhs V128:$Rn, V128:$Rm)), 6244 (UZP2v8i16 6245 (SMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub), 6246 (EXTRACT_SUBREG V128:$Rm, dsub)), 6247 (SMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>; 6248def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)), 6249 (UZP2v4i32 6250 (SMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub), 6251 (EXTRACT_SUBREG V128:$Rm, dsub)), 6252 (SMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>; 6253 6254def : Pat<(v16i8 (mulhu V128:$Rn, V128:$Rm)), 6255 (UZP2v16i8 6256 (UMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub), 6257 (EXTRACT_SUBREG V128:$Rm, dsub)), 6258 (UMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>; 6259def : Pat<(v8i16 (mulhu V128:$Rn, V128:$Rm)), 6260 (UZP2v8i16 6261 (UMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub), 6262 (EXTRACT_SUBREG V128:$Rm, dsub)), 6263 (UMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>; 6264def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)), 6265 (UZP2v4i32 6266 (UMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub), 6267 (EXTRACT_SUBREG V128:$Rm, dsub)), 6268 (UMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>; 6269 6270// Conversions within AdvSIMD types in the same register size are free. 6271// But because we need a consistent lane ordering, in big endian many 6272// conversions require one or more REV instructions. 6273// 6274// Consider a simple memory load followed by a bitconvert then a store. 6275// v0 = load v2i32 6276// v1 = BITCAST v2i32 v0 to v4i16 6277// store v4i16 v2 6278// 6279// In big endian mode every memory access has an implicit byte swap. LDR and 6280// STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that 6281// is, they treat the vector as a sequence of elements to be byte-swapped. 6282// The two pairs of instructions are fundamentally incompatible. We've decided 6283// to use LD1/ST1 only to simplify compiler implementation. 6284// 6285// LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes 6286// the original code sequence: 6287// v0 = load v2i32 6288// v1 = REV v2i32 (implicit) 6289// v2 = BITCAST v2i32 v1 to v4i16 6290// v3 = REV v4i16 v2 (implicit) 6291// store v4i16 v3 6292// 6293// But this is now broken - the value stored is different to the value loaded 6294// due to lane reordering. To fix this, on every BITCAST we must perform two 6295// other REVs: 6296// v0 = load v2i32 6297// v1 = REV v2i32 (implicit) 6298// v2 = REV v2i32 6299// v3 = BITCAST v2i32 v2 to v4i16 6300// v4 = REV v4i16 6301// v5 = REV v4i16 v4 (implicit) 6302// store v4i16 v5 6303// 6304// This means an extra two instructions, but actually in most cases the two REV 6305// instructions can be combined into one. For example: 6306// (REV64_2s (REV64_4h X)) === (REV32_4h X) 6307// 6308// There is also no 128-bit REV instruction. This must be synthesized with an 6309// EXT instruction. 6310// 6311// Most bitconverts require some sort of conversion. The only exceptions are: 6312// a) Identity conversions - vNfX <-> vNiX 6313// b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX 6314// 6315 6316// Natural vector casts (64 bit) 6317def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 6318def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 6319def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 6320def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>; 6321def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 6322def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 6323 6324def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 6325def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>; 6326def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 6327def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 6328def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 6329 6330def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>; 6331def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 6332def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 6333def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 6334def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 6335def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 6336 6337def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 6338def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 6339def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 6340def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 6341def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 6342def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 6343def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 6344 6345def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 6346def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 6347def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 6348def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; 6349def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 6350def : Pat<(v1f64 (AArch64NvCast (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; 6351 6352// Natural vector casts (128 bit) 6353def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 6354def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 6355def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 6356def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>; 6357def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 6358def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 6359def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 6360 6361def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 6362def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>; 6363def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 6364def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 6365def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 6366def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 6367def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 6368 6369def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>; 6370def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 6371def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 6372def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 6373def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 6374def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 6375def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 6376 6377def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 6378def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 6379def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 6380def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 6381def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>; 6382def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 6383def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 6384 6385def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 6386def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 6387def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 6388def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>; 6389def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 6390def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 6391def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 6392 6393def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 6394def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 6395def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 6396def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 6397def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>; 6398def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 6399def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 6400 6401let Predicates = [IsLE] in { 6402def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6403def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6404def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6405def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6406def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6407 6408def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 6409 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6410def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 6411 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6412def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 6413 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6414def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 6415 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6416def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 6417 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6418def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 6419 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6420} 6421let Predicates = [IsBE] in { 6422def : Pat<(v8i8 (bitconvert GPR64:$Xn)), 6423 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 6424def : Pat<(v4i16 (bitconvert GPR64:$Xn)), 6425 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 6426def : Pat<(v2i32 (bitconvert GPR64:$Xn)), 6427 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 6428def : Pat<(v4f16 (bitconvert GPR64:$Xn)), 6429 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 6430def : Pat<(v2f32 (bitconvert GPR64:$Xn)), 6431 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 6432 6433def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 6434 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 6435def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 6436 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 6437def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 6438 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 6439def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 6440 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 6441def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 6442 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 6443} 6444def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6445def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6446def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), 6447 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6448def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), 6449 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6450def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), 6451 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6452def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>; 6453 6454def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), 6455 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>; 6456def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), 6457 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>; 6458def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), 6459 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 6460def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), 6461 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>; 6462def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 6463 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 6464 6465let Predicates = [IsLE] in { 6466def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 6467def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 6468def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 6469def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>; 6470def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 6471} 6472let Predicates = [IsBE] in { 6473def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), 6474 (v1i64 (REV64v2i32 FPR64:$src))>; 6475def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), 6476 (v1i64 (REV64v4i16 FPR64:$src))>; 6477def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), 6478 (v1i64 (REV64v8i8 FPR64:$src))>; 6479def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), 6480 (v1i64 (REV64v4i16 FPR64:$src))>; 6481def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), 6482 (v1i64 (REV64v2i32 FPR64:$src))>; 6483} 6484def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>; 6485def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 6486 6487let Predicates = [IsLE] in { 6488def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>; 6489def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 6490def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 6491def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 6492def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>; 6493def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>; 6494} 6495let Predicates = [IsBE] in { 6496def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), 6497 (v2i32 (REV64v2i32 FPR64:$src))>; 6498def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), 6499 (v2i32 (REV32v4i16 FPR64:$src))>; 6500def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), 6501 (v2i32 (REV32v8i8 FPR64:$src))>; 6502def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), 6503 (v2i32 (REV64v2i32 FPR64:$src))>; 6504def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), 6505 (v2i32 (REV64v2i32 FPR64:$src))>; 6506def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), 6507 (v2i32 (REV32v4i16 FPR64:$src))>; 6508} 6509def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 6510 6511let Predicates = [IsLE] in { 6512def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>; 6513def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 6514def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 6515def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 6516def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 6517def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>; 6518} 6519let Predicates = [IsBE] in { 6520def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), 6521 (v4i16 (REV64v4i16 FPR64:$src))>; 6522def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), 6523 (v4i16 (REV32v4i16 FPR64:$src))>; 6524def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), 6525 (v4i16 (REV16v8i8 FPR64:$src))>; 6526def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), 6527 (v4i16 (REV64v4i16 FPR64:$src))>; 6528def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), 6529 (v4i16 (REV32v4i16 FPR64:$src))>; 6530def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), 6531 (v4i16 (REV64v4i16 FPR64:$src))>; 6532} 6533def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>; 6534 6535let Predicates = [IsLE] in { 6536def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>; 6537def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 6538def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 6539def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 6540def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>; 6541def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>; 6542} 6543let Predicates = [IsBE] in { 6544def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), 6545 (v4f16 (REV64v4i16 FPR64:$src))>; 6546def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), 6547 (v4f16 (REV32v4i16 FPR64:$src))>; 6548def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), 6549 (v4f16 (REV16v8i8 FPR64:$src))>; 6550def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), 6551 (v4f16 (REV64v4i16 FPR64:$src))>; 6552def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), 6553 (v4f16 (REV32v4i16 FPR64:$src))>; 6554def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), 6555 (v4f16 (REV64v4i16 FPR64:$src))>; 6556} 6557def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 6558 6559let Predicates = [IsLE] in { 6560def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>; 6561def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 6562def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 6563def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 6564def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 6565def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>; 6566def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>; 6567} 6568let Predicates = [IsBE] in { 6569def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), 6570 (v8i8 (REV64v8i8 FPR64:$src))>; 6571def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), 6572 (v8i8 (REV32v8i8 FPR64:$src))>; 6573def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), 6574 (v8i8 (REV16v8i8 FPR64:$src))>; 6575def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), 6576 (v8i8 (REV64v8i8 FPR64:$src))>; 6577def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), 6578 (v8i8 (REV32v8i8 FPR64:$src))>; 6579def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), 6580 (v8i8 (REV64v8i8 FPR64:$src))>; 6581def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), 6582 (v8i8 (REV16v8i8 FPR64:$src))>; 6583} 6584 6585let Predicates = [IsLE] in { 6586def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>; 6587def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>; 6588def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>; 6589def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>; 6590def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>; 6591} 6592let Predicates = [IsBE] in { 6593def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), 6594 (f64 (REV64v2i32 FPR64:$src))>; 6595def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), 6596 (f64 (REV64v4i16 FPR64:$src))>; 6597def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), 6598 (f64 (REV64v2i32 FPR64:$src))>; 6599def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), 6600 (f64 (REV64v8i8 FPR64:$src))>; 6601def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), 6602 (f64 (REV64v4i16 FPR64:$src))>; 6603} 6604def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>; 6605def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>; 6606 6607let Predicates = [IsLE] in { 6608def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>; 6609def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>; 6610def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>; 6611def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; 6612def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>; 6613} 6614let Predicates = [IsBE] in { 6615def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), 6616 (v1f64 (REV64v2i32 FPR64:$src))>; 6617def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), 6618 (v1f64 (REV64v4i16 FPR64:$src))>; 6619def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), 6620 (v1f64 (REV64v8i8 FPR64:$src))>; 6621def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), 6622 (v1f64 (REV64v2i32 FPR64:$src))>; 6623def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), 6624 (v1f64 (REV64v4i16 FPR64:$src))>; 6625} 6626def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>; 6627def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 6628 6629let Predicates = [IsLE] in { 6630def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>; 6631def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>; 6632def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 6633def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>; 6634def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 6635def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>; 6636} 6637let Predicates = [IsBE] in { 6638def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), 6639 (v2f32 (REV64v2i32 FPR64:$src))>; 6640def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), 6641 (v2f32 (REV32v4i16 FPR64:$src))>; 6642def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), 6643 (v2f32 (REV32v8i8 FPR64:$src))>; 6644def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), 6645 (v2f32 (REV64v2i32 FPR64:$src))>; 6646def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), 6647 (v2f32 (REV64v2i32 FPR64:$src))>; 6648def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), 6649 (v2f32 (REV32v4i16 FPR64:$src))>; 6650} 6651def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 6652 6653let Predicates = [IsLE] in { 6654def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>; 6655def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>; 6656def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>; 6657def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>; 6658def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>; 6659def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>; 6660def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>; 6661} 6662let Predicates = [IsBE] in { 6663def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), 6664 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 6665def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), 6666 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 6667 (REV64v4i32 FPR128:$src), (i32 8)))>; 6668def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), 6669 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 6670 (REV64v8i16 FPR128:$src), (i32 8)))>; 6671def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), 6672 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 6673 (REV64v8i16 FPR128:$src), (i32 8)))>; 6674def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), 6675 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 6676def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), 6677 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 6678 (REV64v4i32 FPR128:$src), (i32 8)))>; 6679def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), 6680 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src), 6681 (REV64v16i8 FPR128:$src), (i32 8)))>; 6682} 6683 6684let Predicates = [IsLE] in { 6685def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>; 6686def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 6687def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 6688def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>; 6689def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 6690def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 6691} 6692let Predicates = [IsBE] in { 6693def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), 6694 (v2f64 (EXTv16i8 FPR128:$src, 6695 FPR128:$src, (i32 8)))>; 6696def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), 6697 (v2f64 (REV64v4i32 FPR128:$src))>; 6698def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), 6699 (v2f64 (REV64v8i16 FPR128:$src))>; 6700def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), 6701 (v2f64 (REV64v8i16 FPR128:$src))>; 6702def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), 6703 (v2f64 (REV64v16i8 FPR128:$src))>; 6704def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), 6705 (v2f64 (REV64v4i32 FPR128:$src))>; 6706} 6707def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 6708 6709let Predicates = [IsLE] in { 6710def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>; 6711def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 6712def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>; 6713def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 6714def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 6715def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 6716} 6717let Predicates = [IsBE] in { 6718def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), 6719 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src), 6720 (REV64v4i32 FPR128:$src), (i32 8)))>; 6721def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), 6722 (v4f32 (REV32v8i16 FPR128:$src))>; 6723def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), 6724 (v4f32 (REV32v8i16 FPR128:$src))>; 6725def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), 6726 (v4f32 (REV32v16i8 FPR128:$src))>; 6727def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), 6728 (v4f32 (REV64v4i32 FPR128:$src))>; 6729def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), 6730 (v4f32 (REV64v4i32 FPR128:$src))>; 6731} 6732def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 6733 6734let Predicates = [IsLE] in { 6735def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>; 6736def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 6737def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 6738def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 6739def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 6740def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>; 6741} 6742let Predicates = [IsBE] in { 6743def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), 6744 (v2i64 (EXTv16i8 FPR128:$src, 6745 FPR128:$src, (i32 8)))>; 6746def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), 6747 (v2i64 (REV64v4i32 FPR128:$src))>; 6748def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), 6749 (v2i64 (REV64v8i16 FPR128:$src))>; 6750def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), 6751 (v2i64 (REV64v16i8 FPR128:$src))>; 6752def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), 6753 (v2i64 (REV64v4i32 FPR128:$src))>; 6754def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), 6755 (v2i64 (REV64v8i16 FPR128:$src))>; 6756} 6757def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 6758 6759let Predicates = [IsLE] in { 6760def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>; 6761def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 6762def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 6763def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 6764def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 6765def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>; 6766} 6767let Predicates = [IsBE] in { 6768def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), 6769 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src), 6770 (REV64v4i32 FPR128:$src), 6771 (i32 8)))>; 6772def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), 6773 (v4i32 (REV64v4i32 FPR128:$src))>; 6774def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), 6775 (v4i32 (REV32v8i16 FPR128:$src))>; 6776def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), 6777 (v4i32 (REV32v16i8 FPR128:$src))>; 6778def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), 6779 (v4i32 (REV64v4i32 FPR128:$src))>; 6780def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), 6781 (v4i32 (REV32v8i16 FPR128:$src))>; 6782} 6783def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 6784 6785let Predicates = [IsLE] in { 6786def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>; 6787def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 6788def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 6789def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 6790def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 6791def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 6792} 6793let Predicates = [IsBE] in { 6794def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), 6795 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src), 6796 (REV64v8i16 FPR128:$src), 6797 (i32 8)))>; 6798def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), 6799 (v8i16 (REV64v8i16 FPR128:$src))>; 6800def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), 6801 (v8i16 (REV32v8i16 FPR128:$src))>; 6802def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), 6803 (v8i16 (REV16v16i8 FPR128:$src))>; 6804def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), 6805 (v8i16 (REV64v8i16 FPR128:$src))>; 6806def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), 6807 (v8i16 (REV32v8i16 FPR128:$src))>; 6808} 6809def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>; 6810 6811let Predicates = [IsLE] in { 6812def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>; 6813def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 6814def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 6815def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 6816def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 6817def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 6818} 6819let Predicates = [IsBE] in { 6820def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), 6821 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src), 6822 (REV64v8i16 FPR128:$src), 6823 (i32 8)))>; 6824def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), 6825 (v8f16 (REV64v8i16 FPR128:$src))>; 6826def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), 6827 (v8f16 (REV32v8i16 FPR128:$src))>; 6828def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), 6829 (v8f16 (REV16v16i8 FPR128:$src))>; 6830def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), 6831 (v8f16 (REV64v8i16 FPR128:$src))>; 6832def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), 6833 (v8f16 (REV32v8i16 FPR128:$src))>; 6834} 6835def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 6836 6837let Predicates = [IsLE] in { 6838def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>; 6839def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 6840def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 6841def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 6842def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 6843def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 6844def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>; 6845} 6846let Predicates = [IsBE] in { 6847def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), 6848 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src), 6849 (REV64v16i8 FPR128:$src), 6850 (i32 8)))>; 6851def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), 6852 (v16i8 (REV64v16i8 FPR128:$src))>; 6853def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), 6854 (v16i8 (REV32v16i8 FPR128:$src))>; 6855def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), 6856 (v16i8 (REV16v16i8 FPR128:$src))>; 6857def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), 6858 (v16i8 (REV64v16i8 FPR128:$src))>; 6859def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), 6860 (v16i8 (REV32v16i8 FPR128:$src))>; 6861def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), 6862 (v16i8 (REV16v16i8 FPR128:$src))>; 6863} 6864 6865def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))), 6866 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6867def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))), 6868 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6869def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))), 6870 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6871def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))), 6872 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6873def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))), 6874 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6875def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))), 6876 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6877def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))), 6878 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6879 6880def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))), 6881 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6882def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))), 6883 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6884def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))), 6885 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6886def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))), 6887 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6888 6889// A 64-bit subvector insert to the first 128-bit vector position 6890// is a subregister copy that needs no instruction. 6891multiclass InsertSubvectorUndef<ValueType Ty> { 6892 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)), 6893 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6894 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)), 6895 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6896 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)), 6897 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6898 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)), 6899 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6900 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)), 6901 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6902 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)), 6903 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6904 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)), 6905 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6906} 6907 6908defm : InsertSubvectorUndef<i32>; 6909defm : InsertSubvectorUndef<i64>; 6910 6911// Use pair-wise add instructions when summing up the lanes for v2f64, v2i64 6912// or v2f32. 6913def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)), 6914 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))), 6915 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>; 6916def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)), 6917 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))), 6918 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>; 6919 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector, 6920 // so we match on v4f32 here, not v2f32. This will also catch adding 6921 // the low two lanes of a true v4f32 vector. 6922def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)), 6923 (vector_extract (v4f32 FPR128:$Rn), (i64 1))), 6924 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>; 6925 6926// Scalar 64-bit shifts in FPR64 registers. 6927def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6928 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6929def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6930 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6931def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6932 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6933def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6934 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6935 6936// Patterns for nontemporal/no-allocate stores. 6937// We have to resort to tricks to turn a single-input store into a store pair, 6938// because there is no single-input nontemporal store, only STNP. 6939let Predicates = [IsLE] in { 6940let AddedComplexity = 15 in { 6941class NTStore128Pat<ValueType VT> : 6942 Pat<(nontemporalstore (VT FPR128:$Rt), 6943 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), 6944 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub), 6945 (CPYi64 FPR128:$Rt, (i64 1)), 6946 GPR64sp:$Rn, simm7s8:$offset)>; 6947 6948def : NTStore128Pat<v2i64>; 6949def : NTStore128Pat<v4i32>; 6950def : NTStore128Pat<v8i16>; 6951def : NTStore128Pat<v16i8>; 6952 6953class NTStore64Pat<ValueType VT> : 6954 Pat<(nontemporalstore (VT FPR64:$Rt), 6955 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 6956 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), 6957 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), 6958 GPR64sp:$Rn, simm7s4:$offset)>; 6959 6960// FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? 6961def : NTStore64Pat<v1f64>; 6962def : NTStore64Pat<v1i64>; 6963def : NTStore64Pat<v2i32>; 6964def : NTStore64Pat<v4i16>; 6965def : NTStore64Pat<v8i8>; 6966 6967def : Pat<(nontemporalstore GPR64:$Rt, 6968 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 6969 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), 6970 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32), 6971 GPR64sp:$Rn, simm7s4:$offset)>; 6972} // AddedComplexity=10 6973} // Predicates = [IsLE] 6974 6975// Tail call return handling. These are all compiler pseudo-instructions, 6976// so no encoding information or anything like that. 6977let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 6978 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>, 6979 Sched<[WriteBrReg]>; 6980 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>, 6981 Sched<[WriteBrReg]>; 6982 // Indirect tail-call with any register allowed, used by MachineOutliner when 6983 // this is proven safe. 6984 // FIXME: If we have to add any more hacks like this, we should instead relax 6985 // some verifier checks for outlined functions. 6986 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>, 6987 Sched<[WriteBrReg]>; 6988 // Indirect tail-call limited to only use registers (x16 and x17) which are 6989 // allowed to tail-call a "BTI c" instruction. 6990 def TCRETURNriBTI : Pseudo<(outs), (ins rtcGPR64:$dst, i32imm:$FPDiff), []>, 6991 Sched<[WriteBrReg]>; 6992} 6993 6994def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)), 6995 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>, 6996 Requires<[NotUseBTI]>; 6997def : Pat<(AArch64tcret rtcGPR64:$dst, (i32 timm:$FPDiff)), 6998 (TCRETURNriBTI rtcGPR64:$dst, imm:$FPDiff)>, 6999 Requires<[UseBTI]>; 7000def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)), 7001 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 7002def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 7003 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 7004 7005def MOVMCSym : Pseudo<(outs GPR64:$dst), (ins i64imm:$sym), []>, Sched<[]>; 7006def : Pat<(i64 (AArch64LocalRecover mcsym:$sym)), (MOVMCSym mcsym:$sym)>; 7007 7008// Extracting lane zero is a special case where we can just use a plain 7009// EXTRACT_SUBREG instruction, which will become FMOV. This is easier for the 7010// rest of the compiler, especially the register allocator and copy propagation, 7011// to reason about, so is preferred when it's possible to use it. 7012let AddedComplexity = 10 in { 7013 def : Pat<(i64 (extractelt (v2i64 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, dsub)>; 7014 def : Pat<(i32 (extractelt (v4i32 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, ssub)>; 7015 def : Pat<(i32 (extractelt (v2i32 V64:$V), (i64 0))), (EXTRACT_SUBREG V64:$V, ssub)>; 7016} 7017 7018// dot_v4i8 7019class mul_v4i8<SDPatternOperator ldop> : 7020 PatFrag<(ops node:$Rn, node:$Rm, node:$offset), 7021 (mul (ldop (add node:$Rn, node:$offset)), 7022 (ldop (add node:$Rm, node:$offset)))>; 7023class mulz_v4i8<SDPatternOperator ldop> : 7024 PatFrag<(ops node:$Rn, node:$Rm), 7025 (mul (ldop node:$Rn), (ldop node:$Rm))>; 7026 7027def load_v4i8 : 7028 OutPatFrag<(ops node:$R), 7029 (INSERT_SUBREG 7030 (v2i32 (IMPLICIT_DEF)), 7031 (i32 (COPY_TO_REGCLASS (LDRWui node:$R, (i64 0)), FPR32)), 7032 ssub)>; 7033 7034class dot_v4i8<Instruction DOT, SDPatternOperator ldop> : 7035 Pat<(i32 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 3)), 7036 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 2)), 7037 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)), 7038 (mulz_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))), 7039 (EXTRACT_SUBREG (i64 (DOT (DUPv2i32gpr WZR), 7040 (load_v4i8 GPR64sp:$Rn), 7041 (load_v4i8 GPR64sp:$Rm))), 7042 sub_32)>, Requires<[HasDotProd]>; 7043 7044// dot_v8i8 7045class ee_v8i8<SDPatternOperator extend> : 7046 PatFrag<(ops node:$V, node:$K), 7047 (v4i16 (extract_subvector (v8i16 (extend node:$V)), node:$K))>; 7048 7049class mul_v8i8<SDPatternOperator mulop, SDPatternOperator extend> : 7050 PatFrag<(ops node:$M, node:$N, node:$K), 7051 (mulop (v4i16 (ee_v8i8<extend> node:$M, node:$K)), 7052 (v4i16 (ee_v8i8<extend> node:$N, node:$K)))>; 7053 7054class idot_v8i8<SDPatternOperator mulop, SDPatternOperator extend> : 7055 PatFrag<(ops node:$M, node:$N), 7056 (i32 (extractelt 7057 (v4i32 (AArch64uaddv 7058 (add (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 0)), 7059 (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 4))))), 7060 (i64 0)))>; 7061 7062// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 7063def VADDV_32 : OutPatFrag<(ops node:$R), (ADDPv2i32 node:$R, node:$R)>; 7064 7065class odot_v8i8<Instruction DOT> : 7066 OutPatFrag<(ops node:$Vm, node:$Vn), 7067 (EXTRACT_SUBREG 7068 (VADDV_32 7069 (i64 (DOT (DUPv2i32gpr WZR), 7070 (v8i8 node:$Vm), 7071 (v8i8 node:$Vn)))), 7072 sub_32)>; 7073 7074class dot_v8i8<Instruction DOT, SDPatternOperator mulop, 7075 SDPatternOperator extend> : 7076 Pat<(idot_v8i8<mulop, extend> V64:$Vm, V64:$Vn), 7077 (odot_v8i8<DOT> V64:$Vm, V64:$Vn)>, 7078 Requires<[HasDotProd]>; 7079 7080// dot_v16i8 7081class ee_v16i8<SDPatternOperator extend> : 7082 PatFrag<(ops node:$V, node:$K1, node:$K2), 7083 (v4i16 (extract_subvector 7084 (v8i16 (extend 7085 (v8i8 (extract_subvector node:$V, node:$K1)))), node:$K2))>; 7086 7087class mul_v16i8<SDPatternOperator mulop, SDPatternOperator extend> : 7088 PatFrag<(ops node:$M, node:$N, node:$K1, node:$K2), 7089 (v4i32 7090 (mulop (v4i16 (ee_v16i8<extend> node:$M, node:$K1, node:$K2)), 7091 (v4i16 (ee_v16i8<extend> node:$N, node:$K1, node:$K2))))>; 7092 7093class idot_v16i8<SDPatternOperator m, SDPatternOperator x> : 7094 PatFrag<(ops node:$M, node:$N), 7095 (i32 (extractelt 7096 (v4i32 (AArch64uaddv 7097 (add 7098 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 0)), 7099 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 0))), 7100 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 4)), 7101 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 4)))))), 7102 (i64 0)))>; 7103 7104class odot_v16i8<Instruction DOT> : 7105 OutPatFrag<(ops node:$Vm, node:$Vn), 7106 (i32 (ADDVv4i32v 7107 (DOT (DUPv4i32gpr WZR), node:$Vm, node:$Vn)))>; 7108 7109class dot_v16i8<Instruction DOT, SDPatternOperator mulop, 7110 SDPatternOperator extend> : 7111 Pat<(idot_v16i8<mulop, extend> V128:$Vm, V128:$Vn), 7112 (odot_v16i8<DOT> V128:$Vm, V128:$Vn)>, 7113 Requires<[HasDotProd]>; 7114 7115let AddedComplexity = 10 in { 7116 def : dot_v4i8<SDOTv8i8, sextloadi8>; 7117 def : dot_v4i8<UDOTv8i8, zextloadi8>; 7118 def : dot_v8i8<SDOTv8i8, AArch64smull, sext>; 7119 def : dot_v8i8<UDOTv8i8, AArch64umull, zext>; 7120 def : dot_v16i8<SDOTv16i8, AArch64smull, sext>; 7121 def : dot_v16i8<UDOTv16i8, AArch64umull, zext>; 7122 7123 // FIXME: add patterns to generate vector by element dot product. 7124 // FIXME: add SVE dot-product patterns. 7125} 7126 7127include "AArch64InstrAtomics.td" 7128include "AArch64SVEInstrInfo.td" 7129