1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the AArch64 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H 14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H 15 16 #include "AArch64.h" 17 #include "AArch64RegisterInfo.h" 18 #include "llvm/ADT/Optional.h" 19 #include "llvm/CodeGen/MachineCombinerPattern.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include "llvm/Support/TypeSize.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "AArch64GenInstrInfo.inc" 25 26 namespace llvm { 27 28 class AArch64Subtarget; 29 class AArch64TargetMachine; 30 31 static const MachineMemOperand::Flags MOSuppressPair = 32 MachineMemOperand::MOTargetFlag1; 33 static const MachineMemOperand::Flags MOStridedAccess = 34 MachineMemOperand::MOTargetFlag2; 35 36 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access" 37 38 class AArch64InstrInfo final : public AArch64GenInstrInfo { 39 const AArch64RegisterInfo RI; 40 const AArch64Subtarget &Subtarget; 41 42 public: 43 explicit AArch64InstrInfo(const AArch64Subtarget &STI); 44 45 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 46 /// such, whenever a client has an instance of instruction info, it should 47 /// always be able to get register info as well (through this method). 48 const AArch64RegisterInfo &getRegisterInfo() const { return RI; } 49 50 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 51 52 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 53 54 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 55 Register &DstReg, unsigned &SubIdx) const override; 56 57 bool 58 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 59 const MachineInstr &MIb) const override; 60 61 unsigned isLoadFromStackSlot(const MachineInstr &MI, 62 int &FrameIndex) const override; 63 unsigned isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const override; 65 66 /// Does this instruction set its full destination register to zero? 67 static bool isGPRZero(const MachineInstr &MI); 68 69 /// Does this instruction rename a GPR without modifying bits? 70 static bool isGPRCopy(const MachineInstr &MI); 71 72 /// Does this instruction rename an FPR without modifying bits? 73 static bool isFPRCopy(const MachineInstr &MI); 74 75 /// Return true if pairing the given load or store is hinted to be 76 /// unprofitable. 77 static bool isLdStPairSuppressed(const MachineInstr &MI); 78 79 /// Return true if the given load or store is a strided memory access. 80 static bool isStridedAccess(const MachineInstr &MI); 81 82 /// Return true if this is an unscaled load/store. 83 static bool isUnscaledLdSt(unsigned Opc); 84 static bool isUnscaledLdSt(MachineInstr &MI) { 85 return isUnscaledLdSt(MI.getOpcode()); 86 } 87 88 /// Returns the unscaled load/store for the scaled load/store opcode, 89 /// if there is a corresponding unscaled variant available. 90 static Optional<unsigned> getUnscaledLdSt(unsigned Opc); 91 92 /// Scaling factor for (scaled or unscaled) load or store. 93 static int getMemScale(unsigned Opc); 94 static int getMemScale(const MachineInstr &MI) { 95 return getMemScale(MI.getOpcode()); 96 } 97 98 99 /// Returns the index for the immediate for a given instruction. 100 static unsigned getLoadStoreImmIdx(unsigned Opc); 101 102 /// Return true if pairing the given load or store may be paired with another. 103 static bool isPairableLdStInst(const MachineInstr &MI); 104 105 /// Return the opcode that set flags when possible. The caller is 106 /// responsible for ensuring the opc has a flag setting equivalent. 107 static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit); 108 109 /// Return true if this is a load/store that can be potentially paired/merged. 110 bool isCandidateToMergeOrPair(const MachineInstr &MI) const; 111 112 /// Hint that pairing the given load or store is unprofitable. 113 static void suppressLdStPair(MachineInstr &MI); 114 115 Optional<ExtAddrMode> 116 getAddrModeFromMemoryOp(const MachineInstr &MemI, 117 const TargetRegisterInfo *TRI) const override; 118 119 bool getMemOperandsWithOffsetWidth( 120 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, 121 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 122 const TargetRegisterInfo *TRI) const override; 123 124 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`. 125 /// This is true for some SVE instructions like ldr/str that have a 126 /// 'reg + imm' addressing mode where the immediate is an index to the 127 /// scalable vector located at 'reg + imm * vscale x #bytes'. 128 bool getMemOperandWithOffsetWidth(const MachineInstr &MI, 129 const MachineOperand *&BaseOp, 130 int64_t &Offset, bool &OffsetIsScalable, 131 unsigned &Width, 132 const TargetRegisterInfo *TRI) const; 133 134 /// Return the immediate offset of the base register in a load/store \p LdSt. 135 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const; 136 137 /// Returns true if opcode \p Opc is a memory operation. If it is, set 138 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly. 139 /// 140 /// For unscaled instructions, \p Scale is set to 1. 141 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, 142 int64_t &MinOffset, int64_t &MaxOffset); 143 144 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 145 ArrayRef<const MachineOperand *> BaseOps2, 146 unsigned NumLoads, unsigned NumBytes) const override; 147 148 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 149 const DebugLoc &DL, MCRegister DestReg, 150 MCRegister SrcReg, bool KillSrc, unsigned Opcode, 151 llvm::ArrayRef<unsigned> Indices) const; 152 void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 153 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 154 bool KillSrc, unsigned Opcode, unsigned ZeroReg, 155 llvm::ArrayRef<unsigned> Indices) const; 156 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 157 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 158 bool KillSrc) const override; 159 160 void storeRegToStackSlot(MachineBasicBlock &MBB, 161 MachineBasicBlock::iterator MBBI, Register SrcReg, 162 bool isKill, int FrameIndex, 163 const TargetRegisterClass *RC, 164 const TargetRegisterInfo *TRI) const override; 165 166 void loadRegFromStackSlot(MachineBasicBlock &MBB, 167 MachineBasicBlock::iterator MBBI, Register DestReg, 168 int FrameIndex, const TargetRegisterClass *RC, 169 const TargetRegisterInfo *TRI) const override; 170 171 // This tells target independent code that it is okay to pass instructions 172 // with subreg operands to foldMemoryOperandImpl. 173 bool isSubregFoldable() const override { return true; } 174 175 using TargetInstrInfo::foldMemoryOperandImpl; 176 MachineInstr * 177 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 178 ArrayRef<unsigned> Ops, 179 MachineBasicBlock::iterator InsertPt, int FrameIndex, 180 LiveIntervals *LIS = nullptr, 181 VirtRegMap *VRM = nullptr) const override; 182 183 /// \returns true if a branch from an instruction with opcode \p BranchOpc 184 /// bytes is capable of jumping to a position \p BrOffset bytes away. 185 bool isBranchOffsetInRange(unsigned BranchOpc, 186 int64_t BrOffset) const override; 187 188 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 189 190 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 191 MachineBasicBlock *&FBB, 192 SmallVectorImpl<MachineOperand> &Cond, 193 bool AllowModify = false) const override; 194 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 195 MachineBranchPredicate &MBP, 196 bool AllowModify) const override; 197 unsigned removeBranch(MachineBasicBlock &MBB, 198 int *BytesRemoved = nullptr) const override; 199 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 200 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 201 const DebugLoc &DL, 202 int *BytesAdded = nullptr) const override; 203 bool 204 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 205 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 206 Register, Register, Register, int &, int &, 207 int &) const override; 208 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 209 const DebugLoc &DL, Register DstReg, 210 ArrayRef<MachineOperand> Cond, Register TrueReg, 211 Register FalseReg) const override; 212 void getNoop(MCInst &NopInst) const override; 213 214 bool isSchedulingBoundary(const MachineInstr &MI, 215 const MachineBasicBlock *MBB, 216 const MachineFunction &MF) const override; 217 218 /// analyzeCompare - For a comparison instruction, return the source registers 219 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 220 /// Return true if the comparison instruction can be analyzed. 221 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 222 Register &SrcReg2, int &CmpMask, 223 int &CmpValue) const override; 224 /// optimizeCompareInstr - Convert the instruction supplying the argument to 225 /// the comparison into one that sets the zero bit in the flags register. 226 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 227 Register SrcReg2, int CmpMask, int CmpValue, 228 const MachineRegisterInfo *MRI) const override; 229 bool optimizeCondBranch(MachineInstr &MI) const override; 230 231 /// Return true when a code sequence can improve throughput. It 232 /// should be called only for instructions in loops. 233 /// \param Pattern - combiner pattern 234 bool isThroughputPattern(MachineCombinerPattern Pattern) const override; 235 /// Return true when there is potentially a faster code sequence 236 /// for an instruction chain ending in ``Root``. All potential patterns are 237 /// listed in the ``Patterns`` array. 238 bool 239 getMachineCombinerPatterns(MachineInstr &Root, 240 SmallVectorImpl<MachineCombinerPattern> &Patterns, 241 bool DoRegPressureReduce) const override; 242 /// Return true when Inst is associative and commutative so that it can be 243 /// reassociated. 244 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 245 /// When getMachineCombinerPatterns() finds patterns, this function generates 246 /// the instructions that could replace the original code sequence 247 void genAlternativeCodeSequence( 248 MachineInstr &Root, MachineCombinerPattern Pattern, 249 SmallVectorImpl<MachineInstr *> &InsInstrs, 250 SmallVectorImpl<MachineInstr *> &DelInstrs, 251 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 252 /// AArch64 supports MachineCombiner. 253 bool useMachineCombiner() const override; 254 255 bool expandPostRAPseudo(MachineInstr &MI) const override; 256 257 std::pair<unsigned, unsigned> 258 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 259 ArrayRef<std::pair<unsigned, const char *>> 260 getSerializableDirectMachineOperandTargetFlags() const override; 261 ArrayRef<std::pair<unsigned, const char *>> 262 getSerializableBitmaskMachineOperandTargetFlags() const override; 263 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> 264 getSerializableMachineMemOperandTargetFlags() const override; 265 266 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 267 bool OutlineFromLinkOnceODRs) const override; 268 outliner::OutlinedFunction getOutliningCandidateInfo( 269 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 270 outliner::InstrType 271 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 272 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 273 unsigned &Flags) const override; 274 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 275 const outliner::OutlinedFunction &OF) const override; 276 MachineBasicBlock::iterator 277 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 278 MachineBasicBlock::iterator &It, MachineFunction &MF, 279 const outliner::Candidate &C) const override; 280 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 281 /// Returns the vector element size (B, H, S or D) of an SVE opcode. 282 uint64_t getElementSizeForOpcode(unsigned Opc) const; 283 /// Returns true if the opcode is for an SVE instruction that sets the 284 /// condition codes as if it's results had been fed to a PTEST instruction 285 /// along with the same general predicate. 286 bool isPTestLikeOpcode(unsigned Opc) const; 287 /// Returns true if the opcode is for an SVE WHILE## instruction. 288 bool isWhileOpcode(unsigned Opc) const; 289 /// Returns true if the instruction has a shift by immediate that can be 290 /// executed in one cycle less. 291 static bool isFalkorShiftExtFast(const MachineInstr &MI); 292 /// Return true if the instructions is a SEH instruciton used for unwinding 293 /// on Windows. 294 static bool isSEHInstruction(const MachineInstr &MI); 295 296 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 297 Register Reg) const override; 298 299 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 300 Register Reg) const override; 301 302 static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, 303 int64_t &NumBytes, 304 int64_t &NumPredicateVectors, 305 int64_t &NumDataVectors); 306 static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, 307 int64_t &ByteSized, 308 int64_t &VGSized); 309 #define GET_INSTRINFO_HELPER_DECLS 310 #include "AArch64GenInstrInfo.inc" 311 312 protected: 313 /// If the specific machine instruction is an instruction that moves/copies 314 /// value from one register to another register return destination and source 315 /// registers as machine operands. 316 Optional<DestSourcePair> 317 isCopyInstrImpl(const MachineInstr &MI) const override; 318 319 private: 320 unsigned getInstBundleLength(const MachineInstr &MI) const; 321 322 /// Sets the offsets on outlined instructions in \p MBB which use SP 323 /// so that they will be valid post-outlining. 324 /// 325 /// \param MBB A \p MachineBasicBlock in an outlined function. 326 void fixupPostOutline(MachineBasicBlock &MBB) const; 327 328 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL, 329 MachineBasicBlock *TBB, 330 ArrayRef<MachineOperand> Cond) const; 331 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg, 332 const MachineRegisterInfo *MRI) const; 333 334 /// Returns an unused general-purpose register which can be used for 335 /// constructing an outlined call if one exists. Returns 0 otherwise. 336 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 337 338 /// Remove a ptest of a predicate-generating operation that already sets, or 339 /// can be made to set, the condition codes in an identical manner 340 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg, 341 unsigned PredReg, 342 const MachineRegisterInfo *MRI) const; 343 }; 344 345 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI 346 /// which either reads or clobbers NZCV. 347 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, 348 const MachineInstr &UseMI, 349 const TargetRegisterInfo *TRI); 350 351 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg 352 /// plus Offset. This is intended to be used from within the prolog/epilog 353 /// insertion (PEI) pass, where a virtual scratch register may be allocated 354 /// if necessary, to be replaced by the scavenger at the end of PEI. 355 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 356 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 357 StackOffset Offset, const TargetInstrInfo *TII, 358 MachineInstr::MIFlag = MachineInstr::NoFlags, 359 bool SetNZCV = false, bool NeedsWinCFI = false, 360 bool *HasWinCFI = nullptr); 361 362 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the 363 /// FP. Return false if the offset could not be handled directly in MI, and 364 /// return the left-over portion by reference. 365 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 366 unsigned FrameReg, StackOffset &Offset, 367 const AArch64InstrInfo *TII); 368 369 /// Use to report the frame offset status in isAArch64FrameOffsetLegal. 370 enum AArch64FrameOffsetStatus { 371 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply. 372 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal. 373 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly. 374 }; 375 376 /// Check if the @p Offset is a valid frame offset for @p MI. 377 /// The returned value reports the validity of the frame offset for @p MI. 378 /// It uses the values defined by AArch64FrameOffsetStatus for that. 379 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to 380 /// use an offset.eq 381 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be 382 /// rewritten in @p MI. 383 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the 384 /// amount that is off the limit of the legal offset. 385 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be 386 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp. 387 /// If set, @p EmittableOffset contains the amount that can be set in @p MI 388 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that 389 /// is a legal offset. 390 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, 391 bool *OutUseUnscaledOp = nullptr, 392 unsigned *OutUnscaledOp = nullptr, 393 int64_t *EmittableOffset = nullptr); 394 395 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } 396 397 static inline bool isCondBranchOpcode(int Opc) { 398 switch (Opc) { 399 case AArch64::Bcc: 400 case AArch64::CBZW: 401 case AArch64::CBZX: 402 case AArch64::CBNZW: 403 case AArch64::CBNZX: 404 case AArch64::TBZW: 405 case AArch64::TBZX: 406 case AArch64::TBNZW: 407 case AArch64::TBNZX: 408 return true; 409 default: 410 return false; 411 } 412 } 413 414 static inline bool isIndirectBranchOpcode(int Opc) { 415 switch (Opc) { 416 case AArch64::BR: 417 case AArch64::BRAA: 418 case AArch64::BRAB: 419 case AArch64::BRAAZ: 420 case AArch64::BRABZ: 421 return true; 422 } 423 return false; 424 } 425 426 static inline bool isPTrueOpcode(unsigned Opc) { 427 switch (Opc) { 428 case AArch64::PTRUE_B: 429 case AArch64::PTRUE_H: 430 case AArch64::PTRUE_S: 431 case AArch64::PTRUE_D: 432 return true; 433 default: 434 return false; 435 } 436 } 437 438 /// Return opcode to be used for indirect calls. 439 unsigned getBLRCallOpcode(const MachineFunction &MF); 440 441 // struct TSFlags { 442 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits 443 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit 444 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits 445 #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits 446 // } 447 448 namespace AArch64 { 449 450 enum ElementSizeType { 451 ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7), 452 ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0), 453 ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1), 454 ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2), 455 ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3), 456 ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4), 457 }; 458 459 enum DestructiveInstType { 460 DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf), 461 NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0), 462 DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1), 463 DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2), 464 DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3), 465 DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4), 466 DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5), 467 DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6), 468 DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7), 469 DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8), 470 }; 471 472 enum FalseLaneType { 473 FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3), 474 FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1), 475 FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2), 476 }; 477 478 // NOTE: This is a bit field. 479 static const uint64_t InstrFlagIsWhile = TSFLAG_INSTR_FLAGS(0x1); 480 static const uint64_t InstrFlagIsPTestLike = TSFLAG_INSTR_FLAGS(0x2); 481 482 #undef TSFLAG_ELEMENT_SIZE_TYPE 483 #undef TSFLAG_DESTRUCTIVE_INST_TYPE 484 #undef TSFLAG_FALSE_LANE_TYPE 485 #undef TSFLAG_INSTR_FLAGS 486 487 int getSVEPseudoMap(uint16_t Opcode); 488 int getSVERevInstr(uint16_t Opcode); 489 int getSVENonRevInstr(uint16_t Opcode); 490 } 491 492 } // end namespace llvm 493 494 #endif 495