xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrGISel.td (revision dc318a4ffabcbfa23bb56a33403aad36e6de30af) 
1//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// AArch64 GlobalISel target pseudo instruction definitions. This is kept
10// separately from the other tablegen files for organizational purposes, but
11// share the same infrastructure.
12//
13//===----------------------------------------------------------------------===//
14
15
16class AArch64GenericInstruction : GenericInstruction {
17  let Namespace = "AArch64";
18}
19
20// A pseudo to represent a relocatable add instruction as part of address
21// computation.
22def G_ADD_LOW : AArch64GenericInstruction {
23  let OutOperandList = (outs type0:$dst);
24  let InOperandList = (ins type1:$src, type2:$imm);
25  let hasSideEffects = 0;
26}
27
28// Pseudo for a rev16 instruction. Produced post-legalization from
29// G_SHUFFLE_VECTORs with appropriate masks.
30def G_REV16 : AArch64GenericInstruction {
31  let OutOperandList = (outs type0:$dst);
32  let InOperandList = (ins type0:$src);
33  let hasSideEffects = 0;
34}
35
36// Pseudo for a rev32 instruction. Produced post-legalization from
37// G_SHUFFLE_VECTORs with appropriate masks.
38def G_REV32 : AArch64GenericInstruction {
39  let OutOperandList = (outs type0:$dst);
40  let InOperandList = (ins type0:$src);
41  let hasSideEffects = 0;
42}
43
44// Pseudo for a rev64 instruction. Produced post-legalization from
45// G_SHUFFLE_VECTORs with appropriate masks.
46def G_REV64 : AArch64GenericInstruction {
47  let OutOperandList = (outs type0:$dst);
48  let InOperandList = (ins type0:$src);
49  let hasSideEffects = 0;
50}
51
52// Represents an uzp1 instruction. Produced post-legalization from
53// G_SHUFFLE_VECTORs with appropriate masks.
54def G_UZP1 : AArch64GenericInstruction {
55  let OutOperandList = (outs type0:$dst);
56  let InOperandList = (ins type0:$v1, type0:$v2);
57  let hasSideEffects = 0;
58}
59
60// Represents an uzp2 instruction. Produced post-legalization from
61// G_SHUFFLE_VECTORs with appropriate masks.
62def G_UZP2 : AArch64GenericInstruction {
63  let OutOperandList = (outs type0:$dst);
64  let InOperandList = (ins type0:$v1, type0:$v2);
65  let hasSideEffects = 0;
66}
67
68// Represents a zip1 instruction. Produced post-legalization from
69// G_SHUFFLE_VECTORs with appropriate masks.
70def G_ZIP1 : AArch64GenericInstruction {
71  let OutOperandList = (outs type0:$dst);
72  let InOperandList = (ins type0:$v1, type0:$v2);
73  let hasSideEffects = 0;
74}
75
76// Represents a zip2 instruction. Produced post-legalization from
77// G_SHUFFLE_VECTORs with appropriate masks.
78def G_ZIP2 : AArch64GenericInstruction {
79  let OutOperandList = (outs type0:$dst);
80  let InOperandList = (ins type0:$v1, type0:$v2);
81  let hasSideEffects = 0;
82}
83
84// Represents a dup instruction. Produced post-legalization from
85// G_SHUFFLE_VECTORs with appropriate masks.
86def G_DUP: AArch64GenericInstruction {
87  let OutOperandList = (outs type0:$dst);
88  let InOperandList = (ins type1:$lane);
89  let hasSideEffects = 0;
90}
91// Represents a trn1 instruction. Produced post-legalization from
92// G_SHUFFLE_VECTORs with appropriate masks.
93def G_TRN1 : AArch64GenericInstruction {
94  let OutOperandList = (outs type0:$dst);
95  let InOperandList = (ins type0:$v1, type0:$v2);
96  let hasSideEffects = 0;
97}
98
99// Represents a trn2 instruction. Produced post-legalization from
100// G_SHUFFLE_VECTORs with appropriate masks.
101def G_TRN2 : AArch64GenericInstruction {
102  let OutOperandList = (outs type0:$dst);
103  let InOperandList = (ins type0:$v1, type0:$v2);
104  let hasSideEffects = 0;
105}
106
107// Represents an ext instruction. Produced post-legalization from
108// G_SHUFFLE_VECTORs with appropriate masks.
109def G_EXT: AArch64GenericInstruction {
110  let OutOperandList = (outs type0:$dst);
111  let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
112}
113
114def : GINodeEquiv<G_REV16, AArch64rev16>;
115def : GINodeEquiv<G_REV32, AArch64rev32>;
116def : GINodeEquiv<G_REV64, AArch64rev64>;
117def : GINodeEquiv<G_UZP1, AArch64uzp1>;
118def : GINodeEquiv<G_UZP2, AArch64uzp2>;
119def : GINodeEquiv<G_ZIP1, AArch64zip1>;
120def : GINodeEquiv<G_ZIP2, AArch64zip2>;
121def : GINodeEquiv<G_DUP, AArch64dup>;
122def : GINodeEquiv<G_TRN1, AArch64trn1>;
123def : GINodeEquiv<G_TRN2, AArch64trn2>;
124def : GINodeEquiv<G_EXT, AArch64ext>;
125