1//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AArch64 GlobalISel target pseudo instruction definitions. This is kept 10// separately from the other tablegen files for organizational purposes, but 11// share the same infrastructure. 12// 13//===----------------------------------------------------------------------===// 14 15 16class AArch64GenericInstruction : GenericInstruction { 17 let Namespace = "AArch64"; 18} 19 20// A pseudo to represent a relocatable add instruction as part of address 21// computation. 22def G_ADD_LOW : AArch64GenericInstruction { 23 let OutOperandList = (outs type0:$dst); 24 let InOperandList = (ins type1:$src, type2:$imm); 25 let hasSideEffects = 0; 26} 27 28// Pseudo for a rev16 instruction. Produced post-legalization from 29// G_SHUFFLE_VECTORs with appropriate masks. 30def G_REV16 : AArch64GenericInstruction { 31 let OutOperandList = (outs type0:$dst); 32 let InOperandList = (ins type0:$src); 33 let hasSideEffects = 0; 34} 35 36// Pseudo for a rev32 instruction. Produced post-legalization from 37// G_SHUFFLE_VECTORs with appropriate masks. 38def G_REV32 : AArch64GenericInstruction { 39 let OutOperandList = (outs type0:$dst); 40 let InOperandList = (ins type0:$src); 41 let hasSideEffects = 0; 42} 43 44// Pseudo for a rev64 instruction. Produced post-legalization from 45// G_SHUFFLE_VECTORs with appropriate masks. 46def G_REV64 : AArch64GenericInstruction { 47 let OutOperandList = (outs type0:$dst); 48 let InOperandList = (ins type0:$src); 49 let hasSideEffects = 0; 50} 51 52// Represents an uzp1 instruction. Produced post-legalization from 53// G_SHUFFLE_VECTORs with appropriate masks. 54def G_UZP1 : AArch64GenericInstruction { 55 let OutOperandList = (outs type0:$dst); 56 let InOperandList = (ins type0:$v1, type0:$v2); 57 let hasSideEffects = 0; 58} 59 60// Represents an uzp2 instruction. Produced post-legalization from 61// G_SHUFFLE_VECTORs with appropriate masks. 62def G_UZP2 : AArch64GenericInstruction { 63 let OutOperandList = (outs type0:$dst); 64 let InOperandList = (ins type0:$v1, type0:$v2); 65 let hasSideEffects = 0; 66} 67 68// Represents a zip1 instruction. Produced post-legalization from 69// G_SHUFFLE_VECTORs with appropriate masks. 70def G_ZIP1 : AArch64GenericInstruction { 71 let OutOperandList = (outs type0:$dst); 72 let InOperandList = (ins type0:$v1, type0:$v2); 73 let hasSideEffects = 0; 74} 75 76// Represents a zip2 instruction. Produced post-legalization from 77// G_SHUFFLE_VECTORs with appropriate masks. 78def G_ZIP2 : AArch64GenericInstruction { 79 let OutOperandList = (outs type0:$dst); 80 let InOperandList = (ins type0:$v1, type0:$v2); 81 let hasSideEffects = 0; 82} 83 84// Represents a dup instruction. Produced post-legalization from 85// G_SHUFFLE_VECTORs with appropriate masks. 86def G_DUP: AArch64GenericInstruction { 87 let OutOperandList = (outs type0:$dst); 88 let InOperandList = (ins type1:$lane); 89 let hasSideEffects = 0; 90} 91 92// Represents a lane duplicate operation. 93def G_DUPLANE8 : AArch64GenericInstruction { 94 let OutOperandList = (outs type0:$dst); 95 let InOperandList = (ins type0:$src, type1:$lane); 96 let hasSideEffects = 0; 97} 98def G_DUPLANE16 : AArch64GenericInstruction { 99 let OutOperandList = (outs type0:$dst); 100 let InOperandList = (ins type0:$src, type1:$lane); 101 let hasSideEffects = 0; 102} 103def G_DUPLANE32 : AArch64GenericInstruction { 104 let OutOperandList = (outs type0:$dst); 105 let InOperandList = (ins type0:$src, type1:$lane); 106 let hasSideEffects = 0; 107} 108def G_DUPLANE64 : AArch64GenericInstruction { 109 let OutOperandList = (outs type0:$dst); 110 let InOperandList = (ins type0:$src, type1:$lane); 111 let hasSideEffects = 0; 112} 113 114// Represents a trn1 instruction. Produced post-legalization from 115// G_SHUFFLE_VECTORs with appropriate masks. 116def G_TRN1 : AArch64GenericInstruction { 117 let OutOperandList = (outs type0:$dst); 118 let InOperandList = (ins type0:$v1, type0:$v2); 119 let hasSideEffects = 0; 120} 121 122// Represents a trn2 instruction. Produced post-legalization from 123// G_SHUFFLE_VECTORs with appropriate masks. 124def G_TRN2 : AArch64GenericInstruction { 125 let OutOperandList = (outs type0:$dst); 126 let InOperandList = (ins type0:$v1, type0:$v2); 127 let hasSideEffects = 0; 128} 129 130// Represents an ext instruction. Produced post-legalization from 131// G_SHUFFLE_VECTORs with appropriate masks. 132def G_EXT: AArch64GenericInstruction { 133 let OutOperandList = (outs type0:$dst); 134 let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm); 135 let hasSideEffects = 0; 136} 137 138// Represents a vector G_ASHR with an immediate. 139def G_VASHR : AArch64GenericInstruction { 140 let OutOperandList = (outs type0:$dst); 141 let InOperandList = (ins type0:$src1, untyped_imm_0:$imm); 142 let hasSideEffects = 0; 143} 144 145// Represents a vector G_LSHR with an immediate. 146def G_VLSHR : AArch64GenericInstruction { 147 let OutOperandList = (outs type0:$dst); 148 let InOperandList = (ins type0:$src1, untyped_imm_0:$imm); 149 let hasSideEffects = 0; 150} 151 152// Represents an integer to FP conversion on the FPR bank. 153def G_SITOF : AArch64GenericInstruction { 154 let OutOperandList = (outs type0:$dst); 155 let InOperandList = (ins type0:$src); 156 let hasSideEffects = 0; 157} 158def G_UITOF : AArch64GenericInstruction { 159 let OutOperandList = (outs type0:$dst); 160 let InOperandList = (ins type0:$src); 161 let hasSideEffects = 0; 162} 163 164def G_FCMEQ : AArch64GenericInstruction { 165 let OutOperandList = (outs type0:$dst); 166 let InOperandList = (ins type0:$src1, type1:$src2); 167 let hasSideEffects = 0; 168} 169 170def G_FCMGE : AArch64GenericInstruction { 171 let OutOperandList = (outs type0:$dst); 172 let InOperandList = (ins type0:$src1, type1:$src2); 173 let hasSideEffects = 0; 174} 175 176def G_FCMGT : AArch64GenericInstruction { 177 let OutOperandList = (outs type0:$dst); 178 let InOperandList = (ins type0:$src1, type1:$src2); 179 let hasSideEffects = 0; 180} 181 182def G_FCMEQZ : AArch64GenericInstruction { 183 let OutOperandList = (outs type0:$dst); 184 let InOperandList = (ins type0:$src); 185 let hasSideEffects = 0; 186} 187 188def G_FCMGEZ : AArch64GenericInstruction { 189 let OutOperandList = (outs type0:$dst); 190 let InOperandList = (ins type0:$src); 191 let hasSideEffects = 0; 192} 193 194def G_FCMGTZ : AArch64GenericInstruction { 195 let OutOperandList = (outs type0:$dst); 196 let InOperandList = (ins type0:$src); 197 let hasSideEffects = 0; 198} 199 200def G_FCMLEZ : AArch64GenericInstruction { 201 let OutOperandList = (outs type0:$dst); 202 let InOperandList = (ins type0:$src); 203 let hasSideEffects = 0; 204} 205 206def G_FCMLTZ : AArch64GenericInstruction { 207 let OutOperandList = (outs type0:$dst); 208 let InOperandList = (ins type0:$src); 209 let hasSideEffects = 0; 210} 211 212def G_PREFETCH : AArch64GenericInstruction { 213 let OutOperandList = (outs); 214 let InOperandList = (ins type0:$imm, ptype0:$src1); 215 let hasSideEffects = 1; 216} 217 218// Generic bitwise insert if true. 219def G_BIT : AArch64GenericInstruction { 220 let OutOperandList = (outs type0:$dst); 221 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3); 222 let hasSideEffects = 0; 223} 224 225def : GINodeEquiv<G_REV16, AArch64rev16>; 226def : GINodeEquiv<G_REV32, AArch64rev32>; 227def : GINodeEquiv<G_REV64, AArch64rev64>; 228def : GINodeEquiv<G_UZP1, AArch64uzp1>; 229def : GINodeEquiv<G_UZP2, AArch64uzp2>; 230def : GINodeEquiv<G_ZIP1, AArch64zip1>; 231def : GINodeEquiv<G_ZIP2, AArch64zip2>; 232def : GINodeEquiv<G_DUP, AArch64dup>; 233def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>; 234def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>; 235def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>; 236def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>; 237def : GINodeEquiv<G_TRN1, AArch64trn1>; 238def : GINodeEquiv<G_TRN2, AArch64trn2>; 239def : GINodeEquiv<G_EXT, AArch64ext>; 240def : GINodeEquiv<G_VASHR, AArch64vashr>; 241def : GINodeEquiv<G_VLSHR, AArch64vlshr>; 242def : GINodeEquiv<G_SITOF, AArch64sitof>; 243def : GINodeEquiv<G_UITOF, AArch64uitof>; 244 245def : GINodeEquiv<G_FCMEQ, AArch64fcmeq>; 246def : GINodeEquiv<G_FCMGE, AArch64fcmge>; 247def : GINodeEquiv<G_FCMGT, AArch64fcmgt>; 248 249def : GINodeEquiv<G_FCMEQZ, AArch64fcmeqz>; 250def : GINodeEquiv<G_FCMGEZ, AArch64fcmgez>; 251def : GINodeEquiv<G_FCMGTZ, AArch64fcmgtz>; 252def : GINodeEquiv<G_FCMLEZ, AArch64fcmlez>; 253def : GINodeEquiv<G_FCMLTZ, AArch64fcmltz>; 254 255def : GINodeEquiv<G_BIT, AArch64bit>; 256 257def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; 258 259def : GINodeEquiv<G_PREFETCH, AArch64Prefetch>; 260 261// These are patterns that we only use for GlobalISel via the importer. 262def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)), 263 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))), 264 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>; 265 266let Predicates = [HasNEON] in { 267 def : Pat<(v2f64 (sint_to_fp v2i32:$src)), 268 (SCVTFv2f64 (SSHLLv2i32_shift V64:$src, 0))>; 269 def : Pat<(v2f64 (uint_to_fp v2i32:$src)), 270 (UCVTFv2f64 (USHLLv2i32_shift V64:$src, 0))>; 271 def : Pat<(v2f32 (sint_to_fp v2i64:$src)), 272 (FCVTNv2i32 (SCVTFv2f64 V128:$src))>; 273 def : Pat<(v2f32 (uint_to_fp v2i64:$src)), 274 (FCVTNv2i32 (UCVTFv2f64 V128:$src))>; 275 276 def : Pat<(v2i64 (fp_to_sint v2f32:$src)), 277 (FCVTZSv2f64 (FCVTLv2i32 V64:$src))>; 278 def : Pat<(v2i64 (fp_to_uint v2f32:$src)), 279 (FCVTZUv2f64 (FCVTLv2i32 V64:$src))>; 280 def : Pat<(v2i32 (fp_to_sint v2f64:$src)), 281 (XTNv2i32 (FCVTZSv2f64 V128:$src))>; 282 def : Pat<(v2i32 (fp_to_uint v2f64:$src)), 283 (XTNv2i32 (FCVTZUv2f64 V128:$src))>; 284 285} 286 287let Predicates = [HasNoLSE] in { 288def : Pat<(atomic_cmp_swap_8 GPR64:$addr, GPR32:$desired, GPR32:$new), 289 (CMP_SWAP_8 GPR64:$addr, GPR32:$desired, GPR32:$new)>; 290 291def : Pat<(atomic_cmp_swap_16 GPR64:$addr, GPR32:$desired, GPR32:$new), 292 (CMP_SWAP_16 GPR64:$addr, GPR32:$desired, GPR32:$new)>; 293 294def : Pat<(atomic_cmp_swap_32 GPR64:$addr, GPR32:$desired, GPR32:$new), 295 (CMP_SWAP_32 GPR64:$addr, GPR32:$desired, GPR32:$new)>; 296 297def : Pat<(atomic_cmp_swap_64 GPR64:$addr, GPR64:$desired, GPR64:$new), 298 (CMP_SWAP_64 GPR64:$addr, GPR64:$desired, GPR64:$new)>; 299} 300 301def : Pat<(int_aarch64_stlxp GPR64:$lo, GPR64:$hi, GPR64:$addr), 302 (STLXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>; 303def : Pat<(int_aarch64_stxp GPR64:$lo, GPR64:$hi, GPR64:$addr), 304 (STXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>; 305 306multiclass SIMDAcrossLanesSignedIntrinsicBHS<string baseOpc, Intrinsic intOp> { 307 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 308 (i32 (SMOVvi8to32 309 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 310 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 311 (i64 0)))>; 312 def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 313 (i32 (SMOVvi8to32 314 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 315 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 316 (i64 0)))>; 317 318 def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 319 (i32 (SMOVvi16to32 320 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 321 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 322 (i64 0)))>; 323 def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 324 (i32 (SMOVvi16to32 325 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 326 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 327 (i64 0)))>; 328 329 def : Pat<(i32 (intOp (v4i32 V128:$Rn))), 330 (i32 (EXTRACT_SUBREG 331 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 332 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub), 333 ssub))>; 334} 335 336multiclass SIMDAcrossLanesUnsignedIntrinsicBHS<string baseOpc, 337 Intrinsic intOp> { 338 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 339 (i32 (EXTRACT_SUBREG 340 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 341 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 342 ssub))>; 343 def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 344 (i32 (EXTRACT_SUBREG 345 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 346 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 347 ssub))>; 348 349 def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 350 (i32 (EXTRACT_SUBREG 351 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 352 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 353 ssub))>; 354 def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 355 (i32 (EXTRACT_SUBREG 356 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 357 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 358 ssub))>; 359 360 def : Pat<(i32 (intOp (v4i32 V128:$Rn))), 361 (i32 (EXTRACT_SUBREG 362 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 363 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub), 364 ssub))>; 365} 366 367 368defm : SIMDAcrossLanesSignedIntrinsicBHS<"ADDV", int_aarch64_neon_saddv>; 369// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 370def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))), 371 (i32 (EXTRACT_SUBREG 372 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 373 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub), 374 ssub))>; 375 376defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"ADDV", int_aarch64_neon_uaddv>; 377def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))), 378 (i32 (EXTRACT_SUBREG 379 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 380 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub), 381 ssub))>; 382 383defm : SIMDAcrossLanesSignedIntrinsicBHS<"SMAXV", int_aarch64_neon_smaxv>; 384def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))), 385 (i32 (EXTRACT_SUBREG 386 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 387 (SMAXPv2i32 V64:$Rn, V64:$Rn), dsub), 388 ssub))>; 389 390defm : SIMDAcrossLanesSignedIntrinsicBHS<"SMINV", int_aarch64_neon_sminv>; 391def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))), 392 (i32 (EXTRACT_SUBREG 393 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 394 (SMINPv2i32 V64:$Rn, V64:$Rn), dsub), 395 ssub))>; 396 397defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"UMAXV", int_aarch64_neon_umaxv>; 398def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))), 399 (i32 (EXTRACT_SUBREG 400 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 401 (UMAXPv2i32 V64:$Rn, V64:$Rn), dsub), 402 ssub))>; 403 404defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"UMINV", int_aarch64_neon_uminv>; 405def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))), 406 (i32 (EXTRACT_SUBREG 407 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 408 (UMINPv2i32 V64:$Rn, V64:$Rn), dsub), 409 ssub))>; 410