1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that AArch64 uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 15 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 16 17 #include "AArch64.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 #include "llvm/IR/CallingConv.h" 22 #include "llvm/IR/Instruction.h" 23 24 namespace llvm { 25 26 namespace AArch64ISD { 27 28 enum NodeType : unsigned { 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 31 CALL, // Function call. 32 33 // Produces the full sequence of instructions for getting the thread pointer 34 // offset of a variable into X0, using the TLSDesc model. 35 TLSDESC_CALLSEQ, 36 ADRP, // Page address of a TargetGlobalAddress operand. 37 ADR, // ADR 38 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 39 LOADgot, // Load from automatically generated descriptor (e.g. Global 40 // Offset Table, TLS record). 41 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand. 42 BRCOND, // Conditional branch instruction; "b.cond". 43 CSEL, 44 FCSEL, // Conditional move instruction. 45 CSINV, // Conditional select invert. 46 CSNEG, // Conditional select negate. 47 CSINC, // Conditional select increment. 48 49 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 50 // ELF. 51 THREAD_POINTER, 52 ADC, 53 SBC, // adc, sbc instructions 54 55 // Arithmetic instructions which write flags. 56 ADDS, 57 SUBS, 58 ADCS, 59 SBCS, 60 ANDS, 61 62 // Conditional compares. Operands: left,right,falsecc,cc,flags 63 CCMP, 64 CCMN, 65 FCCMP, 66 67 // Floating point comparison 68 FCMP, 69 70 // Scalar extract 71 EXTR, 72 73 // Scalar-to-vector duplication 74 DUP, 75 DUPLANE8, 76 DUPLANE16, 77 DUPLANE32, 78 DUPLANE64, 79 80 // Vector immedate moves 81 MOVI, 82 MOVIshift, 83 MOVIedit, 84 MOVImsl, 85 FMOV, 86 MVNIshift, 87 MVNImsl, 88 89 // Vector immediate ops 90 BICi, 91 ORRi, 92 93 // Vector bit select: similar to ISD::VSELECT but not all bits within an 94 // element must be identical. 95 BSL, 96 97 // Vector arithmetic negation 98 NEG, 99 100 // Vector shuffles 101 ZIP1, 102 ZIP2, 103 UZP1, 104 UZP2, 105 TRN1, 106 TRN2, 107 REV16, 108 REV32, 109 REV64, 110 EXT, 111 112 // Vector shift by scalar 113 VSHL, 114 VLSHR, 115 VASHR, 116 117 // Vector shift by scalar (again) 118 SQSHL_I, 119 UQSHL_I, 120 SQSHLU_I, 121 SRSHR_I, 122 URSHR_I, 123 124 // Vector comparisons 125 CMEQ, 126 CMGE, 127 CMGT, 128 CMHI, 129 CMHS, 130 FCMEQ, 131 FCMGE, 132 FCMGT, 133 134 // Vector zero comparisons 135 CMEQz, 136 CMGEz, 137 CMGTz, 138 CMLEz, 139 CMLTz, 140 FCMEQz, 141 FCMGEz, 142 FCMGTz, 143 FCMLEz, 144 FCMLTz, 145 146 // Vector across-lanes addition 147 // Only the lower result lane is defined. 148 SADDV, 149 UADDV, 150 151 // Vector across-lanes min/max 152 // Only the lower result lane is defined. 153 SMINV, 154 UMINV, 155 SMAXV, 156 UMAXV, 157 158 SMAXV_PRED, 159 UMAXV_PRED, 160 SMINV_PRED, 161 UMINV_PRED, 162 ORV_PRED, 163 EORV_PRED, 164 ANDV_PRED, 165 166 // Vector bitwise negation 167 NOT, 168 169 // Vector bitwise selection 170 BIT, 171 172 // Compare-and-branch 173 CBZ, 174 CBNZ, 175 TBZ, 176 TBNZ, 177 178 // Tail calls 179 TC_RETURN, 180 181 // Custom prefetch handling 182 PREFETCH, 183 184 // {s|u}int to FP within a FP register. 185 SITOF, 186 UITOF, 187 188 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 189 /// world w.r.t vectors; which causes additional REV instructions to be 190 /// generated to compensate for the byte-swapping. But sometimes we do 191 /// need to re-interpret the data in SIMD vector registers in big-endian 192 /// mode without emitting such REV instructions. 193 NVCAST, 194 195 SMULL, 196 UMULL, 197 198 // Reciprocal estimates and steps. 199 FRECPE, FRECPS, 200 FRSQRTE, FRSQRTS, 201 202 SUNPKHI, 203 SUNPKLO, 204 UUNPKHI, 205 UUNPKLO, 206 207 CLASTA_N, 208 CLASTB_N, 209 LASTA, 210 LASTB, 211 REV, 212 TBL, 213 214 INSR, 215 PTEST, 216 PTRUE, 217 218 // Unsigned gather loads. 219 GLD1, 220 GLD1_SCALED, 221 GLD1_UXTW, 222 GLD1_SXTW, 223 GLD1_UXTW_SCALED, 224 GLD1_SXTW_SCALED, 225 GLD1_IMM, 226 227 // Signed gather loads 228 GLD1S, 229 GLD1S_SCALED, 230 GLD1S_UXTW, 231 GLD1S_SXTW, 232 GLD1S_UXTW_SCALED, 233 GLD1S_SXTW_SCALED, 234 GLD1S_IMM, 235 // Scatter store 236 SST1, 237 SST1_SCALED, 238 SST1_UXTW, 239 SST1_SXTW, 240 SST1_UXTW_SCALED, 241 SST1_SXTW_SCALED, 242 SST1_IMM, 243 244 // NEON Load/Store with post-increment base updates 245 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 246 LD3post, 247 LD4post, 248 ST2post, 249 ST3post, 250 ST4post, 251 LD1x2post, 252 LD1x3post, 253 LD1x4post, 254 ST1x2post, 255 ST1x3post, 256 ST1x4post, 257 LD1DUPpost, 258 LD2DUPpost, 259 LD3DUPpost, 260 LD4DUPpost, 261 LD1LANEpost, 262 LD2LANEpost, 263 LD3LANEpost, 264 LD4LANEpost, 265 ST2LANEpost, 266 ST3LANEpost, 267 ST4LANEpost, 268 269 STG, 270 STZG, 271 ST2G, 272 STZ2G, 273 274 LDP, 275 STP 276 }; 277 278 } // end namespace AArch64ISD 279 280 namespace { 281 282 // Any instruction that defines a 32-bit result zeros out the high half of the 283 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 284 // be copying from a truncate. But any other 32-bit operation will zero-extend 285 // up to 64 bits. 286 // FIXME: X86 also checks for CMOV here. Do we need something similar? 287 static inline bool isDef32(const SDNode &N) { 288 unsigned Opc = N.getOpcode(); 289 return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG && 290 Opc != ISD::CopyFromReg; 291 } 292 293 } // end anonymous namespace 294 295 class AArch64Subtarget; 296 class AArch64TargetMachine; 297 298 class AArch64TargetLowering : public TargetLowering { 299 public: 300 explicit AArch64TargetLowering(const TargetMachine &TM, 301 const AArch64Subtarget &STI); 302 303 /// Selects the correct CCAssignFn for a given CallingConvention value. 304 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 305 306 /// Selects the correct CCAssignFn for a given CallingConvention value. 307 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 308 309 /// Determine which of the bits specified in Mask are known to be either zero 310 /// or one and return them in the KnownZero/KnownOne bitsets. 311 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 312 const APInt &DemandedElts, 313 const SelectionDAG &DAG, 314 unsigned Depth = 0) const override; 315 316 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override { 317 // Returning i64 unconditionally here (i.e. even for ILP32) means that the 318 // *DAG* representation of pointers will always be 64-bits. They will be 319 // truncated and extended when transferred to memory, but the 64-bit DAG 320 // allows us to use AArch64's addressing modes much more easily. 321 return MVT::getIntegerVT(64); 322 } 323 324 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, 325 TargetLoweringOpt &TLO) const override; 326 327 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override; 328 329 /// Returns true if the target allows unaligned memory accesses of the 330 /// specified type. 331 bool allowsMisalignedMemoryAccesses( 332 EVT VT, unsigned AddrSpace = 0, unsigned Align = 1, 333 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 334 bool *Fast = nullptr) const override; 335 /// LLT variant. 336 bool allowsMisalignedMemoryAccesses( 337 LLT Ty, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags, 338 bool *Fast = nullptr) const override; 339 340 /// Provide custom lowering hooks for some operations. 341 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 342 343 const char *getTargetNodeName(unsigned Opcode) const override; 344 345 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 346 347 /// Returns true if a cast between SrcAS and DestAS is a noop. 348 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 349 // Addrspacecasts are always noops. 350 return true; 351 } 352 353 /// This method returns a target specific FastISel object, or null if the 354 /// target does not support "fast" ISel. 355 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 356 const TargetLibraryInfo *libInfo) const override; 357 358 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 359 360 bool isFPImmLegal(const APFloat &Imm, EVT VT, 361 bool ForCodeSize) const override; 362 363 /// Return true if the given shuffle mask can be codegen'd directly, or if it 364 /// should be stack expanded. 365 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 366 367 /// Return the ISD::SETCC ValueType. 368 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 369 EVT VT) const override; 370 371 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 372 373 MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, 374 MachineBasicBlock *BB) const; 375 376 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, 377 MachineBasicBlock *BB) const; 378 379 MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI, 380 MachineBasicBlock *BB) const; 381 382 MachineBasicBlock * 383 EmitInstrWithCustomInserter(MachineInstr &MI, 384 MachineBasicBlock *MBB) const override; 385 386 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 387 MachineFunction &MF, 388 unsigned Intrinsic) const override; 389 390 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 391 EVT NewVT) const override; 392 393 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 394 bool isTruncateFree(EVT VT1, EVT VT2) const override; 395 396 bool isProfitableToHoist(Instruction *I) const override; 397 398 bool isZExtFree(Type *Ty1, Type *Ty2) const override; 399 bool isZExtFree(EVT VT1, EVT VT2) const override; 400 bool isZExtFree(SDValue Val, EVT VT2) const override; 401 402 bool shouldSinkOperands(Instruction *I, 403 SmallVectorImpl<Use *> &Ops) const override; 404 405 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override; 406 407 unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 408 409 bool lowerInterleavedLoad(LoadInst *LI, 410 ArrayRef<ShuffleVectorInst *> Shuffles, 411 ArrayRef<unsigned> Indices, 412 unsigned Factor) const override; 413 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 414 unsigned Factor) const override; 415 416 bool isLegalAddImmediate(int64_t) const override; 417 bool isLegalICmpImmediate(int64_t) const override; 418 419 bool shouldConsiderGEPOffsetSplit() const override; 420 421 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 422 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 423 const AttributeList &FuncAttributes) const override; 424 425 LLT getOptimalMemOpLLT(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 426 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 427 const AttributeList &FuncAttributes) const override; 428 429 /// Return true if the addressing mode represented by AM is legal for this 430 /// target, for a load/store of the specified type. 431 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 432 unsigned AS, 433 Instruction *I = nullptr) const override; 434 435 /// Return the cost of the scaling factor used in the addressing 436 /// mode represented by AM for this target, for a load/store 437 /// of the specified type. 438 /// If the AM is supported, the return value must be >= 0. 439 /// If the AM is not supported, it returns a negative value. 440 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 441 unsigned AS) const override; 442 443 /// Return true if an FMA operation is faster than a pair of fmul and fadd 444 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 445 /// returns true, otherwise fmuladd is expanded to fmul + fadd. 446 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 447 EVT VT) const override; 448 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 449 450 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 451 452 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 453 bool isDesirableToCommuteWithShift(const SDNode *N, 454 CombineLevel Level) const override; 455 456 /// Returns true if it is beneficial to convert a load of a constant 457 /// to just the constant itself. 458 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 459 Type *Ty) const override; 460 461 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 462 /// with this index. 463 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 464 unsigned Index) const override; 465 466 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 467 AtomicOrdering Ord) const override; 468 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 469 Value *Addr, AtomicOrdering Ord) const override; 470 471 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 472 473 TargetLoweringBase::AtomicExpansionKind 474 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 475 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 476 TargetLoweringBase::AtomicExpansionKind 477 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 478 479 TargetLoweringBase::AtomicExpansionKind 480 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 481 482 bool useLoadStackGuardNode() const override; 483 TargetLoweringBase::LegalizeTypeAction 484 getPreferredVectorAction(MVT VT) const override; 485 486 /// If the target has a standard location for the stack protector cookie, 487 /// returns the address of that location. Otherwise, returns nullptr. 488 Value *getIRStackGuard(IRBuilder<> &IRB) const override; 489 490 void insertSSPDeclarations(Module &M) const override; 491 Value *getSDagStackGuard(const Module &M) const override; 492 Function *getSSPStackGuardCheck(const Module &M) const override; 493 494 /// If the target has a standard location for the unsafe stack pointer, 495 /// returns the address of that location. Otherwise, returns nullptr. 496 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override; 497 498 /// If a physical register, this returns the register that receives the 499 /// exception address on entry to an EH pad. 500 unsigned 501 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 502 // FIXME: This is a guess. Has this been defined yet? 503 return AArch64::X0; 504 } 505 506 /// If a physical register, this returns the register that receives the 507 /// exception typeid on entry to a landing pad. 508 unsigned 509 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 510 // FIXME: This is a guess. Has this been defined yet? 511 return AArch64::X1; 512 } 513 514 bool isIntDivCheap(EVT VT, AttributeList Attr) const override; 515 516 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 517 const SelectionDAG &DAG) const override { 518 // Do not merge to float value size (128 bytes) if no implicit 519 // float attribute is set. 520 521 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute( 522 Attribute::NoImplicitFloat); 523 524 if (NoFloat) 525 return (MemVT.getSizeInBits() <= 64); 526 return true; 527 } 528 529 bool isCheapToSpeculateCttz() const override { 530 return true; 531 } 532 533 bool isCheapToSpeculateCtlz() const override { 534 return true; 535 } 536 537 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 538 539 bool hasAndNotCompare(SDValue V) const override { 540 // We can use bics for any scalar. 541 return V.getValueType().isScalarInteger(); 542 } 543 544 bool hasAndNot(SDValue Y) const override { 545 EVT VT = Y.getValueType(); 546 547 if (!VT.isVector()) 548 return hasAndNotCompare(Y); 549 550 return VT.getSizeInBits() >= 64; // vector 'bic' 551 } 552 553 bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 554 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 555 unsigned OldShiftOpcode, unsigned NewShiftOpcode, 556 SelectionDAG &DAG) const override; 557 558 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; 559 560 bool shouldTransformSignedTruncationCheck(EVT XVT, 561 unsigned KeptBits) const override { 562 // For vectors, we don't have a preference.. 563 if (XVT.isVector()) 564 return false; 565 566 auto VTIsOk = [](EVT VT) -> bool { 567 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 568 VT == MVT::i64; 569 }; 570 571 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports. 572 // XVT will be larger than KeptBitsVT. 573 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); 574 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); 575 } 576 577 bool preferIncOfAddToSubOfNot(EVT VT) const override; 578 579 bool hasBitPreservingFPLogic(EVT VT) const override { 580 // FIXME: Is this always true? It should be true for vectors at least. 581 return VT == MVT::f32 || VT == MVT::f64; 582 } 583 584 bool supportSplitCSR(MachineFunction *MF) const override { 585 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 586 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 587 } 588 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 589 void insertCopiesSplitCSR( 590 MachineBasicBlock *Entry, 591 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 592 593 bool supportSwiftError() const override { 594 return true; 595 } 596 597 /// Enable aggressive FMA fusion on targets that want it. 598 bool enableAggressiveFMAFusion(EVT VT) const override; 599 600 /// Returns the size of the platform's va_list object. 601 unsigned getVaListSizeInBits(const DataLayout &DL) const override; 602 603 /// Returns true if \p VecTy is a legal interleaved access type. This 604 /// function checks the vector element type and the overall width of the 605 /// vector. 606 bool isLegalInterleavedAccessType(VectorType *VecTy, 607 const DataLayout &DL) const; 608 609 /// Returns the number of interleaved accesses that will be generated when 610 /// lowering accesses of the given type. 611 unsigned getNumInterleavedAccesses(VectorType *VecTy, 612 const DataLayout &DL) const; 613 614 MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override; 615 616 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, 617 CallingConv::ID CallConv, 618 bool isVarArg) const override; 619 /// Used for exception handling on Win64. 620 bool needsFixedCatchObjects() const override; 621 private: 622 /// Keep a pointer to the AArch64Subtarget around so that we can 623 /// make the right decision when generating code for different targets. 624 const AArch64Subtarget *Subtarget; 625 626 bool isExtFreeImpl(const Instruction *Ext) const override; 627 628 void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT); 629 void addDRTypeForNEON(MVT VT); 630 void addQRTypeForNEON(MVT VT); 631 632 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 633 bool isVarArg, 634 const SmallVectorImpl<ISD::InputArg> &Ins, 635 const SDLoc &DL, SelectionDAG &DAG, 636 SmallVectorImpl<SDValue> &InVals) const override; 637 638 SDValue LowerCall(CallLoweringInfo & /*CLI*/, 639 SmallVectorImpl<SDValue> &InVals) const override; 640 641 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 642 CallingConv::ID CallConv, bool isVarArg, 643 const SmallVectorImpl<ISD::InputArg> &Ins, 644 const SDLoc &DL, SelectionDAG &DAG, 645 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 646 SDValue ThisVal) const; 647 648 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 649 650 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 651 652 bool isEligibleForTailCallOptimization( 653 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 654 const SmallVectorImpl<ISD::OutputArg> &Outs, 655 const SmallVectorImpl<SDValue> &OutVals, 656 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 657 658 /// Finds the incoming stack arguments which overlap the given fixed stack 659 /// object and incorporates their load into the current chain. This prevents 660 /// an upcoming store from clobbering the stack argument before it's used. 661 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 662 MachineFrameInfo &MFI, int ClobberedFI) const; 663 664 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 665 666 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, 667 SDValue &Chain) const; 668 669 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 670 bool isVarArg, 671 const SmallVectorImpl<ISD::OutputArg> &Outs, 672 LLVMContext &Context) const override; 673 674 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 675 const SmallVectorImpl<ISD::OutputArg> &Outs, 676 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 677 SelectionDAG &DAG) const override; 678 679 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 680 unsigned Flag) const; 681 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 682 unsigned Flag) const; 683 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 684 unsigned Flag) const; 685 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 686 unsigned Flag) const; 687 template <class NodeTy> 688 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 689 template <class NodeTy> 690 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 691 template <class NodeTy> 692 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 693 template <class NodeTy> 694 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 695 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 696 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 697 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 698 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 699 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 700 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase, 701 const SDLoc &DL, SelectionDAG &DAG) const; 702 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL, 703 SelectionDAG &DAG) const; 704 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 705 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 706 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 707 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 708 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 709 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 710 SDValue TVal, SDValue FVal, const SDLoc &dl, 711 SelectionDAG &DAG) const; 712 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 713 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 714 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 715 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 716 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 717 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 718 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const; 719 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 720 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 721 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 722 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 723 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 724 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 725 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 726 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 727 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 728 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 729 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 730 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 731 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const; 732 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 733 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 734 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 735 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 736 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 737 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 738 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG, 739 RTLIB::Libcall Call) const; 740 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 741 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 742 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 743 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 744 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 745 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 746 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 747 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 748 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 749 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 750 SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 751 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const; 752 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 753 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain, 754 SDValue &Size, 755 SelectionDAG &DAG) const; 756 757 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 758 SmallVectorImpl<SDNode *> &Created) const override; 759 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 760 int &ExtraSteps, bool &UseOneConst, 761 bool Reciprocal) const override; 762 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 763 int &ExtraSteps) const override; 764 unsigned combineRepeatedFPDivisors() const override; 765 766 ConstraintType getConstraintType(StringRef Constraint) const override; 767 Register getRegisterByName(const char* RegName, LLT VT, 768 const MachineFunction &MF) const override; 769 770 /// Examine constraint string and operand type and determine a weight value. 771 /// The operand object must already have been set up with the operand type. 772 ConstraintWeight 773 getSingleConstraintMatchWeight(AsmOperandInfo &info, 774 const char *constraint) const override; 775 776 std::pair<unsigned, const TargetRegisterClass *> 777 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 778 StringRef Constraint, MVT VT) const override; 779 780 const char *LowerXConstraint(EVT ConstraintVT) const override; 781 782 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 783 std::vector<SDValue> &Ops, 784 SelectionDAG &DAG) const override; 785 786 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 787 if (ConstraintCode == "Q") 788 return InlineAsm::Constraint_Q; 789 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 790 // followed by llvm_unreachable so we'll leave them unimplemented in 791 // the backend for now. 792 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 793 } 794 795 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 796 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 797 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 798 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, 799 ISD::MemIndexedMode &AM, bool &IsInc, 800 SelectionDAG &DAG) const; 801 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 802 ISD::MemIndexedMode &AM, 803 SelectionDAG &DAG) const override; 804 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 805 SDValue &Offset, ISD::MemIndexedMode &AM, 806 SelectionDAG &DAG) const override; 807 808 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 809 SelectionDAG &DAG) const override; 810 811 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; 812 813 void finalizeLowering(MachineFunction &MF) const override; 814 }; 815 816 namespace AArch64 { 817 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 818 const TargetLibraryInfo *libInfo); 819 } // end namespace AArch64 820 821 } // end namespace llvm 822 823 #endif 824