10b57cec5SDimitry Andric //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the interfaces that AArch64 uses to lower LLVM code into a 100b57cec5SDimitry Andric // selection DAG. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "AArch64.h" 18bdd1243dSDimitry Andric #include "Utils/AArch64SMEAttributes.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/CallingConvLower.h" 20fe6060f1SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/SelectionDAG.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 230b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h" 240b57cec5SDimitry Andric #include "llvm/IR/Instruction.h" 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric namespace llvm { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric namespace AArch64ISD { 290b57cec5SDimitry Andric 305ffd83dbSDimitry Andric // For predicated nodes where the result is a vector, the operation is 315ffd83dbSDimitry Andric // controlled by a governing predicate and the inactive lanes are explicitly 325ffd83dbSDimitry Andric // defined with a value, please stick the following naming convention: 335ffd83dbSDimitry Andric // 345ffd83dbSDimitry Andric // _MERGE_OP<n> The result value is a vector with inactive lanes equal 355ffd83dbSDimitry Andric // to source operand OP<n>. 365ffd83dbSDimitry Andric // 375ffd83dbSDimitry Andric // _MERGE_ZERO The result value is a vector with inactive lanes 385ffd83dbSDimitry Andric // actively zeroed. 395ffd83dbSDimitry Andric // 405ffd83dbSDimitry Andric // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal 415ffd83dbSDimitry Andric // to the last source operand which only purpose is being 425ffd83dbSDimitry Andric // a passthru value. 435ffd83dbSDimitry Andric // 445ffd83dbSDimitry Andric // For other cases where no explicit action is needed to set the inactive lanes, 455ffd83dbSDimitry Andric // or when the result is not a vector and it is needed or helpful to 465ffd83dbSDimitry Andric // distinguish a node from similar unpredicated nodes, use: 475ffd83dbSDimitry Andric // 485ffd83dbSDimitry Andric // _PRED 495ffd83dbSDimitry Andric // 500b57cec5SDimitry Andric enum NodeType : unsigned { 510b57cec5SDimitry Andric FIRST_NUMBER = ISD::BUILTIN_OP_END, 520b57cec5SDimitry Andric WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 530b57cec5SDimitry Andric CALL, // Function call. 540b57cec5SDimitry Andric 55fe6060f1SDimitry Andric // Pseudo for a OBJC call that gets emitted together with a special `mov 56fe6060f1SDimitry Andric // x29, x29` marker instruction. 57fe6060f1SDimitry Andric CALL_RVMARKER, 58fe6060f1SDimitry Andric 593a9a9c0cSDimitry Andric CALL_BTI, // Function call followed by a BTI instruction. 603a9a9c0cSDimitry Andric 61bdd1243dSDimitry Andric SMSTART, 62bdd1243dSDimitry Andric SMSTOP, 63bdd1243dSDimitry Andric RESTORE_ZA, 64*7a6dacacSDimitry Andric RESTORE_ZT, 65*7a6dacacSDimitry Andric SAVE_ZT, 66*7a6dacacSDimitry Andric 67*7a6dacacSDimitry Andric // A call with the callee in x16, i.e. "blr x16". 68*7a6dacacSDimitry Andric CALL_ARM64EC_TO_X64, 69bdd1243dSDimitry Andric 700b57cec5SDimitry Andric // Produces the full sequence of instructions for getting the thread pointer 710b57cec5SDimitry Andric // offset of a variable into X0, using the TLSDesc model. 720b57cec5SDimitry Andric TLSDESC_CALLSEQ, 730b57cec5SDimitry Andric ADRP, // Page address of a TargetGlobalAddress operand. 740b57cec5SDimitry Andric ADR, // ADR 750b57cec5SDimitry Andric ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 760b57cec5SDimitry Andric LOADgot, // Load from automatically generated descriptor (e.g. Global 770b57cec5SDimitry Andric // Offset Table, TLS record). 7806c3fb27SDimitry Andric RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand. 790b57cec5SDimitry Andric BRCOND, // Conditional branch instruction; "b.cond". 800b57cec5SDimitry Andric CSEL, 810b57cec5SDimitry Andric CSINV, // Conditional select invert. 820b57cec5SDimitry Andric CSNEG, // Conditional select negate. 830b57cec5SDimitry Andric CSINC, // Conditional select increment. 840b57cec5SDimitry Andric 850b57cec5SDimitry Andric // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 860b57cec5SDimitry Andric // ELF. 870b57cec5SDimitry Andric THREAD_POINTER, 880b57cec5SDimitry Andric ADC, 890b57cec5SDimitry Andric SBC, // adc, sbc instructions 900b57cec5SDimitry Andric 915f757f3fSDimitry Andric // To avoid stack clash, allocation is performed by block and each block is 925f757f3fSDimitry Andric // probed. 935f757f3fSDimitry Andric PROBED_ALLOCA, 945f757f3fSDimitry Andric 95e8d8bef9SDimitry Andric // Predicated instructions where inactive lanes produce undefined results. 9604eeddc0SDimitry Andric ABDS_PRED, 9704eeddc0SDimitry Andric ABDU_PRED, 985ffd83dbSDimitry Andric FADD_PRED, 99e8d8bef9SDimitry Andric FDIV_PRED, 1005ffd83dbSDimitry Andric FMA_PRED, 101fe6060f1SDimitry Andric FMAX_PRED, 10204eeddc0SDimitry Andric FMAXNM_PRED, 103fe6060f1SDimitry Andric FMIN_PRED, 10404eeddc0SDimitry Andric FMINNM_PRED, 105e8d8bef9SDimitry Andric FMUL_PRED, 106e8d8bef9SDimitry Andric FSUB_PRED, 107bdd1243dSDimitry Andric HADDS_PRED, 108bdd1243dSDimitry Andric HADDU_PRED, 109e8d8bef9SDimitry Andric MUL_PRED, 110fe6060f1SDimitry Andric MULHS_PRED, 111fe6060f1SDimitry Andric MULHU_PRED, 112bdd1243dSDimitry Andric RHADDS_PRED, 113bdd1243dSDimitry Andric RHADDU_PRED, 114e8d8bef9SDimitry Andric SDIV_PRED, 115e8d8bef9SDimitry Andric SHL_PRED, 116e8d8bef9SDimitry Andric SMAX_PRED, 117e8d8bef9SDimitry Andric SMIN_PRED, 118e8d8bef9SDimitry Andric SRA_PRED, 119e8d8bef9SDimitry Andric SRL_PRED, 120e8d8bef9SDimitry Andric UDIV_PRED, 121e8d8bef9SDimitry Andric UMAX_PRED, 122e8d8bef9SDimitry Andric UMIN_PRED, 123e8d8bef9SDimitry Andric 124fe6060f1SDimitry Andric // Unpredicated vector instructions 125fe6060f1SDimitry Andric BIC, 126fe6060f1SDimitry Andric 1274824e7fdSDimitry Andric SRAD_MERGE_OP1, 1284824e7fdSDimitry Andric 129e8d8bef9SDimitry Andric // Predicated instructions with the result of inactive lanes provided by the 130e8d8bef9SDimitry Andric // last operand. 131e8d8bef9SDimitry Andric FABS_MERGE_PASSTHRU, 132e8d8bef9SDimitry Andric FCEIL_MERGE_PASSTHRU, 133e8d8bef9SDimitry Andric FFLOOR_MERGE_PASSTHRU, 134e8d8bef9SDimitry Andric FNEARBYINT_MERGE_PASSTHRU, 135e8d8bef9SDimitry Andric FNEG_MERGE_PASSTHRU, 136e8d8bef9SDimitry Andric FRECPX_MERGE_PASSTHRU, 137e8d8bef9SDimitry Andric FRINT_MERGE_PASSTHRU, 138e8d8bef9SDimitry Andric FROUND_MERGE_PASSTHRU, 139e8d8bef9SDimitry Andric FROUNDEVEN_MERGE_PASSTHRU, 140e8d8bef9SDimitry Andric FSQRT_MERGE_PASSTHRU, 141e8d8bef9SDimitry Andric FTRUNC_MERGE_PASSTHRU, 142e8d8bef9SDimitry Andric FP_ROUND_MERGE_PASSTHRU, 143e8d8bef9SDimitry Andric FP_EXTEND_MERGE_PASSTHRU, 144e8d8bef9SDimitry Andric UINT_TO_FP_MERGE_PASSTHRU, 145e8d8bef9SDimitry Andric SINT_TO_FP_MERGE_PASSTHRU, 146e8d8bef9SDimitry Andric FCVTZU_MERGE_PASSTHRU, 147e8d8bef9SDimitry Andric FCVTZS_MERGE_PASSTHRU, 148e8d8bef9SDimitry Andric SIGN_EXTEND_INREG_MERGE_PASSTHRU, 149e8d8bef9SDimitry Andric ZERO_EXTEND_INREG_MERGE_PASSTHRU, 150e8d8bef9SDimitry Andric ABS_MERGE_PASSTHRU, 151e8d8bef9SDimitry Andric NEG_MERGE_PASSTHRU, 1525ffd83dbSDimitry Andric 1535ffd83dbSDimitry Andric SETCC_MERGE_ZERO, 1545ffd83dbSDimitry Andric 1550b57cec5SDimitry Andric // Arithmetic instructions which write flags. 1560b57cec5SDimitry Andric ADDS, 1570b57cec5SDimitry Andric SUBS, 1580b57cec5SDimitry Andric ADCS, 1590b57cec5SDimitry Andric SBCS, 1600b57cec5SDimitry Andric ANDS, 1610b57cec5SDimitry Andric 1620b57cec5SDimitry Andric // Conditional compares. Operands: left,right,falsecc,cc,flags 1630b57cec5SDimitry Andric CCMP, 1640b57cec5SDimitry Andric CCMN, 1650b57cec5SDimitry Andric FCCMP, 1660b57cec5SDimitry Andric 1670b57cec5SDimitry Andric // Floating point comparison 1680b57cec5SDimitry Andric FCMP, 1690b57cec5SDimitry Andric 1700b57cec5SDimitry Andric // Scalar-to-vector duplication 1710b57cec5SDimitry Andric DUP, 1720b57cec5SDimitry Andric DUPLANE8, 1730b57cec5SDimitry Andric DUPLANE16, 1740b57cec5SDimitry Andric DUPLANE32, 1750b57cec5SDimitry Andric DUPLANE64, 17681ad6265SDimitry Andric DUPLANE128, 1770b57cec5SDimitry Andric 1780b57cec5SDimitry Andric // Vector immedate moves 1790b57cec5SDimitry Andric MOVI, 1800b57cec5SDimitry Andric MOVIshift, 1810b57cec5SDimitry Andric MOVIedit, 1820b57cec5SDimitry Andric MOVImsl, 1830b57cec5SDimitry Andric FMOV, 1840b57cec5SDimitry Andric MVNIshift, 1850b57cec5SDimitry Andric MVNImsl, 1860b57cec5SDimitry Andric 1870b57cec5SDimitry Andric // Vector immediate ops 1880b57cec5SDimitry Andric BICi, 1890b57cec5SDimitry Andric ORRi, 1900b57cec5SDimitry Andric 1915ffd83dbSDimitry Andric // Vector bitwise select: similar to ISD::VSELECT but not all bits within an 1920b57cec5SDimitry Andric // element must be identical. 1935ffd83dbSDimitry Andric BSP, 1940b57cec5SDimitry Andric 1950b57cec5SDimitry Andric // Vector shuffles 1960b57cec5SDimitry Andric ZIP1, 1970b57cec5SDimitry Andric ZIP2, 1980b57cec5SDimitry Andric UZP1, 1990b57cec5SDimitry Andric UZP2, 2000b57cec5SDimitry Andric TRN1, 2010b57cec5SDimitry Andric TRN2, 2020b57cec5SDimitry Andric REV16, 2030b57cec5SDimitry Andric REV32, 2040b57cec5SDimitry Andric REV64, 2050b57cec5SDimitry Andric EXT, 206fe6060f1SDimitry Andric SPLICE, 2070b57cec5SDimitry Andric 2080b57cec5SDimitry Andric // Vector shift by scalar 2090b57cec5SDimitry Andric VSHL, 2100b57cec5SDimitry Andric VLSHR, 2110b57cec5SDimitry Andric VASHR, 2120b57cec5SDimitry Andric 2130b57cec5SDimitry Andric // Vector shift by scalar (again) 2140b57cec5SDimitry Andric SQSHL_I, 2150b57cec5SDimitry Andric UQSHL_I, 2160b57cec5SDimitry Andric SQSHLU_I, 2170b57cec5SDimitry Andric SRSHR_I, 2180b57cec5SDimitry Andric URSHR_I, 2190b57cec5SDimitry Andric 2205f757f3fSDimitry Andric // Vector narrowing shift by immediate (bottom) 2215f757f3fSDimitry Andric RSHRNB_I, 2225f757f3fSDimitry Andric 2235ffd83dbSDimitry Andric // Vector shift by constant and insert 2245ffd83dbSDimitry Andric VSLI, 2255ffd83dbSDimitry Andric VSRI, 2265ffd83dbSDimitry Andric 2270b57cec5SDimitry Andric // Vector comparisons 2280b57cec5SDimitry Andric CMEQ, 2290b57cec5SDimitry Andric CMGE, 2300b57cec5SDimitry Andric CMGT, 2310b57cec5SDimitry Andric CMHI, 2320b57cec5SDimitry Andric CMHS, 2330b57cec5SDimitry Andric FCMEQ, 2340b57cec5SDimitry Andric FCMGE, 2350b57cec5SDimitry Andric FCMGT, 2360b57cec5SDimitry Andric 2370b57cec5SDimitry Andric // Vector zero comparisons 2380b57cec5SDimitry Andric CMEQz, 2390b57cec5SDimitry Andric CMGEz, 2400b57cec5SDimitry Andric CMGTz, 2410b57cec5SDimitry Andric CMLEz, 2420b57cec5SDimitry Andric CMLTz, 2430b57cec5SDimitry Andric FCMEQz, 2440b57cec5SDimitry Andric FCMGEz, 2450b57cec5SDimitry Andric FCMGTz, 2460b57cec5SDimitry Andric FCMLEz, 2470b57cec5SDimitry Andric FCMLTz, 2480b57cec5SDimitry Andric 2490b57cec5SDimitry Andric // Vector across-lanes addition 2500b57cec5SDimitry Andric // Only the lower result lane is defined. 2510b57cec5SDimitry Andric SADDV, 2520b57cec5SDimitry Andric UADDV, 2530b57cec5SDimitry Andric 2545f757f3fSDimitry Andric // Unsigned sum Long across Vector 2555f757f3fSDimitry Andric UADDLV, 256*7a6dacacSDimitry Andric SADDLV, 2575f757f3fSDimitry Andric 25881ad6265SDimitry Andric // Add Pairwise of two vectors 25981ad6265SDimitry Andric ADDP, 26081ad6265SDimitry Andric // Add Long Pairwise 26181ad6265SDimitry Andric SADDLP, 262fe6060f1SDimitry Andric UADDLP, 263fe6060f1SDimitry Andric 264fe6060f1SDimitry Andric // udot/sdot instructions 265fe6060f1SDimitry Andric UDOT, 266fe6060f1SDimitry Andric SDOT, 267e8d8bef9SDimitry Andric 2680b57cec5SDimitry Andric // Vector across-lanes min/max 2690b57cec5SDimitry Andric // Only the lower result lane is defined. 2700b57cec5SDimitry Andric SMINV, 2710b57cec5SDimitry Andric UMINV, 2720b57cec5SDimitry Andric SMAXV, 2730b57cec5SDimitry Andric UMAXV, 2740b57cec5SDimitry Andric 275e8d8bef9SDimitry Andric SADDV_PRED, 276e8d8bef9SDimitry Andric UADDV_PRED, 277480093f4SDimitry Andric SMAXV_PRED, 278480093f4SDimitry Andric UMAXV_PRED, 279480093f4SDimitry Andric SMINV_PRED, 280480093f4SDimitry Andric UMINV_PRED, 281480093f4SDimitry Andric ORV_PRED, 282480093f4SDimitry Andric EORV_PRED, 283480093f4SDimitry Andric ANDV_PRED, 284480093f4SDimitry Andric 2855ffd83dbSDimitry Andric // Vector bitwise insertion 2860b57cec5SDimitry Andric BIT, 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andric // Compare-and-branch 2890b57cec5SDimitry Andric CBZ, 2900b57cec5SDimitry Andric CBNZ, 2910b57cec5SDimitry Andric TBZ, 2920b57cec5SDimitry Andric TBNZ, 2930b57cec5SDimitry Andric 2940b57cec5SDimitry Andric // Tail calls 2950b57cec5SDimitry Andric TC_RETURN, 2960b57cec5SDimitry Andric 2970b57cec5SDimitry Andric // Custom prefetch handling 2980b57cec5SDimitry Andric PREFETCH, 2990b57cec5SDimitry Andric 3000b57cec5SDimitry Andric // {s|u}int to FP within a FP register. 3010b57cec5SDimitry Andric SITOF, 3020b57cec5SDimitry Andric UITOF, 3030b57cec5SDimitry Andric 3040b57cec5SDimitry Andric /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 3050b57cec5SDimitry Andric /// world w.r.t vectors; which causes additional REV instructions to be 3060b57cec5SDimitry Andric /// generated to compensate for the byte-swapping. But sometimes we do 3070b57cec5SDimitry Andric /// need to re-interpret the data in SIMD vector registers in big-endian 3080b57cec5SDimitry Andric /// mode without emitting such REV instructions. 3090b57cec5SDimitry Andric NVCAST, 3100b57cec5SDimitry Andric 311fe6060f1SDimitry Andric MRS, // MRS, also sets the flags via a glue. 312fe6060f1SDimitry Andric 3130b57cec5SDimitry Andric SMULL, 3140b57cec5SDimitry Andric UMULL, 3150b57cec5SDimitry Andric 316bdd1243dSDimitry Andric PMULL, 317bdd1243dSDimitry Andric 3180b57cec5SDimitry Andric // Reciprocal estimates and steps. 3195ffd83dbSDimitry Andric FRECPE, 3205ffd83dbSDimitry Andric FRECPS, 3215ffd83dbSDimitry Andric FRSQRTE, 3225ffd83dbSDimitry Andric FRSQRTS, 3230b57cec5SDimitry Andric 3248bcb0991SDimitry Andric SUNPKHI, 3258bcb0991SDimitry Andric SUNPKLO, 3268bcb0991SDimitry Andric UUNPKHI, 3278bcb0991SDimitry Andric UUNPKLO, 3288bcb0991SDimitry Andric 329480093f4SDimitry Andric CLASTA_N, 330480093f4SDimitry Andric CLASTB_N, 331480093f4SDimitry Andric LASTA, 332480093f4SDimitry Andric LASTB, 333480093f4SDimitry Andric TBL, 334480093f4SDimitry Andric 3355ffd83dbSDimitry Andric // Floating-point reductions. 3365ffd83dbSDimitry Andric FADDA_PRED, 3375ffd83dbSDimitry Andric FADDV_PRED, 3385ffd83dbSDimitry Andric FMAXV_PRED, 3395ffd83dbSDimitry Andric FMAXNMV_PRED, 3405ffd83dbSDimitry Andric FMINV_PRED, 3415ffd83dbSDimitry Andric FMINNMV_PRED, 3425ffd83dbSDimitry Andric 343480093f4SDimitry Andric INSR, 344480093f4SDimitry Andric PTEST, 345bdd1243dSDimitry Andric PTEST_ANY, 346480093f4SDimitry Andric PTRUE, 347480093f4SDimitry Andric 3485f757f3fSDimitry Andric CTTZ_ELTS, 3495f757f3fSDimitry Andric 350e8d8bef9SDimitry Andric BITREVERSE_MERGE_PASSTHRU, 351e8d8bef9SDimitry Andric BSWAP_MERGE_PASSTHRU, 3520eae32dcSDimitry Andric REVH_MERGE_PASSTHRU, 3530eae32dcSDimitry Andric REVW_MERGE_PASSTHRU, 354e8d8bef9SDimitry Andric CTLZ_MERGE_PASSTHRU, 355e8d8bef9SDimitry Andric CTPOP_MERGE_PASSTHRU, 3565ffd83dbSDimitry Andric DUP_MERGE_PASSTHRU, 3575ffd83dbSDimitry Andric INDEX_VECTOR, 3585ffd83dbSDimitry Andric 359e8d8bef9SDimitry Andric // Cast between vectors of the same element type but differ in length. 3605ffd83dbSDimitry Andric REINTERPRET_CAST, 3615ffd83dbSDimitry Andric 3626e75b2fbSDimitry Andric // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa 3636e75b2fbSDimitry Andric LS64_BUILD, 3646e75b2fbSDimitry Andric LS64_EXTRACT, 3656e75b2fbSDimitry Andric 3665ffd83dbSDimitry Andric LD1_MERGE_ZERO, 3675ffd83dbSDimitry Andric LD1S_MERGE_ZERO, 3685ffd83dbSDimitry Andric LDNF1_MERGE_ZERO, 3695ffd83dbSDimitry Andric LDNF1S_MERGE_ZERO, 3705ffd83dbSDimitry Andric LDFF1_MERGE_ZERO, 3715ffd83dbSDimitry Andric LDFF1S_MERGE_ZERO, 3725ffd83dbSDimitry Andric LD1RQ_MERGE_ZERO, 3735ffd83dbSDimitry Andric LD1RO_MERGE_ZERO, 3745ffd83dbSDimitry Andric 3755ffd83dbSDimitry Andric // Structured loads. 3765ffd83dbSDimitry Andric SVE_LD2_MERGE_ZERO, 3775ffd83dbSDimitry Andric SVE_LD3_MERGE_ZERO, 3785ffd83dbSDimitry Andric SVE_LD4_MERGE_ZERO, 3795ffd83dbSDimitry Andric 380480093f4SDimitry Andric // Unsigned gather loads. 3815ffd83dbSDimitry Andric GLD1_MERGE_ZERO, 3825ffd83dbSDimitry Andric GLD1_SCALED_MERGE_ZERO, 3835ffd83dbSDimitry Andric GLD1_UXTW_MERGE_ZERO, 3845ffd83dbSDimitry Andric GLD1_SXTW_MERGE_ZERO, 3855ffd83dbSDimitry Andric GLD1_UXTW_SCALED_MERGE_ZERO, 3865ffd83dbSDimitry Andric GLD1_SXTW_SCALED_MERGE_ZERO, 3875ffd83dbSDimitry Andric GLD1_IMM_MERGE_ZERO, 3885f757f3fSDimitry Andric GLD1Q_MERGE_ZERO, 3895f757f3fSDimitry Andric GLD1Q_INDEX_MERGE_ZERO, 390480093f4SDimitry Andric 391480093f4SDimitry Andric // Signed gather loads 3925ffd83dbSDimitry Andric GLD1S_MERGE_ZERO, 3935ffd83dbSDimitry Andric GLD1S_SCALED_MERGE_ZERO, 3945ffd83dbSDimitry Andric GLD1S_UXTW_MERGE_ZERO, 3955ffd83dbSDimitry Andric GLD1S_SXTW_MERGE_ZERO, 3965ffd83dbSDimitry Andric GLD1S_UXTW_SCALED_MERGE_ZERO, 3975ffd83dbSDimitry Andric GLD1S_SXTW_SCALED_MERGE_ZERO, 3985ffd83dbSDimitry Andric GLD1S_IMM_MERGE_ZERO, 3995ffd83dbSDimitry Andric 4005ffd83dbSDimitry Andric // Unsigned gather loads. 4015ffd83dbSDimitry Andric GLDFF1_MERGE_ZERO, 4025ffd83dbSDimitry Andric GLDFF1_SCALED_MERGE_ZERO, 4035ffd83dbSDimitry Andric GLDFF1_UXTW_MERGE_ZERO, 4045ffd83dbSDimitry Andric GLDFF1_SXTW_MERGE_ZERO, 4055ffd83dbSDimitry Andric GLDFF1_UXTW_SCALED_MERGE_ZERO, 4065ffd83dbSDimitry Andric GLDFF1_SXTW_SCALED_MERGE_ZERO, 4075ffd83dbSDimitry Andric GLDFF1_IMM_MERGE_ZERO, 4085ffd83dbSDimitry Andric 4095ffd83dbSDimitry Andric // Signed gather loads. 4105ffd83dbSDimitry Andric GLDFF1S_MERGE_ZERO, 4115ffd83dbSDimitry Andric GLDFF1S_SCALED_MERGE_ZERO, 4125ffd83dbSDimitry Andric GLDFF1S_UXTW_MERGE_ZERO, 4135ffd83dbSDimitry Andric GLDFF1S_SXTW_MERGE_ZERO, 4145ffd83dbSDimitry Andric GLDFF1S_UXTW_SCALED_MERGE_ZERO, 4155ffd83dbSDimitry Andric GLDFF1S_SXTW_SCALED_MERGE_ZERO, 4165ffd83dbSDimitry Andric GLDFF1S_IMM_MERGE_ZERO, 4175ffd83dbSDimitry Andric 4185ffd83dbSDimitry Andric // Non-temporal gather loads 4195ffd83dbSDimitry Andric GLDNT1_MERGE_ZERO, 4205ffd83dbSDimitry Andric GLDNT1_INDEX_MERGE_ZERO, 4215ffd83dbSDimitry Andric GLDNT1S_MERGE_ZERO, 4225ffd83dbSDimitry Andric 4235ffd83dbSDimitry Andric // Contiguous masked store. 4245ffd83dbSDimitry Andric ST1_PRED, 4255ffd83dbSDimitry Andric 426480093f4SDimitry Andric // Scatter store 4275ffd83dbSDimitry Andric SST1_PRED, 4285ffd83dbSDimitry Andric SST1_SCALED_PRED, 4295ffd83dbSDimitry Andric SST1_UXTW_PRED, 4305ffd83dbSDimitry Andric SST1_SXTW_PRED, 4315ffd83dbSDimitry Andric SST1_UXTW_SCALED_PRED, 4325ffd83dbSDimitry Andric SST1_SXTW_SCALED_PRED, 4335ffd83dbSDimitry Andric SST1_IMM_PRED, 4345f757f3fSDimitry Andric SST1Q_PRED, 4355f757f3fSDimitry Andric SST1Q_INDEX_PRED, 4365ffd83dbSDimitry Andric 4375ffd83dbSDimitry Andric // Non-temporal scatter store 4385ffd83dbSDimitry Andric SSTNT1_PRED, 4395ffd83dbSDimitry Andric SSTNT1_INDEX_PRED, 440480093f4SDimitry Andric 44181ad6265SDimitry Andric // SME 44281ad6265SDimitry Andric RDSVL, 44381ad6265SDimitry Andric REVD_MERGE_PASSTHRU, 44481ad6265SDimitry Andric 445349cc55cSDimitry Andric // Asserts that a function argument (i32) is zero-extended to i8 by 446349cc55cSDimitry Andric // the caller 447349cc55cSDimitry Andric ASSERT_ZEXT_BOOL, 448349cc55cSDimitry Andric 449bdd1243dSDimitry Andric // 128-bit system register accesses 450bdd1243dSDimitry Andric // lo64, hi64, chain = MRRS(chain, sysregname) 451bdd1243dSDimitry Andric MRRS, 452bdd1243dSDimitry Andric // chain = MSRR(chain, sysregname, lo64, hi64) 453bdd1243dSDimitry Andric MSRR, 454bdd1243dSDimitry Andric 45547395794SDimitry Andric // Strict (exception-raising) floating point comparison 45647395794SDimitry Andric STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 45747395794SDimitry Andric STRICT_FCMPE, 45847395794SDimitry Andric 4595f757f3fSDimitry Andric // SME ZA loads and stores 4605f757f3fSDimitry Andric SME_ZA_LDR, 4615f757f3fSDimitry Andric SME_ZA_STR, 4625f757f3fSDimitry Andric 4630b57cec5SDimitry Andric // NEON Load/Store with post-increment base updates 4640b57cec5SDimitry Andric LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 4650b57cec5SDimitry Andric LD3post, 4660b57cec5SDimitry Andric LD4post, 4670b57cec5SDimitry Andric ST2post, 4680b57cec5SDimitry Andric ST3post, 4690b57cec5SDimitry Andric ST4post, 4700b57cec5SDimitry Andric LD1x2post, 4710b57cec5SDimitry Andric LD1x3post, 4720b57cec5SDimitry Andric LD1x4post, 4730b57cec5SDimitry Andric ST1x2post, 4740b57cec5SDimitry Andric ST1x3post, 4750b57cec5SDimitry Andric ST1x4post, 4760b57cec5SDimitry Andric LD1DUPpost, 4770b57cec5SDimitry Andric LD2DUPpost, 4780b57cec5SDimitry Andric LD3DUPpost, 4790b57cec5SDimitry Andric LD4DUPpost, 4800b57cec5SDimitry Andric LD1LANEpost, 4810b57cec5SDimitry Andric LD2LANEpost, 4820b57cec5SDimitry Andric LD3LANEpost, 4830b57cec5SDimitry Andric LD4LANEpost, 4840b57cec5SDimitry Andric ST2LANEpost, 4850b57cec5SDimitry Andric ST3LANEpost, 4860b57cec5SDimitry Andric ST4LANEpost, 4870b57cec5SDimitry Andric 4880b57cec5SDimitry Andric STG, 4890b57cec5SDimitry Andric STZG, 4900b57cec5SDimitry Andric ST2G, 491480093f4SDimitry Andric STZ2G, 4920b57cec5SDimitry Andric 493480093f4SDimitry Andric LDP, 49406c3fb27SDimitry Andric LDIAPP, 495bdd1243dSDimitry Andric LDNP, 4965ffd83dbSDimitry Andric STP, 49706c3fb27SDimitry Andric STILP, 498e8d8bef9SDimitry Andric STNP, 4991fd87a68SDimitry Andric 5001fd87a68SDimitry Andric // Memory Operations 5011fd87a68SDimitry Andric MOPS_MEMSET, 5021fd87a68SDimitry Andric MOPS_MEMSET_TAGGING, 5031fd87a68SDimitry Andric MOPS_MEMCOPY, 5041fd87a68SDimitry Andric MOPS_MEMMOVE, 5050b57cec5SDimitry Andric }; 5060b57cec5SDimitry Andric 5070b57cec5SDimitry Andric } // end namespace AArch64ISD 5080b57cec5SDimitry Andric 509fe6060f1SDimitry Andric namespace AArch64 { 510fe6060f1SDimitry Andric /// Possible values of current rounding mode, which is specified in bits 511fe6060f1SDimitry Andric /// 23:22 of FPCR. 512fe6060f1SDimitry Andric enum Rounding { 513fe6060f1SDimitry Andric RN = 0, // Round to Nearest 514fe6060f1SDimitry Andric RP = 1, // Round towards Plus infinity 515fe6060f1SDimitry Andric RM = 2, // Round towards Minus infinity 516fe6060f1SDimitry Andric RZ = 3, // Round towards Zero 517fe6060f1SDimitry Andric rmMask = 3 // Bit mask selecting rounding mode 518fe6060f1SDimitry Andric }; 519fe6060f1SDimitry Andric 520fe6060f1SDimitry Andric // Bit position of rounding mode bits in FPCR. 521fe6060f1SDimitry Andric const unsigned RoundingBitsPos = 22; 52206c3fb27SDimitry Andric 52306c3fb27SDimitry Andric // Registers used to pass function arguments. 5245f757f3fSDimitry Andric ArrayRef<MCPhysReg> getGPRArgRegs(); 5255f757f3fSDimitry Andric ArrayRef<MCPhysReg> getFPRArgRegs(); 5265f757f3fSDimitry Andric 5275f757f3fSDimitry Andric /// Maximum allowed number of unprobed bytes above SP at an ABI 5285f757f3fSDimitry Andric /// boundary. 5295f757f3fSDimitry Andric const unsigned StackProbeMaxUnprobedStack = 1024; 5305f757f3fSDimitry Andric 5315f757f3fSDimitry Andric /// Maximum number of iterations to unroll for a constant size probing loop. 5325f757f3fSDimitry Andric const unsigned StackProbeMaxLoopUnroll = 4; 53306c3fb27SDimitry Andric 534fe6060f1SDimitry Andric } // namespace AArch64 535fe6060f1SDimitry Andric 5360b57cec5SDimitry Andric class AArch64Subtarget; 5370b57cec5SDimitry Andric 5380b57cec5SDimitry Andric class AArch64TargetLowering : public TargetLowering { 5390b57cec5SDimitry Andric public: 5400b57cec5SDimitry Andric explicit AArch64TargetLowering(const TargetMachine &TM, 5410b57cec5SDimitry Andric const AArch64Subtarget &STI); 5420b57cec5SDimitry Andric 54381ad6265SDimitry Andric /// Control the following reassociation of operands: (op (op x, c1), y) -> (op 54481ad6265SDimitry Andric /// (op x, y), c1) where N0 is (op x, c1) and N1 is y. 54581ad6265SDimitry Andric bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 54681ad6265SDimitry Andric SDValue N1) const override; 54781ad6265SDimitry Andric 5480b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5490b57cec5SDimitry Andric CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 5500b57cec5SDimitry Andric 5510b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5520b57cec5SDimitry Andric CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 5530b57cec5SDimitry Andric 5540b57cec5SDimitry Andric /// Determine which of the bits specified in Mask are known to be either zero 5550b57cec5SDimitry Andric /// or one and return them in the KnownZero/KnownOne bitsets. 5560b57cec5SDimitry Andric void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 5570b57cec5SDimitry Andric const APInt &DemandedElts, 5580b57cec5SDimitry Andric const SelectionDAG &DAG, 5590b57cec5SDimitry Andric unsigned Depth = 0) const override; 5600b57cec5SDimitry Andric 56106c3fb27SDimitry Andric unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 56206c3fb27SDimitry Andric const APInt &DemandedElts, 56306c3fb27SDimitry Andric const SelectionDAG &DAG, 56406c3fb27SDimitry Andric unsigned Depth) const override; 56506c3fb27SDimitry Andric 5668bcb0991SDimitry Andric MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override { 5678bcb0991SDimitry Andric // Returning i64 unconditionally here (i.e. even for ILP32) means that the 5688bcb0991SDimitry Andric // *DAG* representation of pointers will always be 64-bits. They will be 5698bcb0991SDimitry Andric // truncated and extended when transferred to memory, but the 64-bit DAG 5708bcb0991SDimitry Andric // allows us to use AArch64's addressing modes much more easily. 5718bcb0991SDimitry Andric return MVT::getIntegerVT(64); 5728bcb0991SDimitry Andric } 5738bcb0991SDimitry Andric 5745ffd83dbSDimitry Andric bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 5755ffd83dbSDimitry Andric const APInt &DemandedElts, 5760b57cec5SDimitry Andric TargetLoweringOpt &TLO) const override; 5770b57cec5SDimitry Andric 5780b57cec5SDimitry Andric MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override; 5790b57cec5SDimitry Andric 5800b57cec5SDimitry Andric /// Returns true if the target allows unaligned memory accesses of the 5810b57cec5SDimitry Andric /// specified type. 5820b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses( 583fe6060f1SDimitry Andric EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 5840b57cec5SDimitry Andric MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 585bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5868bcb0991SDimitry Andric /// LLT variant. 5875ffd83dbSDimitry Andric bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, 5885ffd83dbSDimitry Andric Align Alignment, 5895ffd83dbSDimitry Andric MachineMemOperand::Flags Flags, 590bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5910b57cec5SDimitry Andric 5920b57cec5SDimitry Andric /// Provide custom lowering hooks for some operations. 5930b57cec5SDimitry Andric SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 5940b57cec5SDimitry Andric 5950b57cec5SDimitry Andric const char *getTargetNodeName(unsigned Opcode) const override; 5960b57cec5SDimitry Andric 5970b57cec5SDimitry Andric SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 5980b57cec5SDimitry Andric 5990b57cec5SDimitry Andric /// This method returns a target specific FastISel object, or null if the 6000b57cec5SDimitry Andric /// target does not support "fast" ISel. 6010b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 6020b57cec5SDimitry Andric const TargetLibraryInfo *libInfo) const override; 6030b57cec5SDimitry Andric 6040b57cec5SDimitry Andric bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 6050b57cec5SDimitry Andric 6060b57cec5SDimitry Andric bool isFPImmLegal(const APFloat &Imm, EVT VT, 6070b57cec5SDimitry Andric bool ForCodeSize) const override; 6080b57cec5SDimitry Andric 6090b57cec5SDimitry Andric /// Return true if the given shuffle mask can be codegen'd directly, or if it 6100b57cec5SDimitry Andric /// should be stack expanded. 6110b57cec5SDimitry Andric bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 6120b57cec5SDimitry Andric 613fcaf7f86SDimitry Andric /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero' 614fcaf7f86SDimitry Andric /// shuffle mask can be codegen'd directly. 615fcaf7f86SDimitry Andric bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override; 616fcaf7f86SDimitry Andric 6170b57cec5SDimitry Andric /// Return the ISD::SETCC ValueType. 6180b57cec5SDimitry Andric EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 6190b57cec5SDimitry Andric EVT VT) const override; 6200b57cec5SDimitry Andric 6210b57cec5SDimitry Andric SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 6220b57cec5SDimitry Andric 6230b57cec5SDimitry Andric MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, 6240b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6250b57cec5SDimitry Andric 6260b57cec5SDimitry Andric MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, 6270b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6280b57cec5SDimitry Andric 6295f757f3fSDimitry Andric MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI, 6305f757f3fSDimitry Andric MachineBasicBlock *MBB) const; 6315f757f3fSDimitry Andric 63281ad6265SDimitry Andric MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg, 63381ad6265SDimitry Andric MachineInstr &MI, 63481ad6265SDimitry Andric MachineBasicBlock *BB) const; 63581ad6265SDimitry Andric MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const; 636bdd1243dSDimitry Andric MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg, 637bdd1243dSDimitry Andric MachineInstr &MI, MachineBasicBlock *BB, 638bdd1243dSDimitry Andric bool HasTile) const; 6395f757f3fSDimitry Andric MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, 6405f757f3fSDimitry Andric unsigned Opcode, bool Op0IsDef) const; 64181ad6265SDimitry Andric MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const; 64281ad6265SDimitry Andric 6430b57cec5SDimitry Andric MachineBasicBlock * 6440b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 6450b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 6460b57cec5SDimitry Andric 6470b57cec5SDimitry Andric bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 6480b57cec5SDimitry Andric MachineFunction &MF, 6490b57cec5SDimitry Andric unsigned Intrinsic) const override; 6500b57cec5SDimitry Andric 6510b57cec5SDimitry Andric bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 6520b57cec5SDimitry Andric EVT NewVT) const override; 6530b57cec5SDimitry Andric 65406c3fb27SDimitry Andric bool shouldRemoveRedundantExtend(SDValue Op) const override; 65506c3fb27SDimitry Andric 6560b57cec5SDimitry Andric bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 6570b57cec5SDimitry Andric bool isTruncateFree(EVT VT1, EVT VT2) const override; 6580b57cec5SDimitry Andric 6590b57cec5SDimitry Andric bool isProfitableToHoist(Instruction *I) const override; 6600b57cec5SDimitry Andric 6610b57cec5SDimitry Andric bool isZExtFree(Type *Ty1, Type *Ty2) const override; 6620b57cec5SDimitry Andric bool isZExtFree(EVT VT1, EVT VT2) const override; 6630b57cec5SDimitry Andric bool isZExtFree(SDValue Val, EVT VT2) const override; 6640b57cec5SDimitry Andric 6650b57cec5SDimitry Andric bool shouldSinkOperands(Instruction *I, 6660b57cec5SDimitry Andric SmallVectorImpl<Use *> &Ops) const override; 6670b57cec5SDimitry Andric 66806c3fb27SDimitry Andric bool optimizeExtendOrTruncateConversion( 66906c3fb27SDimitry Andric Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override; 670bdd1243dSDimitry Andric 6715ffd83dbSDimitry Andric bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override; 6720b57cec5SDimitry Andric 6730b57cec5SDimitry Andric unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 6740b57cec5SDimitry Andric 6750b57cec5SDimitry Andric bool lowerInterleavedLoad(LoadInst *LI, 6760b57cec5SDimitry Andric ArrayRef<ShuffleVectorInst *> Shuffles, 6770b57cec5SDimitry Andric ArrayRef<unsigned> Indices, 6780b57cec5SDimitry Andric unsigned Factor) const override; 6790b57cec5SDimitry Andric bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 6800b57cec5SDimitry Andric unsigned Factor) const override; 6810b57cec5SDimitry Andric 68206c3fb27SDimitry Andric bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, 68306c3fb27SDimitry Andric LoadInst *LI) const override; 68406c3fb27SDimitry Andric 68506c3fb27SDimitry Andric bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, 68606c3fb27SDimitry Andric StoreInst *SI) const override; 68706c3fb27SDimitry Andric 6880b57cec5SDimitry Andric bool isLegalAddImmediate(int64_t) const override; 6890b57cec5SDimitry Andric bool isLegalICmpImmediate(int64_t) const override; 6900b57cec5SDimitry Andric 69181ad6265SDimitry Andric bool isMulAddWithConstProfitable(SDValue AddNode, 69281ad6265SDimitry Andric SDValue ConstNode) const override; 693349cc55cSDimitry Andric 6940b57cec5SDimitry Andric bool shouldConsiderGEPOffsetSplit() const override; 6950b57cec5SDimitry Andric 6965ffd83dbSDimitry Andric EVT getOptimalMemOpType(const MemOp &Op, 6970b57cec5SDimitry Andric const AttributeList &FuncAttributes) const override; 6980b57cec5SDimitry Andric 6995ffd83dbSDimitry Andric LLT getOptimalMemOpLLT(const MemOp &Op, 7008bcb0991SDimitry Andric const AttributeList &FuncAttributes) const override; 7018bcb0991SDimitry Andric 7020b57cec5SDimitry Andric /// Return true if the addressing mode represented by AM is legal for this 7030b57cec5SDimitry Andric /// target, for a load/store of the specified type. 7040b57cec5SDimitry Andric bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 7050b57cec5SDimitry Andric unsigned AS, 7060b57cec5SDimitry Andric Instruction *I = nullptr) const override; 7070b57cec5SDimitry Andric 7085f757f3fSDimitry Andric int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, 7095f757f3fSDimitry Andric int64_t MaxOffset) const override; 7105f757f3fSDimitry Andric 7110b57cec5SDimitry Andric /// Return true if an FMA operation is faster than a pair of fmul and fadd 7120b57cec5SDimitry Andric /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 7130b57cec5SDimitry Andric /// returns true, otherwise fmuladd is expanded to fmul + fadd. 714480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 715480093f4SDimitry Andric EVT VT) const override; 716480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 7170b57cec5SDimitry Andric 718fe6060f1SDimitry Andric bool generateFMAsInMachineCombiner(EVT VT, 7195f757f3fSDimitry Andric CodeGenOptLevel OptLevel) const override; 720fe6060f1SDimitry Andric 7210b57cec5SDimitry Andric const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 72206c3fb27SDimitry Andric ArrayRef<MCPhysReg> getRoundingControlRegisters() const override; 7230b57cec5SDimitry Andric 7240b57cec5SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 7250b57cec5SDimitry Andric bool isDesirableToCommuteWithShift(const SDNode *N, 7260b57cec5SDimitry Andric CombineLevel Level) const override; 7270b57cec5SDimitry Andric 7285f757f3fSDimitry Andric bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override { 7295f757f3fSDimitry Andric return false; 7305f757f3fSDimitry Andric } 7315f757f3fSDimitry Andric 732fcaf7f86SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 733fcaf7f86SDimitry Andric bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 734fcaf7f86SDimitry Andric 73581ad6265SDimitry Andric /// Return true if it is profitable to fold a pair of shifts into a mask. 73681ad6265SDimitry Andric bool shouldFoldConstantShiftPairToMask(const SDNode *N, 73781ad6265SDimitry Andric CombineLevel Level) const override; 73881ad6265SDimitry Andric 73906c3fb27SDimitry Andric bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 74006c3fb27SDimitry Andric EVT VT) const override; 74106c3fb27SDimitry Andric 7420b57cec5SDimitry Andric /// Returns true if it is beneficial to convert a load of a constant 7430b57cec5SDimitry Andric /// to just the constant itself. 7440b57cec5SDimitry Andric bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 7450b57cec5SDimitry Andric Type *Ty) const override; 7460b57cec5SDimitry Andric 7470b57cec5SDimitry Andric /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 7480b57cec5SDimitry Andric /// with this index. 7490b57cec5SDimitry Andric bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 7500b57cec5SDimitry Andric unsigned Index) const override; 7510b57cec5SDimitry Andric 7525ffd83dbSDimitry Andric bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 7535ffd83dbSDimitry Andric bool MathUsed) const override { 7545ffd83dbSDimitry Andric // Using overflow ops for overflow checks only should beneficial on 7555ffd83dbSDimitry Andric // AArch64. 7565ffd83dbSDimitry Andric return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 7575ffd83dbSDimitry Andric } 7585ffd83dbSDimitry Andric 759fe6060f1SDimitry Andric Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 7600b57cec5SDimitry Andric AtomicOrdering Ord) const override; 761fe6060f1SDimitry Andric Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 762fe6060f1SDimitry Andric AtomicOrdering Ord) const override; 7630b57cec5SDimitry Andric 764fe6060f1SDimitry Andric void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 7650b57cec5SDimitry Andric 766349cc55cSDimitry Andric bool isOpSuitableForLDPSTP(const Instruction *I) const; 76706c3fb27SDimitry Andric bool isOpSuitableForLSE128(const Instruction *I) const; 76806c3fb27SDimitry Andric bool isOpSuitableForRCPC3(const Instruction *I) const; 769349cc55cSDimitry Andric bool shouldInsertFencesForAtomic(const Instruction *I) const override; 770bdd1243dSDimitry Andric bool 771bdd1243dSDimitry Andric shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override; 772349cc55cSDimitry Andric 7730b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7740b57cec5SDimitry Andric shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 77581ad6265SDimitry Andric TargetLoweringBase::AtomicExpansionKind 77681ad6265SDimitry Andric shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 7770b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7780b57cec5SDimitry Andric shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 7790b57cec5SDimitry Andric 7800b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7810b57cec5SDimitry Andric shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 7820b57cec5SDimitry Andric 7830b57cec5SDimitry Andric bool useLoadStackGuardNode() const override; 7840b57cec5SDimitry Andric TargetLoweringBase::LegalizeTypeAction 7850b57cec5SDimitry Andric getPreferredVectorAction(MVT VT) const override; 7860b57cec5SDimitry Andric 7870b57cec5SDimitry Andric /// If the target has a standard location for the stack protector cookie, 7880b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 789fe6060f1SDimitry Andric Value *getIRStackGuard(IRBuilderBase &IRB) const override; 7900b57cec5SDimitry Andric 7910b57cec5SDimitry Andric void insertSSPDeclarations(Module &M) const override; 7920b57cec5SDimitry Andric Value *getSDagStackGuard(const Module &M) const override; 7930b57cec5SDimitry Andric Function *getSSPStackGuardCheck(const Module &M) const override; 7940b57cec5SDimitry Andric 7950b57cec5SDimitry Andric /// If the target has a standard location for the unsafe stack pointer, 7960b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 797fe6060f1SDimitry Andric Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; 7980b57cec5SDimitry Andric 7990b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8000b57cec5SDimitry Andric /// exception address on entry to an EH pad. 8015ffd83dbSDimitry Andric Register 8020b57cec5SDimitry Andric getExceptionPointerRegister(const Constant *PersonalityFn) const override { 8030b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8040b57cec5SDimitry Andric return AArch64::X0; 8050b57cec5SDimitry Andric } 8060b57cec5SDimitry Andric 8070b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8080b57cec5SDimitry Andric /// exception typeid on entry to a landing pad. 8095ffd83dbSDimitry Andric Register 8100b57cec5SDimitry Andric getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 8110b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8120b57cec5SDimitry Andric return AArch64::X1; 8130b57cec5SDimitry Andric } 8140b57cec5SDimitry Andric 8150b57cec5SDimitry Andric bool isIntDivCheap(EVT VT, AttributeList Attr) const override; 8160b57cec5SDimitry Andric 8170b57cec5SDimitry Andric bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 818349cc55cSDimitry Andric const MachineFunction &MF) const override { 8190b57cec5SDimitry Andric // Do not merge to float value size (128 bytes) if no implicit 8200b57cec5SDimitry Andric // float attribute is set. 8210b57cec5SDimitry Andric 822349cc55cSDimitry Andric bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat); 8230b57cec5SDimitry Andric 8240b57cec5SDimitry Andric if (NoFloat) 8250b57cec5SDimitry Andric return (MemVT.getSizeInBits() <= 64); 8260b57cec5SDimitry Andric return true; 8270b57cec5SDimitry Andric } 8280b57cec5SDimitry Andric 829bdd1243dSDimitry Andric bool isCheapToSpeculateCttz(Type *) const override { 8300b57cec5SDimitry Andric return true; 8310b57cec5SDimitry Andric } 8320b57cec5SDimitry Andric 833bdd1243dSDimitry Andric bool isCheapToSpeculateCtlz(Type *) const override { 8340b57cec5SDimitry Andric return true; 8350b57cec5SDimitry Andric } 8360b57cec5SDimitry Andric 8370b57cec5SDimitry Andric bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 8380b57cec5SDimitry Andric 8390b57cec5SDimitry Andric bool hasAndNotCompare(SDValue V) const override { 8400b57cec5SDimitry Andric // We can use bics for any scalar. 8410b57cec5SDimitry Andric return V.getValueType().isScalarInteger(); 8420b57cec5SDimitry Andric } 8430b57cec5SDimitry Andric 8440b57cec5SDimitry Andric bool hasAndNot(SDValue Y) const override { 8450b57cec5SDimitry Andric EVT VT = Y.getValueType(); 8460b57cec5SDimitry Andric 8470b57cec5SDimitry Andric if (!VT.isVector()) 8480b57cec5SDimitry Andric return hasAndNotCompare(Y); 8490b57cec5SDimitry Andric 850349cc55cSDimitry Andric TypeSize TS = VT.getSizeInBits(); 851349cc55cSDimitry Andric // TODO: We should be able to use bic/bif too for SVE. 852349cc55cSDimitry Andric return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic' 8530b57cec5SDimitry Andric } 8540b57cec5SDimitry Andric 8558bcb0991SDimitry Andric bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 8568bcb0991SDimitry Andric SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 8578bcb0991SDimitry Andric unsigned OldShiftOpcode, unsigned NewShiftOpcode, 8588bcb0991SDimitry Andric SelectionDAG &DAG) const override; 8598bcb0991SDimitry Andric 860bdd1243dSDimitry Andric ShiftLegalizationStrategy 861bdd1243dSDimitry Andric preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 862bdd1243dSDimitry Andric unsigned ExpansionFactor) const override; 8630b57cec5SDimitry Andric 8640b57cec5SDimitry Andric bool shouldTransformSignedTruncationCheck(EVT XVT, 8650b57cec5SDimitry Andric unsigned KeptBits) const override { 8660b57cec5SDimitry Andric // For vectors, we don't have a preference.. 8670b57cec5SDimitry Andric if (XVT.isVector()) 8680b57cec5SDimitry Andric return false; 8690b57cec5SDimitry Andric 8700b57cec5SDimitry Andric auto VTIsOk = [](EVT VT) -> bool { 8710b57cec5SDimitry Andric return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 8720b57cec5SDimitry Andric VT == MVT::i64; 8730b57cec5SDimitry Andric }; 8740b57cec5SDimitry Andric 8750b57cec5SDimitry Andric // We are ok with KeptBitsVT being byte/word/dword, what SXT supports. 8760b57cec5SDimitry Andric // XVT will be larger than KeptBitsVT. 8770b57cec5SDimitry Andric MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); 8780b57cec5SDimitry Andric return VTIsOk(XVT) && VTIsOk(KeptBitsVT); 8790b57cec5SDimitry Andric } 8800b57cec5SDimitry Andric 8810b57cec5SDimitry Andric bool preferIncOfAddToSubOfNot(EVT VT) const override; 8820b57cec5SDimitry Andric 8834824e7fdSDimitry Andric bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 8844824e7fdSDimitry Andric 885bdd1243dSDimitry Andric bool isComplexDeinterleavingSupported() const override; 886bdd1243dSDimitry Andric bool isComplexDeinterleavingOperationSupported( 887bdd1243dSDimitry Andric ComplexDeinterleavingOperation Operation, Type *Ty) const override; 888bdd1243dSDimitry Andric 889bdd1243dSDimitry Andric Value *createComplexDeinterleavingIR( 89006c3fb27SDimitry Andric IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 891bdd1243dSDimitry Andric ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 892bdd1243dSDimitry Andric Value *Accumulator = nullptr) const override; 893bdd1243dSDimitry Andric 8940b57cec5SDimitry Andric bool supportSplitCSR(MachineFunction *MF) const override { 8950b57cec5SDimitry Andric return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 8960b57cec5SDimitry Andric MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 8970b57cec5SDimitry Andric } 8980b57cec5SDimitry Andric void initializeSplitCSR(MachineBasicBlock *Entry) const override; 8990b57cec5SDimitry Andric void insertCopiesSplitCSR( 9000b57cec5SDimitry Andric MachineBasicBlock *Entry, 9010b57cec5SDimitry Andric const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 9020b57cec5SDimitry Andric 9030b57cec5SDimitry Andric bool supportSwiftError() const override { 9040b57cec5SDimitry Andric return true; 9050b57cec5SDimitry Andric } 9060b57cec5SDimitry Andric 907bdd1243dSDimitry Andric bool supportKCFIBundles() const override { return true; } 908bdd1243dSDimitry Andric 90906c3fb27SDimitry Andric MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB, 91006c3fb27SDimitry Andric MachineBasicBlock::instr_iterator &MBBI, 91106c3fb27SDimitry Andric const TargetInstrInfo *TII) const override; 91206c3fb27SDimitry Andric 9130b57cec5SDimitry Andric /// Enable aggressive FMA fusion on targets that want it. 9140b57cec5SDimitry Andric bool enableAggressiveFMAFusion(EVT VT) const override; 9150b57cec5SDimitry Andric 9160b57cec5SDimitry Andric /// Returns the size of the platform's va_list object. 9170b57cec5SDimitry Andric unsigned getVaListSizeInBits(const DataLayout &DL) const override; 9180b57cec5SDimitry Andric 9190b57cec5SDimitry Andric /// Returns true if \p VecTy is a legal interleaved access type. This 9200b57cec5SDimitry Andric /// function checks the vector element type and the overall width of the 9210b57cec5SDimitry Andric /// vector. 922349cc55cSDimitry Andric bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, 923349cc55cSDimitry Andric bool &UseScalable) const; 9240b57cec5SDimitry Andric 9250b57cec5SDimitry Andric /// Returns the number of interleaved accesses that will be generated when 9260b57cec5SDimitry Andric /// lowering accesses of the given type. 927349cc55cSDimitry Andric unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, 928349cc55cSDimitry Andric bool UseScalable) const; 9290b57cec5SDimitry Andric 9305ffd83dbSDimitry Andric MachineMemOperand::Flags getTargetMMOFlags( 9315ffd83dbSDimitry Andric const Instruction &I) const override; 9320b57cec5SDimitry Andric 933fe6060f1SDimitry Andric bool functionArgumentNeedsConsecutiveRegisters( 934fe6060f1SDimitry Andric Type *Ty, CallingConv::ID CallConv, bool isVarArg, 935fe6060f1SDimitry Andric const DataLayout &DL) const override; 936fe6060f1SDimitry Andric 9370b57cec5SDimitry Andric /// Used for exception handling on Win64. 9380b57cec5SDimitry Andric bool needsFixedCatchObjects() const override; 9395ffd83dbSDimitry Andric 9405ffd83dbSDimitry Andric bool fallBackToDAGISel(const Instruction &Inst) const override; 9415ffd83dbSDimitry Andric 9425ffd83dbSDimitry Andric /// SVE code generation for fixed length vectors does not custom lower 9435ffd83dbSDimitry Andric /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to 9445ffd83dbSDimitry Andric /// merge. However, merging them creates a BUILD_VECTOR that is just as 9455ffd83dbSDimitry Andric /// illegal as the original, thus leading to an infinite legalisation loop. 9465ffd83dbSDimitry Andric /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal 9475ffd83dbSDimitry Andric /// vector types this override can be removed. 948e8d8bef9SDimitry Andric bool mergeStoresAfterLegalization(EVT VT) const override; 9495ffd83dbSDimitry Andric 950fe6060f1SDimitry Andric // If the platform/function should have a redzone, return the size in bytes. 951fe6060f1SDimitry Andric unsigned getRedZoneSize(const Function &F) const { 952fe6060f1SDimitry Andric if (F.hasFnAttribute(Attribute::NoRedZone)) 953fe6060f1SDimitry Andric return 0; 954fe6060f1SDimitry Andric return 128; 955fe6060f1SDimitry Andric } 956fe6060f1SDimitry Andric 95704eeddc0SDimitry Andric bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const; 958fe6060f1SDimitry Andric EVT getPromotedVTForPredicate(EVT VT) const; 959fe6060f1SDimitry Andric 9606e75b2fbSDimitry Andric EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, 9616e75b2fbSDimitry Andric bool AllowUnknown = false) const override; 9626e75b2fbSDimitry Andric 9634824e7fdSDimitry Andric bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override; 9644824e7fdSDimitry Andric 9655f757f3fSDimitry Andric bool shouldExpandCttzElements(EVT VT) const override; 9665f757f3fSDimitry Andric 967bdd1243dSDimitry Andric /// If a change in streaming mode is required on entry to/return from a 968bdd1243dSDimitry Andric /// function call it emits and returns the corresponding SMSTART or SMSTOP node. 969bdd1243dSDimitry Andric /// \p Entry tells whether this is before/after the Call, which is necessary 970bdd1243dSDimitry Andric /// because PSTATE.SM is only queried once. 971bdd1243dSDimitry Andric SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, 97206c3fb27SDimitry Andric SDValue Chain, SDValue InGlue, 973bdd1243dSDimitry Andric SDValue PStateSM, bool Entry) const; 974bdd1243dSDimitry Andric 97506c3fb27SDimitry Andric bool isVScaleKnownToBeAPowerOfTwo() const override { return true; } 976bdd1243dSDimitry Andric 977bdd1243dSDimitry Andric // Normally SVE is only used for byte size vectors that do not fit within a 978bdd1243dSDimitry Andric // NEON vector. This changes when OverrideNEON is true, allowing SVE to be 979bdd1243dSDimitry Andric // used for 64bit and 128bit vectors as well. 980bdd1243dSDimitry Andric bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const; 981bdd1243dSDimitry Andric 9825f757f3fSDimitry Andric // Follow NEON ABI rules even when using SVE for fixed length vectors. 9835f757f3fSDimitry Andric MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 9845f757f3fSDimitry Andric EVT VT) const override; 9855f757f3fSDimitry Andric unsigned getNumRegistersForCallingConv(LLVMContext &Context, 9865f757f3fSDimitry Andric CallingConv::ID CC, 9875f757f3fSDimitry Andric EVT VT) const override; 9885f757f3fSDimitry Andric unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, 9895f757f3fSDimitry Andric CallingConv::ID CC, EVT VT, 9905f757f3fSDimitry Andric EVT &IntermediateVT, 9915f757f3fSDimitry Andric unsigned &NumIntermediates, 9925f757f3fSDimitry Andric MVT &RegisterVT) const override; 9935f757f3fSDimitry Andric 9945f757f3fSDimitry Andric /// True if stack clash protection is enabled for this functions. 9955f757f3fSDimitry Andric bool hasInlineStackProbe(const MachineFunction &MF) const override; 9965f757f3fSDimitry Andric 9970b57cec5SDimitry Andric private: 9980b57cec5SDimitry Andric /// Keep a pointer to the AArch64Subtarget around so that we can 9990b57cec5SDimitry Andric /// make the right decision when generating code for different targets. 10000b57cec5SDimitry Andric const AArch64Subtarget *Subtarget; 10010b57cec5SDimitry Andric 10020b57cec5SDimitry Andric bool isExtFreeImpl(const Instruction *Ext) const override; 10030b57cec5SDimitry Andric 1004fe6060f1SDimitry Andric void addTypeForNEON(MVT VT); 100506c3fb27SDimitry Andric void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE); 10060b57cec5SDimitry Andric void addDRTypeForNEON(MVT VT); 10070b57cec5SDimitry Andric void addQRTypeForNEON(MVT VT); 10080b57cec5SDimitry Andric 1009bdd1243dSDimitry Andric unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL, 1010bdd1243dSDimitry Andric SelectionDAG &DAG) const; 1011bdd1243dSDimitry Andric 10120b57cec5SDimitry Andric SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 10130b57cec5SDimitry Andric bool isVarArg, 10140b57cec5SDimitry Andric const SmallVectorImpl<ISD::InputArg> &Ins, 10150b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10160b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10170b57cec5SDimitry Andric 10185f757f3fSDimitry Andric void AdjustInstrPostInstrSelection(MachineInstr &MI, 10195f757f3fSDimitry Andric SDNode *Node) const override; 10205f757f3fSDimitry Andric 10210b57cec5SDimitry Andric SDValue LowerCall(CallLoweringInfo & /*CLI*/, 10220b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10230b57cec5SDimitry Andric 102406c3fb27SDimitry Andric SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 10250b57cec5SDimitry Andric CallingConv::ID CallConv, bool isVarArg, 1026f3fd488fSDimitry Andric const SmallVectorImpl<CCValAssign> &RVLocs, 10270b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10280b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 10290b57cec5SDimitry Andric SDValue ThisVal) const; 10300b57cec5SDimitry Andric 1031fe6060f1SDimitry Andric SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 10320b57cec5SDimitry Andric SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1033349cc55cSDimitry Andric SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const; 1034e8d8bef9SDimitry Andric SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1035e8d8bef9SDimitry Andric 1036e8d8bef9SDimitry Andric SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 1037e8d8bef9SDimitry Andric SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 10380b57cec5SDimitry Andric 1039fe6060f1SDimitry Andric SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 1040fe6060f1SDimitry Andric 10411fd87a68SDimitry Andric SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 10420b57cec5SDimitry Andric SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1043bdd1243dSDimitry Andric SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 10440b57cec5SDimitry Andric 10453a9a9c0cSDimitry Andric bool 10463a9a9c0cSDimitry Andric isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const; 10470b57cec5SDimitry Andric 10480b57cec5SDimitry Andric /// Finds the incoming stack arguments which overlap the given fixed stack 10490b57cec5SDimitry Andric /// object and incorporates their load into the current chain. This prevents 10500b57cec5SDimitry Andric /// an upcoming store from clobbering the stack argument before it's used. 10510b57cec5SDimitry Andric SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 10520b57cec5SDimitry Andric MachineFrameInfo &MFI, int ClobberedFI) const; 10530b57cec5SDimitry Andric 10540b57cec5SDimitry Andric bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 10550b57cec5SDimitry Andric 10560b57cec5SDimitry Andric void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, 10570b57cec5SDimitry Andric SDValue &Chain) const; 10580b57cec5SDimitry Andric 10590b57cec5SDimitry Andric bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 10600b57cec5SDimitry Andric bool isVarArg, 10610b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10620b57cec5SDimitry Andric LLVMContext &Context) const override; 10630b57cec5SDimitry Andric 10640b57cec5SDimitry Andric SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 10650b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10660b57cec5SDimitry Andric const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 10670b57cec5SDimitry Andric SelectionDAG &DAG) const override; 10680b57cec5SDimitry Andric 10690b57cec5SDimitry Andric SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10700b57cec5SDimitry Andric unsigned Flag) const; 10710b57cec5SDimitry Andric SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 10720b57cec5SDimitry Andric unsigned Flag) const; 10730b57cec5SDimitry Andric SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 10740b57cec5SDimitry Andric unsigned Flag) const; 10750b57cec5SDimitry Andric SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10760b57cec5SDimitry Andric unsigned Flag) const; 1077*7a6dacacSDimitry Andric SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 1078*7a6dacacSDimitry Andric unsigned Flag) const; 10790b57cec5SDimitry Andric template <class NodeTy> 10800b57cec5SDimitry Andric SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10810b57cec5SDimitry Andric template <class NodeTy> 10820b57cec5SDimitry Andric SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10830b57cec5SDimitry Andric template <class NodeTy> 10840b57cec5SDimitry Andric SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10850b57cec5SDimitry Andric template <class NodeTy> 10860b57cec5SDimitry Andric SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10870b57cec5SDimitry Andric SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 10880b57cec5SDimitry Andric SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 10890b57cec5SDimitry Andric SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10900b57cec5SDimitry Andric SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10910b57cec5SDimitry Andric SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1092480093f4SDimitry Andric SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase, 1093480093f4SDimitry Andric const SDLoc &DL, SelectionDAG &DAG) const; 10940b57cec5SDimitry Andric SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL, 10950b57cec5SDimitry Andric SelectionDAG &DAG) const; 10960b57cec5SDimitry Andric SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10970b57cec5SDimitry Andric SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1098bdd1243dSDimitry Andric SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const; 10990b57cec5SDimitry Andric SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 11000b57cec5SDimitry Andric SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 11010b57cec5SDimitry Andric SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 11020b57cec5SDimitry Andric SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 11030b57cec5SDimitry Andric SDValue TVal, SDValue FVal, const SDLoc &dl, 11040b57cec5SDimitry Andric SelectionDAG &DAG) const; 11050b57cec5SDimitry Andric SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 11060b57cec5SDimitry Andric SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 11070b57cec5SDimitry Andric SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 11080b57cec5SDimitry Andric SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 11090b57cec5SDimitry Andric SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 11100b57cec5SDimitry Andric SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 11110b57cec5SDimitry Andric SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const; 11120b57cec5SDimitry Andric SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 11130b57cec5SDimitry Andric SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 11140b57cec5SDimitry Andric SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 11150b57cec5SDimitry Andric SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 11160b57cec5SDimitry Andric SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 11170b57cec5SDimitry Andric SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1118bdd1243dSDimitry Andric SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 1119fe6060f1SDimitry Andric SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 11200b57cec5SDimitry Andric SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11210b57cec5SDimitry Andric SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11220b57cec5SDimitry Andric SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1123bdd1243dSDimitry Andric SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 11240b57cec5SDimitry Andric SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 11258bcb0991SDimitry Andric SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const; 11265ffd83dbSDimitry Andric SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const; 112781ad6265SDimitry Andric SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, 112881ad6265SDimitry Andric unsigned NewOp) const; 1129e8d8bef9SDimitry Andric SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; 1130fe6060f1SDimitry Andric SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const; 11310b57cec5SDimitry Andric SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 11325ffd83dbSDimitry Andric SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 113306c3fb27SDimitry Andric SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 113406c3fb27SDimitry Andric SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 1135e8d8bef9SDimitry Andric SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const; 1136e8d8bef9SDimitry Andric SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 11370b57cec5SDimitry Andric SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 1138fe6060f1SDimitry Andric SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 11390b57cec5SDimitry Andric SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 1140fcaf7f86SDimitry Andric SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const; 1141e8d8bef9SDimitry Andric SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 1142fe6060f1SDimitry Andric SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const; 1143349cc55cSDimitry Andric SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 11440b57cec5SDimitry Andric SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 11450b57cec5SDimitry Andric SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 11460b57cec5SDimitry Andric SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 11470b57cec5SDimitry Andric SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1148349cc55cSDimitry Andric SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11490b57cec5SDimitry Andric SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1150fe6060f1SDimitry Andric SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11510b57cec5SDimitry Andric SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1152e8d8bef9SDimitry Andric SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 11530b57cec5SDimitry Andric SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 1154e8d8bef9SDimitry Andric SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const; 11550b57cec5SDimitry Andric SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 11560b57cec5SDimitry Andric SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 1157fe6060f1SDimitry Andric SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 11585ffd83dbSDimitry Andric SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const; 11595ffd83dbSDimitry Andric SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 11600b57cec5SDimitry Andric SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 11610b57cec5SDimitry Andric SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const; 11625f757f3fSDimitry Andric SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11635f757f3fSDimitry Andric SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11640b57cec5SDimitry Andric SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11655f757f3fSDimitry Andric 116606c3fb27SDimitry Andric SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const; 11675ffd83dbSDimitry Andric 1168e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, 1169e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1170e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, 1171e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 11725ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1173fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1174e8d8bef9SDimitry Andric SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const; 1175e8d8bef9SDimitry Andric SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const; 1176e8d8bef9SDimitry Andric SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp, 1177e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1178e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const; 1179e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const; 11805ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const; 1181fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op, 1182fe6060f1SDimitry Andric SelectionDAG &DAG) const; 11835ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op, 11845ffd83dbSDimitry Andric SelectionDAG &DAG) const; 1185fe6060f1SDimitry Andric SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const; 1186fe6060f1SDimitry Andric SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const; 1187fe6060f1SDimitry Andric SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const; 1188fe6060f1SDimitry Andric SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op, 1189fe6060f1SDimitry Andric SelectionDAG &DAG) const; 1190fe6060f1SDimitry Andric SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const; 1191fe6060f1SDimitry Andric SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const; 1192fe6060f1SDimitry Andric SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const; 1193fe6060f1SDimitry Andric SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; 1194fe6060f1SDimitry Andric SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op, 1195fe6060f1SDimitry Andric SelectionDAG &DAG) const; 11960b57cec5SDimitry Andric 11970b57cec5SDimitry Andric SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 11980b57cec5SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 119981ad6265SDimitry Andric SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 120081ad6265SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 12010b57cec5SDimitry Andric SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12020b57cec5SDimitry Andric int &ExtraSteps, bool &UseOneConst, 12030b57cec5SDimitry Andric bool Reciprocal) const override; 12040b57cec5SDimitry Andric SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12050b57cec5SDimitry Andric int &ExtraSteps) const override; 1206e8d8bef9SDimitry Andric SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1207e8d8bef9SDimitry Andric const DenormalMode &Mode) const override; 1208e8d8bef9SDimitry Andric SDValue getSqrtResultForDenormInput(SDValue Operand, 1209e8d8bef9SDimitry Andric SelectionDAG &DAG) const override; 12100b57cec5SDimitry Andric unsigned combineRepeatedFPDivisors() const override; 12110b57cec5SDimitry Andric 12120b57cec5SDimitry Andric ConstraintType getConstraintType(StringRef Constraint) const override; 1213480093f4SDimitry Andric Register getRegisterByName(const char* RegName, LLT VT, 12148bcb0991SDimitry Andric const MachineFunction &MF) const override; 12150b57cec5SDimitry Andric 12160b57cec5SDimitry Andric /// Examine constraint string and operand type and determine a weight value. 12170b57cec5SDimitry Andric /// The operand object must already have been set up with the operand type. 12180b57cec5SDimitry Andric ConstraintWeight 12190b57cec5SDimitry Andric getSingleConstraintMatchWeight(AsmOperandInfo &info, 12200b57cec5SDimitry Andric const char *constraint) const override; 12210b57cec5SDimitry Andric 12220b57cec5SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> 12230b57cec5SDimitry Andric getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 12240b57cec5SDimitry Andric StringRef Constraint, MVT VT) const override; 12250b57cec5SDimitry Andric 12260b57cec5SDimitry Andric const char *LowerXConstraint(EVT ConstraintVT) const override; 12270b57cec5SDimitry Andric 12285f757f3fSDimitry Andric void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 12290b57cec5SDimitry Andric std::vector<SDValue> &Ops, 12300b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12310b57cec5SDimitry Andric 12325f757f3fSDimitry Andric InlineAsm::ConstraintCode 12335f757f3fSDimitry Andric getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 12340b57cec5SDimitry Andric if (ConstraintCode == "Q") 12355f757f3fSDimitry Andric return InlineAsm::ConstraintCode::Q; 12360b57cec5SDimitry Andric // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 12370b57cec5SDimitry Andric // followed by llvm_unreachable so we'll leave them unimplemented in 12380b57cec5SDimitry Andric // the backend for now. 12390b57cec5SDimitry Andric return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 12400b57cec5SDimitry Andric } 12410b57cec5SDimitry Andric 124206c3fb27SDimitry Andric /// Handle Lowering flag assembly outputs. 124306c3fb27SDimitry Andric SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, 124406c3fb27SDimitry Andric const SDLoc &DL, 124506c3fb27SDimitry Andric const AsmOperandInfo &Constraint, 124606c3fb27SDimitry Andric SelectionDAG &DAG) const override; 124706c3fb27SDimitry Andric 1248fe6060f1SDimitry Andric bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override; 12495f757f3fSDimitry Andric bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override; 1250480093f4SDimitry Andric bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 12510b57cec5SDimitry Andric bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 12520b57cec5SDimitry Andric bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1253bdd1243dSDimitry Andric bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 125406c3fb27SDimitry Andric SDValue &Offset, SelectionDAG &DAG) const; 12550b57cec5SDimitry Andric bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 12560b57cec5SDimitry Andric ISD::MemIndexedMode &AM, 12570b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12580b57cec5SDimitry Andric bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 12590b57cec5SDimitry Andric SDValue &Offset, ISD::MemIndexedMode &AM, 12600b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12615f757f3fSDimitry Andric bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, 12625f757f3fSDimitry Andric bool IsPre, MachineRegisterInfo &MRI) const override; 12630b57cec5SDimitry Andric 12640b57cec5SDimitry Andric void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 12650b57cec5SDimitry Andric SelectionDAG &DAG) const override; 1266fe6060f1SDimitry Andric void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1267fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12685ffd83dbSDimitry Andric void ReplaceExtractSubVectorResults(SDNode *N, 12695ffd83dbSDimitry Andric SmallVectorImpl<SDValue> &Results, 12705ffd83dbSDimitry Andric SelectionDAG &DAG) const; 12710b57cec5SDimitry Andric 12720b57cec5SDimitry Andric bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; 12730b57cec5SDimitry Andric 12740b57cec5SDimitry Andric void finalizeLowering(MachineFunction &MF) const override; 12755ffd83dbSDimitry Andric 12765ffd83dbSDimitry Andric bool shouldLocalize(const MachineInstr &MI, 12775ffd83dbSDimitry Andric const TargetTransformInfo *TTI) const override; 12785ffd83dbSDimitry Andric 1279fe6060f1SDimitry Andric bool SimplifyDemandedBitsForTargetNode(SDValue Op, 1280fe6060f1SDimitry Andric const APInt &OriginalDemandedBits, 1281fe6060f1SDimitry Andric const APInt &OriginalDemandedElts, 1282fe6060f1SDimitry Andric KnownBits &Known, 1283fe6060f1SDimitry Andric TargetLoweringOpt &TLO, 1284fe6060f1SDimitry Andric unsigned Depth) const override; 1285fe6060f1SDimitry Andric 128681ad6265SDimitry Andric bool isTargetCanonicalConstantNode(SDValue Op) const override; 128781ad6265SDimitry Andric 1288e8d8bef9SDimitry Andric // With the exception of data-predicate transitions, no instructions are 1289e8d8bef9SDimitry Andric // required to cast between legal scalable vector types. However: 1290e8d8bef9SDimitry Andric // 1. Packed and unpacked types have different bit lengths, meaning BITCAST 1291e8d8bef9SDimitry Andric // is not universally useable. 1292e8d8bef9SDimitry Andric // 2. Most unpacked integer types are not legal and thus integer extends 1293e8d8bef9SDimitry Andric // cannot be used to convert between unpacked and packed types. 1294e8d8bef9SDimitry Andric // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used 1295e8d8bef9SDimitry Andric // to transition between unpacked and packed types of the same element type, 1296e8d8bef9SDimitry Andric // with BITCAST used otherwise. 1297753f127fSDimitry Andric // This function does not handle predicate bitcasts. 1298e8d8bef9SDimitry Andric SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; 1299fe6060f1SDimitry Andric 1300*7a6dacacSDimitry Andric // Returns the runtime value for PSTATE.SM by generating a call to 1301*7a6dacacSDimitry Andric // __arm_sme_state. 1302*7a6dacacSDimitry Andric SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL, 1303*7a6dacacSDimitry Andric EVT VT) const; 1304bdd1243dSDimitry Andric 130506c3fb27SDimitry Andric bool preferScalarizeSplat(SDNode *N) const override; 13065f757f3fSDimitry Andric 13075f757f3fSDimitry Andric unsigned getMinimumJumpTableEntries() const override; 13080b57cec5SDimitry Andric }; 13090b57cec5SDimitry Andric 13100b57cec5SDimitry Andric namespace AArch64 { 13110b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 13120b57cec5SDimitry Andric const TargetLibraryInfo *libInfo); 13130b57cec5SDimitry Andric } // end namespace AArch64 13140b57cec5SDimitry Andric 13150b57cec5SDimitry Andric } // end namespace llvm 13160b57cec5SDimitry Andric 13170b57cec5SDimitry Andric #endif 1318