10b57cec5SDimitry Andric //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the interfaces that AArch64 uses to lower LLVM code into a 100b57cec5SDimitry Andric // selection DAG. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "AArch64.h" 18bdd1243dSDimitry Andric #include "Utils/AArch64SMEAttributes.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/CallingConvLower.h" 20fe6060f1SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/SelectionDAG.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 230b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h" 240b57cec5SDimitry Andric #include "llvm/IR/Instruction.h" 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric namespace llvm { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric namespace AArch64ISD { 290b57cec5SDimitry Andric 305ffd83dbSDimitry Andric // For predicated nodes where the result is a vector, the operation is 315ffd83dbSDimitry Andric // controlled by a governing predicate and the inactive lanes are explicitly 325ffd83dbSDimitry Andric // defined with a value, please stick the following naming convention: 335ffd83dbSDimitry Andric // 345ffd83dbSDimitry Andric // _MERGE_OP<n> The result value is a vector with inactive lanes equal 355ffd83dbSDimitry Andric // to source operand OP<n>. 365ffd83dbSDimitry Andric // 375ffd83dbSDimitry Andric // _MERGE_ZERO The result value is a vector with inactive lanes 385ffd83dbSDimitry Andric // actively zeroed. 395ffd83dbSDimitry Andric // 405ffd83dbSDimitry Andric // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal 415ffd83dbSDimitry Andric // to the last source operand which only purpose is being 425ffd83dbSDimitry Andric // a passthru value. 435ffd83dbSDimitry Andric // 445ffd83dbSDimitry Andric // For other cases where no explicit action is needed to set the inactive lanes, 455ffd83dbSDimitry Andric // or when the result is not a vector and it is needed or helpful to 465ffd83dbSDimitry Andric // distinguish a node from similar unpredicated nodes, use: 475ffd83dbSDimitry Andric // 485ffd83dbSDimitry Andric // _PRED 495ffd83dbSDimitry Andric // 500b57cec5SDimitry Andric enum NodeType : unsigned { 510b57cec5SDimitry Andric FIRST_NUMBER = ISD::BUILTIN_OP_END, 520b57cec5SDimitry Andric WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 530b57cec5SDimitry Andric CALL, // Function call. 540b57cec5SDimitry Andric 55fe6060f1SDimitry Andric // Pseudo for a OBJC call that gets emitted together with a special `mov 56fe6060f1SDimitry Andric // x29, x29` marker instruction. 57fe6060f1SDimitry Andric CALL_RVMARKER, 58fe6060f1SDimitry Andric 593a9a9c0cSDimitry Andric CALL_BTI, // Function call followed by a BTI instruction. 603a9a9c0cSDimitry Andric 61bdd1243dSDimitry Andric SMSTART, 62bdd1243dSDimitry Andric SMSTOP, 63bdd1243dSDimitry Andric RESTORE_ZA, 64bdd1243dSDimitry Andric 650b57cec5SDimitry Andric // Produces the full sequence of instructions for getting the thread pointer 660b57cec5SDimitry Andric // offset of a variable into X0, using the TLSDesc model. 670b57cec5SDimitry Andric TLSDESC_CALLSEQ, 680b57cec5SDimitry Andric ADRP, // Page address of a TargetGlobalAddress operand. 690b57cec5SDimitry Andric ADR, // ADR 700b57cec5SDimitry Andric ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 710b57cec5SDimitry Andric LOADgot, // Load from automatically generated descriptor (e.g. Global 720b57cec5SDimitry Andric // Offset Table, TLS record). 7306c3fb27SDimitry Andric RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand. 740b57cec5SDimitry Andric BRCOND, // Conditional branch instruction; "b.cond". 750b57cec5SDimitry Andric CSEL, 760b57cec5SDimitry Andric CSINV, // Conditional select invert. 770b57cec5SDimitry Andric CSNEG, // Conditional select negate. 780b57cec5SDimitry Andric CSINC, // Conditional select increment. 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 810b57cec5SDimitry Andric // ELF. 820b57cec5SDimitry Andric THREAD_POINTER, 830b57cec5SDimitry Andric ADC, 840b57cec5SDimitry Andric SBC, // adc, sbc instructions 850b57cec5SDimitry Andric 86*5f757f3fSDimitry Andric // To avoid stack clash, allocation is performed by block and each block is 87*5f757f3fSDimitry Andric // probed. 88*5f757f3fSDimitry Andric PROBED_ALLOCA, 89*5f757f3fSDimitry Andric 90e8d8bef9SDimitry Andric // Predicated instructions where inactive lanes produce undefined results. 9104eeddc0SDimitry Andric ABDS_PRED, 9204eeddc0SDimitry Andric ABDU_PRED, 935ffd83dbSDimitry Andric FADD_PRED, 94e8d8bef9SDimitry Andric FDIV_PRED, 955ffd83dbSDimitry Andric FMA_PRED, 96fe6060f1SDimitry Andric FMAX_PRED, 9704eeddc0SDimitry Andric FMAXNM_PRED, 98fe6060f1SDimitry Andric FMIN_PRED, 9904eeddc0SDimitry Andric FMINNM_PRED, 100e8d8bef9SDimitry Andric FMUL_PRED, 101e8d8bef9SDimitry Andric FSUB_PRED, 102bdd1243dSDimitry Andric HADDS_PRED, 103bdd1243dSDimitry Andric HADDU_PRED, 104e8d8bef9SDimitry Andric MUL_PRED, 105fe6060f1SDimitry Andric MULHS_PRED, 106fe6060f1SDimitry Andric MULHU_PRED, 107bdd1243dSDimitry Andric RHADDS_PRED, 108bdd1243dSDimitry Andric RHADDU_PRED, 109e8d8bef9SDimitry Andric SDIV_PRED, 110e8d8bef9SDimitry Andric SHL_PRED, 111e8d8bef9SDimitry Andric SMAX_PRED, 112e8d8bef9SDimitry Andric SMIN_PRED, 113e8d8bef9SDimitry Andric SRA_PRED, 114e8d8bef9SDimitry Andric SRL_PRED, 115e8d8bef9SDimitry Andric UDIV_PRED, 116e8d8bef9SDimitry Andric UMAX_PRED, 117e8d8bef9SDimitry Andric UMIN_PRED, 118e8d8bef9SDimitry Andric 119fe6060f1SDimitry Andric // Unpredicated vector instructions 120fe6060f1SDimitry Andric BIC, 121fe6060f1SDimitry Andric 1224824e7fdSDimitry Andric SRAD_MERGE_OP1, 1234824e7fdSDimitry Andric 124e8d8bef9SDimitry Andric // Predicated instructions with the result of inactive lanes provided by the 125e8d8bef9SDimitry Andric // last operand. 126e8d8bef9SDimitry Andric FABS_MERGE_PASSTHRU, 127e8d8bef9SDimitry Andric FCEIL_MERGE_PASSTHRU, 128e8d8bef9SDimitry Andric FFLOOR_MERGE_PASSTHRU, 129e8d8bef9SDimitry Andric FNEARBYINT_MERGE_PASSTHRU, 130e8d8bef9SDimitry Andric FNEG_MERGE_PASSTHRU, 131e8d8bef9SDimitry Andric FRECPX_MERGE_PASSTHRU, 132e8d8bef9SDimitry Andric FRINT_MERGE_PASSTHRU, 133e8d8bef9SDimitry Andric FROUND_MERGE_PASSTHRU, 134e8d8bef9SDimitry Andric FROUNDEVEN_MERGE_PASSTHRU, 135e8d8bef9SDimitry Andric FSQRT_MERGE_PASSTHRU, 136e8d8bef9SDimitry Andric FTRUNC_MERGE_PASSTHRU, 137e8d8bef9SDimitry Andric FP_ROUND_MERGE_PASSTHRU, 138e8d8bef9SDimitry Andric FP_EXTEND_MERGE_PASSTHRU, 139e8d8bef9SDimitry Andric UINT_TO_FP_MERGE_PASSTHRU, 140e8d8bef9SDimitry Andric SINT_TO_FP_MERGE_PASSTHRU, 141e8d8bef9SDimitry Andric FCVTZU_MERGE_PASSTHRU, 142e8d8bef9SDimitry Andric FCVTZS_MERGE_PASSTHRU, 143e8d8bef9SDimitry Andric SIGN_EXTEND_INREG_MERGE_PASSTHRU, 144e8d8bef9SDimitry Andric ZERO_EXTEND_INREG_MERGE_PASSTHRU, 145e8d8bef9SDimitry Andric ABS_MERGE_PASSTHRU, 146e8d8bef9SDimitry Andric NEG_MERGE_PASSTHRU, 1475ffd83dbSDimitry Andric 1485ffd83dbSDimitry Andric SETCC_MERGE_ZERO, 1495ffd83dbSDimitry Andric 1500b57cec5SDimitry Andric // Arithmetic instructions which write flags. 1510b57cec5SDimitry Andric ADDS, 1520b57cec5SDimitry Andric SUBS, 1530b57cec5SDimitry Andric ADCS, 1540b57cec5SDimitry Andric SBCS, 1550b57cec5SDimitry Andric ANDS, 1560b57cec5SDimitry Andric 1570b57cec5SDimitry Andric // Conditional compares. Operands: left,right,falsecc,cc,flags 1580b57cec5SDimitry Andric CCMP, 1590b57cec5SDimitry Andric CCMN, 1600b57cec5SDimitry Andric FCCMP, 1610b57cec5SDimitry Andric 1620b57cec5SDimitry Andric // Floating point comparison 1630b57cec5SDimitry Andric FCMP, 1640b57cec5SDimitry Andric 1650b57cec5SDimitry Andric // Scalar-to-vector duplication 1660b57cec5SDimitry Andric DUP, 1670b57cec5SDimitry Andric DUPLANE8, 1680b57cec5SDimitry Andric DUPLANE16, 1690b57cec5SDimitry Andric DUPLANE32, 1700b57cec5SDimitry Andric DUPLANE64, 17181ad6265SDimitry Andric DUPLANE128, 1720b57cec5SDimitry Andric 1730b57cec5SDimitry Andric // Vector immedate moves 1740b57cec5SDimitry Andric MOVI, 1750b57cec5SDimitry Andric MOVIshift, 1760b57cec5SDimitry Andric MOVIedit, 1770b57cec5SDimitry Andric MOVImsl, 1780b57cec5SDimitry Andric FMOV, 1790b57cec5SDimitry Andric MVNIshift, 1800b57cec5SDimitry Andric MVNImsl, 1810b57cec5SDimitry Andric 1820b57cec5SDimitry Andric // Vector immediate ops 1830b57cec5SDimitry Andric BICi, 1840b57cec5SDimitry Andric ORRi, 1850b57cec5SDimitry Andric 1865ffd83dbSDimitry Andric // Vector bitwise select: similar to ISD::VSELECT but not all bits within an 1870b57cec5SDimitry Andric // element must be identical. 1885ffd83dbSDimitry Andric BSP, 1890b57cec5SDimitry Andric 1900b57cec5SDimitry Andric // Vector shuffles 1910b57cec5SDimitry Andric ZIP1, 1920b57cec5SDimitry Andric ZIP2, 1930b57cec5SDimitry Andric UZP1, 1940b57cec5SDimitry Andric UZP2, 1950b57cec5SDimitry Andric TRN1, 1960b57cec5SDimitry Andric TRN2, 1970b57cec5SDimitry Andric REV16, 1980b57cec5SDimitry Andric REV32, 1990b57cec5SDimitry Andric REV64, 2000b57cec5SDimitry Andric EXT, 201fe6060f1SDimitry Andric SPLICE, 2020b57cec5SDimitry Andric 2030b57cec5SDimitry Andric // Vector shift by scalar 2040b57cec5SDimitry Andric VSHL, 2050b57cec5SDimitry Andric VLSHR, 2060b57cec5SDimitry Andric VASHR, 2070b57cec5SDimitry Andric 2080b57cec5SDimitry Andric // Vector shift by scalar (again) 2090b57cec5SDimitry Andric SQSHL_I, 2100b57cec5SDimitry Andric UQSHL_I, 2110b57cec5SDimitry Andric SQSHLU_I, 2120b57cec5SDimitry Andric SRSHR_I, 2130b57cec5SDimitry Andric URSHR_I, 2140b57cec5SDimitry Andric 215*5f757f3fSDimitry Andric // Vector narrowing shift by immediate (bottom) 216*5f757f3fSDimitry Andric RSHRNB_I, 217*5f757f3fSDimitry Andric 2185ffd83dbSDimitry Andric // Vector shift by constant and insert 2195ffd83dbSDimitry Andric VSLI, 2205ffd83dbSDimitry Andric VSRI, 2215ffd83dbSDimitry Andric 2220b57cec5SDimitry Andric // Vector comparisons 2230b57cec5SDimitry Andric CMEQ, 2240b57cec5SDimitry Andric CMGE, 2250b57cec5SDimitry Andric CMGT, 2260b57cec5SDimitry Andric CMHI, 2270b57cec5SDimitry Andric CMHS, 2280b57cec5SDimitry Andric FCMEQ, 2290b57cec5SDimitry Andric FCMGE, 2300b57cec5SDimitry Andric FCMGT, 2310b57cec5SDimitry Andric 2320b57cec5SDimitry Andric // Vector zero comparisons 2330b57cec5SDimitry Andric CMEQz, 2340b57cec5SDimitry Andric CMGEz, 2350b57cec5SDimitry Andric CMGTz, 2360b57cec5SDimitry Andric CMLEz, 2370b57cec5SDimitry Andric CMLTz, 2380b57cec5SDimitry Andric FCMEQz, 2390b57cec5SDimitry Andric FCMGEz, 2400b57cec5SDimitry Andric FCMGTz, 2410b57cec5SDimitry Andric FCMLEz, 2420b57cec5SDimitry Andric FCMLTz, 2430b57cec5SDimitry Andric 2440b57cec5SDimitry Andric // Vector across-lanes addition 2450b57cec5SDimitry Andric // Only the lower result lane is defined. 2460b57cec5SDimitry Andric SADDV, 2470b57cec5SDimitry Andric UADDV, 2480b57cec5SDimitry Andric 249*5f757f3fSDimitry Andric // Unsigned sum Long across Vector 250*5f757f3fSDimitry Andric UADDLV, 251*5f757f3fSDimitry Andric 25281ad6265SDimitry Andric // Add Pairwise of two vectors 25381ad6265SDimitry Andric ADDP, 25481ad6265SDimitry Andric // Add Long Pairwise 25581ad6265SDimitry Andric SADDLP, 256fe6060f1SDimitry Andric UADDLP, 257fe6060f1SDimitry Andric 258fe6060f1SDimitry Andric // udot/sdot instructions 259fe6060f1SDimitry Andric UDOT, 260fe6060f1SDimitry Andric SDOT, 261e8d8bef9SDimitry Andric 2620b57cec5SDimitry Andric // Vector across-lanes min/max 2630b57cec5SDimitry Andric // Only the lower result lane is defined. 2640b57cec5SDimitry Andric SMINV, 2650b57cec5SDimitry Andric UMINV, 2660b57cec5SDimitry Andric SMAXV, 2670b57cec5SDimitry Andric UMAXV, 2680b57cec5SDimitry Andric 269e8d8bef9SDimitry Andric SADDV_PRED, 270e8d8bef9SDimitry Andric UADDV_PRED, 271480093f4SDimitry Andric SMAXV_PRED, 272480093f4SDimitry Andric UMAXV_PRED, 273480093f4SDimitry Andric SMINV_PRED, 274480093f4SDimitry Andric UMINV_PRED, 275480093f4SDimitry Andric ORV_PRED, 276480093f4SDimitry Andric EORV_PRED, 277480093f4SDimitry Andric ANDV_PRED, 278480093f4SDimitry Andric 2795ffd83dbSDimitry Andric // Vector bitwise insertion 2800b57cec5SDimitry Andric BIT, 2810b57cec5SDimitry Andric 2820b57cec5SDimitry Andric // Compare-and-branch 2830b57cec5SDimitry Andric CBZ, 2840b57cec5SDimitry Andric CBNZ, 2850b57cec5SDimitry Andric TBZ, 2860b57cec5SDimitry Andric TBNZ, 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andric // Tail calls 2890b57cec5SDimitry Andric TC_RETURN, 2900b57cec5SDimitry Andric 2910b57cec5SDimitry Andric // Custom prefetch handling 2920b57cec5SDimitry Andric PREFETCH, 2930b57cec5SDimitry Andric 2940b57cec5SDimitry Andric // {s|u}int to FP within a FP register. 2950b57cec5SDimitry Andric SITOF, 2960b57cec5SDimitry Andric UITOF, 2970b57cec5SDimitry Andric 2980b57cec5SDimitry Andric /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 2990b57cec5SDimitry Andric /// world w.r.t vectors; which causes additional REV instructions to be 3000b57cec5SDimitry Andric /// generated to compensate for the byte-swapping. But sometimes we do 3010b57cec5SDimitry Andric /// need to re-interpret the data in SIMD vector registers in big-endian 3020b57cec5SDimitry Andric /// mode without emitting such REV instructions. 3030b57cec5SDimitry Andric NVCAST, 3040b57cec5SDimitry Andric 305fe6060f1SDimitry Andric MRS, // MRS, also sets the flags via a glue. 306fe6060f1SDimitry Andric 3070b57cec5SDimitry Andric SMULL, 3080b57cec5SDimitry Andric UMULL, 3090b57cec5SDimitry Andric 310bdd1243dSDimitry Andric PMULL, 311bdd1243dSDimitry Andric 3120b57cec5SDimitry Andric // Reciprocal estimates and steps. 3135ffd83dbSDimitry Andric FRECPE, 3145ffd83dbSDimitry Andric FRECPS, 3155ffd83dbSDimitry Andric FRSQRTE, 3165ffd83dbSDimitry Andric FRSQRTS, 3170b57cec5SDimitry Andric 3188bcb0991SDimitry Andric SUNPKHI, 3198bcb0991SDimitry Andric SUNPKLO, 3208bcb0991SDimitry Andric UUNPKHI, 3218bcb0991SDimitry Andric UUNPKLO, 3228bcb0991SDimitry Andric 323480093f4SDimitry Andric CLASTA_N, 324480093f4SDimitry Andric CLASTB_N, 325480093f4SDimitry Andric LASTA, 326480093f4SDimitry Andric LASTB, 327480093f4SDimitry Andric TBL, 328480093f4SDimitry Andric 3295ffd83dbSDimitry Andric // Floating-point reductions. 3305ffd83dbSDimitry Andric FADDA_PRED, 3315ffd83dbSDimitry Andric FADDV_PRED, 3325ffd83dbSDimitry Andric FMAXV_PRED, 3335ffd83dbSDimitry Andric FMAXNMV_PRED, 3345ffd83dbSDimitry Andric FMINV_PRED, 3355ffd83dbSDimitry Andric FMINNMV_PRED, 3365ffd83dbSDimitry Andric 337480093f4SDimitry Andric INSR, 338480093f4SDimitry Andric PTEST, 339bdd1243dSDimitry Andric PTEST_ANY, 340480093f4SDimitry Andric PTRUE, 341480093f4SDimitry Andric 342*5f757f3fSDimitry Andric CTTZ_ELTS, 343*5f757f3fSDimitry Andric 344e8d8bef9SDimitry Andric BITREVERSE_MERGE_PASSTHRU, 345e8d8bef9SDimitry Andric BSWAP_MERGE_PASSTHRU, 3460eae32dcSDimitry Andric REVH_MERGE_PASSTHRU, 3470eae32dcSDimitry Andric REVW_MERGE_PASSTHRU, 348e8d8bef9SDimitry Andric CTLZ_MERGE_PASSTHRU, 349e8d8bef9SDimitry Andric CTPOP_MERGE_PASSTHRU, 3505ffd83dbSDimitry Andric DUP_MERGE_PASSTHRU, 3515ffd83dbSDimitry Andric INDEX_VECTOR, 3525ffd83dbSDimitry Andric 353e8d8bef9SDimitry Andric // Cast between vectors of the same element type but differ in length. 3545ffd83dbSDimitry Andric REINTERPRET_CAST, 3555ffd83dbSDimitry Andric 3566e75b2fbSDimitry Andric // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa 3576e75b2fbSDimitry Andric LS64_BUILD, 3586e75b2fbSDimitry Andric LS64_EXTRACT, 3596e75b2fbSDimitry Andric 3605ffd83dbSDimitry Andric LD1_MERGE_ZERO, 3615ffd83dbSDimitry Andric LD1S_MERGE_ZERO, 3625ffd83dbSDimitry Andric LDNF1_MERGE_ZERO, 3635ffd83dbSDimitry Andric LDNF1S_MERGE_ZERO, 3645ffd83dbSDimitry Andric LDFF1_MERGE_ZERO, 3655ffd83dbSDimitry Andric LDFF1S_MERGE_ZERO, 3665ffd83dbSDimitry Andric LD1RQ_MERGE_ZERO, 3675ffd83dbSDimitry Andric LD1RO_MERGE_ZERO, 3685ffd83dbSDimitry Andric 3695ffd83dbSDimitry Andric // Structured loads. 3705ffd83dbSDimitry Andric SVE_LD2_MERGE_ZERO, 3715ffd83dbSDimitry Andric SVE_LD3_MERGE_ZERO, 3725ffd83dbSDimitry Andric SVE_LD4_MERGE_ZERO, 3735ffd83dbSDimitry Andric 374480093f4SDimitry Andric // Unsigned gather loads. 3755ffd83dbSDimitry Andric GLD1_MERGE_ZERO, 3765ffd83dbSDimitry Andric GLD1_SCALED_MERGE_ZERO, 3775ffd83dbSDimitry Andric GLD1_UXTW_MERGE_ZERO, 3785ffd83dbSDimitry Andric GLD1_SXTW_MERGE_ZERO, 3795ffd83dbSDimitry Andric GLD1_UXTW_SCALED_MERGE_ZERO, 3805ffd83dbSDimitry Andric GLD1_SXTW_SCALED_MERGE_ZERO, 3815ffd83dbSDimitry Andric GLD1_IMM_MERGE_ZERO, 382*5f757f3fSDimitry Andric GLD1Q_MERGE_ZERO, 383*5f757f3fSDimitry Andric GLD1Q_INDEX_MERGE_ZERO, 384480093f4SDimitry Andric 385480093f4SDimitry Andric // Signed gather loads 3865ffd83dbSDimitry Andric GLD1S_MERGE_ZERO, 3875ffd83dbSDimitry Andric GLD1S_SCALED_MERGE_ZERO, 3885ffd83dbSDimitry Andric GLD1S_UXTW_MERGE_ZERO, 3895ffd83dbSDimitry Andric GLD1S_SXTW_MERGE_ZERO, 3905ffd83dbSDimitry Andric GLD1S_UXTW_SCALED_MERGE_ZERO, 3915ffd83dbSDimitry Andric GLD1S_SXTW_SCALED_MERGE_ZERO, 3925ffd83dbSDimitry Andric GLD1S_IMM_MERGE_ZERO, 3935ffd83dbSDimitry Andric 3945ffd83dbSDimitry Andric // Unsigned gather loads. 3955ffd83dbSDimitry Andric GLDFF1_MERGE_ZERO, 3965ffd83dbSDimitry Andric GLDFF1_SCALED_MERGE_ZERO, 3975ffd83dbSDimitry Andric GLDFF1_UXTW_MERGE_ZERO, 3985ffd83dbSDimitry Andric GLDFF1_SXTW_MERGE_ZERO, 3995ffd83dbSDimitry Andric GLDFF1_UXTW_SCALED_MERGE_ZERO, 4005ffd83dbSDimitry Andric GLDFF1_SXTW_SCALED_MERGE_ZERO, 4015ffd83dbSDimitry Andric GLDFF1_IMM_MERGE_ZERO, 4025ffd83dbSDimitry Andric 4035ffd83dbSDimitry Andric // Signed gather loads. 4045ffd83dbSDimitry Andric GLDFF1S_MERGE_ZERO, 4055ffd83dbSDimitry Andric GLDFF1S_SCALED_MERGE_ZERO, 4065ffd83dbSDimitry Andric GLDFF1S_UXTW_MERGE_ZERO, 4075ffd83dbSDimitry Andric GLDFF1S_SXTW_MERGE_ZERO, 4085ffd83dbSDimitry Andric GLDFF1S_UXTW_SCALED_MERGE_ZERO, 4095ffd83dbSDimitry Andric GLDFF1S_SXTW_SCALED_MERGE_ZERO, 4105ffd83dbSDimitry Andric GLDFF1S_IMM_MERGE_ZERO, 4115ffd83dbSDimitry Andric 4125ffd83dbSDimitry Andric // Non-temporal gather loads 4135ffd83dbSDimitry Andric GLDNT1_MERGE_ZERO, 4145ffd83dbSDimitry Andric GLDNT1_INDEX_MERGE_ZERO, 4155ffd83dbSDimitry Andric GLDNT1S_MERGE_ZERO, 4165ffd83dbSDimitry Andric 4175ffd83dbSDimitry Andric // Contiguous masked store. 4185ffd83dbSDimitry Andric ST1_PRED, 4195ffd83dbSDimitry Andric 420480093f4SDimitry Andric // Scatter store 4215ffd83dbSDimitry Andric SST1_PRED, 4225ffd83dbSDimitry Andric SST1_SCALED_PRED, 4235ffd83dbSDimitry Andric SST1_UXTW_PRED, 4245ffd83dbSDimitry Andric SST1_SXTW_PRED, 4255ffd83dbSDimitry Andric SST1_UXTW_SCALED_PRED, 4265ffd83dbSDimitry Andric SST1_SXTW_SCALED_PRED, 4275ffd83dbSDimitry Andric SST1_IMM_PRED, 428*5f757f3fSDimitry Andric SST1Q_PRED, 429*5f757f3fSDimitry Andric SST1Q_INDEX_PRED, 4305ffd83dbSDimitry Andric 4315ffd83dbSDimitry Andric // Non-temporal scatter store 4325ffd83dbSDimitry Andric SSTNT1_PRED, 4335ffd83dbSDimitry Andric SSTNT1_INDEX_PRED, 434480093f4SDimitry Andric 43581ad6265SDimitry Andric // SME 43681ad6265SDimitry Andric RDSVL, 43781ad6265SDimitry Andric REVD_MERGE_PASSTHRU, 43881ad6265SDimitry Andric 439349cc55cSDimitry Andric // Asserts that a function argument (i32) is zero-extended to i8 by 440349cc55cSDimitry Andric // the caller 441349cc55cSDimitry Andric ASSERT_ZEXT_BOOL, 442349cc55cSDimitry Andric 443bdd1243dSDimitry Andric // 128-bit system register accesses 444bdd1243dSDimitry Andric // lo64, hi64, chain = MRRS(chain, sysregname) 445bdd1243dSDimitry Andric MRRS, 446bdd1243dSDimitry Andric // chain = MSRR(chain, sysregname, lo64, hi64) 447bdd1243dSDimitry Andric MSRR, 448bdd1243dSDimitry Andric 44947395794SDimitry Andric // Strict (exception-raising) floating point comparison 45047395794SDimitry Andric STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 45147395794SDimitry Andric STRICT_FCMPE, 45247395794SDimitry Andric 453*5f757f3fSDimitry Andric // SME ZA loads and stores 454*5f757f3fSDimitry Andric SME_ZA_LDR, 455*5f757f3fSDimitry Andric SME_ZA_STR, 456*5f757f3fSDimitry Andric 4570b57cec5SDimitry Andric // NEON Load/Store with post-increment base updates 4580b57cec5SDimitry Andric LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 4590b57cec5SDimitry Andric LD3post, 4600b57cec5SDimitry Andric LD4post, 4610b57cec5SDimitry Andric ST2post, 4620b57cec5SDimitry Andric ST3post, 4630b57cec5SDimitry Andric ST4post, 4640b57cec5SDimitry Andric LD1x2post, 4650b57cec5SDimitry Andric LD1x3post, 4660b57cec5SDimitry Andric LD1x4post, 4670b57cec5SDimitry Andric ST1x2post, 4680b57cec5SDimitry Andric ST1x3post, 4690b57cec5SDimitry Andric ST1x4post, 4700b57cec5SDimitry Andric LD1DUPpost, 4710b57cec5SDimitry Andric LD2DUPpost, 4720b57cec5SDimitry Andric LD3DUPpost, 4730b57cec5SDimitry Andric LD4DUPpost, 4740b57cec5SDimitry Andric LD1LANEpost, 4750b57cec5SDimitry Andric LD2LANEpost, 4760b57cec5SDimitry Andric LD3LANEpost, 4770b57cec5SDimitry Andric LD4LANEpost, 4780b57cec5SDimitry Andric ST2LANEpost, 4790b57cec5SDimitry Andric ST3LANEpost, 4800b57cec5SDimitry Andric ST4LANEpost, 4810b57cec5SDimitry Andric 4820b57cec5SDimitry Andric STG, 4830b57cec5SDimitry Andric STZG, 4840b57cec5SDimitry Andric ST2G, 485480093f4SDimitry Andric STZ2G, 4860b57cec5SDimitry Andric 487480093f4SDimitry Andric LDP, 48806c3fb27SDimitry Andric LDIAPP, 489bdd1243dSDimitry Andric LDNP, 4905ffd83dbSDimitry Andric STP, 49106c3fb27SDimitry Andric STILP, 492e8d8bef9SDimitry Andric STNP, 4931fd87a68SDimitry Andric 4941fd87a68SDimitry Andric // Memory Operations 4951fd87a68SDimitry Andric MOPS_MEMSET, 4961fd87a68SDimitry Andric MOPS_MEMSET_TAGGING, 4971fd87a68SDimitry Andric MOPS_MEMCOPY, 4981fd87a68SDimitry Andric MOPS_MEMMOVE, 4990b57cec5SDimitry Andric }; 5000b57cec5SDimitry Andric 5010b57cec5SDimitry Andric } // end namespace AArch64ISD 5020b57cec5SDimitry Andric 503fe6060f1SDimitry Andric namespace AArch64 { 504fe6060f1SDimitry Andric /// Possible values of current rounding mode, which is specified in bits 505fe6060f1SDimitry Andric /// 23:22 of FPCR. 506fe6060f1SDimitry Andric enum Rounding { 507fe6060f1SDimitry Andric RN = 0, // Round to Nearest 508fe6060f1SDimitry Andric RP = 1, // Round towards Plus infinity 509fe6060f1SDimitry Andric RM = 2, // Round towards Minus infinity 510fe6060f1SDimitry Andric RZ = 3, // Round towards Zero 511fe6060f1SDimitry Andric rmMask = 3 // Bit mask selecting rounding mode 512fe6060f1SDimitry Andric }; 513fe6060f1SDimitry Andric 514fe6060f1SDimitry Andric // Bit position of rounding mode bits in FPCR. 515fe6060f1SDimitry Andric const unsigned RoundingBitsPos = 22; 51606c3fb27SDimitry Andric 51706c3fb27SDimitry Andric // Registers used to pass function arguments. 518*5f757f3fSDimitry Andric ArrayRef<MCPhysReg> getGPRArgRegs(); 519*5f757f3fSDimitry Andric ArrayRef<MCPhysReg> getFPRArgRegs(); 520*5f757f3fSDimitry Andric 521*5f757f3fSDimitry Andric /// Maximum allowed number of unprobed bytes above SP at an ABI 522*5f757f3fSDimitry Andric /// boundary. 523*5f757f3fSDimitry Andric const unsigned StackProbeMaxUnprobedStack = 1024; 524*5f757f3fSDimitry Andric 525*5f757f3fSDimitry Andric /// Maximum number of iterations to unroll for a constant size probing loop. 526*5f757f3fSDimitry Andric const unsigned StackProbeMaxLoopUnroll = 4; 52706c3fb27SDimitry Andric 528fe6060f1SDimitry Andric } // namespace AArch64 529fe6060f1SDimitry Andric 5300b57cec5SDimitry Andric class AArch64Subtarget; 5310b57cec5SDimitry Andric 5320b57cec5SDimitry Andric class AArch64TargetLowering : public TargetLowering { 5330b57cec5SDimitry Andric public: 5340b57cec5SDimitry Andric explicit AArch64TargetLowering(const TargetMachine &TM, 5350b57cec5SDimitry Andric const AArch64Subtarget &STI); 5360b57cec5SDimitry Andric 53781ad6265SDimitry Andric /// Control the following reassociation of operands: (op (op x, c1), y) -> (op 53881ad6265SDimitry Andric /// (op x, y), c1) where N0 is (op x, c1) and N1 is y. 53981ad6265SDimitry Andric bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 54081ad6265SDimitry Andric SDValue N1) const override; 54181ad6265SDimitry Andric 5420b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5430b57cec5SDimitry Andric CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 5440b57cec5SDimitry Andric 5450b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5460b57cec5SDimitry Andric CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 5470b57cec5SDimitry Andric 5480b57cec5SDimitry Andric /// Determine which of the bits specified in Mask are known to be either zero 5490b57cec5SDimitry Andric /// or one and return them in the KnownZero/KnownOne bitsets. 5500b57cec5SDimitry Andric void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 5510b57cec5SDimitry Andric const APInt &DemandedElts, 5520b57cec5SDimitry Andric const SelectionDAG &DAG, 5530b57cec5SDimitry Andric unsigned Depth = 0) const override; 5540b57cec5SDimitry Andric 55506c3fb27SDimitry Andric unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 55606c3fb27SDimitry Andric const APInt &DemandedElts, 55706c3fb27SDimitry Andric const SelectionDAG &DAG, 55806c3fb27SDimitry Andric unsigned Depth) const override; 55906c3fb27SDimitry Andric 5608bcb0991SDimitry Andric MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override { 5618bcb0991SDimitry Andric // Returning i64 unconditionally here (i.e. even for ILP32) means that the 5628bcb0991SDimitry Andric // *DAG* representation of pointers will always be 64-bits. They will be 5638bcb0991SDimitry Andric // truncated and extended when transferred to memory, but the 64-bit DAG 5648bcb0991SDimitry Andric // allows us to use AArch64's addressing modes much more easily. 5658bcb0991SDimitry Andric return MVT::getIntegerVT(64); 5668bcb0991SDimitry Andric } 5678bcb0991SDimitry Andric 5685ffd83dbSDimitry Andric bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 5695ffd83dbSDimitry Andric const APInt &DemandedElts, 5700b57cec5SDimitry Andric TargetLoweringOpt &TLO) const override; 5710b57cec5SDimitry Andric 5720b57cec5SDimitry Andric MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override; 5730b57cec5SDimitry Andric 5740b57cec5SDimitry Andric /// Returns true if the target allows unaligned memory accesses of the 5750b57cec5SDimitry Andric /// specified type. 5760b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses( 577fe6060f1SDimitry Andric EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 5780b57cec5SDimitry Andric MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 579bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5808bcb0991SDimitry Andric /// LLT variant. 5815ffd83dbSDimitry Andric bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, 5825ffd83dbSDimitry Andric Align Alignment, 5835ffd83dbSDimitry Andric MachineMemOperand::Flags Flags, 584bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5850b57cec5SDimitry Andric 5860b57cec5SDimitry Andric /// Provide custom lowering hooks for some operations. 5870b57cec5SDimitry Andric SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 5880b57cec5SDimitry Andric 5890b57cec5SDimitry Andric const char *getTargetNodeName(unsigned Opcode) const override; 5900b57cec5SDimitry Andric 5910b57cec5SDimitry Andric SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 5920b57cec5SDimitry Andric 5930b57cec5SDimitry Andric /// This method returns a target specific FastISel object, or null if the 5940b57cec5SDimitry Andric /// target does not support "fast" ISel. 5950b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 5960b57cec5SDimitry Andric const TargetLibraryInfo *libInfo) const override; 5970b57cec5SDimitry Andric 5980b57cec5SDimitry Andric bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 5990b57cec5SDimitry Andric 6000b57cec5SDimitry Andric bool isFPImmLegal(const APFloat &Imm, EVT VT, 6010b57cec5SDimitry Andric bool ForCodeSize) const override; 6020b57cec5SDimitry Andric 6030b57cec5SDimitry Andric /// Return true if the given shuffle mask can be codegen'd directly, or if it 6040b57cec5SDimitry Andric /// should be stack expanded. 6050b57cec5SDimitry Andric bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 6060b57cec5SDimitry Andric 607fcaf7f86SDimitry Andric /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero' 608fcaf7f86SDimitry Andric /// shuffle mask can be codegen'd directly. 609fcaf7f86SDimitry Andric bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override; 610fcaf7f86SDimitry Andric 6110b57cec5SDimitry Andric /// Return the ISD::SETCC ValueType. 6120b57cec5SDimitry Andric EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 6130b57cec5SDimitry Andric EVT VT) const override; 6140b57cec5SDimitry Andric 6150b57cec5SDimitry Andric SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 6160b57cec5SDimitry Andric 6170b57cec5SDimitry Andric MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, 6180b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6190b57cec5SDimitry Andric 6200b57cec5SDimitry Andric MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, 6210b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6220b57cec5SDimitry Andric 623*5f757f3fSDimitry Andric MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI, 624*5f757f3fSDimitry Andric MachineBasicBlock *MBB) const; 625*5f757f3fSDimitry Andric 62681ad6265SDimitry Andric MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg, 62781ad6265SDimitry Andric MachineInstr &MI, 62881ad6265SDimitry Andric MachineBasicBlock *BB) const; 62981ad6265SDimitry Andric MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const; 630bdd1243dSDimitry Andric MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg, 631bdd1243dSDimitry Andric MachineInstr &MI, MachineBasicBlock *BB, 632bdd1243dSDimitry Andric bool HasTile) const; 633*5f757f3fSDimitry Andric MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, 634*5f757f3fSDimitry Andric unsigned Opcode, bool Op0IsDef) const; 63581ad6265SDimitry Andric MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const; 63681ad6265SDimitry Andric 6370b57cec5SDimitry Andric MachineBasicBlock * 6380b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 6390b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 6400b57cec5SDimitry Andric 6410b57cec5SDimitry Andric bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 6420b57cec5SDimitry Andric MachineFunction &MF, 6430b57cec5SDimitry Andric unsigned Intrinsic) const override; 6440b57cec5SDimitry Andric 6450b57cec5SDimitry Andric bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 6460b57cec5SDimitry Andric EVT NewVT) const override; 6470b57cec5SDimitry Andric 64806c3fb27SDimitry Andric bool shouldRemoveRedundantExtend(SDValue Op) const override; 64906c3fb27SDimitry Andric 6500b57cec5SDimitry Andric bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 6510b57cec5SDimitry Andric bool isTruncateFree(EVT VT1, EVT VT2) const override; 6520b57cec5SDimitry Andric 6530b57cec5SDimitry Andric bool isProfitableToHoist(Instruction *I) const override; 6540b57cec5SDimitry Andric 6550b57cec5SDimitry Andric bool isZExtFree(Type *Ty1, Type *Ty2) const override; 6560b57cec5SDimitry Andric bool isZExtFree(EVT VT1, EVT VT2) const override; 6570b57cec5SDimitry Andric bool isZExtFree(SDValue Val, EVT VT2) const override; 6580b57cec5SDimitry Andric 6590b57cec5SDimitry Andric bool shouldSinkOperands(Instruction *I, 6600b57cec5SDimitry Andric SmallVectorImpl<Use *> &Ops) const override; 6610b57cec5SDimitry Andric 66206c3fb27SDimitry Andric bool optimizeExtendOrTruncateConversion( 66306c3fb27SDimitry Andric Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override; 664bdd1243dSDimitry Andric 6655ffd83dbSDimitry Andric bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override; 6660b57cec5SDimitry Andric 6670b57cec5SDimitry Andric unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 6680b57cec5SDimitry Andric 6690b57cec5SDimitry Andric bool lowerInterleavedLoad(LoadInst *LI, 6700b57cec5SDimitry Andric ArrayRef<ShuffleVectorInst *> Shuffles, 6710b57cec5SDimitry Andric ArrayRef<unsigned> Indices, 6720b57cec5SDimitry Andric unsigned Factor) const override; 6730b57cec5SDimitry Andric bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 6740b57cec5SDimitry Andric unsigned Factor) const override; 6750b57cec5SDimitry Andric 67606c3fb27SDimitry Andric bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, 67706c3fb27SDimitry Andric LoadInst *LI) const override; 67806c3fb27SDimitry Andric 67906c3fb27SDimitry Andric bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, 68006c3fb27SDimitry Andric StoreInst *SI) const override; 68106c3fb27SDimitry Andric 6820b57cec5SDimitry Andric bool isLegalAddImmediate(int64_t) const override; 6830b57cec5SDimitry Andric bool isLegalICmpImmediate(int64_t) const override; 6840b57cec5SDimitry Andric 68581ad6265SDimitry Andric bool isMulAddWithConstProfitable(SDValue AddNode, 68681ad6265SDimitry Andric SDValue ConstNode) const override; 687349cc55cSDimitry Andric 6880b57cec5SDimitry Andric bool shouldConsiderGEPOffsetSplit() const override; 6890b57cec5SDimitry Andric 6905ffd83dbSDimitry Andric EVT getOptimalMemOpType(const MemOp &Op, 6910b57cec5SDimitry Andric const AttributeList &FuncAttributes) const override; 6920b57cec5SDimitry Andric 6935ffd83dbSDimitry Andric LLT getOptimalMemOpLLT(const MemOp &Op, 6948bcb0991SDimitry Andric const AttributeList &FuncAttributes) const override; 6958bcb0991SDimitry Andric 6960b57cec5SDimitry Andric /// Return true if the addressing mode represented by AM is legal for this 6970b57cec5SDimitry Andric /// target, for a load/store of the specified type. 6980b57cec5SDimitry Andric bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 6990b57cec5SDimitry Andric unsigned AS, 7000b57cec5SDimitry Andric Instruction *I = nullptr) const override; 7010b57cec5SDimitry Andric 702*5f757f3fSDimitry Andric int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, 703*5f757f3fSDimitry Andric int64_t MaxOffset) const override; 704*5f757f3fSDimitry Andric 7050b57cec5SDimitry Andric /// Return true if an FMA operation is faster than a pair of fmul and fadd 7060b57cec5SDimitry Andric /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 7070b57cec5SDimitry Andric /// returns true, otherwise fmuladd is expanded to fmul + fadd. 708480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 709480093f4SDimitry Andric EVT VT) const override; 710480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 7110b57cec5SDimitry Andric 712fe6060f1SDimitry Andric bool generateFMAsInMachineCombiner(EVT VT, 713*5f757f3fSDimitry Andric CodeGenOptLevel OptLevel) const override; 714fe6060f1SDimitry Andric 7150b57cec5SDimitry Andric const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 71606c3fb27SDimitry Andric ArrayRef<MCPhysReg> getRoundingControlRegisters() const override; 7170b57cec5SDimitry Andric 7180b57cec5SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 7190b57cec5SDimitry Andric bool isDesirableToCommuteWithShift(const SDNode *N, 7200b57cec5SDimitry Andric CombineLevel Level) const override; 7210b57cec5SDimitry Andric 722*5f757f3fSDimitry Andric bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override { 723*5f757f3fSDimitry Andric return false; 724*5f757f3fSDimitry Andric } 725*5f757f3fSDimitry Andric 726fcaf7f86SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 727fcaf7f86SDimitry Andric bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 728fcaf7f86SDimitry Andric 72981ad6265SDimitry Andric /// Return true if it is profitable to fold a pair of shifts into a mask. 73081ad6265SDimitry Andric bool shouldFoldConstantShiftPairToMask(const SDNode *N, 73181ad6265SDimitry Andric CombineLevel Level) const override; 73281ad6265SDimitry Andric 73306c3fb27SDimitry Andric bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 73406c3fb27SDimitry Andric EVT VT) const override; 73506c3fb27SDimitry Andric 7360b57cec5SDimitry Andric /// Returns true if it is beneficial to convert a load of a constant 7370b57cec5SDimitry Andric /// to just the constant itself. 7380b57cec5SDimitry Andric bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 7390b57cec5SDimitry Andric Type *Ty) const override; 7400b57cec5SDimitry Andric 7410b57cec5SDimitry Andric /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 7420b57cec5SDimitry Andric /// with this index. 7430b57cec5SDimitry Andric bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 7440b57cec5SDimitry Andric unsigned Index) const override; 7450b57cec5SDimitry Andric 7465ffd83dbSDimitry Andric bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 7475ffd83dbSDimitry Andric bool MathUsed) const override { 7485ffd83dbSDimitry Andric // Using overflow ops for overflow checks only should beneficial on 7495ffd83dbSDimitry Andric // AArch64. 7505ffd83dbSDimitry Andric return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 7515ffd83dbSDimitry Andric } 7525ffd83dbSDimitry Andric 753fe6060f1SDimitry Andric Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 7540b57cec5SDimitry Andric AtomicOrdering Ord) const override; 755fe6060f1SDimitry Andric Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 756fe6060f1SDimitry Andric AtomicOrdering Ord) const override; 7570b57cec5SDimitry Andric 758fe6060f1SDimitry Andric void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 7590b57cec5SDimitry Andric 760349cc55cSDimitry Andric bool isOpSuitableForLDPSTP(const Instruction *I) const; 76106c3fb27SDimitry Andric bool isOpSuitableForLSE128(const Instruction *I) const; 76206c3fb27SDimitry Andric bool isOpSuitableForRCPC3(const Instruction *I) const; 763349cc55cSDimitry Andric bool shouldInsertFencesForAtomic(const Instruction *I) const override; 764bdd1243dSDimitry Andric bool 765bdd1243dSDimitry Andric shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override; 766349cc55cSDimitry Andric 7670b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7680b57cec5SDimitry Andric shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 76981ad6265SDimitry Andric TargetLoweringBase::AtomicExpansionKind 77081ad6265SDimitry Andric shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 7710b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7720b57cec5SDimitry Andric shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 7730b57cec5SDimitry Andric 7740b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7750b57cec5SDimitry Andric shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 7760b57cec5SDimitry Andric 7770b57cec5SDimitry Andric bool useLoadStackGuardNode() const override; 7780b57cec5SDimitry Andric TargetLoweringBase::LegalizeTypeAction 7790b57cec5SDimitry Andric getPreferredVectorAction(MVT VT) const override; 7800b57cec5SDimitry Andric 7810b57cec5SDimitry Andric /// If the target has a standard location for the stack protector cookie, 7820b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 783fe6060f1SDimitry Andric Value *getIRStackGuard(IRBuilderBase &IRB) const override; 7840b57cec5SDimitry Andric 7850b57cec5SDimitry Andric void insertSSPDeclarations(Module &M) const override; 7860b57cec5SDimitry Andric Value *getSDagStackGuard(const Module &M) const override; 7870b57cec5SDimitry Andric Function *getSSPStackGuardCheck(const Module &M) const override; 7880b57cec5SDimitry Andric 7890b57cec5SDimitry Andric /// If the target has a standard location for the unsafe stack pointer, 7900b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 791fe6060f1SDimitry Andric Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; 7920b57cec5SDimitry Andric 7930b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 7940b57cec5SDimitry Andric /// exception address on entry to an EH pad. 7955ffd83dbSDimitry Andric Register 7960b57cec5SDimitry Andric getExceptionPointerRegister(const Constant *PersonalityFn) const override { 7970b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 7980b57cec5SDimitry Andric return AArch64::X0; 7990b57cec5SDimitry Andric } 8000b57cec5SDimitry Andric 8010b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8020b57cec5SDimitry Andric /// exception typeid on entry to a landing pad. 8035ffd83dbSDimitry Andric Register 8040b57cec5SDimitry Andric getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 8050b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8060b57cec5SDimitry Andric return AArch64::X1; 8070b57cec5SDimitry Andric } 8080b57cec5SDimitry Andric 8090b57cec5SDimitry Andric bool isIntDivCheap(EVT VT, AttributeList Attr) const override; 8100b57cec5SDimitry Andric 8110b57cec5SDimitry Andric bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 812349cc55cSDimitry Andric const MachineFunction &MF) const override { 8130b57cec5SDimitry Andric // Do not merge to float value size (128 bytes) if no implicit 8140b57cec5SDimitry Andric // float attribute is set. 8150b57cec5SDimitry Andric 816349cc55cSDimitry Andric bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat); 8170b57cec5SDimitry Andric 8180b57cec5SDimitry Andric if (NoFloat) 8190b57cec5SDimitry Andric return (MemVT.getSizeInBits() <= 64); 8200b57cec5SDimitry Andric return true; 8210b57cec5SDimitry Andric } 8220b57cec5SDimitry Andric 823bdd1243dSDimitry Andric bool isCheapToSpeculateCttz(Type *) const override { 8240b57cec5SDimitry Andric return true; 8250b57cec5SDimitry Andric } 8260b57cec5SDimitry Andric 827bdd1243dSDimitry Andric bool isCheapToSpeculateCtlz(Type *) const override { 8280b57cec5SDimitry Andric return true; 8290b57cec5SDimitry Andric } 8300b57cec5SDimitry Andric 8310b57cec5SDimitry Andric bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 8320b57cec5SDimitry Andric 8330b57cec5SDimitry Andric bool hasAndNotCompare(SDValue V) const override { 8340b57cec5SDimitry Andric // We can use bics for any scalar. 8350b57cec5SDimitry Andric return V.getValueType().isScalarInteger(); 8360b57cec5SDimitry Andric } 8370b57cec5SDimitry Andric 8380b57cec5SDimitry Andric bool hasAndNot(SDValue Y) const override { 8390b57cec5SDimitry Andric EVT VT = Y.getValueType(); 8400b57cec5SDimitry Andric 8410b57cec5SDimitry Andric if (!VT.isVector()) 8420b57cec5SDimitry Andric return hasAndNotCompare(Y); 8430b57cec5SDimitry Andric 844349cc55cSDimitry Andric TypeSize TS = VT.getSizeInBits(); 845349cc55cSDimitry Andric // TODO: We should be able to use bic/bif too for SVE. 846349cc55cSDimitry Andric return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic' 8470b57cec5SDimitry Andric } 8480b57cec5SDimitry Andric 8498bcb0991SDimitry Andric bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 8508bcb0991SDimitry Andric SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 8518bcb0991SDimitry Andric unsigned OldShiftOpcode, unsigned NewShiftOpcode, 8528bcb0991SDimitry Andric SelectionDAG &DAG) const override; 8538bcb0991SDimitry Andric 854bdd1243dSDimitry Andric ShiftLegalizationStrategy 855bdd1243dSDimitry Andric preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 856bdd1243dSDimitry Andric unsigned ExpansionFactor) const override; 8570b57cec5SDimitry Andric 8580b57cec5SDimitry Andric bool shouldTransformSignedTruncationCheck(EVT XVT, 8590b57cec5SDimitry Andric unsigned KeptBits) const override { 8600b57cec5SDimitry Andric // For vectors, we don't have a preference.. 8610b57cec5SDimitry Andric if (XVT.isVector()) 8620b57cec5SDimitry Andric return false; 8630b57cec5SDimitry Andric 8640b57cec5SDimitry Andric auto VTIsOk = [](EVT VT) -> bool { 8650b57cec5SDimitry Andric return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 8660b57cec5SDimitry Andric VT == MVT::i64; 8670b57cec5SDimitry Andric }; 8680b57cec5SDimitry Andric 8690b57cec5SDimitry Andric // We are ok with KeptBitsVT being byte/word/dword, what SXT supports. 8700b57cec5SDimitry Andric // XVT will be larger than KeptBitsVT. 8710b57cec5SDimitry Andric MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); 8720b57cec5SDimitry Andric return VTIsOk(XVT) && VTIsOk(KeptBitsVT); 8730b57cec5SDimitry Andric } 8740b57cec5SDimitry Andric 8750b57cec5SDimitry Andric bool preferIncOfAddToSubOfNot(EVT VT) const override; 8760b57cec5SDimitry Andric 8774824e7fdSDimitry Andric bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 8784824e7fdSDimitry Andric 879bdd1243dSDimitry Andric bool isComplexDeinterleavingSupported() const override; 880bdd1243dSDimitry Andric bool isComplexDeinterleavingOperationSupported( 881bdd1243dSDimitry Andric ComplexDeinterleavingOperation Operation, Type *Ty) const override; 882bdd1243dSDimitry Andric 883bdd1243dSDimitry Andric Value *createComplexDeinterleavingIR( 88406c3fb27SDimitry Andric IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 885bdd1243dSDimitry Andric ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 886bdd1243dSDimitry Andric Value *Accumulator = nullptr) const override; 887bdd1243dSDimitry Andric 8880b57cec5SDimitry Andric bool supportSplitCSR(MachineFunction *MF) const override { 8890b57cec5SDimitry Andric return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 8900b57cec5SDimitry Andric MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 8910b57cec5SDimitry Andric } 8920b57cec5SDimitry Andric void initializeSplitCSR(MachineBasicBlock *Entry) const override; 8930b57cec5SDimitry Andric void insertCopiesSplitCSR( 8940b57cec5SDimitry Andric MachineBasicBlock *Entry, 8950b57cec5SDimitry Andric const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 8960b57cec5SDimitry Andric 8970b57cec5SDimitry Andric bool supportSwiftError() const override { 8980b57cec5SDimitry Andric return true; 8990b57cec5SDimitry Andric } 9000b57cec5SDimitry Andric 901bdd1243dSDimitry Andric bool supportKCFIBundles() const override { return true; } 902bdd1243dSDimitry Andric 90306c3fb27SDimitry Andric MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB, 90406c3fb27SDimitry Andric MachineBasicBlock::instr_iterator &MBBI, 90506c3fb27SDimitry Andric const TargetInstrInfo *TII) const override; 90606c3fb27SDimitry Andric 9070b57cec5SDimitry Andric /// Enable aggressive FMA fusion on targets that want it. 9080b57cec5SDimitry Andric bool enableAggressiveFMAFusion(EVT VT) const override; 9090b57cec5SDimitry Andric 9100b57cec5SDimitry Andric /// Returns the size of the platform's va_list object. 9110b57cec5SDimitry Andric unsigned getVaListSizeInBits(const DataLayout &DL) const override; 9120b57cec5SDimitry Andric 9130b57cec5SDimitry Andric /// Returns true if \p VecTy is a legal interleaved access type. This 9140b57cec5SDimitry Andric /// function checks the vector element type and the overall width of the 9150b57cec5SDimitry Andric /// vector. 916349cc55cSDimitry Andric bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, 917349cc55cSDimitry Andric bool &UseScalable) const; 9180b57cec5SDimitry Andric 9190b57cec5SDimitry Andric /// Returns the number of interleaved accesses that will be generated when 9200b57cec5SDimitry Andric /// lowering accesses of the given type. 921349cc55cSDimitry Andric unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, 922349cc55cSDimitry Andric bool UseScalable) const; 9230b57cec5SDimitry Andric 9245ffd83dbSDimitry Andric MachineMemOperand::Flags getTargetMMOFlags( 9255ffd83dbSDimitry Andric const Instruction &I) const override; 9260b57cec5SDimitry Andric 927fe6060f1SDimitry Andric bool functionArgumentNeedsConsecutiveRegisters( 928fe6060f1SDimitry Andric Type *Ty, CallingConv::ID CallConv, bool isVarArg, 929fe6060f1SDimitry Andric const DataLayout &DL) const override; 930fe6060f1SDimitry Andric 9310b57cec5SDimitry Andric /// Used for exception handling on Win64. 9320b57cec5SDimitry Andric bool needsFixedCatchObjects() const override; 9335ffd83dbSDimitry Andric 9345ffd83dbSDimitry Andric bool fallBackToDAGISel(const Instruction &Inst) const override; 9355ffd83dbSDimitry Andric 9365ffd83dbSDimitry Andric /// SVE code generation for fixed length vectors does not custom lower 9375ffd83dbSDimitry Andric /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to 9385ffd83dbSDimitry Andric /// merge. However, merging them creates a BUILD_VECTOR that is just as 9395ffd83dbSDimitry Andric /// illegal as the original, thus leading to an infinite legalisation loop. 9405ffd83dbSDimitry Andric /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal 9415ffd83dbSDimitry Andric /// vector types this override can be removed. 942e8d8bef9SDimitry Andric bool mergeStoresAfterLegalization(EVT VT) const override; 9435ffd83dbSDimitry Andric 944fe6060f1SDimitry Andric // If the platform/function should have a redzone, return the size in bytes. 945fe6060f1SDimitry Andric unsigned getRedZoneSize(const Function &F) const { 946fe6060f1SDimitry Andric if (F.hasFnAttribute(Attribute::NoRedZone)) 947fe6060f1SDimitry Andric return 0; 948fe6060f1SDimitry Andric return 128; 949fe6060f1SDimitry Andric } 950fe6060f1SDimitry Andric 95104eeddc0SDimitry Andric bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const; 952fe6060f1SDimitry Andric EVT getPromotedVTForPredicate(EVT VT) const; 953fe6060f1SDimitry Andric 9546e75b2fbSDimitry Andric EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, 9556e75b2fbSDimitry Andric bool AllowUnknown = false) const override; 9566e75b2fbSDimitry Andric 9574824e7fdSDimitry Andric bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override; 9584824e7fdSDimitry Andric 959*5f757f3fSDimitry Andric bool shouldExpandCttzElements(EVT VT) const override; 960*5f757f3fSDimitry Andric 961bdd1243dSDimitry Andric /// If a change in streaming mode is required on entry to/return from a 962bdd1243dSDimitry Andric /// function call it emits and returns the corresponding SMSTART or SMSTOP node. 963bdd1243dSDimitry Andric /// \p Entry tells whether this is before/after the Call, which is necessary 964bdd1243dSDimitry Andric /// because PSTATE.SM is only queried once. 965bdd1243dSDimitry Andric SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, 96606c3fb27SDimitry Andric SDValue Chain, SDValue InGlue, 967bdd1243dSDimitry Andric SDValue PStateSM, bool Entry) const; 968bdd1243dSDimitry Andric 96906c3fb27SDimitry Andric bool isVScaleKnownToBeAPowerOfTwo() const override { return true; } 970bdd1243dSDimitry Andric 971bdd1243dSDimitry Andric // Normally SVE is only used for byte size vectors that do not fit within a 972bdd1243dSDimitry Andric // NEON vector. This changes when OverrideNEON is true, allowing SVE to be 973bdd1243dSDimitry Andric // used for 64bit and 128bit vectors as well. 974bdd1243dSDimitry Andric bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const; 975bdd1243dSDimitry Andric 976*5f757f3fSDimitry Andric // Follow NEON ABI rules even when using SVE for fixed length vectors. 977*5f757f3fSDimitry Andric MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 978*5f757f3fSDimitry Andric EVT VT) const override; 979*5f757f3fSDimitry Andric unsigned getNumRegistersForCallingConv(LLVMContext &Context, 980*5f757f3fSDimitry Andric CallingConv::ID CC, 981*5f757f3fSDimitry Andric EVT VT) const override; 982*5f757f3fSDimitry Andric unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, 983*5f757f3fSDimitry Andric CallingConv::ID CC, EVT VT, 984*5f757f3fSDimitry Andric EVT &IntermediateVT, 985*5f757f3fSDimitry Andric unsigned &NumIntermediates, 986*5f757f3fSDimitry Andric MVT &RegisterVT) const override; 987*5f757f3fSDimitry Andric 988*5f757f3fSDimitry Andric /// True if stack clash protection is enabled for this functions. 989*5f757f3fSDimitry Andric bool hasInlineStackProbe(const MachineFunction &MF) const override; 990*5f757f3fSDimitry Andric 9910b57cec5SDimitry Andric private: 9920b57cec5SDimitry Andric /// Keep a pointer to the AArch64Subtarget around so that we can 9930b57cec5SDimitry Andric /// make the right decision when generating code for different targets. 9940b57cec5SDimitry Andric const AArch64Subtarget *Subtarget; 9950b57cec5SDimitry Andric 9960b57cec5SDimitry Andric bool isExtFreeImpl(const Instruction *Ext) const override; 9970b57cec5SDimitry Andric 998fe6060f1SDimitry Andric void addTypeForNEON(MVT VT); 99906c3fb27SDimitry Andric void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE); 10000b57cec5SDimitry Andric void addDRTypeForNEON(MVT VT); 10010b57cec5SDimitry Andric void addQRTypeForNEON(MVT VT); 10020b57cec5SDimitry Andric 1003bdd1243dSDimitry Andric unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL, 1004bdd1243dSDimitry Andric SelectionDAG &DAG) const; 1005bdd1243dSDimitry Andric 10060b57cec5SDimitry Andric SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 10070b57cec5SDimitry Andric bool isVarArg, 10080b57cec5SDimitry Andric const SmallVectorImpl<ISD::InputArg> &Ins, 10090b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10100b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10110b57cec5SDimitry Andric 1012*5f757f3fSDimitry Andric void AdjustInstrPostInstrSelection(MachineInstr &MI, 1013*5f757f3fSDimitry Andric SDNode *Node) const override; 1014*5f757f3fSDimitry Andric 10150b57cec5SDimitry Andric SDValue LowerCall(CallLoweringInfo & /*CLI*/, 10160b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10170b57cec5SDimitry Andric 101806c3fb27SDimitry Andric SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 10190b57cec5SDimitry Andric CallingConv::ID CallConv, bool isVarArg, 1020f3fd488fSDimitry Andric const SmallVectorImpl<CCValAssign> &RVLocs, 10210b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10220b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 10230b57cec5SDimitry Andric SDValue ThisVal) const; 10240b57cec5SDimitry Andric 1025fe6060f1SDimitry Andric SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 10260b57cec5SDimitry Andric SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1027349cc55cSDimitry Andric SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const; 1028e8d8bef9SDimitry Andric SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1029e8d8bef9SDimitry Andric 1030e8d8bef9SDimitry Andric SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 1031e8d8bef9SDimitry Andric SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 10320b57cec5SDimitry Andric 1033fe6060f1SDimitry Andric SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 1034fe6060f1SDimitry Andric 10351fd87a68SDimitry Andric SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 10360b57cec5SDimitry Andric SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1037bdd1243dSDimitry Andric SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 10380b57cec5SDimitry Andric 10393a9a9c0cSDimitry Andric bool 10403a9a9c0cSDimitry Andric isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const; 10410b57cec5SDimitry Andric 10420b57cec5SDimitry Andric /// Finds the incoming stack arguments which overlap the given fixed stack 10430b57cec5SDimitry Andric /// object and incorporates their load into the current chain. This prevents 10440b57cec5SDimitry Andric /// an upcoming store from clobbering the stack argument before it's used. 10450b57cec5SDimitry Andric SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 10460b57cec5SDimitry Andric MachineFrameInfo &MFI, int ClobberedFI) const; 10470b57cec5SDimitry Andric 10480b57cec5SDimitry Andric bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 10490b57cec5SDimitry Andric 10500b57cec5SDimitry Andric void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, 10510b57cec5SDimitry Andric SDValue &Chain) const; 10520b57cec5SDimitry Andric 10530b57cec5SDimitry Andric bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 10540b57cec5SDimitry Andric bool isVarArg, 10550b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10560b57cec5SDimitry Andric LLVMContext &Context) const override; 10570b57cec5SDimitry Andric 10580b57cec5SDimitry Andric SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 10590b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10600b57cec5SDimitry Andric const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 10610b57cec5SDimitry Andric SelectionDAG &DAG) const override; 10620b57cec5SDimitry Andric 10630b57cec5SDimitry Andric SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10640b57cec5SDimitry Andric unsigned Flag) const; 10650b57cec5SDimitry Andric SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 10660b57cec5SDimitry Andric unsigned Flag) const; 10670b57cec5SDimitry Andric SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 10680b57cec5SDimitry Andric unsigned Flag) const; 10690b57cec5SDimitry Andric SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10700b57cec5SDimitry Andric unsigned Flag) const; 10710b57cec5SDimitry Andric template <class NodeTy> 10720b57cec5SDimitry Andric SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10730b57cec5SDimitry Andric template <class NodeTy> 10740b57cec5SDimitry Andric SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10750b57cec5SDimitry Andric template <class NodeTy> 10760b57cec5SDimitry Andric SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10770b57cec5SDimitry Andric template <class NodeTy> 10780b57cec5SDimitry Andric SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10790b57cec5SDimitry Andric SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 10800b57cec5SDimitry Andric SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 10810b57cec5SDimitry Andric SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10820b57cec5SDimitry Andric SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10830b57cec5SDimitry Andric SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1084480093f4SDimitry Andric SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase, 1085480093f4SDimitry Andric const SDLoc &DL, SelectionDAG &DAG) const; 10860b57cec5SDimitry Andric SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL, 10870b57cec5SDimitry Andric SelectionDAG &DAG) const; 10880b57cec5SDimitry Andric SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10890b57cec5SDimitry Andric SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1090bdd1243dSDimitry Andric SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const; 10910b57cec5SDimitry Andric SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 10920b57cec5SDimitry Andric SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 10930b57cec5SDimitry Andric SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 10940b57cec5SDimitry Andric SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 10950b57cec5SDimitry Andric SDValue TVal, SDValue FVal, const SDLoc &dl, 10960b57cec5SDimitry Andric SelectionDAG &DAG) const; 10970b57cec5SDimitry Andric SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 10980b57cec5SDimitry Andric SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 10990b57cec5SDimitry Andric SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 11000b57cec5SDimitry Andric SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 11010b57cec5SDimitry Andric SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 11020b57cec5SDimitry Andric SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 11030b57cec5SDimitry Andric SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const; 11040b57cec5SDimitry Andric SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 11050b57cec5SDimitry Andric SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 11060b57cec5SDimitry Andric SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 11070b57cec5SDimitry Andric SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 11080b57cec5SDimitry Andric SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 11090b57cec5SDimitry Andric SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1110bdd1243dSDimitry Andric SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 1111fe6060f1SDimitry Andric SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 11120b57cec5SDimitry Andric SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11130b57cec5SDimitry Andric SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11140b57cec5SDimitry Andric SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1115bdd1243dSDimitry Andric SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 11160b57cec5SDimitry Andric SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 11178bcb0991SDimitry Andric SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const; 11185ffd83dbSDimitry Andric SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const; 111981ad6265SDimitry Andric SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, 112081ad6265SDimitry Andric unsigned NewOp) const; 1121e8d8bef9SDimitry Andric SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; 1122fe6060f1SDimitry Andric SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const; 11230b57cec5SDimitry Andric SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 11245ffd83dbSDimitry Andric SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 112506c3fb27SDimitry Andric SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 112606c3fb27SDimitry Andric SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 1127e8d8bef9SDimitry Andric SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const; 1128e8d8bef9SDimitry Andric SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 11290b57cec5SDimitry Andric SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 1130fe6060f1SDimitry Andric SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 11310b57cec5SDimitry Andric SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 1132fcaf7f86SDimitry Andric SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const; 1133e8d8bef9SDimitry Andric SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 1134fe6060f1SDimitry Andric SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const; 1135349cc55cSDimitry Andric SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 11360b57cec5SDimitry Andric SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 11370b57cec5SDimitry Andric SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 11380b57cec5SDimitry Andric SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 11390b57cec5SDimitry Andric SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1140349cc55cSDimitry Andric SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11410b57cec5SDimitry Andric SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1142fe6060f1SDimitry Andric SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11430b57cec5SDimitry Andric SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1144e8d8bef9SDimitry Andric SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 11450b57cec5SDimitry Andric SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 1146e8d8bef9SDimitry Andric SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const; 11470b57cec5SDimitry Andric SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 11480b57cec5SDimitry Andric SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 1149fe6060f1SDimitry Andric SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 11505ffd83dbSDimitry Andric SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const; 11515ffd83dbSDimitry Andric SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 11520b57cec5SDimitry Andric SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 11530b57cec5SDimitry Andric SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const; 1154*5f757f3fSDimitry Andric SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1155*5f757f3fSDimitry Andric SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11560b57cec5SDimitry Andric SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1157*5f757f3fSDimitry Andric 115806c3fb27SDimitry Andric SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const; 11595ffd83dbSDimitry Andric 1160e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, 1161e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1162e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, 1163e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 11645ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1165fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1166e8d8bef9SDimitry Andric SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const; 1167e8d8bef9SDimitry Andric SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const; 1168e8d8bef9SDimitry Andric SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp, 1169e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1170e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const; 1171e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const; 11725ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const; 1173fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op, 1174fe6060f1SDimitry Andric SelectionDAG &DAG) const; 11755ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op, 11765ffd83dbSDimitry Andric SelectionDAG &DAG) const; 1177fe6060f1SDimitry Andric SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const; 1178fe6060f1SDimitry Andric SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const; 1179fe6060f1SDimitry Andric SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const; 1180fe6060f1SDimitry Andric SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op, 1181fe6060f1SDimitry Andric SelectionDAG &DAG) const; 1182fe6060f1SDimitry Andric SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const; 1183fe6060f1SDimitry Andric SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const; 1184fe6060f1SDimitry Andric SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const; 1185fe6060f1SDimitry Andric SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; 1186fe6060f1SDimitry Andric SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op, 1187fe6060f1SDimitry Andric SelectionDAG &DAG) const; 11880b57cec5SDimitry Andric 11890b57cec5SDimitry Andric SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 11900b57cec5SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 119181ad6265SDimitry Andric SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 119281ad6265SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 11930b57cec5SDimitry Andric SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 11940b57cec5SDimitry Andric int &ExtraSteps, bool &UseOneConst, 11950b57cec5SDimitry Andric bool Reciprocal) const override; 11960b57cec5SDimitry Andric SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 11970b57cec5SDimitry Andric int &ExtraSteps) const override; 1198e8d8bef9SDimitry Andric SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1199e8d8bef9SDimitry Andric const DenormalMode &Mode) const override; 1200e8d8bef9SDimitry Andric SDValue getSqrtResultForDenormInput(SDValue Operand, 1201e8d8bef9SDimitry Andric SelectionDAG &DAG) const override; 12020b57cec5SDimitry Andric unsigned combineRepeatedFPDivisors() const override; 12030b57cec5SDimitry Andric 12040b57cec5SDimitry Andric ConstraintType getConstraintType(StringRef Constraint) const override; 1205480093f4SDimitry Andric Register getRegisterByName(const char* RegName, LLT VT, 12068bcb0991SDimitry Andric const MachineFunction &MF) const override; 12070b57cec5SDimitry Andric 12080b57cec5SDimitry Andric /// Examine constraint string and operand type and determine a weight value. 12090b57cec5SDimitry Andric /// The operand object must already have been set up with the operand type. 12100b57cec5SDimitry Andric ConstraintWeight 12110b57cec5SDimitry Andric getSingleConstraintMatchWeight(AsmOperandInfo &info, 12120b57cec5SDimitry Andric const char *constraint) const override; 12130b57cec5SDimitry Andric 12140b57cec5SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> 12150b57cec5SDimitry Andric getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 12160b57cec5SDimitry Andric StringRef Constraint, MVT VT) const override; 12170b57cec5SDimitry Andric 12180b57cec5SDimitry Andric const char *LowerXConstraint(EVT ConstraintVT) const override; 12190b57cec5SDimitry Andric 1220*5f757f3fSDimitry Andric void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 12210b57cec5SDimitry Andric std::vector<SDValue> &Ops, 12220b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12230b57cec5SDimitry Andric 1224*5f757f3fSDimitry Andric InlineAsm::ConstraintCode 1225*5f757f3fSDimitry Andric getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 12260b57cec5SDimitry Andric if (ConstraintCode == "Q") 1227*5f757f3fSDimitry Andric return InlineAsm::ConstraintCode::Q; 12280b57cec5SDimitry Andric // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 12290b57cec5SDimitry Andric // followed by llvm_unreachable so we'll leave them unimplemented in 12300b57cec5SDimitry Andric // the backend for now. 12310b57cec5SDimitry Andric return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 12320b57cec5SDimitry Andric } 12330b57cec5SDimitry Andric 123406c3fb27SDimitry Andric /// Handle Lowering flag assembly outputs. 123506c3fb27SDimitry Andric SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, 123606c3fb27SDimitry Andric const SDLoc &DL, 123706c3fb27SDimitry Andric const AsmOperandInfo &Constraint, 123806c3fb27SDimitry Andric SelectionDAG &DAG) const override; 123906c3fb27SDimitry Andric 1240fe6060f1SDimitry Andric bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override; 1241*5f757f3fSDimitry Andric bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override; 1242480093f4SDimitry Andric bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 12430b57cec5SDimitry Andric bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 12440b57cec5SDimitry Andric bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1245bdd1243dSDimitry Andric bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 124606c3fb27SDimitry Andric SDValue &Offset, SelectionDAG &DAG) const; 12470b57cec5SDimitry Andric bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 12480b57cec5SDimitry Andric ISD::MemIndexedMode &AM, 12490b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12500b57cec5SDimitry Andric bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 12510b57cec5SDimitry Andric SDValue &Offset, ISD::MemIndexedMode &AM, 12520b57cec5SDimitry Andric SelectionDAG &DAG) const override; 1253*5f757f3fSDimitry Andric bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, 1254*5f757f3fSDimitry Andric bool IsPre, MachineRegisterInfo &MRI) const override; 12550b57cec5SDimitry Andric 12560b57cec5SDimitry Andric void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 12570b57cec5SDimitry Andric SelectionDAG &DAG) const override; 1258fe6060f1SDimitry Andric void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1259fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12605ffd83dbSDimitry Andric void ReplaceExtractSubVectorResults(SDNode *N, 12615ffd83dbSDimitry Andric SmallVectorImpl<SDValue> &Results, 12625ffd83dbSDimitry Andric SelectionDAG &DAG) const; 12630b57cec5SDimitry Andric 12640b57cec5SDimitry Andric bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; 12650b57cec5SDimitry Andric 12660b57cec5SDimitry Andric void finalizeLowering(MachineFunction &MF) const override; 12675ffd83dbSDimitry Andric 12685ffd83dbSDimitry Andric bool shouldLocalize(const MachineInstr &MI, 12695ffd83dbSDimitry Andric const TargetTransformInfo *TTI) const override; 12705ffd83dbSDimitry Andric 1271fe6060f1SDimitry Andric bool SimplifyDemandedBitsForTargetNode(SDValue Op, 1272fe6060f1SDimitry Andric const APInt &OriginalDemandedBits, 1273fe6060f1SDimitry Andric const APInt &OriginalDemandedElts, 1274fe6060f1SDimitry Andric KnownBits &Known, 1275fe6060f1SDimitry Andric TargetLoweringOpt &TLO, 1276fe6060f1SDimitry Andric unsigned Depth) const override; 1277fe6060f1SDimitry Andric 127881ad6265SDimitry Andric bool isTargetCanonicalConstantNode(SDValue Op) const override; 127981ad6265SDimitry Andric 1280e8d8bef9SDimitry Andric // With the exception of data-predicate transitions, no instructions are 1281e8d8bef9SDimitry Andric // required to cast between legal scalable vector types. However: 1282e8d8bef9SDimitry Andric // 1. Packed and unpacked types have different bit lengths, meaning BITCAST 1283e8d8bef9SDimitry Andric // is not universally useable. 1284e8d8bef9SDimitry Andric // 2. Most unpacked integer types are not legal and thus integer extends 1285e8d8bef9SDimitry Andric // cannot be used to convert between unpacked and packed types. 1286e8d8bef9SDimitry Andric // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used 1287e8d8bef9SDimitry Andric // to transition between unpacked and packed types of the same element type, 1288e8d8bef9SDimitry Andric // with BITCAST used otherwise. 1289753f127fSDimitry Andric // This function does not handle predicate bitcasts. 1290e8d8bef9SDimitry Andric SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; 1291fe6060f1SDimitry Andric 1292bdd1243dSDimitry Andric // Returns the runtime value for PSTATE.SM. When the function is streaming- 1293bdd1243dSDimitry Andric // compatible, this generates a call to __arm_sme_state. 1294bdd1243dSDimitry Andric SDValue getPStateSM(SelectionDAG &DAG, SDValue Chain, SMEAttrs Attrs, 1295bdd1243dSDimitry Andric SDLoc DL, EVT VT) const; 1296bdd1243dSDimitry Andric 129706c3fb27SDimitry Andric bool preferScalarizeSplat(SDNode *N) const override; 1298*5f757f3fSDimitry Andric 1299*5f757f3fSDimitry Andric unsigned getMinimumJumpTableEntries() const override; 13000b57cec5SDimitry Andric }; 13010b57cec5SDimitry Andric 13020b57cec5SDimitry Andric namespace AArch64 { 13030b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 13040b57cec5SDimitry Andric const TargetLibraryInfo *libInfo); 13050b57cec5SDimitry Andric } // end namespace AArch64 13060b57cec5SDimitry Andric 13070b57cec5SDimitry Andric } // end namespace llvm 13080b57cec5SDimitry Andric 13090b57cec5SDimitry Andric #endif 1310