10b57cec5SDimitry Andric //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric /// \file When allowed by the instruction, replace a dead definition of a GPR 90b57cec5SDimitry Andric /// with the zero register. This makes the code a bit friendlier towards the 100b57cec5SDimitry Andric /// hardware's register renamer. 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #include "AArch64.h" 140b57cec5SDimitry Andric #include "AArch64RegisterInfo.h" 150b57cec5SDimitry Andric #include "AArch64Subtarget.h" 160b57cec5SDimitry Andric #include "llvm/ADT/Statistic.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/ISDOpcodes.h" 180b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h" 200b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstr.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 230b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h" 240b57cec5SDimitry Andric #include "llvm/Support/Debug.h" 250b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h" 260b57cec5SDimitry Andric using namespace llvm; 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric #define DEBUG_TYPE "aarch64-dead-defs" 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced"); 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions" 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric namespace { 350b57cec5SDimitry Andric class AArch64DeadRegisterDefinitions : public MachineFunctionPass { 360b57cec5SDimitry Andric private: 370b57cec5SDimitry Andric const TargetRegisterInfo *TRI; 380b57cec5SDimitry Andric const MachineRegisterInfo *MRI; 390b57cec5SDimitry Andric const TargetInstrInfo *TII; 400b57cec5SDimitry Andric bool Changed; 410b57cec5SDimitry Andric void processMachineBasicBlock(MachineBasicBlock &MBB); 420b57cec5SDimitry Andric public: 430b57cec5SDimitry Andric static char ID; // Pass identification, replacement for typeid. 440b57cec5SDimitry Andric AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) { 450b57cec5SDimitry Andric initializeAArch64DeadRegisterDefinitionsPass( 460b57cec5SDimitry Andric *PassRegistry::getPassRegistry()); 470b57cec5SDimitry Andric } 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric bool runOnMachineFunction(MachineFunction &F) override; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric void getAnalysisUsage(AnalysisUsage &AU) const override { 540b57cec5SDimitry Andric AU.setPreservesCFG(); 550b57cec5SDimitry Andric MachineFunctionPass::getAnalysisUsage(AU); 560b57cec5SDimitry Andric } 570b57cec5SDimitry Andric }; 580b57cec5SDimitry Andric char AArch64DeadRegisterDefinitions::ID = 0; 590b57cec5SDimitry Andric } // end anonymous namespace 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs", 620b57cec5SDimitry Andric AARCH64_DEAD_REG_DEF_NAME, false, false) 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric static bool usesFrameIndex(const MachineInstr &MI) { 650b57cec5SDimitry Andric for (const MachineOperand &MO : MI.uses()) 660b57cec5SDimitry Andric if (MO.isFI()) 670b57cec5SDimitry Andric return true; 680b57cec5SDimitry Andric return false; 690b57cec5SDimitry Andric } 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric // Instructions that lose their 'read' operation for a subesquent fence acquire 720b57cec5SDimitry Andric // (DMB LD) once the zero register is used. 730b57cec5SDimitry Andric // 740b57cec5SDimitry Andric // WARNING: The aquire variants of the instructions are also affected, but they 750b57cec5SDimitry Andric // are split out into `atomicBarrierDroppedOnZero()` to support annotations on 760b57cec5SDimitry Andric // assembly. 770b57cec5SDimitry Andric static bool atomicReadDroppedOnZero(unsigned Opcode) { 780b57cec5SDimitry Andric switch (Opcode) { 790b57cec5SDimitry Andric case AArch64::LDADDB: case AArch64::LDADDH: 800b57cec5SDimitry Andric case AArch64::LDADDW: case AArch64::LDADDX: 810b57cec5SDimitry Andric case AArch64::LDADDLB: case AArch64::LDADDLH: 820b57cec5SDimitry Andric case AArch64::LDADDLW: case AArch64::LDADDLX: 830b57cec5SDimitry Andric case AArch64::LDCLRB: case AArch64::LDCLRH: 840b57cec5SDimitry Andric case AArch64::LDCLRW: case AArch64::LDCLRX: 850b57cec5SDimitry Andric case AArch64::LDCLRLB: case AArch64::LDCLRLH: 860b57cec5SDimitry Andric case AArch64::LDCLRLW: case AArch64::LDCLRLX: 870b57cec5SDimitry Andric case AArch64::LDEORB: case AArch64::LDEORH: 880b57cec5SDimitry Andric case AArch64::LDEORW: case AArch64::LDEORX: 890b57cec5SDimitry Andric case AArch64::LDEORLB: case AArch64::LDEORLH: 900b57cec5SDimitry Andric case AArch64::LDEORLW: case AArch64::LDEORLX: 910b57cec5SDimitry Andric case AArch64::LDSETB: case AArch64::LDSETH: 920b57cec5SDimitry Andric case AArch64::LDSETW: case AArch64::LDSETX: 930b57cec5SDimitry Andric case AArch64::LDSETLB: case AArch64::LDSETLH: 940b57cec5SDimitry Andric case AArch64::LDSETLW: case AArch64::LDSETLX: 950b57cec5SDimitry Andric case AArch64::LDSMAXB: case AArch64::LDSMAXH: 960b57cec5SDimitry Andric case AArch64::LDSMAXW: case AArch64::LDSMAXX: 970b57cec5SDimitry Andric case AArch64::LDSMAXLB: case AArch64::LDSMAXLH: 980b57cec5SDimitry Andric case AArch64::LDSMAXLW: case AArch64::LDSMAXLX: 990b57cec5SDimitry Andric case AArch64::LDSMINB: case AArch64::LDSMINH: 1000b57cec5SDimitry Andric case AArch64::LDSMINW: case AArch64::LDSMINX: 1010b57cec5SDimitry Andric case AArch64::LDSMINLB: case AArch64::LDSMINLH: 1020b57cec5SDimitry Andric case AArch64::LDSMINLW: case AArch64::LDSMINLX: 1030b57cec5SDimitry Andric case AArch64::LDUMAXB: case AArch64::LDUMAXH: 1040b57cec5SDimitry Andric case AArch64::LDUMAXW: case AArch64::LDUMAXX: 1050b57cec5SDimitry Andric case AArch64::LDUMAXLB: case AArch64::LDUMAXLH: 1060b57cec5SDimitry Andric case AArch64::LDUMAXLW: case AArch64::LDUMAXLX: 1070b57cec5SDimitry Andric case AArch64::LDUMINB: case AArch64::LDUMINH: 1080b57cec5SDimitry Andric case AArch64::LDUMINW: case AArch64::LDUMINX: 1090b57cec5SDimitry Andric case AArch64::LDUMINLB: case AArch64::LDUMINLH: 1100b57cec5SDimitry Andric case AArch64::LDUMINLW: case AArch64::LDUMINLX: 1110b57cec5SDimitry Andric return true; 1120b57cec5SDimitry Andric } 1130b57cec5SDimitry Andric return false; 1140b57cec5SDimitry Andric } 1150b57cec5SDimitry Andric 1160b57cec5SDimitry Andric void AArch64DeadRegisterDefinitions::processMachineBasicBlock( 1170b57cec5SDimitry Andric MachineBasicBlock &MBB) { 1180b57cec5SDimitry Andric const MachineFunction &MF = *MBB.getParent(); 1190b57cec5SDimitry Andric for (MachineInstr &MI : MBB) { 1200b57cec5SDimitry Andric if (usesFrameIndex(MI)) { 1210b57cec5SDimitry Andric // We need to skip this instruction because while it appears to have a 1220b57cec5SDimitry Andric // dead def it uses a frame index which might expand into a multi 1230b57cec5SDimitry Andric // instruction sequence during EPI. 1240b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); 1250b57cec5SDimitry Andric continue; 1260b57cec5SDimitry Andric } 127*0fca6ea1SDimitry Andric if (MI.definesRegister(AArch64::XZR, /*TRI=*/nullptr) || 128*0fca6ea1SDimitry Andric MI.definesRegister(AArch64::WZR, /*TRI=*/nullptr)) { 1290b57cec5SDimitry Andric // It is not allowed to write to the same register (not even the zero 1300b57cec5SDimitry Andric // register) twice in a single instruction. 1310b57cec5SDimitry Andric LLVM_DEBUG( 1320b57cec5SDimitry Andric dbgs() 1330b57cec5SDimitry Andric << " Ignoring, XZR or WZR already used by the instruction\n"); 1340b57cec5SDimitry Andric continue; 1350b57cec5SDimitry Andric } 1360b57cec5SDimitry Andric 1370b57cec5SDimitry Andric if (atomicBarrierDroppedOnZero(MI.getOpcode()) || atomicReadDroppedOnZero(MI.getOpcode())) { 1380b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Ignoring, semantics change with xzr/wzr.\n"); 1390b57cec5SDimitry Andric continue; 1400b57cec5SDimitry Andric } 1410b57cec5SDimitry Andric 1420b57cec5SDimitry Andric const MCInstrDesc &Desc = MI.getDesc(); 1430b57cec5SDimitry Andric for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { 1440b57cec5SDimitry Andric MachineOperand &MO = MI.getOperand(I); 1450b57cec5SDimitry Andric if (!MO.isReg() || !MO.isDef()) 1460b57cec5SDimitry Andric continue; 1470b57cec5SDimitry Andric // We should not have any relevant physreg defs that are replacable by 1480b57cec5SDimitry Andric // zero before register allocation. So we just check for dead vreg defs. 1498bcb0991SDimitry Andric Register Reg = MO.getReg(); 150bdd1243dSDimitry Andric if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg))) 1510b57cec5SDimitry Andric continue; 1520b57cec5SDimitry Andric assert(!MO.isImplicit() && "Unexpected implicit def!"); 1530b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; 1540b57cec5SDimitry Andric MI.print(dbgs())); 1550b57cec5SDimitry Andric // Be careful not to change the register if it's a tied operand. 1560b57cec5SDimitry Andric if (MI.isRegTiedToUseOperand(I)) { 1570b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); 1580b57cec5SDimitry Andric continue; 1590b57cec5SDimitry Andric } 1600b57cec5SDimitry Andric const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); 1610b57cec5SDimitry Andric unsigned NewReg; 1620b57cec5SDimitry Andric if (RC == nullptr) { 1630b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 1640b57cec5SDimitry Andric continue; 1650b57cec5SDimitry Andric } else if (RC->contains(AArch64::WZR)) 1660b57cec5SDimitry Andric NewReg = AArch64::WZR; 1670b57cec5SDimitry Andric else if (RC->contains(AArch64::XZR)) 1680b57cec5SDimitry Andric NewReg = AArch64::XZR; 1690b57cec5SDimitry Andric else { 1700b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 1710b57cec5SDimitry Andric continue; 1720b57cec5SDimitry Andric } 1730b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "); 1740b57cec5SDimitry Andric MO.setReg(NewReg); 1750b57cec5SDimitry Andric MO.setIsDead(); 1760b57cec5SDimitry Andric LLVM_DEBUG(MI.print(dbgs())); 1770b57cec5SDimitry Andric ++NumDeadDefsReplaced; 1780b57cec5SDimitry Andric Changed = true; 1790b57cec5SDimitry Andric // Only replace one dead register, see check for zero register above. 1800b57cec5SDimitry Andric break; 1810b57cec5SDimitry Andric } 1820b57cec5SDimitry Andric } 1830b57cec5SDimitry Andric } 1840b57cec5SDimitry Andric 1850b57cec5SDimitry Andric // Scan the function for instructions that have a dead definition of a 1860b57cec5SDimitry Andric // register. Replace that register with the zero register when possible. 1870b57cec5SDimitry Andric bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { 1880b57cec5SDimitry Andric if (skipFunction(MF.getFunction())) 1890b57cec5SDimitry Andric return false; 1900b57cec5SDimitry Andric 1910b57cec5SDimitry Andric TRI = MF.getSubtarget().getRegisterInfo(); 1920b57cec5SDimitry Andric TII = MF.getSubtarget().getInstrInfo(); 1930b57cec5SDimitry Andric MRI = &MF.getRegInfo(); 1940b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); 1950b57cec5SDimitry Andric Changed = false; 1960b57cec5SDimitry Andric for (auto &MBB : MF) 1970b57cec5SDimitry Andric processMachineBasicBlock(MBB); 1980b57cec5SDimitry Andric return Changed; 1990b57cec5SDimitry Andric } 2000b57cec5SDimitry Andric 2010b57cec5SDimitry Andric FunctionPass *llvm::createAArch64DeadRegisterDefinitions() { 2020b57cec5SDimitry Andric return new AArch64DeadRegisterDefinitions(); 2030b57cec5SDimitry Andric } 204