1//=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12include "llvm/Target/GlobalISel/Combine.td" 13 14def fconstant_to_constant : GICombineRule< 15 (defs root:$root), 16 (match (wip_match_opcode G_FCONSTANT):$root, 17 [{ return matchFConstantToConstant(*${root}, MRI); }]), 18 (apply [{ applyFConstantToConstant(*${root}); }])>; 19 20def AArch64PreLegalizerCombinerHelper: GICombinerHelper< 21 "AArch64GenPreLegalizerCombinerHelper", [all_combines, 22 fconstant_to_constant]> { 23 let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule"; 24 let StateClass = "AArch64PreLegalizerCombinerHelperState"; 25 let AdditionalArguments = []; 26} 27 28// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a 29// target-specific opcode. 30def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">; 31 32def rev : GICombineRule< 33 (defs root:$root, shuffle_matchdata:$matchinfo), 34 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 35 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]), 36 (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }]) 37>; 38 39def zip : GICombineRule< 40 (defs root:$root, shuffle_matchdata:$matchinfo), 41 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 42 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]), 43 (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }]) 44>; 45 46def uzp : GICombineRule< 47 (defs root:$root, shuffle_matchdata:$matchinfo), 48 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 49 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]), 50 (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }]) 51>; 52 53def dup: GICombineRule < 54 (defs root:$root, shuffle_matchdata:$matchinfo), 55 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 56 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]), 57 (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }]) 58>; 59 60def trn : GICombineRule< 61 (defs root:$root, shuffle_matchdata:$matchinfo), 62 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 63 [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]), 64 (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }]) 65>; 66 67def ext: GICombineRule < 68 (defs root:$root, shuffle_matchdata:$matchinfo), 69 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 70 [{ return matchEXT(*${root}, MRI, ${matchinfo}); }]), 71 (apply [{ applyEXT(*${root}, ${matchinfo}); }]) 72>; 73 74// Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo 75// instruction. 76def shuffle_vector_pseudos : GICombineGroup<[dup, rev, ext, zip, uzp, trn]>; 77 78def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">; 79def vashr_vlshr_imm : GICombineRule< 80 (defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo), 81 (match (wip_match_opcode G_ASHR, G_LSHR):$root, 82 [{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]), 83 (apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]) 84>; 85 86def form_duplane_matchdata : 87 GIDefMatchData<"std::pair<unsigned, int>">; 88def form_duplane : GICombineRule < 89 (defs root:$root, form_duplane_matchdata:$matchinfo), 90 (match (wip_match_opcode G_SHUFFLE_VECTOR):$root, 91 [{ return matchDupLane(*${root}, MRI, ${matchinfo}); }]), 92 (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }]) 93>; 94 95def adjust_icmp_imm_matchdata : 96 GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">; 97def adjust_icmp_imm : GICombineRule < 98 (defs root:$root, adjust_icmp_imm_matchdata:$matchinfo), 99 (match (wip_match_opcode G_ICMP):$root, 100 [{ return matchAdjustICmpImmAndPred(*${root}, MRI, ${matchinfo}); }]), 101 (apply [{ applyAdjustICmpImmAndPred(*${root}, ${matchinfo}, B, Observer); }]) 102>; 103 104def icmp_lowering : GICombineGroup<[adjust_icmp_imm]>; 105 106def extractvecelt_pairwise_add_matchdata : GIDefMatchData<"std::tuple<unsigned, LLT, Register>">; 107def extractvecelt_pairwise_add : GICombineRule< 108 (defs root:$root, extractvecelt_pairwise_add_matchdata:$matchinfo), 109 (match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root, 110 [{ return matchExtractVecEltPairwiseAdd(*${root}, MRI, ${matchinfo}); }]), 111 (apply [{ applyExtractVecEltPairwiseAdd(*${root}, MRI, B, ${matchinfo}); }]) 112>; 113 114def mul_const_matchdata : GIDefMatchData<"std::function<void(MachineIRBuilder&, Register)>">; 115def mul_const : GICombineRule< 116 (defs root:$root, mul_const_matchdata:$matchinfo), 117 (match (wip_match_opcode G_MUL):$root, 118 [{ return matchAArch64MulConstCombine(*${root}, MRI, ${matchinfo}); }]), 119 (apply [{ applyAArch64MulConstCombine(*${root}, MRI, B, ${matchinfo}); }]) 120>; 121 122// Post-legalization combines which should happen at all optimization levels. 123// (E.g. ones that facilitate matching for the selector) For example, matching 124// pseudos. 125def AArch64PostLegalizerLoweringHelper 126 : GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper", 127 [shuffle_vector_pseudos, vashr_vlshr_imm, 128 icmp_lowering, form_duplane]> { 129 let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule"; 130} 131 132// Post-legalization combines which are primarily optimizations. 133def AArch64PostLegalizerCombinerHelper 134 : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper", 135 [copy_prop, erase_undef_store, combines_for_extload, 136 sext_trunc_sextload, 137 hoist_logic_op_with_same_opcode_hands, 138 redundant_and, xor_of_and_with_same_reg, 139 extractvecelt_pairwise_add, redundant_or, 140 mul_const]> { 141 let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule"; 142} 143