1//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for AArch64 architecture. 10// 11//===----------------------------------------------------------------------===// 12 13/// CCIfBigEndian - Match only if we're in big endian mode. 14class CCIfBigEndian<CCAction A> : 15 CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; 16 17class CCIfILP32<CCAction A> : 18 CCIf<"State.getMachineFunction().getDataLayout().getPointerSize() == 4", A>; 19 20 21//===----------------------------------------------------------------------===// 22// ARM AAPCS64 Calling Convention 23//===----------------------------------------------------------------------===// 24 25let Entry = 1 in 26def CC_AArch64_AAPCS : CallingConv<[ 27 CCIfType<[iPTR], CCBitConvertToType<i64>>, 28 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 29 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 30 31 // Big endian vectors must be passed as if they were 1-element vectors so that 32 // their lanes are in a consistent order. 33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 34 CCBitConvertToType<f64>>>, 35 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 36 CCBitConvertToType<f128>>>, 37 38 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter. 39 // However, on windows, in some circumstances, the SRet is passed in X0 or X1 40 // instead. The presence of the inreg attribute indicates that SRet is 41 // passed in the alternative register (X0 or X1), not X8: 42 // - X0 for non-instance methods. 43 // - X1 for instance methods. 44 45 // The "sret" attribute identifies indirect returns. 46 // The "inreg" attribute identifies non-aggregate types. 47 // The position of the "sret" attribute identifies instance/non-instance 48 // methods. 49 // "sret" on argument 0 means non-instance methods. 50 // "sret" on argument 1 means instance methods. 51 52 CCIfInReg<CCIfType<[i64], 53 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>, 54 55 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>, 56 57 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 58 // slot is 64-bit. 59 CCIfByVal<CCPassByVal<8, 8>>, 60 61 // The 'nest' parameter, if any, is passed in X18. 62 // Darwin uses X18 as the platform register and hence 'nest' isn't currently 63 // supported there. 64 CCIfNest<CCAssignToReg<[X18]>>, 65 66 // Pass SwiftSelf in a callee saved register. 67 CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>, 68 69 // A SwiftError is passed in X21. 70 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 71 72 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 73 74 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 75 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 76 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 77 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 78 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 79 CCPassIndirect<i64>>, 80 81 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 82 CCAssignToReg<[P0, P1, P2, P3]>>, 83 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 84 CCPassIndirect<i64>>, 85 86 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 87 // up to eight each of GPR and FPR. 88 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 89 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 90 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 91 // i128 is split to two i64s, we can't fit half to register X7. 92 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6], 93 [X0, X1, X3, X5]>>>, 94 95 // i128 is split to two i64s, and its stack alignment is 16 bytes. 96 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 97 98 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 99 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 100 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 101 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 102 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 103 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 104 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 105 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 106 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 107 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 108 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 109 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 111 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 112 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 113 114 // If more than will fit in registers, pass them on the stack instead. 115 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>, 116 CCIfType<[i32, f32], CCAssignToStack<8, 8>>, 117 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 118 CCAssignToStack<8, 8>>, 119 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 120 CCAssignToStack<16, 16>> 121]>; 122 123let Entry = 1 in 124def RetCC_AArch64_AAPCS : CallingConv<[ 125 CCIfType<[iPTR], CCBitConvertToType<i64>>, 126 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 127 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 128 129 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 130 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 131 132 // Big endian vectors must be passed as if they were 1-element vectors so that 133 // their lanes are in a consistent order. 134 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 135 CCBitConvertToType<f64>>>, 136 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 137 CCBitConvertToType<f128>>>, 138 139 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 140 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 141 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 142 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 143 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 144 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 145 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 146 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 147 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 148 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 149 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 150 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 151 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 152 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 153 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 154 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 155 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 156 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 157 158 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 159 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 160 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 161 162 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 163 CCAssignToReg<[P0, P1, P2, P3]>> 164]>; 165 166// Vararg functions on windows pass floats in integer registers 167let Entry = 1 in 168def CC_AArch64_Win64_VarArg : CallingConv<[ 169 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>, 170 CCIfType<[f64], CCBitConvertToType<i64>>, 171 CCDelegateTo<CC_AArch64_AAPCS> 172]>; 173 174// Windows Control Flow Guard checks take a single argument (the target function 175// address) and have no return value. 176let Entry = 1 in 177def CC_AArch64_Win64_CFGuard_Check : CallingConv<[ 178 CCIfType<[i64], CCAssignToReg<[X15]>> 179]>; 180 181 182// Darwin uses a calling convention which differs in only two ways 183// from the standard one at this level: 184// + i128s (i.e. split i64s) don't need even registers. 185// + Stack slots are sized as needed rather than being at least 64-bit. 186let Entry = 1 in 187def CC_AArch64_DarwinPCS : CallingConv<[ 188 CCIfType<[iPTR], CCBitConvertToType<i64>>, 189 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 190 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 191 192 // An SRet is passed in X8, not X0 like a normal pointer parameter. 193 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>, 194 195 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 196 // slot is 64-bit. 197 CCIfByVal<CCPassByVal<8, 8>>, 198 199 // Pass SwiftSelf in a callee saved register. 200 CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>, 201 202 // A SwiftError is passed in X21. 203 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 204 205 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 206 207 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 208 // up to eight each of GPR and FPR. 209 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 210 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 211 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 212 // i128 is split to two i64s, we can't fit half to register X7. 213 CCIfType<[i64], 214 CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6], 215 [W0, W1, W2, W3, W4, W5, W6]>>>, 216 // i128 is split to two i64s, and its stack alignment is 16 bytes. 217 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 218 219 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 220 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 221 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 222 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 223 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 224 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 225 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 226 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 227 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 228 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 229 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 230 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 231 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 232 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 233 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 234 235 // If more than will fit in registers, pass them on the stack instead. 236 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>, 237 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16", 238 CCAssignToStack<2, 2>>, 239 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 240 241 // Re-demote pointers to 32-bits so we don't end up storing 64-bit 242 // values and clobbering neighbouring stack locations. Not very pretty. 243 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 244 CCIfPtr<CCIfILP32<CCAssignToStack<4, 4>>>, 245 246 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 247 CCAssignToStack<8, 8>>, 248 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 249 CCAssignToStack<16, 16>> 250]>; 251 252let Entry = 1 in 253def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ 254 CCIfType<[iPTR], CCBitConvertToType<i64>>, 255 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 256 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 257 258 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>, 259 260 // Handle all scalar types as either i64 or f64. 261 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 262 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>, 263 264 // Everything is on the stack. 265 // i128 is split to two i64s, and its stack alignment is 16 bytes. 266 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 267 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 268 CCAssignToStack<8, 8>>, 269 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 270 CCAssignToStack<16, 16>> 271]>; 272 273// In the ILP32 world, the minimum stack slot size is 4 bytes. Otherwise the 274// same as the normal Darwin VarArgs handling. 275let Entry = 1 in 276def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[ 277 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 278 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 279 280 // Handle all scalar types as either i32 or f32. 281 CCIfType<[i8, i16], CCPromoteToType<i32>>, 282 CCIfType<[f16, bf16], CCPromoteToType<f32>>, 283 284 // Everything is on the stack. 285 // i128 is split to two i64s, and its stack alignment is 16 bytes. 286 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 287 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 288 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 289 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 290 CCAssignToStack<8, 8>>, 291 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 292 CCAssignToStack<16, 16>> 293]>; 294 295 296// The WebKit_JS calling convention only passes the first argument (the callee) 297// in register and the remaining arguments on stack. We allow 32bit stack slots, 298// so that WebKit can write partial values in the stack and define the other 299// 32bit quantity as undef. 300let Entry = 1 in 301def CC_AArch64_WebKit_JS : CallingConv<[ 302 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0). 303 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 304 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>, 305 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>, 306 307 // Pass the remaining arguments on the stack instead. 308 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 309 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 310]>; 311 312let Entry = 1 in 313def RetCC_AArch64_WebKit_JS : CallingConv<[ 314 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 315 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 316 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 317 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 318 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 319 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 320 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 321 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> 322]>; 323 324//===----------------------------------------------------------------------===// 325// ARM64 Calling Convention for GHC 326//===----------------------------------------------------------------------===// 327 328// This calling convention is specific to the Glasgow Haskell Compiler. 329// The only documentation is the GHC source code, specifically the C header 330// file: 331// 332// https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h 333// 334// which defines the registers for the Spineless Tagless G-Machine (STG) that 335// GHC uses to implement lazy evaluation. The generic STG machine has a set of 336// registers which are mapped to appropriate set of architecture specific 337// registers for each CPU architecture. 338// 339// The STG Machine is documented here: 340// 341// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode 342// 343// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI 344// register mapping". 345 346let Entry = 1 in 347def CC_AArch64_GHC : CallingConv<[ 348 CCIfType<[iPTR], CCBitConvertToType<i64>>, 349 350 // Handle all vector types as either f64 or v2f64. 351 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 352 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>, 353 354 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 355 CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>, 356 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>, 357 358 // Promote i8/i16/i32 arguments to i64. 359 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 360 361 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 362 CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>> 363]>; 364 365// The order of the callee-saves in this file is important, because the 366// FrameLowering code will use this order to determine the layout the 367// callee-save area in the stack frame. As can be observed below, Darwin 368// requires the frame-record (LR, FP) to be at the top the callee-save area, 369// whereas for other platforms they are at the bottom. 370 371// FIXME: LR is only callee-saved in the sense that *we* preserve it and are 372// presumably a callee to someone. External functions may not do so, but this 373// is currently safe since BL has LR as an implicit-def and what happens after a 374// tail call doesn't matter. 375// 376// It would be better to model its preservation semantics properly (create a 377// vreg on entry, use it in RET & tail call generation; make that vreg def if we 378// end up saving LR as part of a call frame). Watch this space... 379def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 380 X25, X26, X27, X28, LR, FP, 381 D8, D9, D10, D11, 382 D12, D13, D14, D15)>; 383 384// A variant for treating X18 as callee saved, when interfacing with 385// code that needs X18 to be preserved. 386def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>; 387 388// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x. 389// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs, 390// and not (LR,FP) pairs. 391def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 392 X25, X26, X27, X28, FP, LR, 393 D8, D9, D10, D11, 394 D12, D13, D14, D15)>; 395 396// The Control Flow Guard check call uses a custom calling convention that also 397// preserves X0-X8 and Q0-Q7. 398def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, 399 (sequence "X%u", 0, 8), 400 (sequence "Q%u", 0, 7))>; 401 402// AArch64 PCS for vector functions (VPCS) 403// must (additionally) preserve full Q8-Q23 registers 404def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 405 X25, X26, X27, X28, LR, FP, 406 (sequence "Q%u", 8, 23))>; 407 408// Functions taking SVE arguments or returning an SVE type 409// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15 410def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23), 411 (sequence "P%u", 4, 15), 412 X19, X20, X21, X22, X23, X24, 413 X25, X26, X27, X28, LR, FP)>; 414 415// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since 416// 'this' and the pointer return value are both passed in X0 in these cases, 417// this can be partially modelled by treating X0 as a callee-saved register; 418// only the resulting RegMask is used; the SaveList is ignored 419// 420// (For generic ARM 64-bit ABI code, clang will not generate constructors or 421// destructors with 'this' returns, so this RegMask will not be used in that 422// case) 423def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>; 424 425def CSR_AArch64_AAPCS_SwiftError 426 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>; 427 428// The ELF stub used for TLS-descriptor access saves every feasible 429// register. Only X0 and LR are clobbered. 430def CSR_AArch64_TLS_ELF 431 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP, 432 (sequence "Q%u", 0, 31))>; 433 434def CSR_AArch64_AllRegs 435 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP, 436 (sequence "X%u", 0, 28), FP, LR, SP, 437 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31), 438 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31), 439 (sequence "Q%u", 0, 31))>; 440 441def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>; 442 443def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS, 444 (sequence "X%u", 9, 15))>; 445 446def CSR_AArch64_StackProbe_Windows 447 : CalleeSavedRegs<(add (sequence "X%u", 0, 15), 448 (sequence "X%u", 18, 28), FP, SP, 449 (sequence "Q%u", 0, 31))>; 450 451// Darwin variants of AAPCS. 452// Darwin puts the frame-record at the top of the callee-save area. 453def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22, 454 X23, X24, X25, X26, X27, X28, 455 D8, D9, D10, D11, 456 D12, D13, D14, D15)>; 457 458def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, 459 X22, X23, X24, X25, X26, X27, 460 X28, (sequence "Q%u", 8, 23))>; 461def CSR_Darwin_AArch64_AAPCS_ThisReturn 462 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X0)>; 463 464def CSR_Darwin_AArch64_AAPCS_SwiftError 465 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>; 466 467// The function used by Darwin to obtain the address of a thread-local variable 468// guarantees more than a normal AAPCS function. x16 and x17 are used on the 469// fast path for calculation, but other registers except X0 (argument/return) 470// and LR (it is a call, after all) are preserved. 471def CSR_Darwin_AArch64_TLS 472 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17), 473 FP, 474 (sequence "Q%u", 0, 31))>; 475 476// We can only handle a register pair with adjacent registers, the register pair 477// should belong to the same class as well. Since the access function on the 478// fast path calls a function that follows CSR_Darwin_AArch64_TLS, 479// CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS. 480def CSR_Darwin_AArch64_CXX_TLS 481 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, 482 (sub (sequence "X%u", 1, 28), X15, X16, X17, X18), 483 (sequence "D%u", 0, 31))>; 484 485// CSRs that are handled by prologue, epilogue. 486def CSR_Darwin_AArch64_CXX_TLS_PE 487 : CalleeSavedRegs<(add LR, FP)>; 488 489// CSRs that are handled explicitly via copies. 490def CSR_Darwin_AArch64_CXX_TLS_ViaCopy 491 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_CXX_TLS, LR, FP)>; 492 493def CSR_Darwin_AArch64_RT_MostRegs 494 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, (sequence "X%u", 9, 15))>; 495 496// Variants of the standard calling conventions for shadow call stack. 497// These all preserve x18 in addition to any other registers. 498def CSR_AArch64_NoRegs_SCS 499 : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>; 500def CSR_AArch64_AllRegs_SCS 501 : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>; 502def CSR_AArch64_AAPCS_SwiftError_SCS 503 : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>; 504def CSR_AArch64_RT_MostRegs_SCS 505 : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>; 506def CSR_AArch64_AAVPCS_SCS 507 : CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>; 508def CSR_AArch64_SVE_AAPCS_SCS 509 : CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>; 510def CSR_AArch64_AAPCS_SCS 511 : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>; 512