1//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for AArch64 architecture. 10// 11//===----------------------------------------------------------------------===// 12 13/// CCIfBigEndian - Match only if we're in big endian mode. 14class CCIfBigEndian<CCAction A> : 15 CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; 16 17class CCIfILP32<CCAction A> : 18 CCIf<"State.getMachineFunction().getDataLayout().getPointerSize() == 4", A>; 19 20 21//===----------------------------------------------------------------------===// 22// ARM AAPCS64 Calling Convention 23//===----------------------------------------------------------------------===// 24 25let Entry = 1 in 26def CC_AArch64_AAPCS : CallingConv<[ 27 CCIfType<[iPTR], CCBitConvertToType<i64>>, 28 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 29 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 30 31 // Big endian vectors must be passed as if they were 1-element vectors so that 32 // their lanes are in a consistent order. 33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 34 CCBitConvertToType<f64>>>, 35 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 36 CCBitConvertToType<f128>>>, 37 38 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter. 39 // However, on windows, in some circumstances, the SRet is passed in X0 or X1 40 // instead. The presence of the inreg attribute indicates that SRet is 41 // passed in the alternative register (X0 or X1), not X8: 42 // - X0 for non-instance methods. 43 // - X1 for instance methods. 44 45 // The "sret" attribute identifies indirect returns. 46 // The "inreg" attribute identifies non-aggregate types. 47 // The position of the "sret" attribute identifies instance/non-instance 48 // methods. 49 // "sret" on argument 0 means non-instance methods. 50 // "sret" on argument 1 means instance methods. 51 52 CCIfInReg<CCIfType<[i64], 53 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>, 54 55 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>, 56 57 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 58 // slot is 64-bit. 59 CCIfByVal<CCPassByVal<8, 8>>, 60 61 // The 'nest' parameter, if any, is passed in X18. 62 // Darwin uses X18 as the platform register and hence 'nest' isn't currently 63 // supported there. 64 CCIfNest<CCAssignToReg<[X18]>>, 65 66 // Pass SwiftSelf in a callee saved register. 67 CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>, 68 69 // A SwiftError is passed in X21. 70 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 71 72 // Pass SwiftAsync in an otherwise callee saved register so that it will be 73 // preserved for normal function calls. 74 CCIfSwiftAsync<CCIfType<[i64], CCAssignToRegWithShadow<[X22], [W22]>>>, 75 76 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 77 78 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 79 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 80 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 81 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 82 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 83 CCPassIndirect<i64>>, 84 85 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 86 CCAssignToReg<[P0, P1, P2, P3]>>, 87 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 88 CCPassIndirect<i64>>, 89 90 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 91 // up to eight each of GPR and FPR. 92 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 93 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 94 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 95 // i128 is split to two i64s, we can't fit half to register X7. 96 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6], 97 [X0, X1, X3, X5]>>>, 98 99 // i128 is split to two i64s, and its stack alignment is 16 bytes. 100 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 101 102 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 103 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 104 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 105 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 106 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 107 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 108 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 109 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 110 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 112 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 113 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 114 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 115 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 116 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 117 118 // If more than will fit in registers, pass them on the stack instead. 119 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>, 120 CCIfType<[i32, f32], CCAssignToStack<8, 8>>, 121 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 122 CCAssignToStack<8, 8>>, 123 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 124 CCAssignToStack<16, 16>> 125]>; 126 127let Entry = 1 in 128def RetCC_AArch64_AAPCS : CallingConv<[ 129 CCIfType<[iPTR], CCBitConvertToType<i64>>, 130 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 131 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 132 133 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 134 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 135 136 // Big endian vectors must be passed as if they were 1-element vectors so that 137 // their lanes are in a consistent order. 138 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 139 CCBitConvertToType<f64>>>, 140 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 141 CCBitConvertToType<f128>>>, 142 143 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 144 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 145 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 146 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 147 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 148 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 149 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 150 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 151 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 152 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 154 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 155 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 156 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 157 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 158 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 159 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 160 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 161 162 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 163 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 164 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 165 166 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 167 CCAssignToReg<[P0, P1, P2, P3]>> 168]>; 169 170// Vararg functions on windows pass floats in integer registers 171let Entry = 1 in 172def CC_AArch64_Win64_VarArg : CallingConv<[ 173 CCIfType<[f16, bf16], CCBitConvertToType<i16>>, 174 CCIfType<[f32], CCBitConvertToType<i32>>, 175 CCIfType<[f64], CCBitConvertToType<i64>>, 176 CCDelegateTo<CC_AArch64_AAPCS> 177]>; 178 179// Windows Control Flow Guard checks take a single argument (the target function 180// address) and have no return value. 181let Entry = 1 in 182def CC_AArch64_Win64_CFGuard_Check : CallingConv<[ 183 CCIfType<[i64], CCAssignToReg<[X15]>> 184]>; 185 186 187// Darwin uses a calling convention which differs in only two ways 188// from the standard one at this level: 189// + i128s (i.e. split i64s) don't need even registers. 190// + Stack slots are sized as needed rather than being at least 64-bit. 191let Entry = 1 in 192def CC_AArch64_DarwinPCS : CallingConv<[ 193 CCIfType<[iPTR], CCBitConvertToType<i64>>, 194 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 195 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 196 197 // An SRet is passed in X8, not X0 like a normal pointer parameter. 198 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>, 199 200 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 201 // slot is 64-bit. 202 CCIfByVal<CCPassByVal<8, 8>>, 203 204 // Pass SwiftSelf in a callee saved register. 205 CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>, 206 207 // A SwiftError is passed in X21. 208 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>, 209 210 // Pass SwiftAsync in an otherwise callee saved register so that it will be 211 // preserved for normal function calls. 212 CCIfSwiftAsync<CCIfType<[i64], CCAssignToRegWithShadow<[X22], [W22]>>>, 213 214 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 215 216 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 217 // up to eight each of GPR and FPR. 218 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 219 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 220 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 221 // i128 is split to two i64s, we can't fit half to register X7. 222 CCIfType<[i64], 223 CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6], 224 [W0, W1, W2, W3, W4, W5, W6]>>>, 225 // i128 is split to two i64s, and its stack alignment is 16 bytes. 226 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 227 228 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 229 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 230 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 231 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 232 CCIfType<[bf16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], 233 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 234 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 235 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 236 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 237 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 238 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 239 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 240 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 241 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 242 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 243 244 // If more than will fit in registers, pass them on the stack instead. 245 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>, 246 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16", 247 CCAssignToStack<2, 2>>, 248 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 249 250 // Re-demote pointers to 32-bits so we don't end up storing 64-bit 251 // values and clobbering neighbouring stack locations. Not very pretty. 252 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 253 CCIfPtr<CCIfILP32<CCAssignToStack<4, 4>>>, 254 255 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 256 CCAssignToStack<8, 8>>, 257 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 258 CCAssignToStack<16, 16>> 259]>; 260 261let Entry = 1 in 262def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ 263 CCIfType<[iPTR], CCBitConvertToType<i64>>, 264 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 265 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 266 267 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>, 268 269 // Handle all scalar types as either i64 or f64. 270 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 271 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>, 272 273 // Everything is on the stack. 274 // i128 is split to two i64s, and its stack alignment is 16 bytes. 275 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 276 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 277 CCAssignToStack<8, 8>>, 278 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 279 CCAssignToStack<16, 16>> 280]>; 281 282// In the ILP32 world, the minimum stack slot size is 4 bytes. Otherwise the 283// same as the normal Darwin VarArgs handling. 284let Entry = 1 in 285def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[ 286 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 287 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 288 289 // Handle all scalar types as either i32 or f32. 290 CCIfType<[i8, i16], CCPromoteToType<i32>>, 291 CCIfType<[f16, bf16], CCPromoteToType<f32>>, 292 293 // Everything is on the stack. 294 // i128 is split to two i64s, and its stack alignment is 16 bytes. 295 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 296 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 297 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 298 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 299 CCAssignToStack<8, 8>>, 300 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 301 CCAssignToStack<16, 16>> 302]>; 303 304 305// The WebKit_JS calling convention only passes the first argument (the callee) 306// in register and the remaining arguments on stack. We allow 32bit stack slots, 307// so that WebKit can write partial values in the stack and define the other 308// 32bit quantity as undef. 309let Entry = 1 in 310def CC_AArch64_WebKit_JS : CallingConv<[ 311 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0). 312 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 313 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>, 314 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>, 315 316 // Pass the remaining arguments on the stack instead. 317 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 318 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 319]>; 320 321let Entry = 1 in 322def RetCC_AArch64_WebKit_JS : CallingConv<[ 323 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 324 [X0, X1, X2, X3, X4, X5, X6, X7]>>, 325 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], 326 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 327 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], 328 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 329 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], 330 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> 331]>; 332 333//===----------------------------------------------------------------------===// 334// ARM64 Calling Convention for GHC 335//===----------------------------------------------------------------------===// 336 337// This calling convention is specific to the Glasgow Haskell Compiler. 338// The only documentation is the GHC source code, specifically the C header 339// file: 340// 341// https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h 342// 343// which defines the registers for the Spineless Tagless G-Machine (STG) that 344// GHC uses to implement lazy evaluation. The generic STG machine has a set of 345// registers which are mapped to appropriate set of architecture specific 346// registers for each CPU architecture. 347// 348// The STG Machine is documented here: 349// 350// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode 351// 352// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI 353// register mapping". 354 355let Entry = 1 in 356def CC_AArch64_GHC : CallingConv<[ 357 CCIfType<[iPTR], CCBitConvertToType<i64>>, 358 359 // Handle all vector types as either f64 or v2f64. 360 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 361 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>, 362 363 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 364 CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>, 365 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>, 366 367 // Promote i8/i16/i32 arguments to i64. 368 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 369 370 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 371 CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>> 372]>; 373 374// The order of the callee-saves in this file is important, because the 375// FrameLowering code will use this order to determine the layout the 376// callee-save area in the stack frame. As can be observed below, Darwin 377// requires the frame-record (LR, FP) to be at the top the callee-save area, 378// whereas for other platforms they are at the bottom. 379 380// FIXME: LR is only callee-saved in the sense that *we* preserve it and are 381// presumably a callee to someone. External functions may not do so, but this 382// is currently safe since BL has LR as an implicit-def and what happens after a 383// tail call doesn't matter. 384// 385// It would be better to model its preservation semantics properly (create a 386// vreg on entry, use it in RET & tail call generation; make that vreg def if we 387// end up saving LR as part of a call frame). Watch this space... 388def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 389 X25, X26, X27, X28, LR, FP, 390 D8, D9, D10, D11, 391 D12, D13, D14, D15)>; 392 393// A variant for treating X18 as callee saved, when interfacing with 394// code that needs X18 to be preserved. 395def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>; 396 397// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x. 398// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs, 399// and not (LR,FP) pairs. 400def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 401 X25, X26, X27, X28, FP, LR, 402 D8, D9, D10, D11, 403 D12, D13, D14, D15)>; 404 405// The Control Flow Guard check call uses a custom calling convention that also 406// preserves X0-X8 and Q0-Q7. 407def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, 408 (sequence "X%u", 0, 8), 409 (sequence "Q%u", 0, 7))>; 410 411// AArch64 PCS for vector functions (VPCS) 412// must (additionally) preserve full Q8-Q23 registers 413def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 414 X25, X26, X27, X28, LR, FP, 415 (sequence "Q%u", 8, 23))>; 416 417// Functions taking SVE arguments or returning an SVE type 418// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15 419def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23), 420 (sequence "P%u", 4, 15), 421 X19, X20, X21, X22, X23, X24, 422 X25, X26, X27, X28, LR, FP)>; 423 424def CSR_AArch64_AAPCS_SwiftTail 425 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X20, X22)>; 426 427// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since 428// 'this' and the pointer return value are both passed in X0 in these cases, 429// this can be partially modelled by treating X0 as a callee-saved register; 430// only the resulting RegMask is used; the SaveList is ignored 431// 432// (For generic ARM 64-bit ABI code, clang will not generate constructors or 433// destructors with 'this' returns, so this RegMask will not be used in that 434// case) 435def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>; 436 437def CSR_AArch64_AAPCS_SwiftError 438 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>; 439 440// The ELF stub used for TLS-descriptor access saves every feasible 441// register. Only X0 and LR are clobbered. 442def CSR_AArch64_TLS_ELF 443 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP, 444 (sequence "Q%u", 0, 31))>; 445 446def CSR_AArch64_AllRegs 447 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP, 448 (sequence "X%u", 0, 28), FP, LR, SP, 449 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31), 450 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31), 451 (sequence "Q%u", 0, 31))>; 452 453def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>; 454 455def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS, 456 (sequence "X%u", 9, 15))>; 457 458def CSR_AArch64_StackProbe_Windows 459 : CalleeSavedRegs<(add (sequence "X%u", 0, 15), 460 (sequence "X%u", 18, 28), FP, SP, 461 (sequence "Q%u", 0, 31))>; 462 463// Darwin variants of AAPCS. 464// Darwin puts the frame-record at the top of the callee-save area. 465def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22, 466 X23, X24, X25, X26, X27, X28, 467 D8, D9, D10, D11, 468 D12, D13, D14, D15)>; 469 470def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, 471 X22, X23, X24, X25, X26, X27, 472 X28, (sequence "Q%u", 8, 23))>; 473def CSR_Darwin_AArch64_AAPCS_ThisReturn 474 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X0)>; 475 476def CSR_Darwin_AArch64_AAPCS_SwiftError 477 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>; 478 479def CSR_Darwin_AArch64_AAPCS_SwiftTail 480 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X20, X22)>; 481 482// The function used by Darwin to obtain the address of a thread-local variable 483// guarantees more than a normal AAPCS function. x16 and x17 are used on the 484// fast path for calculation, but other registers except X0 (argument/return) 485// and LR (it is a call, after all) are preserved. 486def CSR_Darwin_AArch64_TLS 487 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17), 488 FP, 489 (sequence "Q%u", 0, 31))>; 490 491// We can only handle a register pair with adjacent registers, the register pair 492// should belong to the same class as well. Since the access function on the 493// fast path calls a function that follows CSR_Darwin_AArch64_TLS, 494// CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS. 495def CSR_Darwin_AArch64_CXX_TLS 496 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, 497 (sub (sequence "X%u", 1, 28), X15, X16, X17, X18), 498 (sequence "D%u", 0, 31))>; 499 500// CSRs that are handled by prologue, epilogue. 501def CSR_Darwin_AArch64_CXX_TLS_PE 502 : CalleeSavedRegs<(add LR, FP)>; 503 504// CSRs that are handled explicitly via copies. 505def CSR_Darwin_AArch64_CXX_TLS_ViaCopy 506 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_CXX_TLS, LR, FP)>; 507 508def CSR_Darwin_AArch64_RT_MostRegs 509 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, (sequence "X%u", 9, 15))>; 510 511// Variants of the standard calling conventions for shadow call stack. 512// These all preserve x18 in addition to any other registers. 513def CSR_AArch64_NoRegs_SCS 514 : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>; 515def CSR_AArch64_AllRegs_SCS 516 : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>; 517def CSR_AArch64_AAPCS_SwiftError_SCS 518 : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>; 519def CSR_AArch64_RT_MostRegs_SCS 520 : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>; 521def CSR_AArch64_AAVPCS_SCS 522 : CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>; 523def CSR_AArch64_SVE_AAPCS_SCS 524 : CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>; 525def CSR_AArch64_AAPCS_SCS 526 : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>; 527