1 //===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines methods on the MCOperandInfo and MCInstrDesc classes, which 10 // are used to describe target instructions and their operands. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/MC/MCInstrDesc.h" 15 #include "llvm/MC/MCInst.h" 16 #include "llvm/MC/MCRegisterInfo.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 19 using namespace llvm; 20 21 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, 22 const MCRegisterInfo &RI) const { 23 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) 24 return true; 25 unsigned PC = RI.getProgramCounter(); 26 if (PC == 0) 27 return false; 28 if (hasDefOfPhysReg(MI, PC, RI)) 29 return true; 30 return false; 31 } 32 33 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, 34 const MCRegisterInfo *MRI) const { 35 if (const MCPhysReg *ImpDefs = ImplicitDefs) 36 for (; *ImpDefs; ++ImpDefs) 37 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) 38 return true; 39 return false; 40 } 41 42 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 43 const MCRegisterInfo &RI) const { 44 for (int i = 0, e = NumDefs; i != e; ++i) 45 if (MI.getOperand(i).isReg() && 46 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 47 return true; 48 if (variadicOpsAreDefs()) 49 for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i) 50 if (MI.getOperand(i).isReg() && 51 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 52 return true; 53 return hasImplicitDefOfPhysReg(Reg, &RI); 54 } 55