1 //===--------- aarch32.cpp - Generic JITLink arm/thumb utilities ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Generic utilities for graphs representing arm/thumb objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ExecutionEngine/JITLink/aarch32.h" 14 15 #include "llvm/ADT/StringExtras.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/ExecutionEngine/JITLink/JITLink.h" 18 #include "llvm/Object/ELFObjectFile.h" 19 #include "llvm/Support/Endian.h" 20 #include "llvm/Support/MathExtras.h" 21 22 #define DEBUG_TYPE "jitlink" 23 24 namespace llvm { 25 namespace jitlink { 26 namespace aarch32 { 27 28 /// Encode 22-bit immediate value for branch instructions without J1J2 range 29 /// extension (formats B T4, BL T1 and BLX T2). 30 /// 31 /// 00000:Imm11H:Imm11L:0 -> [ 00000:Imm11H, 00000:Imm11L ] 32 /// J1^ ^J2 will always be 1 33 /// 34 HalfWords encodeImmBT4BlT1BlxT2(int64_t Value) { 35 constexpr uint32_t J1J2 = 0x2800; 36 uint32_t Imm11H = (Value >> 12) & 0x07ff; 37 uint32_t Imm11L = (Value >> 1) & 0x07ff; 38 return HalfWords{Imm11H, Imm11L | J1J2}; 39 } 40 41 /// Decode 22-bit immediate value for branch instructions without J1J2 range 42 /// extension (formats B T4, BL T1 and BLX T2). 43 /// 44 /// [ 00000:Imm11H, 00000:Imm11L ] -> 00000:Imm11H:Imm11L:0 45 /// J1^ ^J2 will always be 1 46 /// 47 int64_t decodeImmBT4BlT1BlxT2(uint32_t Hi, uint32_t Lo) { 48 uint32_t Imm11H = Hi & 0x07ff; 49 uint32_t Imm11L = Lo & 0x07ff; 50 return SignExtend64<22>(Imm11H << 12 | Imm11L << 1); 51 } 52 53 /// Encode 25-bit immediate value for branch instructions with J1J2 range 54 /// extension (formats B T4, BL T1 and BLX T2). 55 /// 56 /// S:I1:I2:Imm10:Imm11:0 -> [ 00000:S:Imm10, 00:J1:0:J2:Imm11 ] 57 /// 58 HalfWords encodeImmBT4BlT1BlxT2_J1J2(int64_t Value) { 59 uint32_t S = (Value >> 14) & 0x0400; 60 uint32_t J1 = (((~(Value >> 10)) ^ (Value >> 11)) & 0x2000); 61 uint32_t J2 = (((~(Value >> 11)) ^ (Value >> 13)) & 0x0800); 62 uint32_t Imm10 = (Value >> 12) & 0x03ff; 63 uint32_t Imm11 = (Value >> 1) & 0x07ff; 64 return HalfWords{S | Imm10, J1 | J2 | Imm11}; 65 } 66 67 /// Decode 25-bit immediate value for branch instructions with J1J2 range 68 /// extension (formats B T4, BL T1 and BLX T2). 69 /// 70 /// [ 00000:S:Imm10, 00:J1:0:J2:Imm11] -> S:I1:I2:Imm10:Imm11:0 71 /// 72 int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo) { 73 uint32_t S = Hi & 0x0400; 74 uint32_t I1 = ~((Lo ^ (Hi << 3)) << 10) & 0x00800000; 75 uint32_t I2 = ~((Lo ^ (Hi << 1)) << 11) & 0x00400000; 76 uint32_t Imm10 = Hi & 0x03ff; 77 uint32_t Imm11 = Lo & 0x07ff; 78 return SignExtend64<25>(S << 14 | I1 | I2 | Imm10 << 12 | Imm11 << 1); 79 } 80 81 /// Encode 16-bit immediate value for move instruction formats MOVT T1 and 82 /// MOVW T3. 83 /// 84 /// Imm4:Imm1:Imm3:Imm8 -> [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] 85 /// 86 HalfWords encodeImmMovtT1MovwT3(uint16_t Value) { 87 uint32_t Imm4 = (Value >> 12) & 0x0f; 88 uint32_t Imm1 = (Value >> 11) & 0x01; 89 uint32_t Imm3 = (Value >> 8) & 0x07; 90 uint32_t Imm8 = Value & 0xff; 91 return HalfWords{Imm1 << 10 | Imm4, Imm3 << 12 | Imm8}; 92 } 93 94 /// Decode 16-bit immediate value from move instruction formats MOVT T1 and 95 /// MOVW T3. 96 /// 97 /// [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] -> Imm4:Imm1:Imm3:Imm8 98 /// 99 uint16_t decodeImmMovtT1MovwT3(uint32_t Hi, uint32_t Lo) { 100 uint32_t Imm4 = Hi & 0x0f; 101 uint32_t Imm1 = (Hi >> 10) & 0x01; 102 uint32_t Imm3 = (Lo >> 12) & 0x07; 103 uint32_t Imm8 = Lo & 0xff; 104 uint32_t Imm16 = Imm4 << 12 | Imm1 << 11 | Imm3 << 8 | Imm8; 105 assert(Imm16 <= 0xffff && "Decoded value out-of-range"); 106 return Imm16; 107 } 108 109 /// Encode register ID for instruction formats MOVT T1 and MOVW T3. 110 /// 111 /// Rd4 -> [0000000000000000, 0000:Rd4:00000000] 112 /// 113 HalfWords encodeRegMovtT1MovwT3(int64_t Value) { 114 uint32_t Rd4 = (Value & 0x0f) << 8; 115 return HalfWords{0, Rd4}; 116 } 117 118 /// Decode register ID from instruction formats MOVT T1 and MOVW T3. 119 /// 120 /// [0000000000000000, 0000:Rd4:00000000] -> Rd4 121 /// 122 int64_t decodeRegMovtT1MovwT3(uint32_t Hi, uint32_t Lo) { 123 uint32_t Rd4 = (Lo >> 8) & 0x0f; 124 return Rd4; 125 } 126 127 /// 32-bit Thumb instructions are stored as two little-endian halfwords. 128 /// An instruction at address A encodes bytes A+1, A in the first halfword (Hi), 129 /// followed by bytes A+3, A+2 in the second halfword (Lo). 130 struct WritableThumbRelocation { 131 /// Create a writable reference to a Thumb32 fixup. 132 WritableThumbRelocation(char *FixupPtr) 133 : Hi{*reinterpret_cast<support::ulittle16_t *>(FixupPtr)}, 134 Lo{*reinterpret_cast<support::ulittle16_t *>(FixupPtr + 2)} {} 135 136 support::ulittle16_t &Hi; // First halfword 137 support::ulittle16_t &Lo; // Second halfword 138 }; 139 140 struct ThumbRelocation { 141 /// Create a read-only reference to a Thumb32 fixup. 142 ThumbRelocation(const char *FixupPtr) 143 : Hi{*reinterpret_cast<const support::ulittle16_t *>(FixupPtr)}, 144 Lo{*reinterpret_cast<const support::ulittle16_t *>(FixupPtr + 2)} {} 145 146 /// Create a read-only Thumb32 fixup from a writeable one. 147 ThumbRelocation(WritableThumbRelocation &Writable) 148 : Hi{Writable.Hi}, Lo(Writable.Lo) {} 149 150 const support::ulittle16_t &Hi; // First halfword 151 const support::ulittle16_t &Lo; // Second halfword 152 }; 153 154 Error makeUnexpectedOpcodeError(const LinkGraph &G, const ThumbRelocation &R, 155 Edge::Kind Kind) { 156 return make_error<JITLinkError>( 157 formatv("Invalid opcode [ 0x{0:x4}, 0x{1:x4} ] for relocation: {2}", 158 static_cast<uint16_t>(R.Hi), static_cast<uint16_t>(R.Lo), 159 G.getEdgeKindName(Kind))); 160 } 161 162 template <EdgeKind_aarch32 Kind> bool checkOpcode(const ThumbRelocation &R) { 163 uint16_t Hi = R.Hi & FixupInfo<Kind>::OpcodeMask.Hi; 164 uint16_t Lo = R.Lo & FixupInfo<Kind>::OpcodeMask.Lo; 165 return Hi == FixupInfo<Kind>::Opcode.Hi && Lo == FixupInfo<Kind>::Opcode.Lo; 166 } 167 168 template <EdgeKind_aarch32 Kind> 169 bool checkRegister(const ThumbRelocation &R, HalfWords Reg) { 170 uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi; 171 uint16_t Lo = R.Lo & FixupInfo<Kind>::RegMask.Lo; 172 return Hi == Reg.Hi && Lo == Reg.Lo; 173 } 174 175 template <EdgeKind_aarch32 Kind> 176 void writeRegister(WritableThumbRelocation &R, HalfWords Reg) { 177 static constexpr HalfWords Mask = FixupInfo<Kind>::RegMask; 178 assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Hi & Reg.Hi) == Reg.Hi && 179 "Value bits exceed bit range of given mask"); 180 R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi; 181 R.Lo = (R.Lo & ~Mask.Lo) | Reg.Lo; 182 } 183 184 template <EdgeKind_aarch32 Kind> 185 void writeImmediate(WritableThumbRelocation &R, HalfWords Imm) { 186 static constexpr HalfWords Mask = FixupInfo<Kind>::ImmMask; 187 assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Hi & Imm.Hi) == Imm.Hi && 188 "Value bits exceed bit range of given mask"); 189 R.Hi = (R.Hi & ~Mask.Hi) | Imm.Hi; 190 R.Lo = (R.Lo & ~Mask.Lo) | Imm.Lo; 191 } 192 193 Expected<int64_t> readAddendData(LinkGraph &G, Block &B, const Edge &E) { 194 support::endianness Endian = G.getEndianness(); 195 assert(Endian != support::native && "Declare as little or big explicitly"); 196 197 Edge::Kind Kind = E.getKind(); 198 const char *BlockWorkingMem = B.getContent().data(); 199 const char *FixupPtr = BlockWorkingMem + E.getOffset(); 200 201 switch (Kind) { 202 case Data_Delta32: 203 case Data_Pointer32: 204 return SignExtend64<32>(support::endian::read32(FixupPtr, Endian)); 205 default: 206 return make_error<JITLinkError>( 207 "In graph " + G.getName() + ", section " + B.getSection().getName() + 208 " can not read implicit addend for aarch32 edge kind " + 209 G.getEdgeKindName(E.getKind())); 210 } 211 } 212 213 Expected<int64_t> readAddendArm(LinkGraph &G, Block &B, const Edge &E) { 214 Edge::Kind Kind = E.getKind(); 215 216 switch (Kind) { 217 case Arm_Call: 218 return make_error<JITLinkError>( 219 "Addend extraction for relocation type not yet implemented: " + 220 StringRef(G.getEdgeKindName(Kind))); 221 default: 222 return make_error<JITLinkError>( 223 "In graph " + G.getName() + ", section " + B.getSection().getName() + 224 " can not read implicit addend for aarch32 edge kind " + 225 G.getEdgeKindName(E.getKind())); 226 } 227 } 228 229 Expected<int64_t> readAddendThumb(LinkGraph &G, Block &B, const Edge &E, 230 const ArmConfig &ArmCfg) { 231 ThumbRelocation R(B.getContent().data() + E.getOffset()); 232 Edge::Kind Kind = E.getKind(); 233 234 switch (Kind) { 235 case Thumb_Call: 236 if (!checkOpcode<Thumb_Call>(R)) 237 return makeUnexpectedOpcodeError(G, R, Kind); 238 return LLVM_LIKELY(ArmCfg.J1J2BranchEncoding) 239 ? decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo) 240 : decodeImmBT4BlT1BlxT2(R.Hi, R.Lo); 241 242 case Thumb_Jump24: 243 if (!checkOpcode<Thumb_Jump24>(R)) 244 return makeUnexpectedOpcodeError(G, R, Kind); 245 if (R.Lo & FixupInfo<Thumb_Jump24>::LoBitConditional) 246 return make_error<JITLinkError>("Relocation expects an unconditional " 247 "B.W branch instruction: " + 248 StringRef(G.getEdgeKindName(Kind))); 249 return LLVM_LIKELY(ArmCfg.J1J2BranchEncoding) 250 ? decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo) 251 : decodeImmBT4BlT1BlxT2(R.Hi, R.Lo); 252 253 case Thumb_MovwAbsNC: 254 if (!checkOpcode<Thumb_MovwAbsNC>(R)) 255 return makeUnexpectedOpcodeError(G, R, Kind); 256 // Initial addend is interpreted as a signed value 257 return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo)); 258 259 case Thumb_MovtAbs: 260 if (!checkOpcode<Thumb_MovtAbs>(R)) 261 return makeUnexpectedOpcodeError(G, R, Kind); 262 // Initial addend is interpreted as a signed value 263 return SignExtend64<16>(decodeImmMovtT1MovwT3(R.Hi, R.Lo)); 264 265 default: 266 return make_error<JITLinkError>( 267 "In graph " + G.getName() + ", section " + B.getSection().getName() + 268 " can not read implicit addend for aarch32 edge kind " + 269 G.getEdgeKindName(E.getKind())); 270 } 271 } 272 273 Error applyFixupData(LinkGraph &G, Block &B, const Edge &E) { 274 using namespace support; 275 276 char *BlockWorkingMem = B.getAlreadyMutableContent().data(); 277 char *FixupPtr = BlockWorkingMem + E.getOffset(); 278 279 auto Write32 = [FixupPtr, Endian = G.getEndianness()](int64_t Value) { 280 assert(Endian != native && "Must be explicit: little or big"); 281 assert(isInt<32>(Value) && "Must be in signed 32-bit range"); 282 uint32_t Imm = static_cast<int32_t>(Value); 283 if (LLVM_LIKELY(Endian == little)) 284 endian::write32<little>(FixupPtr, Imm); 285 else 286 endian::write32<big>(FixupPtr, Imm); 287 }; 288 289 Edge::Kind Kind = E.getKind(); 290 uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue(); 291 int64_t Addend = E.getAddend(); 292 Symbol &TargetSymbol = E.getTarget(); 293 uint64_t TargetAddress = TargetSymbol.getAddress().getValue(); 294 assert(!TargetSymbol.hasTargetFlags(ThumbSymbol)); 295 296 // Regular data relocations have size 4, alignment 1 and write the full 32-bit 297 // result to the place; no need for overflow checking. There are three 298 // exceptions: R_ARM_ABS8, R_ARM_ABS16, R_ARM_PREL31 299 switch (Kind) { 300 case Data_Delta32: { 301 int64_t Value = TargetAddress - FixupAddress + Addend; 302 if (!isInt<32>(Value)) 303 return makeTargetOutOfRangeError(G, B, E); 304 Write32(Value); 305 return Error::success(); 306 } 307 case Data_Pointer32: { 308 int64_t Value = TargetAddress + Addend; 309 if (!isInt<32>(Value)) 310 return makeTargetOutOfRangeError(G, B, E); 311 Write32(Value); 312 return Error::success(); 313 } 314 default: 315 return make_error<JITLinkError>( 316 "In graph " + G.getName() + ", section " + B.getSection().getName() + 317 " encountered unfixable aarch32 edge kind " + 318 G.getEdgeKindName(E.getKind())); 319 } 320 } 321 322 Error applyFixupArm(LinkGraph &G, Block &B, const Edge &E) { 323 Edge::Kind Kind = E.getKind(); 324 325 switch (Kind) { 326 case Arm_Call: 327 return make_error<JITLinkError>( 328 "Fix-up for relocation type not yet implemented: " + 329 StringRef(G.getEdgeKindName(Kind))); 330 default: 331 return make_error<JITLinkError>( 332 "In graph " + G.getName() + ", section " + B.getSection().getName() + 333 " encountered unfixable aarch32 edge kind " + 334 G.getEdgeKindName(E.getKind())); 335 } 336 } 337 338 Error applyFixupThumb(LinkGraph &G, Block &B, const Edge &E, 339 const ArmConfig &ArmCfg) { 340 WritableThumbRelocation R(B.getAlreadyMutableContent().data() + 341 E.getOffset()); 342 343 Edge::Kind Kind = E.getKind(); 344 uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue(); 345 int64_t Addend = E.getAddend(); 346 Symbol &TargetSymbol = E.getTarget(); 347 uint64_t TargetAddress = TargetSymbol.getAddress().getValue(); 348 if (TargetSymbol.hasTargetFlags(ThumbSymbol)) 349 TargetAddress |= 0x01; 350 351 switch (Kind) { 352 case Thumb_Jump24: { 353 if (!checkOpcode<Thumb_Jump24>(R)) 354 return makeUnexpectedOpcodeError(G, R, Kind); 355 if (R.Lo & FixupInfo<Thumb_Jump24>::LoBitConditional) 356 return make_error<JITLinkError>("Relocation expects an unconditional " 357 "B.W branch instruction: " + 358 StringRef(G.getEdgeKindName(Kind))); 359 if (!(TargetSymbol.hasTargetFlags(ThumbSymbol))) 360 return make_error<JITLinkError>("Branch relocation needs interworking " 361 "stub when bridging to ARM: " + 362 StringRef(G.getEdgeKindName(Kind))); 363 364 int64_t Value = TargetAddress - FixupAddress + Addend; 365 if (LLVM_LIKELY(ArmCfg.J1J2BranchEncoding)) { 366 if (!isInt<25>(Value)) 367 return makeTargetOutOfRangeError(G, B, E); 368 writeImmediate<Thumb_Jump24>(R, encodeImmBT4BlT1BlxT2_J1J2(Value)); 369 } else { 370 if (!isInt<22>(Value)) 371 return makeTargetOutOfRangeError(G, B, E); 372 writeImmediate<Thumb_Jump24>(R, encodeImmBT4BlT1BlxT2(Value)); 373 } 374 375 return Error::success(); 376 } 377 378 case Thumb_Call: { 379 if (!checkOpcode<Thumb_Call>(R)) 380 return makeUnexpectedOpcodeError(G, R, Kind); 381 382 int64_t Value = TargetAddress - FixupAddress + Addend; 383 384 // The call instruction itself is Thumb. The call destination can either be 385 // Thumb or Arm. We use BL to stay in Thumb and BLX to change to Arm. 386 bool TargetIsArm = !TargetSymbol.hasTargetFlags(ThumbSymbol); 387 bool InstrIsBlx = (R.Lo & FixupInfo<Thumb_Call>::LoBitNoBlx) == 0; 388 if (TargetIsArm != InstrIsBlx) { 389 if (LLVM_LIKELY(TargetIsArm)) { 390 // Change opcode BL -> BLX and fix range value (account for 4-byte 391 // aligned destination while instruction may only be 2-byte aligned 392 // and clear Thumb bit). 393 R.Lo = R.Lo & ~FixupInfo<Thumb_Call>::LoBitNoBlx; 394 R.Lo = R.Lo & ~FixupInfo<Thumb_Call>::LoBitH; 395 Value = alignTo(Value, 4); 396 } else { 397 // Change opcode BLX -> BL and set Thumb bit 398 R.Lo = R.Lo & ~FixupInfo<Thumb_Call>::LoBitNoBlx; 399 Value |= 0x01; 400 } 401 } 402 403 if (LLVM_LIKELY(ArmCfg.J1J2BranchEncoding)) { 404 if (!isInt<25>(Value)) 405 return makeTargetOutOfRangeError(G, B, E); 406 writeImmediate<Thumb_Call>(R, encodeImmBT4BlT1BlxT2_J1J2(Value)); 407 } else { 408 if (!isInt<22>(Value)) 409 return makeTargetOutOfRangeError(G, B, E); 410 writeImmediate<Thumb_Call>(R, encodeImmBT4BlT1BlxT2(Value)); 411 } 412 413 assert(((R.Lo & FixupInfo<Thumb_Call>::LoBitNoBlx) || 414 (R.Lo & FixupInfo<Thumb_Call>::LoBitH) == 0) && 415 "Opcode BLX implies H bit is clear (avoid UB in BLX T2)"); 416 return Error::success(); 417 } 418 419 case Thumb_MovwAbsNC: { 420 if (!checkOpcode<Thumb_MovwAbsNC>(R)) 421 return makeUnexpectedOpcodeError(G, R, Kind); 422 uint16_t Value = (TargetAddress + Addend) & 0xffff; 423 writeImmediate<Thumb_MovwAbsNC>(R, encodeImmMovtT1MovwT3(Value)); 424 return Error::success(); 425 } 426 427 case Thumb_MovtAbs: { 428 if (!checkOpcode<Thumb_MovtAbs>(R)) 429 return makeUnexpectedOpcodeError(G, R, Kind); 430 uint16_t Value = ((TargetAddress + Addend) >> 16) & 0xffff; 431 writeImmediate<Thumb_MovtAbs>(R, encodeImmMovtT1MovwT3(Value)); 432 return Error::success(); 433 } 434 435 default: 436 return make_error<JITLinkError>( 437 "In graph " + G.getName() + ", section " + B.getSection().getName() + 438 " encountered unfixable aarch32 edge kind " + 439 G.getEdgeKindName(E.getKind())); 440 } 441 } 442 443 const uint8_t Thumbv7ABS[] = { 444 0x40, 0xf2, 0x00, 0x0c, // movw r12, #0x0000 ; lower 16-bit 445 0xc0, 0xf2, 0x00, 0x0c, // movt r12, #0x0000 ; upper 16-bit 446 0x60, 0x47 // bx r12 447 }; 448 449 template <> 450 Symbol &StubsManager<Thumbv7>::createEntry(LinkGraph &G, Symbol &Target) { 451 constexpr uint64_t Alignment = 4; 452 Block &B = addStub(G, Thumbv7ABS, Alignment); 453 LLVM_DEBUG({ 454 const char *StubPtr = B.getContent().data(); 455 HalfWords Reg12 = encodeRegMovtT1MovwT3(12); 456 assert(checkRegister<Thumb_MovwAbsNC>(StubPtr, Reg12) && 457 checkRegister<Thumb_MovtAbs>(StubPtr + 4, Reg12) && 458 "Linker generated stubs may only corrupt register r12 (IP)"); 459 }); 460 B.addEdge(Thumb_MovwAbsNC, 0, Target, 0); 461 B.addEdge(Thumb_MovtAbs, 4, Target, 0); 462 Symbol &Stub = G.addAnonymousSymbol(B, 0, B.getSize(), true, false); 463 Stub.setTargetFlags(ThumbSymbol); 464 return Stub; 465 } 466 467 const char *getEdgeKindName(Edge::Kind K) { 468 #define KIND_NAME_CASE(K) \ 469 case K: \ 470 return #K; 471 472 switch (K) { 473 KIND_NAME_CASE(Data_Delta32) 474 KIND_NAME_CASE(Arm_Call) 475 KIND_NAME_CASE(Thumb_Call) 476 KIND_NAME_CASE(Thumb_Jump24) 477 KIND_NAME_CASE(Thumb_MovwAbsNC) 478 KIND_NAME_CASE(Thumb_MovtAbs) 479 default: 480 return getGenericEdgeKindName(K); 481 } 482 #undef KIND_NAME_CASE 483 } 484 485 const char *getCPUArchName(ARMBuildAttrs::CPUArch K) { 486 #define CPUARCH_NAME_CASE(K) \ 487 case K: \ 488 return #K; 489 490 using namespace ARMBuildAttrs; 491 switch (K) { 492 CPUARCH_NAME_CASE(Pre_v4) 493 CPUARCH_NAME_CASE(v4) 494 CPUARCH_NAME_CASE(v4T) 495 CPUARCH_NAME_CASE(v5T) 496 CPUARCH_NAME_CASE(v5TE) 497 CPUARCH_NAME_CASE(v5TEJ) 498 CPUARCH_NAME_CASE(v6) 499 CPUARCH_NAME_CASE(v6KZ) 500 CPUARCH_NAME_CASE(v6T2) 501 CPUARCH_NAME_CASE(v6K) 502 CPUARCH_NAME_CASE(v7) 503 CPUARCH_NAME_CASE(v6_M) 504 CPUARCH_NAME_CASE(v6S_M) 505 CPUARCH_NAME_CASE(v7E_M) 506 CPUARCH_NAME_CASE(v8_A) 507 CPUARCH_NAME_CASE(v8_R) 508 CPUARCH_NAME_CASE(v8_M_Base) 509 CPUARCH_NAME_CASE(v8_M_Main) 510 CPUARCH_NAME_CASE(v8_1_M_Main) 511 CPUARCH_NAME_CASE(v9_A) 512 } 513 llvm_unreachable("Missing CPUArch in switch?"); 514 #undef CPUARCH_NAME_CASE 515 } 516 517 } // namespace aarch32 518 } // namespace jitlink 519 } // namespace llvm 520