1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the TargetRegisterInfo interface. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/CodeGen/TargetRegisterInfo.h" 14 #include "llvm/ADT/ArrayRef.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallSet.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/LiveInterval.h" 23 #include "llvm/CodeGen/TargetFrameLowering.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetSubtargetInfo.h" 26 #include "llvm/CodeGen/VirtRegMap.h" 27 #include "llvm/Config/llvm-config.h" 28 #include "llvm/IR/Attributes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Compiler.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/MachineValueType.h" 35 #include "llvm/Support/MathExtras.h" 36 #include "llvm/Support/Printable.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <cassert> 39 #include <utility> 40 41 #define DEBUG_TYPE "target-reg-info" 42 43 using namespace llvm; 44 45 static cl::opt<unsigned> 46 HugeSizeForSplit("huge-size-for-split", cl::Hidden, 47 cl::desc("A threshold of live range size which may cause " 48 "high compile time cost in global splitting."), 49 cl::init(5000)); 50 51 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 52 regclass_iterator RCB, regclass_iterator RCE, 53 const char *const *SRINames, 54 const LaneBitmask *SRILaneMasks, 55 LaneBitmask SRICoveringLanes, 56 const RegClassInfo *const RCIs, 57 unsigned Mode) 58 : InfoDesc(ID), SubRegIndexNames(SRINames), 59 SubRegIndexLaneMasks(SRILaneMasks), 60 RegClassBegin(RCB), RegClassEnd(RCE), 61 CoveringLanes(SRICoveringLanes), 62 RCInfos(RCIs), HwMode(Mode) { 63 } 64 65 TargetRegisterInfo::~TargetRegisterInfo() = default; 66 67 bool TargetRegisterInfo::shouldRegionSplitForVirtReg( 68 const MachineFunction &MF, const LiveInterval &VirtReg) const { 69 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); 70 const MachineRegisterInfo &MRI = MF.getRegInfo(); 71 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg); 72 if (MI && TII->isTriviallyReMaterializable(*MI) && 73 VirtReg.size() > HugeSizeForSplit) 74 return false; 75 return true; 76 } 77 78 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, 79 MCRegister Reg) const { 80 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI) 81 RegisterSet.set(*AI); 82 } 83 84 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, 85 ArrayRef<MCPhysReg> Exceptions) const { 86 // Check that all super registers of reserved regs are reserved as well. 87 BitVector Checked(getNumRegs()); 88 for (unsigned Reg : RegisterSet.set_bits()) { 89 if (Checked[Reg]) 90 continue; 91 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { 92 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { 93 dbgs() << "Error: Super register " << printReg(*SR, this) 94 << " of reserved register " << printReg(Reg, this) 95 << " is not reserved.\n"; 96 return false; 97 } 98 99 // We transitively check superregs. So we can remember this for later 100 // to avoid compiletime explosion in deep register hierarchies. 101 Checked.set(*SR); 102 } 103 } 104 return true; 105 } 106 107 namespace llvm { 108 109 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, 110 unsigned SubIdx, const MachineRegisterInfo *MRI) { 111 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { 112 if (!Reg) 113 OS << "$noreg"; 114 else if (Register::isStackSlot(Reg)) 115 OS << "SS#" << Register::stackSlot2Index(Reg); 116 else if (Register::isVirtualRegister(Reg)) { 117 StringRef Name = MRI ? MRI->getVRegName(Reg) : ""; 118 if (Name != "") { 119 OS << '%' << Name; 120 } else { 121 OS << '%' << Register::virtReg2Index(Reg); 122 } 123 } else if (!TRI) 124 OS << '$' << "physreg" << Reg; 125 else if (Reg < TRI->getNumRegs()) { 126 OS << '$'; 127 printLowerCase(TRI->getName(Reg), OS); 128 } else 129 llvm_unreachable("Register kind is unsupported."); 130 131 if (SubIdx) { 132 if (TRI) 133 OS << ':' << TRI->getSubRegIndexName(SubIdx); 134 else 135 OS << ":sub(" << SubIdx << ')'; 136 } 137 }); 138 } 139 140 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 141 return Printable([Unit, TRI](raw_ostream &OS) { 142 // Generic printout when TRI is missing. 143 if (!TRI) { 144 OS << "Unit~" << Unit; 145 return; 146 } 147 148 // Check for invalid register units. 149 if (Unit >= TRI->getNumRegUnits()) { 150 OS << "BadUnit~" << Unit; 151 return; 152 } 153 154 // Normal units have at least one root. 155 MCRegUnitRootIterator Roots(Unit, TRI); 156 assert(Roots.isValid() && "Unit has no roots."); 157 OS << TRI->getName(*Roots); 158 for (++Roots; Roots.isValid(); ++Roots) 159 OS << '~' << TRI->getName(*Roots); 160 }); 161 } 162 163 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 164 return Printable([Unit, TRI](raw_ostream &OS) { 165 if (Register::isVirtualRegister(Unit)) { 166 OS << '%' << Register::virtReg2Index(Unit); 167 } else { 168 OS << printRegUnit(Unit, TRI); 169 } 170 }); 171 } 172 173 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, 174 const TargetRegisterInfo *TRI) { 175 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { 176 if (RegInfo.getRegClassOrNull(Reg)) 177 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); 178 else if (RegInfo.getRegBankOrNull(Reg)) 179 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); 180 else { 181 OS << "_"; 182 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && 183 "Generic registers must have a valid type"); 184 } 185 }); 186 } 187 188 } // end namespace llvm 189 190 /// getAllocatableClass - Return the maximal subclass of the given register 191 /// class that is alloctable, or NULL. 192 const TargetRegisterClass * 193 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 194 if (!RC || RC->isAllocatable()) 195 return RC; 196 197 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); 198 ++It) { 199 const TargetRegisterClass *SubRC = getRegClass(It.getID()); 200 if (SubRC->isAllocatable()) 201 return SubRC; 202 } 203 return nullptr; 204 } 205 206 /// getMinimalPhysRegClass - Returns the Register Class of a physical 207 /// register of the given type, picking the most sub register class of 208 /// the right type that contains this physreg. 209 const TargetRegisterClass * 210 TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const { 211 assert(Register::isPhysicalRegister(reg) && 212 "reg must be a physical register"); 213 214 // Pick the most sub register class of the right type that contains 215 // this physreg. 216 const TargetRegisterClass* BestRC = nullptr; 217 for (const TargetRegisterClass* RC : regclasses()) { 218 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) && 219 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) 220 BestRC = RC; 221 } 222 223 assert(BestRC && "Couldn't find the register class"); 224 return BestRC; 225 } 226 227 /// getAllocatableSetForRC - Toggle the bits that represent allocatable 228 /// registers for the specific register class. 229 static void getAllocatableSetForRC(const MachineFunction &MF, 230 const TargetRegisterClass *RC, BitVector &R){ 231 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 232 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); 233 for (unsigned i = 0; i != Order.size(); ++i) 234 R.set(Order[i]); 235 } 236 237 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 238 const TargetRegisterClass *RC) const { 239 BitVector Allocatable(getNumRegs()); 240 if (RC) { 241 // A register class with no allocatable subclass returns an empty set. 242 const TargetRegisterClass *SubClass = getAllocatableClass(RC); 243 if (SubClass) 244 getAllocatableSetForRC(MF, SubClass, Allocatable); 245 } else { 246 for (const TargetRegisterClass *C : regclasses()) 247 if (C->isAllocatable()) 248 getAllocatableSetForRC(MF, C, Allocatable); 249 } 250 251 // Mask out the reserved registers 252 BitVector Reserved = getReservedRegs(MF); 253 Allocatable &= Reserved.flip(); 254 255 return Allocatable; 256 } 257 258 static inline 259 const TargetRegisterClass *firstCommonClass(const uint32_t *A, 260 const uint32_t *B, 261 const TargetRegisterInfo *TRI) { 262 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 263 if (unsigned Common = *A++ & *B++) 264 return TRI->getRegClass(I + countTrailingZeros(Common)); 265 return nullptr; 266 } 267 268 const TargetRegisterClass * 269 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 270 const TargetRegisterClass *B) const { 271 // First take care of the trivial cases. 272 if (A == B) 273 return A; 274 if (!A || !B) 275 return nullptr; 276 277 // Register classes are ordered topologically, so the largest common 278 // sub-class it the common sub-class with the smallest ID. 279 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); 280 } 281 282 const TargetRegisterClass * 283 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 284 const TargetRegisterClass *B, 285 unsigned Idx) const { 286 assert(A && B && "Missing register class"); 287 assert(Idx && "Bad sub-register index"); 288 289 // Find Idx in the list of super-register indices. 290 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 291 if (RCI.getSubReg() == Idx) 292 // The bit mask contains all register classes that are projected into B 293 // by Idx. Find a class that is also a sub-class of A. 294 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 295 return nullptr; 296 } 297 298 const TargetRegisterClass *TargetRegisterInfo:: 299 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 300 const TargetRegisterClass *RCB, unsigned SubB, 301 unsigned &PreA, unsigned &PreB) const { 302 assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 303 304 // Search all pairs of sub-register indices that project into RCA and RCB 305 // respectively. This is quadratic, but usually the sets are very small. On 306 // most targets like X86, there will only be a single sub-register index 307 // (e.g., sub_16bit projecting into GR16). 308 // 309 // The worst case is a register class like DPR on ARM. 310 // We have indices dsub_0..dsub_7 projecting into that class. 311 // 312 // It is very common that one register class is a sub-register of the other. 313 // Arrange for RCA to be the larger register so the answer will be found in 314 // the first iteration. This makes the search linear for the most common 315 // case. 316 const TargetRegisterClass *BestRC = nullptr; 317 unsigned *BestPreA = &PreA; 318 unsigned *BestPreB = &PreB; 319 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { 320 std::swap(RCA, RCB); 321 std::swap(SubA, SubB); 322 std::swap(BestPreA, BestPreB); 323 } 324 325 // Also terminate the search one we have found a register class as small as 326 // RCA. 327 unsigned MinSize = getRegSizeInBits(*RCA); 328 329 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 330 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 331 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 332 // Check if a common super-register class exists for this index pair. 333 const TargetRegisterClass *RC = 334 firstCommonClass(IA.getMask(), IB.getMask(), this); 335 if (!RC || getRegSizeInBits(*RC) < MinSize) 336 continue; 337 338 // The indexes must compose identically: PreA+SubA == PreB+SubB. 339 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 340 if (FinalA != FinalB) 341 continue; 342 343 // Is RC a better candidate than BestRC? 344 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) 345 continue; 346 347 // Yes, RC is the smallest super-register seen so far. 348 BestRC = RC; 349 *BestPreA = IA.getSubReg(); 350 *BestPreB = IB.getSubReg(); 351 352 // Bail early if we reached MinSize. We won't find a better candidate. 353 if (getRegSizeInBits(*BestRC) == MinSize) 354 return BestRC; 355 } 356 } 357 return BestRC; 358 } 359 360 /// Check if the registers defined by the pair (RegisterClass, SubReg) 361 /// share the same register file. 362 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, 363 const TargetRegisterClass *DefRC, 364 unsigned DefSubReg, 365 const TargetRegisterClass *SrcRC, 366 unsigned SrcSubReg) { 367 // Same register class. 368 if (DefRC == SrcRC) 369 return true; 370 371 // Both operands are sub registers. Check if they share a register class. 372 unsigned SrcIdx, DefIdx; 373 if (SrcSubReg && DefSubReg) { 374 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, 375 SrcIdx, DefIdx) != nullptr; 376 } 377 378 // At most one of the register is a sub register, make it Src to avoid 379 // duplicating the test. 380 if (!SrcSubReg) { 381 std::swap(DefSubReg, SrcSubReg); 382 std::swap(DefRC, SrcRC); 383 } 384 385 // One of the register is a sub register, check if we can get a superclass. 386 if (SrcSubReg) 387 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; 388 389 // Plain copy. 390 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; 391 } 392 393 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 394 unsigned DefSubReg, 395 const TargetRegisterClass *SrcRC, 396 unsigned SrcSubReg) const { 397 // If this source does not incur a cross register bank copy, use it. 398 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); 399 } 400 401 // Compute target-independent register allocator hints to help eliminate copies. 402 bool TargetRegisterInfo::getRegAllocationHints( 403 Register VirtReg, ArrayRef<MCPhysReg> Order, 404 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, 405 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { 406 const MachineRegisterInfo &MRI = MF.getRegInfo(); 407 const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI = 408 MRI.getRegAllocationHints(VirtReg); 409 410 SmallSet<Register, 32> HintedRegs; 411 // First hint may be a target hint. 412 bool Skip = (Hints_MRI.first != 0); 413 for (auto Reg : Hints_MRI.second) { 414 if (Skip) { 415 Skip = false; 416 continue; 417 } 418 419 // Target-independent hints are either a physical or a virtual register. 420 Register Phys = Reg; 421 if (VRM && Phys.isVirtual()) 422 Phys = VRM->getPhys(Phys); 423 424 // Don't add the same reg twice (Hints_MRI may contain multiple virtual 425 // registers allocated to the same physreg). 426 if (!HintedRegs.insert(Phys).second) 427 continue; 428 // Check that Phys is a valid hint in VirtReg's register class. 429 if (!Phys.isPhysical()) 430 continue; 431 if (MRI.isReserved(Phys)) 432 continue; 433 // Check that Phys is in the allocation order. We shouldn't heed hints 434 // from VirtReg's register class if they aren't in the allocation order. The 435 // target probably has a reason for removing the register. 436 if (!is_contained(Order, Phys)) 437 continue; 438 439 // All clear, tell the register allocator to prefer this register. 440 Hints.push_back(Phys); 441 } 442 return false; 443 } 444 445 bool TargetRegisterInfo::isCalleeSavedPhysReg( 446 MCRegister PhysReg, const MachineFunction &MF) const { 447 if (PhysReg == 0) 448 return false; 449 const uint32_t *callerPreservedRegs = 450 getCallPreservedMask(MF, MF.getFunction().getCallingConv()); 451 if (callerPreservedRegs) { 452 assert(Register::isPhysicalRegister(PhysReg) && 453 "Expected physical register"); 454 return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1; 455 } 456 return false; 457 } 458 459 bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const { 460 return !MF.getFunction().hasFnAttribute("no-realign-stack"); 461 } 462 463 bool TargetRegisterInfo::needsStackRealignment( 464 const MachineFunction &MF) const { 465 const MachineFrameInfo &MFI = MF.getFrameInfo(); 466 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 467 const Function &F = MF.getFunction(); 468 Align StackAlign = TFI->getStackAlign(); 469 bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) || 470 F.hasFnAttribute(Attribute::StackAlignment)); 471 if (F.hasFnAttribute("stackrealign") || requiresRealignment) { 472 if (canRealignStack(MF)) 473 return true; 474 LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() 475 << "\n"); 476 } 477 return false; 478 } 479 480 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, 481 const uint32_t *mask1) const { 482 unsigned N = (getNumRegs()+31) / 32; 483 for (unsigned I = 0; I < N; ++I) 484 if ((mask0[I] & mask1[I]) != mask0[I]) 485 return false; 486 return true; 487 } 488 489 unsigned 490 TargetRegisterInfo::getRegSizeInBits(Register Reg, 491 const MachineRegisterInfo &MRI) const { 492 const TargetRegisterClass *RC{}; 493 if (Reg.isPhysical()) { 494 // The size is not directly available for physical registers. 495 // Instead, we need to access a register class that contains Reg and 496 // get the size of that register class. 497 RC = getMinimalPhysRegClass(Reg); 498 } else { 499 LLT Ty = MRI.getType(Reg); 500 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; 501 // If Reg is not a generic register, query the register class to 502 // get its size. 503 if (RegSize) 504 return RegSize; 505 // Since Reg is not a generic register, it must have a register class. 506 RC = MRI.getRegClass(Reg); 507 } 508 assert(RC && "Unable to deduce the register class"); 509 return getRegSizeInBits(*RC); 510 } 511 512 Register 513 TargetRegisterInfo::lookThruCopyLike(Register SrcReg, 514 const MachineRegisterInfo *MRI) const { 515 while (true) { 516 const MachineInstr *MI = MRI->getVRegDef(SrcReg); 517 if (!MI->isCopyLike()) 518 return SrcReg; 519 520 Register CopySrcReg; 521 if (MI->isCopy()) 522 CopySrcReg = MI->getOperand(1).getReg(); 523 else { 524 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"); 525 CopySrcReg = MI->getOperand(2).getReg(); 526 } 527 528 if (!CopySrcReg.isVirtual()) 529 return CopySrcReg; 530 531 SrcReg = CopySrcReg; 532 } 533 } 534 535 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 536 LLVM_DUMP_METHOD 537 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex, 538 const TargetRegisterInfo *TRI) { 539 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; 540 } 541 #endif 542