1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines interfaces to access the target independent code 10 // generation passes provided by the LLVM backend. 11 // 12 //===---------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/TargetPassConfig.h" 15 #include "llvm/ADT/DenseMap.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/Analysis/BasicAliasAnalysis.h" 19 #include "llvm/Analysis/CFLAndersAliasAnalysis.h" 20 #include "llvm/Analysis/CFLSteensAliasAnalysis.h" 21 #include "llvm/Analysis/CallGraphSCCPass.h" 22 #include "llvm/Analysis/ScopedNoAliasAA.h" 23 #include "llvm/Analysis/TargetTransformInfo.h" 24 #include "llvm/Analysis/TypeBasedAliasAnalysis.h" 25 #include "llvm/CodeGen/CSEConfigBase.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/MachinePassRegistry.h" 28 #include "llvm/CodeGen/Passes.h" 29 #include "llvm/CodeGen/RegAllocRegistry.h" 30 #include "llvm/IR/IRPrintingPasses.h" 31 #include "llvm/IR/LegacyPassManager.h" 32 #include "llvm/IR/Verifier.h" 33 #include "llvm/InitializePasses.h" 34 #include "llvm/MC/MCAsmInfo.h" 35 #include "llvm/MC/MCTargetOptions.h" 36 #include "llvm/Pass.h" 37 #include "llvm/Support/CodeGen.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Compiler.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/ErrorHandling.h" 42 #include "llvm/Support/SaveAndRestore.h" 43 #include "llvm/Support/Threading.h" 44 #include "llvm/Target/TargetMachine.h" 45 #include "llvm/Transforms/Scalar.h" 46 #include "llvm/Transforms/Utils.h" 47 #include "llvm/Transforms/Utils/SymbolRewriter.h" 48 #include <cassert> 49 #include <string> 50 51 using namespace llvm; 52 53 static cl::opt<bool> 54 EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, 55 cl::desc("Enable interprocedural register allocation " 56 "to reduce load/store at procedure calls.")); 57 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden, 58 cl::desc("Disable Post Regalloc Scheduler")); 59 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 60 cl::desc("Disable branch folding")); 61 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 62 cl::desc("Disable tail duplication")); 63 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 64 cl::desc("Disable pre-register allocation tail duplication")); 65 static cl::opt<bool> DisableBlockPlacement("disable-block-placement", 66 cl::Hidden, cl::desc("Disable probability-driven block placement")); 67 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 68 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 69 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 70 cl::desc("Disable Stack Slot Coloring")); 71 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 72 cl::desc("Disable Machine Dead Code Elimination")); 73 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 74 cl::desc("Disable Early If-conversion")); 75 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 76 cl::desc("Disable Machine LICM")); 77 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 78 cl::desc("Disable Machine Common Subexpression Elimination")); 79 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc( 80 "optimize-regalloc", cl::Hidden, 81 cl::desc("Enable optimized register allocation compilation path.")); 82 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 83 cl::Hidden, 84 cl::desc("Disable Machine LICM")); 85 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 86 cl::desc("Disable Machine Sinking")); 87 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink", 88 cl::Hidden, 89 cl::desc("Disable PostRA Machine Sinking")); 90 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 91 cl::desc("Disable Loop Strength Reduction Pass")); 92 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting", 93 cl::Hidden, cl::desc("Disable ConstantHoisting")); 94 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 95 cl::desc("Disable Codegen Prepare")); 96 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 97 cl::desc("Disable Copy Propagation pass")); 98 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining", 99 cl::Hidden, cl::desc("Disable Partial Libcall Inlining")); 100 static cl::opt<bool> EnableImplicitNullChecks( 101 "enable-implicit-null-checks", 102 cl::desc("Fold null checks into faulting memory operations"), 103 cl::init(false), cl::Hidden); 104 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps", 105 cl::desc("Disable MergeICmps Pass"), 106 cl::init(false), cl::Hidden); 107 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 108 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 109 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 110 cl::desc("Print LLVM IR input to isel pass")); 111 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 112 cl::desc("Dump garbage collector data")); 113 static cl::opt<cl::boolOrDefault> 114 VerifyMachineCode("verify-machineinstrs", cl::Hidden, 115 cl::desc("Verify generated machine code"), 116 cl::ZeroOrMore); 117 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault }; 118 // Enable or disable the MachineOutliner. 119 static cl::opt<RunOutliner> EnableMachineOutliner( 120 "enable-machine-outliner", cl::desc("Enable the machine outliner"), 121 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), 122 cl::values(clEnumValN(AlwaysOutline, "always", 123 "Run on all functions guaranteed to be beneficial"), 124 clEnumValN(NeverOutline, "never", "Disable all outlining"), 125 // Sentinel value for unspecified option. 126 clEnumValN(AlwaysOutline, "", ""))); 127 // Enable or disable FastISel. Both options are needed, because 128 // FastISel is enabled by default with -fast, and we wish to be 129 // able to enable or disable fast-isel independently from -O0. 130 static cl::opt<cl::boolOrDefault> 131 EnableFastISelOption("fast-isel", cl::Hidden, 132 cl::desc("Enable the \"fast\" instruction selector")); 133 134 static cl::opt<cl::boolOrDefault> EnableGlobalISelOption( 135 "global-isel", cl::Hidden, 136 cl::desc("Enable the \"global\" instruction selector")); 137 138 static cl::opt<std::string> PrintMachineInstrs( 139 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), 140 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden); 141 142 static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort( 143 "global-isel-abort", cl::Hidden, 144 cl::desc("Enable abort calls when \"global\" instruction selection " 145 "fails to lower/select an instruction"), 146 cl::values( 147 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), 148 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), 149 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", 150 "Disable the abort but emit a diagnostic on failure"))); 151 152 // Temporary option to allow experimenting with MachineScheduler as a post-RA 153 // scheduler. Targets can "properly" enable this with 154 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID). 155 // Targets can return true in targetSchedulesPostRAScheduling() and 156 // insert a PostRA scheduling pass wherever it wants. 157 static cl::opt<bool> MISchedPostRA( 158 "misched-postra", cl::Hidden, 159 cl::desc( 160 "Run MachineScheduler post regalloc (independent of preRA sched)")); 161 162 // Experimental option to run live interval analysis early. 163 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 164 cl::desc("Run live interval analysis earlier in the pipeline")); 165 166 // Experimental option to use CFL-AA in codegen 167 enum class CFLAAType { None, Steensgaard, Andersen, Both }; 168 static cl::opt<CFLAAType> UseCFLAA( 169 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, 170 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), 171 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), 172 clEnumValN(CFLAAType::Steensgaard, "steens", 173 "Enable unification-based CFL-AA"), 174 clEnumValN(CFLAAType::Andersen, "anders", 175 "Enable inclusion-based CFL-AA"), 176 clEnumValN(CFLAAType::Both, "both", 177 "Enable both variants of CFL-AA"))); 178 179 /// Option names for limiting the codegen pipeline. 180 /// Those are used in error reporting and we didn't want 181 /// to duplicate their names all over the place. 182 static const char StartAfterOptName[] = "start-after"; 183 static const char StartBeforeOptName[] = "start-before"; 184 static const char StopAfterOptName[] = "stop-after"; 185 static const char StopBeforeOptName[] = "stop-before"; 186 187 static cl::opt<std::string> 188 StartAfterOpt(StringRef(StartAfterOptName), 189 cl::desc("Resume compilation after a specific pass"), 190 cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 191 192 static cl::opt<std::string> 193 StartBeforeOpt(StringRef(StartBeforeOptName), 194 cl::desc("Resume compilation before a specific pass"), 195 cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 196 197 static cl::opt<std::string> 198 StopAfterOpt(StringRef(StopAfterOptName), 199 cl::desc("Stop compilation after a specific pass"), 200 cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 201 202 static cl::opt<std::string> 203 StopBeforeOpt(StringRef(StopBeforeOptName), 204 cl::desc("Stop compilation before a specific pass"), 205 cl::value_desc("pass-name"), cl::init(""), cl::Hidden); 206 207 /// Allow standard passes to be disabled by command line options. This supports 208 /// simple binary flags that either suppress the pass or do nothing. 209 /// i.e. -disable-mypass=false has no effect. 210 /// These should be converted to boolOrDefault in order to use applyOverride. 211 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 212 bool Override) { 213 if (Override) 214 return IdentifyingPassPtr(); 215 return PassID; 216 } 217 218 /// Allow standard passes to be disabled by the command line, regardless of who 219 /// is adding the pass. 220 /// 221 /// StandardID is the pass identified in the standard pass pipeline and provided 222 /// to addPass(). It may be a target-specific ID in the case that the target 223 /// directly adds its own pass, but in that case we harmlessly fall through. 224 /// 225 /// TargetID is the pass that the target has configured to override StandardID. 226 /// 227 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real 228 /// pass to run. This allows multiple options to control a single pass depending 229 /// on where in the pipeline that pass is added. 230 static IdentifyingPassPtr overridePass(AnalysisID StandardID, 231 IdentifyingPassPtr TargetID) { 232 if (StandardID == &PostRASchedulerID) 233 return applyDisable(TargetID, DisablePostRASched); 234 235 if (StandardID == &BranchFolderPassID) 236 return applyDisable(TargetID, DisableBranchFold); 237 238 if (StandardID == &TailDuplicateID) 239 return applyDisable(TargetID, DisableTailDuplicate); 240 241 if (StandardID == &EarlyTailDuplicateID) 242 return applyDisable(TargetID, DisableEarlyTailDup); 243 244 if (StandardID == &MachineBlockPlacementID) 245 return applyDisable(TargetID, DisableBlockPlacement); 246 247 if (StandardID == &StackSlotColoringID) 248 return applyDisable(TargetID, DisableSSC); 249 250 if (StandardID == &DeadMachineInstructionElimID) 251 return applyDisable(TargetID, DisableMachineDCE); 252 253 if (StandardID == &EarlyIfConverterID) 254 return applyDisable(TargetID, DisableEarlyIfConversion); 255 256 if (StandardID == &EarlyMachineLICMID) 257 return applyDisable(TargetID, DisableMachineLICM); 258 259 if (StandardID == &MachineCSEID) 260 return applyDisable(TargetID, DisableMachineCSE); 261 262 if (StandardID == &MachineLICMID) 263 return applyDisable(TargetID, DisablePostRAMachineLICM); 264 265 if (StandardID == &MachineSinkingID) 266 return applyDisable(TargetID, DisableMachineSink); 267 268 if (StandardID == &PostRAMachineSinkingID) 269 return applyDisable(TargetID, DisablePostRAMachineSink); 270 271 if (StandardID == &MachineCopyPropagationID) 272 return applyDisable(TargetID, DisableCopyProp); 273 274 return TargetID; 275 } 276 277 //===---------------------------------------------------------------------===// 278 /// TargetPassConfig 279 //===---------------------------------------------------------------------===// 280 281 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 282 "Target Pass Configuration", false, false) 283 char TargetPassConfig::ID = 0; 284 285 namespace { 286 287 struct InsertedPass { 288 AnalysisID TargetPassID; 289 IdentifyingPassPtr InsertedPassID; 290 bool VerifyAfter; 291 bool PrintAfter; 292 293 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, 294 bool VerifyAfter, bool PrintAfter) 295 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID), 296 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {} 297 298 Pass *getInsertedPass() const { 299 assert(InsertedPassID.isValid() && "Illegal Pass ID!"); 300 if (InsertedPassID.isInstance()) 301 return InsertedPassID.getInstance(); 302 Pass *NP = Pass::createPass(InsertedPassID.getID()); 303 assert(NP && "Pass ID not registered"); 304 return NP; 305 } 306 }; 307 308 } // end anonymous namespace 309 310 namespace llvm { 311 312 class PassConfigImpl { 313 public: 314 // List of passes explicitly substituted by this target. Normally this is 315 // empty, but it is a convenient way to suppress or replace specific passes 316 // that are part of a standard pass pipeline without overridding the entire 317 // pipeline. This mechanism allows target options to inherit a standard pass's 318 // user interface. For example, a target may disable a standard pass by 319 // default by substituting a pass ID of zero, and the user may still enable 320 // that standard pass with an explicit command line option. 321 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 322 323 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 324 /// is inserted after each instance of the first one. 325 SmallVector<InsertedPass, 4> InsertedPasses; 326 }; 327 328 } // end namespace llvm 329 330 // Out of line virtual method. 331 TargetPassConfig::~TargetPassConfig() { 332 delete Impl; 333 } 334 335 static const PassInfo *getPassInfo(StringRef PassName) { 336 if (PassName.empty()) 337 return nullptr; 338 339 const PassRegistry &PR = *PassRegistry::getPassRegistry(); 340 const PassInfo *PI = PR.getPassInfo(PassName); 341 if (!PI) 342 report_fatal_error(Twine('\"') + Twine(PassName) + 343 Twine("\" pass is not registered.")); 344 return PI; 345 } 346 347 static AnalysisID getPassIDFromName(StringRef PassName) { 348 const PassInfo *PI = getPassInfo(PassName); 349 return PI ? PI->getTypeInfo() : nullptr; 350 } 351 352 static std::pair<StringRef, unsigned> 353 getPassNameAndInstanceNum(StringRef PassName) { 354 StringRef Name, InstanceNumStr; 355 std::tie(Name, InstanceNumStr) = PassName.split(','); 356 357 unsigned InstanceNum = 0; 358 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum)) 359 report_fatal_error("invalid pass instance specifier " + PassName); 360 361 return std::make_pair(Name, InstanceNum); 362 } 363 364 void TargetPassConfig::setStartStopPasses() { 365 StringRef StartBeforeName; 366 std::tie(StartBeforeName, StartBeforeInstanceNum) = 367 getPassNameAndInstanceNum(StartBeforeOpt); 368 369 StringRef StartAfterName; 370 std::tie(StartAfterName, StartAfterInstanceNum) = 371 getPassNameAndInstanceNum(StartAfterOpt); 372 373 StringRef StopBeforeName; 374 std::tie(StopBeforeName, StopBeforeInstanceNum) 375 = getPassNameAndInstanceNum(StopBeforeOpt); 376 377 StringRef StopAfterName; 378 std::tie(StopAfterName, StopAfterInstanceNum) 379 = getPassNameAndInstanceNum(StopAfterOpt); 380 381 StartBefore = getPassIDFromName(StartBeforeName); 382 StartAfter = getPassIDFromName(StartAfterName); 383 StopBefore = getPassIDFromName(StopBeforeName); 384 StopAfter = getPassIDFromName(StopAfterName); 385 if (StartBefore && StartAfter) 386 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") + 387 Twine(StartAfterOptName) + Twine(" specified!")); 388 if (StopBefore && StopAfter) 389 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") + 390 Twine(StopAfterOptName) + Twine(" specified!")); 391 Started = (StartAfter == nullptr) && (StartBefore == nullptr); 392 } 393 394 // Out of line constructor provides default values for pass options and 395 // registers all common codegen passes. 396 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm) 397 : ImmutablePass(ID), PM(&pm), TM(&TM) { 398 Impl = new PassConfigImpl(); 399 400 // Register all target independent codegen passes to activate their PassIDs, 401 // including this pass itself. 402 initializeCodeGen(*PassRegistry::getPassRegistry()); 403 404 // Also register alias analysis passes required by codegen passes. 405 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry()); 406 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry()); 407 408 if (StringRef(PrintMachineInstrs.getValue()).equals("")) 409 TM.Options.PrintMachineCode = true; 410 411 if (EnableIPRA.getNumOccurrences()) 412 TM.Options.EnableIPRA = EnableIPRA; 413 else { 414 // If not explicitly specified, use target default. 415 TM.Options.EnableIPRA |= TM.useIPRA(); 416 } 417 418 if (TM.Options.EnableIPRA) 419 setRequiresCodeGenSCCOrder(); 420 421 if (EnableGlobalISelAbort.getNumOccurrences()) 422 TM.Options.GlobalISelAbort = EnableGlobalISelAbort; 423 424 setStartStopPasses(); 425 } 426 427 CodeGenOpt::Level TargetPassConfig::getOptLevel() const { 428 return TM->getOptLevel(); 429 } 430 431 /// Insert InsertedPassID pass after TargetPassID. 432 void TargetPassConfig::insertPass(AnalysisID TargetPassID, 433 IdentifyingPassPtr InsertedPassID, 434 bool VerifyAfter, bool PrintAfter) { 435 assert(((!InsertedPassID.isInstance() && 436 TargetPassID != InsertedPassID.getID()) || 437 (InsertedPassID.isInstance() && 438 TargetPassID != InsertedPassID.getInstance()->getPassID())) && 439 "Insert a pass after itself!"); 440 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter, 441 PrintAfter); 442 } 443 444 /// createPassConfig - Create a pass configuration object to be used by 445 /// addPassToEmitX methods for generating a pipeline of CodeGen passes. 446 /// 447 /// Targets may override this to extend TargetPassConfig. 448 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 449 return new TargetPassConfig(*this, PM); 450 } 451 452 TargetPassConfig::TargetPassConfig() 453 : ImmutablePass(ID) { 454 report_fatal_error("Trying to construct TargetPassConfig without a target " 455 "machine. Scheduling a CodeGen pass without a target " 456 "triple set?"); 457 } 458 459 bool TargetPassConfig::willCompleteCodeGenPipeline() { 460 return StopBeforeOpt.empty() && StopAfterOpt.empty(); 461 } 462 463 bool TargetPassConfig::hasLimitedCodeGenPipeline() { 464 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() || 465 !willCompleteCodeGenPipeline(); 466 } 467 468 std::string 469 TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const { 470 if (!hasLimitedCodeGenPipeline()) 471 return std::string(); 472 std::string Res; 473 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt, 474 &StopAfterOpt, &StopBeforeOpt}; 475 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName, 476 StopAfterOptName, StopBeforeOptName}; 477 bool IsFirst = true; 478 for (int Idx = 0; Idx < 4; ++Idx) 479 if (!PassNames[Idx]->empty()) { 480 if (!IsFirst) 481 Res += Separator; 482 IsFirst = false; 483 Res += OptNames[Idx]; 484 } 485 return Res; 486 } 487 488 // Helper to verify the analysis is really immutable. 489 void TargetPassConfig::setOpt(bool &Opt, bool Val) { 490 assert(!Initialized && "PassConfig is immutable"); 491 Opt = Val; 492 } 493 494 void TargetPassConfig::substitutePass(AnalysisID StandardID, 495 IdentifyingPassPtr TargetID) { 496 Impl->TargetPasses[StandardID] = TargetID; 497 } 498 499 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 500 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 501 I = Impl->TargetPasses.find(ID); 502 if (I == Impl->TargetPasses.end()) 503 return ID; 504 return I->second; 505 } 506 507 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const { 508 IdentifyingPassPtr TargetID = getPassSubstitution(ID); 509 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID); 510 return !FinalPtr.isValid() || FinalPtr.isInstance() || 511 FinalPtr.getID() != ID; 512 } 513 514 /// Add a pass to the PassManager if that pass is supposed to be run. If the 515 /// Started/Stopped flags indicate either that the compilation should start at 516 /// a later pass or that it should stop after an earlier pass, then do not add 517 /// the pass. Finally, compare the current pass against the StartAfter 518 /// and StopAfter options and change the Started/Stopped flags accordingly. 519 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) { 520 assert(!Initialized && "PassConfig is immutable"); 521 522 // Cache the Pass ID here in case the pass manager finds this pass is 523 // redundant with ones already scheduled / available, and deletes it. 524 // Fundamentally, once we add the pass to the manager, we no longer own it 525 // and shouldn't reference it. 526 AnalysisID PassID = P->getPassID(); 527 528 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum) 529 Started = true; 530 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum) 531 Stopped = true; 532 if (Started && !Stopped) { 533 std::string Banner; 534 // Construct banner message before PM->add() as that may delete the pass. 535 if (AddingMachinePasses && (printAfter || verifyAfter)) 536 Banner = std::string("After ") + std::string(P->getPassName()); 537 PM->add(P); 538 if (AddingMachinePasses) { 539 if (printAfter) 540 addPrintPass(Banner); 541 if (verifyAfter) 542 addVerifyPass(Banner); 543 } 544 545 // Add the passes after the pass P if there is any. 546 for (auto IP : Impl->InsertedPasses) { 547 if (IP.TargetPassID == PassID) 548 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter); 549 } 550 } else { 551 delete P; 552 } 553 554 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum) 555 Stopped = true; 556 557 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum) 558 Started = true; 559 if (Stopped && !Started) 560 report_fatal_error("Cannot stop compilation after pass that is not run"); 561 } 562 563 /// Add a CodeGen pass at this point in the pipeline after checking for target 564 /// and command line overrides. 565 /// 566 /// addPass cannot return a pointer to the pass instance because is internal the 567 /// PassManager and the instance we create here may already be freed. 568 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter, 569 bool printAfter) { 570 IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 571 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 572 if (!FinalPtr.isValid()) 573 return nullptr; 574 575 Pass *P; 576 if (FinalPtr.isInstance()) 577 P = FinalPtr.getInstance(); 578 else { 579 P = Pass::createPass(FinalPtr.getID()); 580 if (!P) 581 llvm_unreachable("Pass ID not registered"); 582 } 583 AnalysisID FinalID = P->getPassID(); 584 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P. 585 586 return FinalID; 587 } 588 589 void TargetPassConfig::printAndVerify(const std::string &Banner) { 590 addPrintPass(Banner); 591 addVerifyPass(Banner); 592 } 593 594 void TargetPassConfig::addPrintPass(const std::string &Banner) { 595 if (TM->shouldPrintMachineCode()) 596 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner)); 597 } 598 599 void TargetPassConfig::addVerifyPass(const std::string &Banner) { 600 bool Verify = VerifyMachineCode == cl::BOU_TRUE; 601 #ifdef EXPENSIVE_CHECKS 602 if (VerifyMachineCode == cl::BOU_UNSET) 603 Verify = TM->isMachineVerifierClean(); 604 #endif 605 if (Verify) 606 PM->add(createMachineVerifierPass(Banner)); 607 } 608 609 /// Add common target configurable passes that perform LLVM IR to IR transforms 610 /// following machine independent optimization. 611 void TargetPassConfig::addIRPasses() { 612 switch (UseCFLAA) { 613 case CFLAAType::Steensgaard: 614 addPass(createCFLSteensAAWrapperPass()); 615 break; 616 case CFLAAType::Andersen: 617 addPass(createCFLAndersAAWrapperPass()); 618 break; 619 case CFLAAType::Both: 620 addPass(createCFLAndersAAWrapperPass()); 621 addPass(createCFLSteensAAWrapperPass()); 622 break; 623 default: 624 break; 625 } 626 627 // Basic AliasAnalysis support. 628 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 629 // BasicAliasAnalysis wins if they disagree. This is intended to help 630 // support "obvious" type-punning idioms. 631 addPass(createTypeBasedAAWrapperPass()); 632 addPass(createScopedNoAliasAAWrapperPass()); 633 addPass(createBasicAAWrapperPass()); 634 635 // Before running any passes, run the verifier to determine if the input 636 // coming from the front-end and/or optimizer is valid. 637 if (!DisableVerify) 638 addPass(createVerifierPass()); 639 640 // Run loop strength reduction before anything else. 641 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 642 addPass(createLoopStrengthReducePass()); 643 if (PrintLSR) 644 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 645 } 646 647 if (getOptLevel() != CodeGenOpt::None) { 648 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of 649 // loads and compares. ExpandMemCmpPass then tries to expand those calls 650 // into optimally-sized loads and compares. The transforms are enabled by a 651 // target lowering hook. 652 if (!DisableMergeICmps) 653 addPass(createMergeICmpsLegacyPass()); 654 addPass(createExpandMemCmpPass()); 655 } 656 657 // Run GC lowering passes for builtin collectors 658 // TODO: add a pass insertion point here 659 addPass(createGCLoweringPass()); 660 addPass(createShadowStackGCLoweringPass()); 661 addPass(createLowerConstantIntrinsicsPass()); 662 663 // Make sure that no unreachable blocks are instruction selected. 664 addPass(createUnreachableBlockEliminationPass()); 665 666 // Prepare expensive constants for SelectionDAG. 667 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting) 668 addPass(createConstantHoistingPass()); 669 670 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining) 671 addPass(createPartiallyInlineLibCallsPass()); 672 673 // Instrument function entry and exit, e.g. with calls to mcount(). 674 addPass(createPostInlineEntryExitInstrumenterPass()); 675 676 // Add scalarization of target's unsupported masked memory intrinsics pass. 677 // the unsupported intrinsic will be replaced with a chain of basic blocks, 678 // that stores/loads element one-by-one if the appropriate mask bit is set. 679 addPass(createScalarizeMaskedMemIntrinPass()); 680 681 // Expand reduction intrinsics into shuffle sequences if the target wants to. 682 addPass(createExpandReductionsPass()); 683 } 684 685 /// Turn exception handling constructs into something the code generators can 686 /// handle. 687 void TargetPassConfig::addPassesToHandleExceptions() { 688 const MCAsmInfo *MCAI = TM->getMCAsmInfo(); 689 assert(MCAI && "No MCAsmInfo"); 690 switch (MCAI->getExceptionHandlingType()) { 691 case ExceptionHandling::SjLj: 692 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 693 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 694 // catch info can get misplaced when a selector ends up more than one block 695 // removed from the parent invoke(s). This could happen when a landing 696 // pad is shared by multiple invokes and is also a target of a normal 697 // edge from elsewhere. 698 addPass(createSjLjEHPreparePass()); 699 LLVM_FALLTHROUGH; 700 case ExceptionHandling::DwarfCFI: 701 case ExceptionHandling::ARM: 702 addPass(createDwarfEHPass()); 703 break; 704 case ExceptionHandling::WinEH: 705 // We support using both GCC-style and MSVC-style exceptions on Windows, so 706 // add both preparation passes. Each pass will only actually run if it 707 // recognizes the personality function. 708 addPass(createWinEHPass()); 709 addPass(createDwarfEHPass()); 710 break; 711 case ExceptionHandling::Wasm: 712 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs 713 // on catchpads and cleanuppads because it does not outline them into 714 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we 715 // should remove PHIs there. 716 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false)); 717 addPass(createWasmEHPass()); 718 break; 719 case ExceptionHandling::None: 720 addPass(createLowerInvokePass()); 721 722 // The lower invoke pass may create unreachable code. Remove it. 723 addPass(createUnreachableBlockEliminationPass()); 724 break; 725 } 726 } 727 728 /// Add pass to prepare the LLVM IR for code generation. This should be done 729 /// before exception handling preparation passes. 730 void TargetPassConfig::addCodeGenPrepare() { 731 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 732 addPass(createCodeGenPreparePass()); 733 addPass(createRewriteSymbolsPass()); 734 } 735 736 /// Add common passes that perform LLVM IR to IR transforms in preparation for 737 /// instruction selection. 738 void TargetPassConfig::addISelPrepare() { 739 addPreISel(); 740 741 // Force codegen to run according to the callgraph. 742 if (requiresCodeGenSCCOrder()) 743 addPass(new DummyCGSCCPass); 744 745 // Add both the safe stack and the stack protection passes: each of them will 746 // only protect functions that have corresponding attributes. 747 addPass(createSafeStackPass()); 748 addPass(createStackProtectorPass()); 749 750 if (PrintISelInput) 751 addPass(createPrintFunctionPass( 752 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n")); 753 754 // All passes which modify the LLVM IR are now complete; run the verifier 755 // to ensure that the IR is valid. 756 if (!DisableVerify) 757 addPass(createVerifierPass()); 758 } 759 760 bool TargetPassConfig::addCoreISelPasses() { 761 // Enable FastISel with -fast-isel, but allow that to be overridden. 762 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE); 763 764 // Determine an instruction selector. 765 enum class SelectorType { SelectionDAG, FastISel, GlobalISel }; 766 SelectorType Selector; 767 768 if (EnableFastISelOption == cl::BOU_TRUE) 769 Selector = SelectorType::FastISel; 770 else if (EnableGlobalISelOption == cl::BOU_TRUE || 771 (TM->Options.EnableGlobalISel && 772 EnableGlobalISelOption != cl::BOU_FALSE)) 773 Selector = SelectorType::GlobalISel; 774 else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()) 775 Selector = SelectorType::FastISel; 776 else 777 Selector = SelectorType::SelectionDAG; 778 779 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel. 780 if (Selector == SelectorType::FastISel) { 781 TM->setFastISel(true); 782 TM->setGlobalISel(false); 783 } else if (Selector == SelectorType::GlobalISel) { 784 TM->setFastISel(false); 785 TM->setGlobalISel(true); 786 } 787 788 // Add instruction selector passes. 789 if (Selector == SelectorType::GlobalISel) { 790 SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true); 791 if (addIRTranslator()) 792 return true; 793 794 addPreLegalizeMachineIR(); 795 796 if (addLegalizeMachineIR()) 797 return true; 798 799 // Before running the register bank selector, ask the target if it 800 // wants to run some passes. 801 addPreRegBankSelect(); 802 803 if (addRegBankSelect()) 804 return true; 805 806 addPreGlobalInstructionSelect(); 807 808 if (addGlobalInstructionSelect()) 809 return true; 810 811 // Pass to reset the MachineFunction if the ISel failed. 812 addPass(createResetMachineFunctionPass( 813 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled())); 814 815 // Provide a fallback path when we do not want to abort on 816 // not-yet-supported input. 817 if (!isGlobalISelAbortEnabled() && addInstSelector()) 818 return true; 819 820 } else if (addInstSelector()) 821 return true; 822 823 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before 824 // FinalizeISel. 825 addPass(&FinalizeISelID); 826 827 // Print the instruction selected machine code... 828 printAndVerify("After Instruction Selection"); 829 830 return false; 831 } 832 833 bool TargetPassConfig::addISelPasses() { 834 if (TM->useEmulatedTLS()) 835 addPass(createLowerEmuTLSPass()); 836 837 addPass(createPreISelIntrinsicLoweringPass()); 838 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis())); 839 addIRPasses(); 840 addCodeGenPrepare(); 841 addPassesToHandleExceptions(); 842 addISelPrepare(); 843 844 return addCoreISelPasses(); 845 } 846 847 /// -regalloc=... command line option. 848 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } 849 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 850 RegisterPassParser<RegisterRegAlloc>> 851 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), 852 cl::desc("Register allocator to use")); 853 854 /// Add the complete set of target-independent postISel code generator passes. 855 /// 856 /// This can be read as the standard order of major LLVM CodeGen stages. Stages 857 /// with nontrivial configuration or multiple passes are broken out below in 858 /// add%Stage routines. 859 /// 860 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The 861 /// addPre/Post methods with empty header implementations allow injecting 862 /// target-specific fixups just before or after major stages. Additionally, 863 /// targets have the flexibility to change pass order within a stage by 864 /// overriding default implementation of add%Stage routines below. Each 865 /// technique has maintainability tradeoffs because alternate pass orders are 866 /// not well supported. addPre/Post works better if the target pass is easily 867 /// tied to a common pass. But if it has subtle dependencies on multiple passes, 868 /// the target should override the stage instead. 869 /// 870 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 871 /// before/after any target-independent pass. But it's currently overkill. 872 void TargetPassConfig::addMachinePasses() { 873 AddingMachinePasses = true; 874 875 // Insert a machine instr printer pass after the specified pass. 876 StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue(); 877 if (!PrintMachineInstrsPassName.equals("") && 878 !PrintMachineInstrsPassName.equals("option-unspecified")) { 879 if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) { 880 const PassRegistry *PR = PassRegistry::getPassRegistry(); 881 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); 882 assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!"); 883 const char *TID = (const char *)(TPI->getTypeInfo()); 884 const char *IID = (const char *)(IPI->getTypeInfo()); 885 insertPass(TID, IID); 886 } 887 } 888 889 // Add passes that optimize machine instructions in SSA form. 890 if (getOptLevel() != CodeGenOpt::None) { 891 addMachineSSAOptimization(); 892 } else { 893 // If the target requests it, assign local variables to stack slots relative 894 // to one another and simplify frame index references where possible. 895 addPass(&LocalStackSlotAllocationID, false); 896 } 897 898 if (TM->Options.EnableIPRA) 899 addPass(createRegUsageInfoPropPass()); 900 901 // Run pre-ra passes. 902 addPreRegAlloc(); 903 904 // Run register allocation and passes that are tightly coupled with it, 905 // including phi elimination and scheduling. 906 if (getOptimizeRegAlloc()) 907 addOptimizedRegAlloc(); 908 else 909 addFastRegAlloc(); 910 911 // Run post-ra passes. 912 addPostRegAlloc(); 913 914 // Insert prolog/epilog code. Eliminate abstract frame index references... 915 if (getOptLevel() != CodeGenOpt::None) { 916 addPass(&PostRAMachineSinkingID); 917 addPass(&ShrinkWrapID); 918 } 919 920 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only 921 // do so if it hasn't been disabled, substituted, or overridden. 922 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID)) 923 addPass(createPrologEpilogInserterPass()); 924 925 /// Add passes that optimize machine instructions after register allocation. 926 if (getOptLevel() != CodeGenOpt::None) 927 addMachineLateOptimization(); 928 929 // Expand pseudo instructions before second scheduling pass. 930 addPass(&ExpandPostRAPseudosID); 931 932 // Run pre-sched2 passes. 933 addPreSched2(); 934 935 if (EnableImplicitNullChecks) 936 addPass(&ImplicitNullChecksID); 937 938 // Second pass scheduler. 939 // Let Target optionally insert this pass by itself at some other 940 // point. 941 if (getOptLevel() != CodeGenOpt::None && 942 !TM->targetSchedulesPostRAScheduling()) { 943 if (MISchedPostRA) 944 addPass(&PostMachineSchedulerID); 945 else 946 addPass(&PostRASchedulerID); 947 } 948 949 // GC 950 if (addGCPasses()) { 951 if (PrintGCInfo) 952 addPass(createGCInfoPrinter(dbgs()), false, false); 953 } 954 955 // Basic block placement. 956 if (getOptLevel() != CodeGenOpt::None) 957 addBlockPlacement(); 958 959 // Insert before XRay Instrumentation. 960 addPass(&FEntryInserterID, false); 961 962 addPass(&XRayInstrumentationID, false); 963 addPass(&PatchableFunctionID, false); 964 965 addPreEmitPass(); 966 967 if (TM->Options.EnableIPRA) 968 // Collect register usage information and produce a register mask of 969 // clobbered registers, to be used to optimize call sites. 970 addPass(createRegUsageInfoCollector()); 971 972 addPass(&FuncletLayoutID, false); 973 974 addPass(&StackMapLivenessID, false); 975 addPass(&LiveDebugValuesID, false); 976 977 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None && 978 EnableMachineOutliner != NeverOutline) { 979 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline); 980 bool AddOutliner = RunOnAllFunctions || 981 TM->Options.SupportsDefaultOutlining; 982 if (AddOutliner) 983 addPass(createMachineOutlinerPass(RunOnAllFunctions)); 984 } 985 986 // Add passes that directly emit MI after all other MI passes. 987 addPreEmitPass2(); 988 989 AddingMachinePasses = false; 990 } 991 992 /// Add passes that optimize machine instructions in SSA form. 993 void TargetPassConfig::addMachineSSAOptimization() { 994 // Pre-ra tail duplication. 995 addPass(&EarlyTailDuplicateID); 996 997 // Optimize PHIs before DCE: removing dead PHI cycles may make more 998 // instructions dead. 999 addPass(&OptimizePHIsID, false); 1000 1001 // This pass merges large allocas. StackSlotColoring is a different pass 1002 // which merges spill slots. 1003 addPass(&StackColoringID, false); 1004 1005 // If the target requests it, assign local variables to stack slots relative 1006 // to one another and simplify frame index references where possible. 1007 addPass(&LocalStackSlotAllocationID, false); 1008 1009 // With optimization, dead code should already be eliminated. However 1010 // there is one known exception: lowered code for arguments that are only 1011 // used by tail calls, where the tail calls reuse the incoming stack 1012 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 1013 addPass(&DeadMachineInstructionElimID); 1014 1015 // Allow targets to insert passes that improve instruction level parallelism, 1016 // like if-conversion. Such passes will typically need dominator trees and 1017 // loop info, just like LICM and CSE below. 1018 addILPOpts(); 1019 1020 addPass(&EarlyMachineLICMID, false); 1021 addPass(&MachineCSEID, false); 1022 1023 addPass(&MachineSinkingID); 1024 1025 addPass(&PeepholeOptimizerID); 1026 // Clean-up the dead code that may have been generated by peephole 1027 // rewriting. 1028 addPass(&DeadMachineInstructionElimID); 1029 } 1030 1031 //===---------------------------------------------------------------------===// 1032 /// Register Allocation Pass Configuration 1033 //===---------------------------------------------------------------------===// 1034 1035 bool TargetPassConfig::getOptimizeRegAlloc() const { 1036 switch (OptimizeRegAlloc) { 1037 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 1038 case cl::BOU_TRUE: return true; 1039 case cl::BOU_FALSE: return false; 1040 } 1041 llvm_unreachable("Invalid optimize-regalloc state"); 1042 } 1043 1044 /// A dummy default pass factory indicates whether the register allocator is 1045 /// overridden on the command line. 1046 static llvm::once_flag InitializeDefaultRegisterAllocatorFlag; 1047 1048 static RegisterRegAlloc 1049 defaultRegAlloc("default", 1050 "pick register allocator based on -O option", 1051 useDefaultRegisterAllocator); 1052 1053 static void initializeDefaultRegisterAllocatorOnce() { 1054 if (!RegisterRegAlloc::getDefault()) 1055 RegisterRegAlloc::setDefault(RegAlloc); 1056 } 1057 1058 /// Instantiate the default register allocator pass for this target for either 1059 /// the optimized or unoptimized allocation path. This will be added to the pass 1060 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 1061 /// in the optimized case. 1062 /// 1063 /// A target that uses the standard regalloc pass order for fast or optimized 1064 /// allocation may still override this for per-target regalloc 1065 /// selection. But -regalloc=... always takes precedence. 1066 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 1067 if (Optimized) 1068 return createGreedyRegisterAllocator(); 1069 else 1070 return createFastRegisterAllocator(); 1071 } 1072 1073 /// Find and instantiate the register allocation pass requested by this target 1074 /// at the current optimization level. Different register allocators are 1075 /// defined as separate passes because they may require different analysis. 1076 /// 1077 /// This helper ensures that the regalloc= option is always available, 1078 /// even for targets that override the default allocator. 1079 /// 1080 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 1081 /// this can be folded into addPass. 1082 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 1083 // Initialize the global default. 1084 llvm::call_once(InitializeDefaultRegisterAllocatorFlag, 1085 initializeDefaultRegisterAllocatorOnce); 1086 1087 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 1088 if (Ctor != useDefaultRegisterAllocator) 1089 return Ctor(); 1090 1091 // With no -regalloc= override, ask the target for a regalloc pass. 1092 return createTargetRegisterAllocator(Optimized); 1093 } 1094 1095 bool TargetPassConfig::addRegAssignmentFast() { 1096 if (RegAlloc != &useDefaultRegisterAllocator && 1097 RegAlloc != &createFastRegisterAllocator) 1098 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc."); 1099 1100 addPass(createRegAllocPass(false)); 1101 return true; 1102 } 1103 1104 bool TargetPassConfig::addRegAssignmentOptimized() { 1105 // Add the selected register allocation pass. 1106 addPass(createRegAllocPass(true)); 1107 1108 // Allow targets to change the register assignments before rewriting. 1109 addPreRewrite(); 1110 1111 // Finally rewrite virtual registers. 1112 addPass(&VirtRegRewriterID); 1113 // Perform stack slot coloring and post-ra machine LICM. 1114 // 1115 // FIXME: Re-enable coloring with register when it's capable of adding 1116 // kill markers. 1117 addPass(&StackSlotColoringID); 1118 1119 return true; 1120 } 1121 1122 /// Return true if the default global register allocator is in use and 1123 /// has not be overriden on the command line with '-regalloc=...' 1124 bool TargetPassConfig::usingDefaultRegAlloc() const { 1125 return RegAlloc.getNumOccurrences() == 0; 1126 } 1127 1128 /// Add the minimum set of target-independent passes that are required for 1129 /// register allocation. No coalescing or scheduling. 1130 void TargetPassConfig::addFastRegAlloc() { 1131 addPass(&PHIEliminationID, false); 1132 addPass(&TwoAddressInstructionPassID, false); 1133 1134 addRegAssignmentFast(); 1135 } 1136 1137 /// Add standard target-independent passes that are tightly coupled with 1138 /// optimized register allocation, including coalescing, machine instruction 1139 /// scheduling, and register allocation itself. 1140 void TargetPassConfig::addOptimizedRegAlloc() { 1141 addPass(&DetectDeadLanesID, false); 1142 1143 addPass(&ProcessImplicitDefsID, false); 1144 1145 // LiveVariables currently requires pure SSA form. 1146 // 1147 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 1148 // LiveVariables can be removed completely, and LiveIntervals can be directly 1149 // computed. (We still either need to regenerate kill flags after regalloc, or 1150 // preferably fix the scavenger to not depend on them). 1151 addPass(&LiveVariablesID, false); 1152 1153 // Edge splitting is smarter with machine loop info. 1154 addPass(&MachineLoopInfoID, false); 1155 addPass(&PHIEliminationID, false); 1156 1157 // Eventually, we want to run LiveIntervals before PHI elimination. 1158 if (EarlyLiveIntervals) 1159 addPass(&LiveIntervalsID, false); 1160 1161 addPass(&TwoAddressInstructionPassID, false); 1162 addPass(&RegisterCoalescerID); 1163 1164 // The machine scheduler may accidentally create disconnected components 1165 // when moving subregister definitions around, avoid this by splitting them to 1166 // separate vregs before. Splitting can also improve reg. allocation quality. 1167 addPass(&RenameIndependentSubregsID); 1168 1169 // PreRA instruction scheduling. 1170 addPass(&MachineSchedulerID); 1171 1172 if (addRegAssignmentOptimized()) { 1173 // Allow targets to expand pseudo instructions depending on the choice of 1174 // registers before MachineCopyPropagation. 1175 addPostRewrite(); 1176 1177 // Copy propagate to forward register uses and try to eliminate COPYs that 1178 // were not coalesced. 1179 addPass(&MachineCopyPropagationID); 1180 1181 // Run post-ra machine LICM to hoist reloads / remats. 1182 // 1183 // FIXME: can this move into MachineLateOptimization? 1184 addPass(&MachineLICMID); 1185 } 1186 } 1187 1188 //===---------------------------------------------------------------------===// 1189 /// Post RegAlloc Pass Configuration 1190 //===---------------------------------------------------------------------===// 1191 1192 /// Add passes that optimize machine instructions after register allocation. 1193 void TargetPassConfig::addMachineLateOptimization() { 1194 // Branch folding must be run after regalloc and prolog/epilog insertion. 1195 addPass(&BranchFolderPassID); 1196 1197 // Tail duplication. 1198 // Note that duplicating tail just increases code size and degrades 1199 // performance for targets that require Structured Control Flow. 1200 // In addition it can also make CFG irreducible. Thus we disable it. 1201 if (!TM->requiresStructuredCFG()) 1202 addPass(&TailDuplicateID); 1203 1204 // Copy propagation. 1205 addPass(&MachineCopyPropagationID); 1206 } 1207 1208 /// Add standard GC passes. 1209 bool TargetPassConfig::addGCPasses() { 1210 addPass(&GCMachineCodeAnalysisID, false); 1211 return true; 1212 } 1213 1214 /// Add standard basic block placement passes. 1215 void TargetPassConfig::addBlockPlacement() { 1216 if (addPass(&MachineBlockPlacementID)) { 1217 // Run a separate pass to collect block placement statistics. 1218 if (EnableBlockPlacementStats) 1219 addPass(&MachineBlockPlacementStatsID); 1220 } 1221 } 1222 1223 //===---------------------------------------------------------------------===// 1224 /// GlobalISel Configuration 1225 //===---------------------------------------------------------------------===// 1226 bool TargetPassConfig::isGlobalISelAbortEnabled() const { 1227 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable; 1228 } 1229 1230 bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const { 1231 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; 1232 } 1233 1234 bool TargetPassConfig::isGISelCSEEnabled() const { 1235 return true; 1236 } 1237 1238 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const { 1239 return std::make_unique<CSEConfigBase>(); 1240 } 1241