10b57cec5SDimitry Andric //===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // Implements the layout of a stack frame on the target machine. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 135ffd83dbSDimitry Andric #include "llvm/CodeGen/TargetFrameLowering.h" 140b57cec5SDimitry Andric #include "llvm/ADT/BitVector.h" 150b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFrameInfo.h" 160b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 180b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h" 200b57cec5SDimitry Andric #include "llvm/IR/Attributes.h" 210b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h" 220b57cec5SDimitry Andric #include "llvm/IR/Function.h" 235ffd83dbSDimitry Andric #include "llvm/IR/InstrTypes.h" 240b57cec5SDimitry Andric #include "llvm/MC/MCRegisterInfo.h" 250b57cec5SDimitry Andric #include "llvm/Support/Compiler.h" 260b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h" 270b57cec5SDimitry Andric #include "llvm/Target/TargetOptions.h" 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric using namespace llvm; 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric TargetFrameLowering::~TargetFrameLowering() = default; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric bool TargetFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const { 340b57cec5SDimitry Andric assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) && 350b57cec5SDimitry Andric MF.getFunction().hasFnAttribute(Attribute::NoUnwind) && 360b57cec5SDimitry Andric !MF.getFunction().hasFnAttribute(Attribute::UWTable)); 370b57cec5SDimitry Andric return false; 380b57cec5SDimitry Andric } 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric /// Returns the displacement from the frame register to the stack 410b57cec5SDimitry Andric /// frame of the specified index, along with the frame register used 420b57cec5SDimitry Andric /// (in output arg FrameReg). This is the default implementation which 430b57cec5SDimitry Andric /// is overridden for some targets. 44*e8d8bef9SDimitry Andric StackOffset 45*e8d8bef9SDimitry Andric TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 465ffd83dbSDimitry Andric Register &FrameReg) const { 470b57cec5SDimitry Andric const MachineFrameInfo &MFI = MF.getFrameInfo(); 480b57cec5SDimitry Andric const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 490b57cec5SDimitry Andric 500b57cec5SDimitry Andric // By default, assume all frame indices are referenced via whatever 510b57cec5SDimitry Andric // getFrameRegister() says. The target can override this if it's doing 520b57cec5SDimitry Andric // something different. 530b57cec5SDimitry Andric FrameReg = RI->getFrameRegister(MF); 540b57cec5SDimitry Andric 55*e8d8bef9SDimitry Andric return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - 56*e8d8bef9SDimitry Andric getOffsetOfLocalArea() + 57*e8d8bef9SDimitry Andric MFI.getOffsetAdjustment()); 580b57cec5SDimitry Andric } 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric bool TargetFrameLowering::needsFrameIndexResolution( 610b57cec5SDimitry Andric const MachineFunction &MF) const { 620b57cec5SDimitry Andric return MF.getFrameInfo().hasStackObjects(); 630b57cec5SDimitry Andric } 640b57cec5SDimitry Andric 65480093f4SDimitry Andric void TargetFrameLowering::getCalleeSaves(const MachineFunction &MF, 66480093f4SDimitry Andric BitVector &CalleeSaves) const { 67480093f4SDimitry Andric const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 68480093f4SDimitry Andric CalleeSaves.resize(TRI.getNumRegs()); 69480093f4SDimitry Andric 70480093f4SDimitry Andric const MachineFrameInfo &MFI = MF.getFrameInfo(); 71480093f4SDimitry Andric if (!MFI.isCalleeSavedInfoValid()) 72480093f4SDimitry Andric return; 73480093f4SDimitry Andric 74480093f4SDimitry Andric for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) 75480093f4SDimitry Andric CalleeSaves.set(Info.getReg()); 76480093f4SDimitry Andric } 77480093f4SDimitry Andric 780b57cec5SDimitry Andric void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF, 790b57cec5SDimitry Andric BitVector &SavedRegs, 800b57cec5SDimitry Andric RegScavenger *RS) const { 810b57cec5SDimitry Andric const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric // Resize before the early returns. Some backends expect that 840b57cec5SDimitry Andric // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no 850b57cec5SDimitry Andric // saved registers. 860b57cec5SDimitry Andric SavedRegs.resize(TRI.getNumRegs()); 870b57cec5SDimitry Andric 880b57cec5SDimitry Andric // When interprocedural register allocation is enabled caller saved registers 890b57cec5SDimitry Andric // are preferred over callee saved registers. 908bcb0991SDimitry Andric if (MF.getTarget().Options.EnableIPRA && 918bcb0991SDimitry Andric isSafeForNoCSROpt(MF.getFunction()) && 928bcb0991SDimitry Andric isProfitableForNoCSROpt(MF.getFunction())) 930b57cec5SDimitry Andric return; 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric // Get the callee saved register list... 960b57cec5SDimitry Andric const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric // Early exit if there are no callee saved registers. 990b57cec5SDimitry Andric if (!CSRegs || CSRegs[0] == 0) 1000b57cec5SDimitry Andric return; 1010b57cec5SDimitry Andric 1020b57cec5SDimitry Andric // In Naked functions we aren't going to save any registers. 1030b57cec5SDimitry Andric if (MF.getFunction().hasFnAttribute(Attribute::Naked)) 1040b57cec5SDimitry Andric return; 1050b57cec5SDimitry Andric 1060b57cec5SDimitry Andric // Noreturn+nounwind functions never restore CSR, so no saves are needed. 1070b57cec5SDimitry Andric // Purely noreturn functions may still return through throws, so those must 1080b57cec5SDimitry Andric // save CSR for caller exception handlers. 1090b57cec5SDimitry Andric // 1100b57cec5SDimitry Andric // If the function uses longjmp to break out of its current path of 1110b57cec5SDimitry Andric // execution we do not need the CSR spills either: setjmp stores all CSRs 1120b57cec5SDimitry Andric // it was called with into the jmp_buf, which longjmp then restores. 1130b57cec5SDimitry Andric if (MF.getFunction().hasFnAttribute(Attribute::NoReturn) && 1140b57cec5SDimitry Andric MF.getFunction().hasFnAttribute(Attribute::NoUnwind) && 1150b57cec5SDimitry Andric !MF.getFunction().hasFnAttribute(Attribute::UWTable) && 1160b57cec5SDimitry Andric enableCalleeSaveSkip(MF)) 1170b57cec5SDimitry Andric return; 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric // Functions which call __builtin_unwind_init get all their registers saved. 1200b57cec5SDimitry Andric bool CallsUnwindInit = MF.callsUnwindInit(); 1210b57cec5SDimitry Andric const MachineRegisterInfo &MRI = MF.getRegInfo(); 1220b57cec5SDimitry Andric for (unsigned i = 0; CSRegs[i]; ++i) { 1230b57cec5SDimitry Andric unsigned Reg = CSRegs[i]; 1240b57cec5SDimitry Andric if (CallsUnwindInit || MRI.isPhysRegModified(Reg)) 1250b57cec5SDimitry Andric SavedRegs.set(Reg); 1260b57cec5SDimitry Andric } 1270b57cec5SDimitry Andric } 1280b57cec5SDimitry Andric 1290b57cec5SDimitry Andric unsigned TargetFrameLowering::getStackAlignmentSkew( 1300b57cec5SDimitry Andric const MachineFunction &MF) const { 1310b57cec5SDimitry Andric // When HHVM function is called, the stack is skewed as the return address 1320b57cec5SDimitry Andric // is removed from the stack before we enter the function. 1330b57cec5SDimitry Andric if (LLVM_UNLIKELY(MF.getFunction().getCallingConv() == CallingConv::HHVM)) 1340b57cec5SDimitry Andric return MF.getTarget().getAllocaPointerSize(); 1350b57cec5SDimitry Andric 1360b57cec5SDimitry Andric return 0; 1370b57cec5SDimitry Andric } 1380b57cec5SDimitry Andric 1398bcb0991SDimitry Andric bool TargetFrameLowering::isSafeForNoCSROpt(const Function &F) { 1408bcb0991SDimitry Andric if (!F.hasLocalLinkage() || F.hasAddressTaken() || 1418bcb0991SDimitry Andric !F.hasFnAttribute(Attribute::NoRecurse)) 1428bcb0991SDimitry Andric return false; 1438bcb0991SDimitry Andric // Function should not be optimized as tail call. 1448bcb0991SDimitry Andric for (const User *U : F.users()) 1455ffd83dbSDimitry Andric if (auto *CB = dyn_cast<CallBase>(U)) 1465ffd83dbSDimitry Andric if (CB->isTailCall()) 1478bcb0991SDimitry Andric return false; 1488bcb0991SDimitry Andric return true; 1498bcb0991SDimitry Andric } 1508bcb0991SDimitry Andric 1510b57cec5SDimitry Andric int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const { 1520b57cec5SDimitry Andric llvm_unreachable("getInitialCFAOffset() not implemented!"); 1530b57cec5SDimitry Andric } 1540b57cec5SDimitry Andric 1555ffd83dbSDimitry Andric Register 1565ffd83dbSDimitry Andric TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) const { 1570b57cec5SDimitry Andric llvm_unreachable("getInitialCFARegister() not implemented!"); 1580b57cec5SDimitry Andric } 1595ffd83dbSDimitry Andric 1605ffd83dbSDimitry Andric TargetFrameLowering::DwarfFrameBase 1615ffd83dbSDimitry Andric TargetFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const { 1625ffd83dbSDimitry Andric const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 1635ffd83dbSDimitry Andric return DwarfFrameBase{DwarfFrameBase::Register, {RI->getFrameRegister(MF)}}; 1645ffd83dbSDimitry Andric } 165