xref: /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (revision 6966ac055c3b7a39266fb982493330df7a097997)
1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/TargetLowering.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/KnownBits.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include <cctype>
36 using namespace llvm;
37 
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40   : TargetLoweringBase(tm) {}
41 
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
43   return nullptr;
44 }
45 
46 bool TargetLowering::isPositionIndependent() const {
47   return getTargetMachine().isPositionIndependent();
48 }
49 
50 /// Check whether a given call node is in tail position within its function. If
51 /// so, it sets Chain to the input chain of the tail call.
52 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
53                                           SDValue &Chain) const {
54   const Function &F = DAG.getMachineFunction().getFunction();
55 
56   // Conservatively require the attributes of the call to match those of
57   // the return. Ignore NoAlias and NonNull because they don't affect the
58   // call sequence.
59   AttributeList CallerAttrs = F.getAttributes();
60   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
61           .removeAttribute(Attribute::NoAlias)
62           .removeAttribute(Attribute::NonNull)
63           .hasAttributes())
64     return false;
65 
66   // It's not safe to eliminate the sign / zero extension of the return value.
67   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
68       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
69     return false;
70 
71   // Check if the only use is a function return node.
72   return isUsedByReturnOnly(Node, Chain);
73 }
74 
75 bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
76     const uint32_t *CallerPreservedMask,
77     const SmallVectorImpl<CCValAssign> &ArgLocs,
78     const SmallVectorImpl<SDValue> &OutVals) const {
79   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
80     const CCValAssign &ArgLoc = ArgLocs[I];
81     if (!ArgLoc.isRegLoc())
82       continue;
83     unsigned Reg = ArgLoc.getLocReg();
84     // Only look at callee saved registers.
85     if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
86       continue;
87     // Check that we pass the value used for the caller.
88     // (We look for a CopyFromReg reading a virtual register that is used
89     //  for the function live-in value of register Reg)
90     SDValue Value = OutVals[I];
91     if (Value->getOpcode() != ISD::CopyFromReg)
92       return false;
93     unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
94     if (MRI.getLiveInPhysReg(ArgReg) != Reg)
95       return false;
96   }
97   return true;
98 }
99 
100 /// Set CallLoweringInfo attribute flags based on a call instruction
101 /// and called function attributes.
102 void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call,
103                                                      unsigned ArgIdx) {
104   IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt);
105   IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt);
106   IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg);
107   IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet);
108   IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest);
109   IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal);
110   IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca);
111   IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned);
112   IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
113   IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError);
114   Alignment = Call->getParamAlignment(ArgIdx);
115   ByValType = nullptr;
116   if (Call->paramHasAttr(ArgIdx, Attribute::ByVal))
117     ByValType = Call->getParamByValType(ArgIdx);
118 }
119 
120 /// Generate a libcall taking the given operands as arguments and returning a
121 /// result of type RetVT.
122 std::pair<SDValue, SDValue>
123 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
124                             ArrayRef<SDValue> Ops, bool isSigned,
125                             const SDLoc &dl, bool doesNotReturn,
126                             bool isReturnValueUsed,
127                             bool isPostTypeLegalization) const {
128   TargetLowering::ArgListTy Args;
129   Args.reserve(Ops.size());
130 
131   TargetLowering::ArgListEntry Entry;
132   for (SDValue Op : Ops) {
133     Entry.Node = Op;
134     Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
135     Entry.IsSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
136     Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
137     Args.push_back(Entry);
138   }
139 
140   if (LC == RTLIB::UNKNOWN_LIBCALL)
141     report_fatal_error("Unsupported library call operation!");
142   SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
143                                          getPointerTy(DAG.getDataLayout()));
144 
145   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
146   TargetLowering::CallLoweringInfo CLI(DAG);
147   bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
148   CLI.setDebugLoc(dl)
149       .setChain(DAG.getEntryNode())
150       .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
151       .setNoReturn(doesNotReturn)
152       .setDiscardResult(!isReturnValueUsed)
153       .setIsPostTypeLegalization(isPostTypeLegalization)
154       .setSExtResult(signExtend)
155       .setZExtResult(!signExtend);
156   return LowerCallTo(CLI);
157 }
158 
159 bool
160 TargetLowering::findOptimalMemOpLowering(std::vector<EVT> &MemOps,
161                                          unsigned Limit, uint64_t Size,
162                                          unsigned DstAlign, unsigned SrcAlign,
163                                          bool IsMemset,
164                                          bool ZeroMemset,
165                                          bool MemcpyStrSrc,
166                                          bool AllowOverlap,
167                                          unsigned DstAS, unsigned SrcAS,
168                                          const AttributeList &FuncAttributes) const {
169   // If 'SrcAlign' is zero, that means the memory operation does not need to
170   // load the value, i.e. memset or memcpy from constant string. Otherwise,
171   // it's the inferred alignment of the source. 'DstAlign', on the other hand,
172   // is the specified alignment of the memory operation. If it is zero, that
173   // means it's possible to change the alignment of the destination.
174   // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does
175   // not need to be loaded.
176   if (!(SrcAlign == 0 || SrcAlign >= DstAlign))
177     return false;
178 
179   EVT VT = getOptimalMemOpType(Size, DstAlign, SrcAlign,
180                                IsMemset, ZeroMemset, MemcpyStrSrc,
181                                FuncAttributes);
182 
183   if (VT == MVT::Other) {
184     // Use the largest integer type whose alignment constraints are satisfied.
185     // We only need to check DstAlign here as SrcAlign is always greater or
186     // equal to DstAlign (or zero).
187     VT = MVT::i64;
188     while (DstAlign && DstAlign < VT.getSizeInBits() / 8 &&
189            !allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign))
190       VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
191     assert(VT.isInteger());
192 
193     // Find the largest legal integer type.
194     MVT LVT = MVT::i64;
195     while (!isTypeLegal(LVT))
196       LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1);
197     assert(LVT.isInteger());
198 
199     // If the type we've chosen is larger than the largest legal integer type
200     // then use that instead.
201     if (VT.bitsGT(LVT))
202       VT = LVT;
203   }
204 
205   unsigned NumMemOps = 0;
206   while (Size != 0) {
207     unsigned VTSize = VT.getSizeInBits() / 8;
208     while (VTSize > Size) {
209       // For now, only use non-vector load / store's for the left-over pieces.
210       EVT NewVT = VT;
211       unsigned NewVTSize;
212 
213       bool Found = false;
214       if (VT.isVector() || VT.isFloatingPoint()) {
215         NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32;
216         if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
217             isSafeMemOpType(NewVT.getSimpleVT()))
218           Found = true;
219         else if (NewVT == MVT::i64 &&
220                  isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
221                  isSafeMemOpType(MVT::f64)) {
222           // i64 is usually not legal on 32-bit targets, but f64 may be.
223           NewVT = MVT::f64;
224           Found = true;
225         }
226       }
227 
228       if (!Found) {
229         do {
230           NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1);
231           if (NewVT == MVT::i8)
232             break;
233         } while (!isSafeMemOpType(NewVT.getSimpleVT()));
234       }
235       NewVTSize = NewVT.getSizeInBits() / 8;
236 
237       // If the new VT cannot cover all of the remaining bits, then consider
238       // issuing a (or a pair of) unaligned and overlapping load / store.
239       bool Fast;
240       if (NumMemOps && AllowOverlap && NewVTSize < Size &&
241           allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign,
242                                          MachineMemOperand::MONone, &Fast) &&
243           Fast)
244         VTSize = Size;
245       else {
246         VT = NewVT;
247         VTSize = NewVTSize;
248       }
249     }
250 
251     if (++NumMemOps > Limit)
252       return false;
253 
254     MemOps.push_back(VT);
255     Size -= VTSize;
256   }
257 
258   return true;
259 }
260 
261 /// Soften the operands of a comparison. This code is shared among BR_CC,
262 /// SELECT_CC, and SETCC handlers.
263 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
264                                          SDValue &NewLHS, SDValue &NewRHS,
265                                          ISD::CondCode &CCCode,
266                                          const SDLoc &dl) const {
267   assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
268          && "Unsupported setcc type!");
269 
270   // Expand into one or more soft-fp libcall(s).
271   RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
272   bool ShouldInvertCC = false;
273   switch (CCCode) {
274   case ISD::SETEQ:
275   case ISD::SETOEQ:
276     LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
277           (VT == MVT::f64) ? RTLIB::OEQ_F64 :
278           (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
279     break;
280   case ISD::SETNE:
281   case ISD::SETUNE:
282     LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
283           (VT == MVT::f64) ? RTLIB::UNE_F64 :
284           (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
285     break;
286   case ISD::SETGE:
287   case ISD::SETOGE:
288     LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
289           (VT == MVT::f64) ? RTLIB::OGE_F64 :
290           (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
291     break;
292   case ISD::SETLT:
293   case ISD::SETOLT:
294     LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
295           (VT == MVT::f64) ? RTLIB::OLT_F64 :
296           (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
297     break;
298   case ISD::SETLE:
299   case ISD::SETOLE:
300     LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
301           (VT == MVT::f64) ? RTLIB::OLE_F64 :
302           (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
303     break;
304   case ISD::SETGT:
305   case ISD::SETOGT:
306     LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
307           (VT == MVT::f64) ? RTLIB::OGT_F64 :
308           (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
309     break;
310   case ISD::SETUO:
311     LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
312           (VT == MVT::f64) ? RTLIB::UO_F64 :
313           (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
314     break;
315   case ISD::SETO:
316     LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
317           (VT == MVT::f64) ? RTLIB::O_F64 :
318           (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
319     break;
320   case ISD::SETONE:
321     // SETONE = SETOLT | SETOGT
322     LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
323           (VT == MVT::f64) ? RTLIB::OLT_F64 :
324           (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
325     LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
326           (VT == MVT::f64) ? RTLIB::OGT_F64 :
327           (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
328     break;
329   case ISD::SETUEQ:
330     LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
331           (VT == MVT::f64) ? RTLIB::UO_F64 :
332           (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
333     LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
334           (VT == MVT::f64) ? RTLIB::OEQ_F64 :
335           (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
336     break;
337   default:
338     // Invert CC for unordered comparisons
339     ShouldInvertCC = true;
340     switch (CCCode) {
341     case ISD::SETULT:
342       LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
343             (VT == MVT::f64) ? RTLIB::OGE_F64 :
344             (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
345       break;
346     case ISD::SETULE:
347       LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
348             (VT == MVT::f64) ? RTLIB::OGT_F64 :
349             (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
350       break;
351     case ISD::SETUGT:
352       LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
353             (VT == MVT::f64) ? RTLIB::OLE_F64 :
354             (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
355       break;
356     case ISD::SETUGE:
357       LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
358             (VT == MVT::f64) ? RTLIB::OLT_F64 :
359             (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
360       break;
361     default: llvm_unreachable("Do not know how to soften this setcc!");
362     }
363   }
364 
365   // Use the target specific return value for comparions lib calls.
366   EVT RetVT = getCmpLibcallReturnType();
367   SDValue Ops[2] = {NewLHS, NewRHS};
368   NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/,
369                        dl).first;
370   NewRHS = DAG.getConstant(0, dl, RetVT);
371 
372   CCCode = getCmpLibcallCC(LC1);
373   if (ShouldInvertCC)
374     CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
375 
376   if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
377     SDValue Tmp = DAG.getNode(
378         ISD::SETCC, dl,
379         getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
380         NewLHS, NewRHS, DAG.getCondCode(CCCode));
381     NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/,
382                          dl).first;
383     NewLHS = DAG.getNode(
384         ISD::SETCC, dl,
385         getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
386         NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
387     NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
388     NewRHS = SDValue();
389   }
390 }
391 
392 /// Return the entry encoding for a jump table in the current function. The
393 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
394 unsigned TargetLowering::getJumpTableEncoding() const {
395   // In non-pic modes, just use the address of a block.
396   if (!isPositionIndependent())
397     return MachineJumpTableInfo::EK_BlockAddress;
398 
399   // In PIC mode, if the target supports a GPRel32 directive, use it.
400   if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
401     return MachineJumpTableInfo::EK_GPRel32BlockAddress;
402 
403   // Otherwise, use a label difference.
404   return MachineJumpTableInfo::EK_LabelDifference32;
405 }
406 
407 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
408                                                  SelectionDAG &DAG) const {
409   // If our PIC model is GP relative, use the global offset table as the base.
410   unsigned JTEncoding = getJumpTableEncoding();
411 
412   if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
413       (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
414     return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
415 
416   return Table;
417 }
418 
419 /// This returns the relocation base for the given PIC jumptable, the same as
420 /// getPICJumpTableRelocBase, but as an MCExpr.
421 const MCExpr *
422 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
423                                              unsigned JTI,MCContext &Ctx) const{
424   // The normal PIC reloc base is the label at the start of the jump table.
425   return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
426 }
427 
428 bool
429 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
430   const TargetMachine &TM = getTargetMachine();
431   const GlobalValue *GV = GA->getGlobal();
432 
433   // If the address is not even local to this DSO we will have to load it from
434   // a got and then add the offset.
435   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
436     return false;
437 
438   // If the code is position independent we will have to add a base register.
439   if (isPositionIndependent())
440     return false;
441 
442   // Otherwise we can do it.
443   return true;
444 }
445 
446 //===----------------------------------------------------------------------===//
447 //  Optimization Methods
448 //===----------------------------------------------------------------------===//
449 
450 /// If the specified instruction has a constant integer operand and there are
451 /// bits set in that constant that are not demanded, then clear those bits and
452 /// return true.
453 bool TargetLowering::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
454                                             TargetLoweringOpt &TLO) const {
455   SDLoc DL(Op);
456   unsigned Opcode = Op.getOpcode();
457 
458   // Do target-specific constant optimization.
459   if (targetShrinkDemandedConstant(Op, Demanded, TLO))
460     return TLO.New.getNode();
461 
462   // FIXME: ISD::SELECT, ISD::SELECT_CC
463   switch (Opcode) {
464   default:
465     break;
466   case ISD::XOR:
467   case ISD::AND:
468   case ISD::OR: {
469     auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
470     if (!Op1C)
471       return false;
472 
473     // If this is a 'not' op, don't touch it because that's a canonical form.
474     const APInt &C = Op1C->getAPIntValue();
475     if (Opcode == ISD::XOR && Demanded.isSubsetOf(C))
476       return false;
477 
478     if (!C.isSubsetOf(Demanded)) {
479       EVT VT = Op.getValueType();
480       SDValue NewC = TLO.DAG.getConstant(Demanded & C, DL, VT);
481       SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
482       return TLO.CombineTo(Op, NewOp);
483     }
484 
485     break;
486   }
487   }
488 
489   return false;
490 }
491 
492 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
493 /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
494 /// generalized for targets with other types of implicit widening casts.
495 bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
496                                       const APInt &Demanded,
497                                       TargetLoweringOpt &TLO) const {
498   assert(Op.getNumOperands() == 2 &&
499          "ShrinkDemandedOp only supports binary operators!");
500   assert(Op.getNode()->getNumValues() == 1 &&
501          "ShrinkDemandedOp only supports nodes with one result!");
502 
503   SelectionDAG &DAG = TLO.DAG;
504   SDLoc dl(Op);
505 
506   // Early return, as this function cannot handle vector types.
507   if (Op.getValueType().isVector())
508     return false;
509 
510   // Don't do this if the node has another user, which may require the
511   // full value.
512   if (!Op.getNode()->hasOneUse())
513     return false;
514 
515   // Search for the smallest integer type with free casts to and from
516   // Op's type. For expedience, just check power-of-2 integer types.
517   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
518   unsigned DemandedSize = Demanded.getActiveBits();
519   unsigned SmallVTBits = DemandedSize;
520   if (!isPowerOf2_32(SmallVTBits))
521     SmallVTBits = NextPowerOf2(SmallVTBits);
522   for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
523     EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
524     if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
525         TLI.isZExtFree(SmallVT, Op.getValueType())) {
526       // We found a type with free casts.
527       SDValue X = DAG.getNode(
528           Op.getOpcode(), dl, SmallVT,
529           DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
530           DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
531       assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
532       SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
533       return TLO.CombineTo(Op, Z);
534     }
535   }
536   return false;
537 }
538 
539 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
540                                           DAGCombinerInfo &DCI) const {
541   SelectionDAG &DAG = DCI.DAG;
542   TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
543                         !DCI.isBeforeLegalizeOps());
544   KnownBits Known;
545 
546   bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO);
547   if (Simplified) {
548     DCI.AddToWorklist(Op.getNode());
549     DCI.CommitTargetLoweringOpt(TLO);
550   }
551   return Simplified;
552 }
553 
554 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
555                                           KnownBits &Known,
556                                           TargetLoweringOpt &TLO,
557                                           unsigned Depth,
558                                           bool AssumeSingleUse) const {
559   EVT VT = Op.getValueType();
560   APInt DemandedElts = VT.isVector()
561                            ? APInt::getAllOnesValue(VT.getVectorNumElements())
562                            : APInt(1, 1);
563   return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
564                               AssumeSingleUse);
565 }
566 
567 /// Look at Op. At this point, we know that only the OriginalDemandedBits of the
568 /// result of Op are ever used downstream. If we can use this information to
569 /// simplify Op, create a new simplified DAG node and return true, returning the
570 /// original and new nodes in Old and New. Otherwise, analyze the expression and
571 /// return a mask of Known bits for the expression (used to simplify the
572 /// caller).  The Known bits may only be accurate for those bits in the
573 /// OriginalDemandedBits and OriginalDemandedElts.
574 bool TargetLowering::SimplifyDemandedBits(
575     SDValue Op, const APInt &OriginalDemandedBits,
576     const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
577     unsigned Depth, bool AssumeSingleUse) const {
578   unsigned BitWidth = OriginalDemandedBits.getBitWidth();
579   assert(Op.getScalarValueSizeInBits() == BitWidth &&
580          "Mask size mismatches value type size!");
581 
582   unsigned NumElts = OriginalDemandedElts.getBitWidth();
583   assert((!Op.getValueType().isVector() ||
584           NumElts == Op.getValueType().getVectorNumElements()) &&
585          "Unexpected vector size");
586 
587   APInt DemandedBits = OriginalDemandedBits;
588   APInt DemandedElts = OriginalDemandedElts;
589   SDLoc dl(Op);
590   auto &DL = TLO.DAG.getDataLayout();
591 
592   // Don't know anything.
593   Known = KnownBits(BitWidth);
594 
595   // Undef operand.
596   if (Op.isUndef())
597     return false;
598 
599   if (Op.getOpcode() == ISD::Constant) {
600     // We know all of the bits for a constant!
601     Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
602     Known.Zero = ~Known.One;
603     return false;
604   }
605 
606   // Other users may use these bits.
607   EVT VT = Op.getValueType();
608   if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
609     if (Depth != 0) {
610       // If not at the root, Just compute the Known bits to
611       // simplify things downstream.
612       Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
613       return false;
614     }
615     // If this is the root being simplified, allow it to have multiple uses,
616     // just set the DemandedBits/Elts to all bits.
617     DemandedBits = APInt::getAllOnesValue(BitWidth);
618     DemandedElts = APInt::getAllOnesValue(NumElts);
619   } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) {
620     // Not demanding any bits/elts from Op.
621     return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
622   } else if (Depth == 6) { // Limit search depth.
623     return false;
624   }
625 
626   KnownBits Known2, KnownOut;
627   switch (Op.getOpcode()) {
628   case ISD::SCALAR_TO_VECTOR: {
629     if (!DemandedElts[0])
630       return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
631 
632     KnownBits SrcKnown;
633     SDValue Src = Op.getOperand(0);
634     unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
635     APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth);
636     if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1))
637       return true;
638     Known = SrcKnown.zextOrTrunc(BitWidth, false);
639     break;
640   }
641   case ISD::BUILD_VECTOR:
642     // Collect the known bits that are shared by every demanded element.
643     // TODO: Call SimplifyDemandedBits for non-constant demanded elements.
644     Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
645     return false; // Don't fall through, will infinitely loop.
646   case ISD::LOAD: {
647     LoadSDNode *LD = cast<LoadSDNode>(Op);
648     if (getTargetConstantFromLoad(LD)) {
649       Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
650       return false; // Don't fall through, will infinitely loop.
651     }
652     break;
653   }
654   case ISD::INSERT_VECTOR_ELT: {
655     SDValue Vec = Op.getOperand(0);
656     SDValue Scl = Op.getOperand(1);
657     auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
658     EVT VecVT = Vec.getValueType();
659 
660     // If index isn't constant, assume we need all vector elements AND the
661     // inserted element.
662     APInt DemandedVecElts(DemandedElts);
663     if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) {
664       unsigned Idx = CIdx->getZExtValue();
665       DemandedVecElts.clearBit(Idx);
666 
667       // Inserted element is not required.
668       if (!DemandedElts[Idx])
669         return TLO.CombineTo(Op, Vec);
670     }
671 
672     KnownBits KnownScl;
673     unsigned NumSclBits = Scl.getScalarValueSizeInBits();
674     APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits);
675     if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
676       return true;
677 
678     Known = KnownScl.zextOrTrunc(BitWidth, false);
679 
680     KnownBits KnownVec;
681     if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO,
682                              Depth + 1))
683       return true;
684 
685     if (!!DemandedVecElts) {
686       Known.One &= KnownVec.One;
687       Known.Zero &= KnownVec.Zero;
688     }
689 
690     return false;
691   }
692   case ISD::INSERT_SUBVECTOR: {
693     SDValue Base = Op.getOperand(0);
694     SDValue Sub = Op.getOperand(1);
695     EVT SubVT = Sub.getValueType();
696     unsigned NumSubElts = SubVT.getVectorNumElements();
697 
698     // If index isn't constant, assume we need the original demanded base
699     // elements and ALL the inserted subvector elements.
700     APInt BaseElts = DemandedElts;
701     APInt SubElts = APInt::getAllOnesValue(NumSubElts);
702     if (isa<ConstantSDNode>(Op.getOperand(2))) {
703       const APInt &Idx = Op.getConstantOperandAPInt(2);
704       if (Idx.ule(NumElts - NumSubElts)) {
705         unsigned SubIdx = Idx.getZExtValue();
706         SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
707         BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
708       }
709     }
710 
711     KnownBits KnownSub, KnownBase;
712     if (SimplifyDemandedBits(Sub, DemandedBits, SubElts, KnownSub, TLO,
713                              Depth + 1))
714       return true;
715     if (SimplifyDemandedBits(Base, DemandedBits, BaseElts, KnownBase, TLO,
716                              Depth + 1))
717       return true;
718 
719     Known.Zero.setAllBits();
720     Known.One.setAllBits();
721     if (!!SubElts) {
722         Known.One &= KnownSub.One;
723         Known.Zero &= KnownSub.Zero;
724     }
725     if (!!BaseElts) {
726         Known.One &= KnownBase.One;
727         Known.Zero &= KnownBase.Zero;
728     }
729     break;
730   }
731   case ISD::CONCAT_VECTORS: {
732     Known.Zero.setAllBits();
733     Known.One.setAllBits();
734     EVT SubVT = Op.getOperand(0).getValueType();
735     unsigned NumSubVecs = Op.getNumOperands();
736     unsigned NumSubElts = SubVT.getVectorNumElements();
737     for (unsigned i = 0; i != NumSubVecs; ++i) {
738       APInt DemandedSubElts =
739           DemandedElts.extractBits(NumSubElts, i * NumSubElts);
740       if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts,
741                                Known2, TLO, Depth + 1))
742         return true;
743       // Known bits are shared by every demanded subvector element.
744       if (!!DemandedSubElts) {
745         Known.One &= Known2.One;
746         Known.Zero &= Known2.Zero;
747       }
748     }
749     break;
750   }
751   case ISD::VECTOR_SHUFFLE: {
752     ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
753 
754     // Collect demanded elements from shuffle operands..
755     APInt DemandedLHS(NumElts, 0);
756     APInt DemandedRHS(NumElts, 0);
757     for (unsigned i = 0; i != NumElts; ++i) {
758       if (!DemandedElts[i])
759         continue;
760       int M = ShuffleMask[i];
761       if (M < 0) {
762         // For UNDEF elements, we don't know anything about the common state of
763         // the shuffle result.
764         DemandedLHS.clearAllBits();
765         DemandedRHS.clearAllBits();
766         break;
767       }
768       assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
769       if (M < (int)NumElts)
770         DemandedLHS.setBit(M);
771       else
772         DemandedRHS.setBit(M - NumElts);
773     }
774 
775     if (!!DemandedLHS || !!DemandedRHS) {
776       Known.Zero.setAllBits();
777       Known.One.setAllBits();
778       if (!!DemandedLHS) {
779         if (SimplifyDemandedBits(Op.getOperand(0), DemandedBits, DemandedLHS,
780                                  Known2, TLO, Depth + 1))
781           return true;
782         Known.One &= Known2.One;
783         Known.Zero &= Known2.Zero;
784       }
785       if (!!DemandedRHS) {
786         if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedRHS,
787                                  Known2, TLO, Depth + 1))
788           return true;
789         Known.One &= Known2.One;
790         Known.Zero &= Known2.Zero;
791       }
792     }
793     break;
794   }
795   case ISD::AND: {
796     SDValue Op0 = Op.getOperand(0);
797     SDValue Op1 = Op.getOperand(1);
798 
799     // If the RHS is a constant, check to see if the LHS would be zero without
800     // using the bits from the RHS.  Below, we use knowledge about the RHS to
801     // simplify the LHS, here we're using information from the LHS to simplify
802     // the RHS.
803     if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) {
804       // Do not increment Depth here; that can cause an infinite loop.
805       KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
806       // If the LHS already has zeros where RHSC does, this 'and' is dead.
807       if ((LHSKnown.Zero & DemandedBits) ==
808           (~RHSC->getAPIntValue() & DemandedBits))
809         return TLO.CombineTo(Op, Op0);
810 
811       // If any of the set bits in the RHS are known zero on the LHS, shrink
812       // the constant.
813       if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, TLO))
814         return true;
815 
816       // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
817       // constant, but if this 'and' is only clearing bits that were just set by
818       // the xor, then this 'and' can be eliminated by shrinking the mask of
819       // the xor. For example, for a 32-bit X:
820       // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
821       if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
822           LHSKnown.One == ~RHSC->getAPIntValue()) {
823         SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1);
824         return TLO.CombineTo(Op, Xor);
825       }
826     }
827 
828     if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
829                              Depth + 1))
830       return true;
831     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
832     if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
833                              Known2, TLO, Depth + 1))
834       return true;
835     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
836 
837     // If all of the demanded bits are known one on one side, return the other.
838     // These bits cannot contribute to the result of the 'and'.
839     if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
840       return TLO.CombineTo(Op, Op0);
841     if (DemandedBits.isSubsetOf(Known.Zero | Known2.One))
842       return TLO.CombineTo(Op, Op1);
843     // If all of the demanded bits in the inputs are known zeros, return zero.
844     if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
845       return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT));
846     // If the RHS is a constant, see if we can simplify it.
847     if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, TLO))
848       return true;
849     // If the operation can be done in a smaller type, do so.
850     if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
851       return true;
852 
853     // Output known-1 bits are only known if set in both the LHS & RHS.
854     Known.One &= Known2.One;
855     // Output known-0 are known to be clear if zero in either the LHS | RHS.
856     Known.Zero |= Known2.Zero;
857     break;
858   }
859   case ISD::OR: {
860     SDValue Op0 = Op.getOperand(0);
861     SDValue Op1 = Op.getOperand(1);
862 
863     if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
864                              Depth + 1))
865       return true;
866     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
867     if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
868                              Known2, TLO, Depth + 1))
869       return true;
870     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
871 
872     // If all of the demanded bits are known zero on one side, return the other.
873     // These bits cannot contribute to the result of the 'or'.
874     if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
875       return TLO.CombineTo(Op, Op0);
876     if (DemandedBits.isSubsetOf(Known.One | Known2.Zero))
877       return TLO.CombineTo(Op, Op1);
878     // If the RHS is a constant, see if we can simplify it.
879     if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
880       return true;
881     // If the operation can be done in a smaller type, do so.
882     if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
883       return true;
884 
885     // Output known-0 bits are only known if clear in both the LHS & RHS.
886     Known.Zero &= Known2.Zero;
887     // Output known-1 are known to be set if set in either the LHS | RHS.
888     Known.One |= Known2.One;
889     break;
890   }
891   case ISD::XOR: {
892     SDValue Op0 = Op.getOperand(0);
893     SDValue Op1 = Op.getOperand(1);
894 
895     if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
896                              Depth + 1))
897       return true;
898     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
899     if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
900                              Depth + 1))
901       return true;
902     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
903 
904     // If all of the demanded bits are known zero on one side, return the other.
905     // These bits cannot contribute to the result of the 'xor'.
906     if (DemandedBits.isSubsetOf(Known.Zero))
907       return TLO.CombineTo(Op, Op0);
908     if (DemandedBits.isSubsetOf(Known2.Zero))
909       return TLO.CombineTo(Op, Op1);
910     // If the operation can be done in a smaller type, do so.
911     if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
912       return true;
913 
914     // If all of the unknown bits are known to be zero on one side or the other
915     // (but not both) turn this into an *inclusive* or.
916     //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
917     if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
918       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
919 
920     // Output known-0 bits are known if clear or set in both the LHS & RHS.
921     KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
922     // Output known-1 are known to be set if set in only one of the LHS, RHS.
923     KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
924 
925     if (ConstantSDNode *C = isConstOrConstSplat(Op1)) {
926       // If one side is a constant, and all of the known set bits on the other
927       // side are also set in the constant, turn this into an AND, as we know
928       // the bits will be cleared.
929       //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
930       // NB: it is okay if more bits are known than are requested
931       if (C->getAPIntValue() == Known2.One) {
932         SDValue ANDC =
933             TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT);
934         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
935       }
936 
937       // If the RHS is a constant, see if we can change it. Don't alter a -1
938       // constant because that's a 'not' op, and that is better for combining
939       // and codegen.
940       if (!C->isAllOnesValue()) {
941         if (DemandedBits.isSubsetOf(C->getAPIntValue())) {
942           // We're flipping all demanded bits. Flip the undemanded bits too.
943           SDValue New = TLO.DAG.getNOT(dl, Op0, VT);
944           return TLO.CombineTo(Op, New);
945         }
946         // If we can't turn this into a 'not', try to shrink the constant.
947         if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
948           return true;
949       }
950     }
951 
952     Known = std::move(KnownOut);
953     break;
954   }
955   case ISD::SELECT:
956     if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO,
957                              Depth + 1))
958       return true;
959     if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO,
960                              Depth + 1))
961       return true;
962     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
963     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
964 
965     // If the operands are constants, see if we can simplify them.
966     if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
967       return true;
968 
969     // Only known if known in both the LHS and RHS.
970     Known.One &= Known2.One;
971     Known.Zero &= Known2.Zero;
972     break;
973   case ISD::SELECT_CC:
974     if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO,
975                              Depth + 1))
976       return true;
977     if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO,
978                              Depth + 1))
979       return true;
980     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
981     assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
982 
983     // If the operands are constants, see if we can simplify them.
984     if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
985       return true;
986 
987     // Only known if known in both the LHS and RHS.
988     Known.One &= Known2.One;
989     Known.Zero &= Known2.Zero;
990     break;
991   case ISD::SETCC: {
992     SDValue Op0 = Op.getOperand(0);
993     SDValue Op1 = Op.getOperand(1);
994     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
995     // If (1) we only need the sign-bit, (2) the setcc operands are the same
996     // width as the setcc result, and (3) the result of a setcc conforms to 0 or
997     // -1, we may be able to bypass the setcc.
998     if (DemandedBits.isSignMask() &&
999         Op0.getScalarValueSizeInBits() == BitWidth &&
1000         getBooleanContents(VT) ==
1001             BooleanContent::ZeroOrNegativeOneBooleanContent) {
1002       // If we're testing X < 0, then this compare isn't needed - just use X!
1003       // FIXME: We're limiting to integer types here, but this should also work
1004       // if we don't care about FP signed-zero. The use of SETLT with FP means
1005       // that we don't care about NaNs.
1006       if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
1007           (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
1008         return TLO.CombineTo(Op, Op0);
1009 
1010       // TODO: Should we check for other forms of sign-bit comparisons?
1011       // Examples: X <= -1, X >= 0
1012     }
1013     if (getBooleanContents(Op0.getValueType()) ==
1014             TargetLowering::ZeroOrOneBooleanContent &&
1015         BitWidth > 1)
1016       Known.Zero.setBitsFrom(1);
1017     break;
1018   }
1019   case ISD::SHL: {
1020     SDValue Op0 = Op.getOperand(0);
1021     SDValue Op1 = Op.getOperand(1);
1022 
1023     if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1024       // If the shift count is an invalid immediate, don't do anything.
1025       if (SA->getAPIntValue().uge(BitWidth))
1026         break;
1027 
1028       unsigned ShAmt = SA->getZExtValue();
1029       if (ShAmt == 0)
1030         return TLO.CombineTo(Op, Op0);
1031 
1032       // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1033       // single shift.  We can do this if the bottom bits (which are shifted
1034       // out) are never demanded.
1035       // TODO - support non-uniform vector amounts.
1036       if (Op0.getOpcode() == ISD::SRL) {
1037         if ((DemandedBits & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1038           if (ConstantSDNode *SA2 =
1039                   isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1040             if (SA2->getAPIntValue().ult(BitWidth)) {
1041               unsigned C1 = SA2->getZExtValue();
1042               unsigned Opc = ISD::SHL;
1043               int Diff = ShAmt - C1;
1044               if (Diff < 0) {
1045                 Diff = -Diff;
1046                 Opc = ISD::SRL;
1047               }
1048 
1049               SDValue NewSA = TLO.DAG.getConstant(Diff, dl, Op1.getValueType());
1050               return TLO.CombineTo(
1051                   Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1052             }
1053           }
1054         }
1055       }
1056 
1057       if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts,
1058                                Known, TLO, Depth + 1))
1059         return true;
1060 
1061       // Try shrinking the operation as long as the shift amount will still be
1062       // in range.
1063       if ((ShAmt < DemandedBits.getActiveBits()) &&
1064           ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1065         return true;
1066 
1067       // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1068       // are not demanded. This will likely allow the anyext to be folded away.
1069       if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1070         SDValue InnerOp = Op0.getOperand(0);
1071         EVT InnerVT = InnerOp.getValueType();
1072         unsigned InnerBits = InnerVT.getScalarSizeInBits();
1073         if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
1074             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1075           EVT ShTy = getShiftAmountTy(InnerVT, DL);
1076           if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1077             ShTy = InnerVT;
1078           SDValue NarrowShl =
1079               TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1080                               TLO.DAG.getConstant(ShAmt, dl, ShTy));
1081           return TLO.CombineTo(
1082               Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
1083         }
1084         // Repeat the SHL optimization above in cases where an extension
1085         // intervenes: (shl (anyext (shr x, c1)), c2) to
1086         // (shl (anyext x), c2-c1).  This requires that the bottom c1 bits
1087         // aren't demanded (as above) and that the shifted upper c1 bits of
1088         // x aren't demanded.
1089         if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1090             InnerOp.hasOneUse()) {
1091           if (ConstantSDNode *SA2 =
1092                   isConstOrConstSplat(InnerOp.getOperand(1))) {
1093             unsigned InnerShAmt = SA2->getLimitedValue(InnerBits);
1094             if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
1095                 DemandedBits.getActiveBits() <=
1096                     (InnerBits - InnerShAmt + ShAmt) &&
1097                 DemandedBits.countTrailingZeros() >= ShAmt) {
1098               SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
1099                                                   Op1.getValueType());
1100               SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1101                                                InnerOp.getOperand(0));
1102               return TLO.CombineTo(
1103                   Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
1104             }
1105           }
1106         }
1107       }
1108 
1109       Known.Zero <<= ShAmt;
1110       Known.One <<= ShAmt;
1111       // low bits known zero.
1112       Known.Zero.setLowBits(ShAmt);
1113     }
1114     break;
1115   }
1116   case ISD::SRL: {
1117     SDValue Op0 = Op.getOperand(0);
1118     SDValue Op1 = Op.getOperand(1);
1119 
1120     if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1121       // If the shift count is an invalid immediate, don't do anything.
1122       if (SA->getAPIntValue().uge(BitWidth))
1123         break;
1124 
1125       unsigned ShAmt = SA->getZExtValue();
1126       if (ShAmt == 0)
1127         return TLO.CombineTo(Op, Op0);
1128 
1129       EVT ShiftVT = Op1.getValueType();
1130       APInt InDemandedMask = (DemandedBits << ShAmt);
1131 
1132       // If the shift is exact, then it does demand the low bits (and knows that
1133       // they are zero).
1134       if (Op->getFlags().hasExact())
1135         InDemandedMask.setLowBits(ShAmt);
1136 
1137       // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1138       // single shift.  We can do this if the top bits (which are shifted out)
1139       // are never demanded.
1140       // TODO - support non-uniform vector amounts.
1141       if (Op0.getOpcode() == ISD::SHL) {
1142         if (ConstantSDNode *SA2 =
1143                 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1144           if ((DemandedBits & APInt::getHighBitsSet(BitWidth, ShAmt)) == 0) {
1145             if (SA2->getAPIntValue().ult(BitWidth)) {
1146               unsigned C1 = SA2->getZExtValue();
1147               unsigned Opc = ISD::SRL;
1148               int Diff = ShAmt - C1;
1149               if (Diff < 0) {
1150                 Diff = -Diff;
1151                 Opc = ISD::SHL;
1152               }
1153 
1154               SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT);
1155               return TLO.CombineTo(
1156                   Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1157             }
1158           }
1159         }
1160       }
1161 
1162       // Compute the new bits that are at the top now.
1163       if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1164                                Depth + 1))
1165         return true;
1166       assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1167       Known.Zero.lshrInPlace(ShAmt);
1168       Known.One.lshrInPlace(ShAmt);
1169 
1170       Known.Zero.setHighBits(ShAmt); // High bits known zero.
1171     }
1172     break;
1173   }
1174   case ISD::SRA: {
1175     SDValue Op0 = Op.getOperand(0);
1176     SDValue Op1 = Op.getOperand(1);
1177 
1178     // If this is an arithmetic shift right and only the low-bit is set, we can
1179     // always convert this into a logical shr, even if the shift amount is
1180     // variable.  The low bit of the shift cannot be an input sign bit unless
1181     // the shift amount is >= the size of the datatype, which is undefined.
1182     if (DemandedBits.isOneValue())
1183       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
1184 
1185     if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1186       // If the shift count is an invalid immediate, don't do anything.
1187       if (SA->getAPIntValue().uge(BitWidth))
1188         break;
1189 
1190       unsigned ShAmt = SA->getZExtValue();
1191       if (ShAmt == 0)
1192         return TLO.CombineTo(Op, Op0);
1193 
1194       APInt InDemandedMask = (DemandedBits << ShAmt);
1195 
1196       // If the shift is exact, then it does demand the low bits (and knows that
1197       // they are zero).
1198       if (Op->getFlags().hasExact())
1199         InDemandedMask.setLowBits(ShAmt);
1200 
1201       // If any of the demanded bits are produced by the sign extension, we also
1202       // demand the input sign bit.
1203       if (DemandedBits.countLeadingZeros() < ShAmt)
1204         InDemandedMask.setSignBit();
1205 
1206       if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1207                                Depth + 1))
1208         return true;
1209       assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1210       Known.Zero.lshrInPlace(ShAmt);
1211       Known.One.lshrInPlace(ShAmt);
1212 
1213       // If the input sign bit is known to be zero, or if none of the top bits
1214       // are demanded, turn this into an unsigned shift right.
1215       if (Known.Zero[BitWidth - ShAmt - 1] ||
1216           DemandedBits.countLeadingZeros() >= ShAmt) {
1217         SDNodeFlags Flags;
1218         Flags.setExact(Op->getFlags().hasExact());
1219         return TLO.CombineTo(
1220             Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1221       }
1222 
1223       int Log2 = DemandedBits.exactLogBase2();
1224       if (Log2 >= 0) {
1225         // The bit must come from the sign.
1226         SDValue NewSA =
1227             TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, Op1.getValueType());
1228         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1229       }
1230 
1231       if (Known.One[BitWidth - ShAmt - 1])
1232         // New bits are known one.
1233         Known.One.setHighBits(ShAmt);
1234     }
1235     break;
1236   }
1237   case ISD::FSHL:
1238   case ISD::FSHR: {
1239     SDValue Op0 = Op.getOperand(0);
1240     SDValue Op1 = Op.getOperand(1);
1241     SDValue Op2 = Op.getOperand(2);
1242     bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
1243 
1244     if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) {
1245       unsigned Amt = SA->getAPIntValue().urem(BitWidth);
1246 
1247       // For fshl, 0-shift returns the 1st arg.
1248       // For fshr, 0-shift returns the 2nd arg.
1249       if (Amt == 0) {
1250         if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1251                                  Known, TLO, Depth + 1))
1252           return true;
1253         break;
1254       }
1255 
1256       // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt))
1257       // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
1258       APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1259       APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
1260       if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
1261                                Depth + 1))
1262         return true;
1263       if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
1264                                Depth + 1))
1265         return true;
1266 
1267       Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
1268       Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
1269       Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1270       Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1271       Known.One |= Known2.One;
1272       Known.Zero |= Known2.Zero;
1273     }
1274     break;
1275   }
1276   case ISD::BITREVERSE: {
1277     SDValue Src = Op.getOperand(0);
1278     APInt DemandedSrcBits = DemandedBits.reverseBits();
1279     if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1280                              Depth + 1))
1281       return true;
1282     Known.One = Known2.One.reverseBits();
1283     Known.Zero = Known2.Zero.reverseBits();
1284     break;
1285   }
1286   case ISD::SIGN_EXTEND_INREG: {
1287     SDValue Op0 = Op.getOperand(0);
1288     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1289     unsigned ExVTBits = ExVT.getScalarSizeInBits();
1290 
1291     // If we only care about the highest bit, don't bother shifting right.
1292     if (DemandedBits.isSignMask()) {
1293       unsigned NumSignBits = TLO.DAG.ComputeNumSignBits(Op0);
1294       bool AlreadySignExtended = NumSignBits >= BitWidth - ExVTBits + 1;
1295       // However if the input is already sign extended we expect the sign
1296       // extension to be dropped altogether later and do not simplify.
1297       if (!AlreadySignExtended) {
1298         // Compute the correct shift amount type, which must be getShiftAmountTy
1299         // for scalar types after legalization.
1300         EVT ShiftAmtTy = VT;
1301         if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1302           ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1303 
1304         SDValue ShiftAmt =
1305             TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy);
1306         return TLO.CombineTo(Op,
1307                              TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1308       }
1309     }
1310 
1311     // If none of the extended bits are demanded, eliminate the sextinreg.
1312     if (DemandedBits.getActiveBits() <= ExVTBits)
1313       return TLO.CombineTo(Op, Op0);
1314 
1315     APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits);
1316 
1317     // Since the sign extended bits are demanded, we know that the sign
1318     // bit is demanded.
1319     InputDemandedBits.setBit(ExVTBits - 1);
1320 
1321     if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1))
1322       return true;
1323     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1324 
1325     // If the sign bit of the input is known set or clear, then we know the
1326     // top bits of the result.
1327 
1328     // If the input sign bit is known zero, convert this into a zero extension.
1329     if (Known.Zero[ExVTBits - 1])
1330       return TLO.CombineTo(
1331           Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType()));
1332 
1333     APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
1334     if (Known.One[ExVTBits - 1]) { // Input sign bit known set
1335       Known.One.setBitsFrom(ExVTBits);
1336       Known.Zero &= Mask;
1337     } else { // Input sign bit unknown
1338       Known.Zero &= Mask;
1339       Known.One &= Mask;
1340     }
1341     break;
1342   }
1343   case ISD::BUILD_PAIR: {
1344     EVT HalfVT = Op.getOperand(0).getValueType();
1345     unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
1346 
1347     APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1348     APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
1349 
1350     KnownBits KnownLo, KnownHi;
1351 
1352     if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
1353       return true;
1354 
1355     if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
1356       return true;
1357 
1358     Known.Zero = KnownLo.Zero.zext(BitWidth) |
1359                  KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1360 
1361     Known.One = KnownLo.One.zext(BitWidth) |
1362                 KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
1363     break;
1364   }
1365   case ISD::ZERO_EXTEND:
1366   case ISD::ZERO_EXTEND_VECTOR_INREG: {
1367     SDValue Src = Op.getOperand(0);
1368     EVT SrcVT = Src.getValueType();
1369     unsigned InBits = SrcVT.getScalarSizeInBits();
1370     unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1371     bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
1372 
1373     // If none of the top bits are demanded, convert this into an any_extend.
1374     if (DemandedBits.getActiveBits() <= InBits) {
1375       // If we only need the non-extended bits of the bottom element
1376       // then we can just bitcast to the result.
1377       if (IsVecInReg && DemandedElts == 1 &&
1378           VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1379           TLO.DAG.getDataLayout().isLittleEndian())
1380         return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1381 
1382       unsigned Opc =
1383           IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1384       if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1385         return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1386     }
1387 
1388     APInt InDemandedBits = DemandedBits.trunc(InBits);
1389     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1390     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1391                              Depth + 1))
1392       return true;
1393     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1394     assert(Known.getBitWidth() == InBits && "Src width has changed?");
1395     Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */);
1396     break;
1397   }
1398   case ISD::SIGN_EXTEND:
1399   case ISD::SIGN_EXTEND_VECTOR_INREG: {
1400     SDValue Src = Op.getOperand(0);
1401     EVT SrcVT = Src.getValueType();
1402     unsigned InBits = SrcVT.getScalarSizeInBits();
1403     unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1404     bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
1405 
1406     // If none of the top bits are demanded, convert this into an any_extend.
1407     if (DemandedBits.getActiveBits() <= InBits) {
1408       // If we only need the non-extended bits of the bottom element
1409       // then we can just bitcast to the result.
1410       if (IsVecInReg && DemandedElts == 1 &&
1411           VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1412           TLO.DAG.getDataLayout().isLittleEndian())
1413         return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1414 
1415       unsigned Opc =
1416           IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1417       if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1418         return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1419     }
1420 
1421     APInt InDemandedBits = DemandedBits.trunc(InBits);
1422     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1423 
1424     // Since some of the sign extended bits are demanded, we know that the sign
1425     // bit is demanded.
1426     InDemandedBits.setBit(InBits - 1);
1427 
1428     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1429                              Depth + 1))
1430       return true;
1431     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1432     assert(Known.getBitWidth() == InBits && "Src width has changed?");
1433 
1434     // If the sign bit is known one, the top bits match.
1435     Known = Known.sext(BitWidth);
1436 
1437     // If the sign bit is known zero, convert this to a zero extend.
1438     if (Known.isNonNegative()) {
1439       unsigned Opc =
1440           IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
1441       if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1442         return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1443     }
1444     break;
1445   }
1446   case ISD::ANY_EXTEND:
1447   case ISD::ANY_EXTEND_VECTOR_INREG: {
1448     SDValue Src = Op.getOperand(0);
1449     EVT SrcVT = Src.getValueType();
1450     unsigned InBits = SrcVT.getScalarSizeInBits();
1451     unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1452     bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
1453 
1454     // If we only need the bottom element then we can just bitcast.
1455     // TODO: Handle ANY_EXTEND?
1456     if (IsVecInReg && DemandedElts == 1 &&
1457         VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1458         TLO.DAG.getDataLayout().isLittleEndian())
1459       return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1460 
1461     APInt InDemandedBits = DemandedBits.trunc(InBits);
1462     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1463     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1464                              Depth + 1))
1465       return true;
1466     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1467     assert(Known.getBitWidth() == InBits && "Src width has changed?");
1468     Known = Known.zext(BitWidth, false /* => any extend */);
1469     break;
1470   }
1471   case ISD::TRUNCATE: {
1472     SDValue Src = Op.getOperand(0);
1473 
1474     // Simplify the input, using demanded bit information, and compute the known
1475     // zero/one bits live out.
1476     unsigned OperandBitWidth = Src.getScalarValueSizeInBits();
1477     APInt TruncMask = DemandedBits.zext(OperandBitWidth);
1478     if (SimplifyDemandedBits(Src, TruncMask, Known, TLO, Depth + 1))
1479       return true;
1480     Known = Known.trunc(BitWidth);
1481 
1482     // If the input is only used by this truncate, see if we can shrink it based
1483     // on the known demanded bits.
1484     if (Src.getNode()->hasOneUse()) {
1485       switch (Src.getOpcode()) {
1486       default:
1487         break;
1488       case ISD::SRL:
1489         // Shrink SRL by a constant if none of the high bits shifted in are
1490         // demanded.
1491         if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
1492           // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1493           // undesirable.
1494           break;
1495 
1496         auto *ShAmt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1497         if (!ShAmt || ShAmt->getAPIntValue().uge(BitWidth))
1498           break;
1499 
1500         SDValue Shift = Src.getOperand(1);
1501         uint64_t ShVal = ShAmt->getZExtValue();
1502 
1503         if (TLO.LegalTypes())
1504           Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL));
1505 
1506         APInt HighBits =
1507             APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth);
1508         HighBits.lshrInPlace(ShVal);
1509         HighBits = HighBits.trunc(BitWidth);
1510 
1511         if (!(HighBits & DemandedBits)) {
1512           // None of the shifted in bits are needed.  Add a truncate of the
1513           // shift input, then shift it.
1514           SDValue NewTrunc =
1515               TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
1516           return TLO.CombineTo(
1517               Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift));
1518         }
1519         break;
1520       }
1521     }
1522 
1523     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1524     break;
1525   }
1526   case ISD::AssertZext: {
1527     // AssertZext demands all of the high bits, plus any of the low bits
1528     // demanded by its users.
1529     EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1530     APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits());
1531     if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known,
1532                              TLO, Depth + 1))
1533       return true;
1534     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1535 
1536     Known.Zero |= ~InMask;
1537     break;
1538   }
1539   case ISD::EXTRACT_VECTOR_ELT: {
1540     SDValue Src = Op.getOperand(0);
1541     SDValue Idx = Op.getOperand(1);
1542     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1543     unsigned EltBitWidth = Src.getScalarValueSizeInBits();
1544 
1545     // Demand the bits from every vector element without a constant index.
1546     APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts);
1547     if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx))
1548       if (CIdx->getAPIntValue().ult(NumSrcElts))
1549         DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue());
1550 
1551     // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
1552     // anything about the extended bits.
1553     APInt DemandedSrcBits = DemandedBits;
1554     if (BitWidth > EltBitWidth)
1555       DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
1556 
1557     if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
1558                              Depth + 1))
1559       return true;
1560 
1561     Known = Known2;
1562     if (BitWidth > EltBitWidth)
1563       Known = Known.zext(BitWidth, false /* => any extend */);
1564     break;
1565   }
1566   case ISD::BITCAST: {
1567     SDValue Src = Op.getOperand(0);
1568     EVT SrcVT = Src.getValueType();
1569     unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
1570 
1571     // If this is an FP->Int bitcast and if the sign bit is the only
1572     // thing demanded, turn this into a FGETSIGN.
1573     if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() &&
1574         DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) &&
1575         SrcVT.isFloatingPoint()) {
1576       bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
1577       bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1578       if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 &&
1579           SrcVT != MVT::f128) {
1580         // Cannot eliminate/lower SHL for f128 yet.
1581         EVT Ty = OpVTLegal ? VT : MVT::i32;
1582         // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1583         // place.  We expect the SHL to be eliminated by other optimizations.
1584         SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src);
1585         unsigned OpVTSizeInBits = Op.getValueSizeInBits();
1586         if (!OpVTLegal && OpVTSizeInBits > 32)
1587           Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
1588         unsigned ShVal = Op.getValueSizeInBits() - 1;
1589         SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT);
1590         return TLO.CombineTo(Op,
1591                              TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
1592       }
1593     }
1594 
1595     // Bitcast from a vector using SimplifyDemanded Bits/VectorElts.
1596     // Demand the elt/bit if any of the original elts/bits are demanded.
1597     // TODO - bigendian once we have test coverage.
1598     // TODO - bool vectors once SimplifyDemandedVectorElts has SETCC support.
1599     if (SrcVT.isVector() && NumSrcEltBits > 1 &&
1600         (BitWidth % NumSrcEltBits) == 0 &&
1601         TLO.DAG.getDataLayout().isLittleEndian()) {
1602       unsigned Scale = BitWidth / NumSrcEltBits;
1603       unsigned NumSrcElts = SrcVT.getVectorNumElements();
1604       APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
1605       APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
1606       for (unsigned i = 0; i != Scale; ++i) {
1607         unsigned Offset = i * NumSrcEltBits;
1608         APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
1609         if (!Sub.isNullValue()) {
1610           DemandedSrcBits |= Sub;
1611           for (unsigned j = 0; j != NumElts; ++j)
1612             if (DemandedElts[j])
1613               DemandedSrcElts.setBit((j * Scale) + i);
1614         }
1615       }
1616 
1617       APInt KnownSrcUndef, KnownSrcZero;
1618       if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
1619                                      KnownSrcZero, TLO, Depth + 1))
1620         return true;
1621 
1622       KnownBits KnownSrcBits;
1623       if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
1624                                KnownSrcBits, TLO, Depth + 1))
1625         return true;
1626     } else if ((NumSrcEltBits % BitWidth) == 0 &&
1627                TLO.DAG.getDataLayout().isLittleEndian()) {
1628       unsigned Scale = NumSrcEltBits / BitWidth;
1629       unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1630       APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
1631       APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
1632       for (unsigned i = 0; i != NumElts; ++i)
1633         if (DemandedElts[i]) {
1634           unsigned Offset = (i % Scale) * BitWidth;
1635           DemandedSrcBits.insertBits(DemandedBits, Offset);
1636           DemandedSrcElts.setBit(i / Scale);
1637         }
1638 
1639       if (SrcVT.isVector()) {
1640         APInt KnownSrcUndef, KnownSrcZero;
1641         if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
1642                                        KnownSrcZero, TLO, Depth + 1))
1643           return true;
1644       }
1645 
1646       KnownBits KnownSrcBits;
1647       if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
1648                                KnownSrcBits, TLO, Depth + 1))
1649         return true;
1650     }
1651 
1652     // If this is a bitcast, let computeKnownBits handle it.  Only do this on a
1653     // recursive call where Known may be useful to the caller.
1654     if (Depth > 0) {
1655       Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1656       return false;
1657     }
1658     break;
1659   }
1660   case ISD::ADD:
1661   case ISD::MUL:
1662   case ISD::SUB: {
1663     // Add, Sub, and Mul don't demand any bits in positions beyond that
1664     // of the highest bit demanded of them.
1665     SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
1666     unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros();
1667     APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
1668     if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
1669                              Depth + 1) ||
1670         SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO,
1671                              Depth + 1) ||
1672         // See if the operation should be performed at a smaller bit width.
1673         ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
1674       SDNodeFlags Flags = Op.getNode()->getFlags();
1675       if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
1676         // Disable the nsw and nuw flags. We can no longer guarantee that we
1677         // won't wrap after simplification.
1678         Flags.setNoSignedWrap(false);
1679         Flags.setNoUnsignedWrap(false);
1680         SDValue NewOp =
1681             TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
1682         return TLO.CombineTo(Op, NewOp);
1683       }
1684       return true;
1685     }
1686 
1687     // If we have a constant operand, we may be able to turn it into -1 if we
1688     // do not demand the high bits. This can make the constant smaller to
1689     // encode, allow more general folding, or match specialized instruction
1690     // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that
1691     // is probably not useful (and could be detrimental).
1692     ConstantSDNode *C = isConstOrConstSplat(Op1);
1693     APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ);
1694     if (C && !C->isAllOnesValue() && !C->isOne() &&
1695         (C->getAPIntValue() | HighMask).isAllOnesValue()) {
1696       SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
1697       // We can't guarantee that the new math op doesn't wrap, so explicitly
1698       // clear those flags to prevent folding with a potential existing node
1699       // that has those flags set.
1700       SDNodeFlags Flags;
1701       Flags.setNoSignedWrap(false);
1702       Flags.setNoUnsignedWrap(false);
1703       SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
1704       return TLO.CombineTo(Op, NewOp);
1705     }
1706 
1707     LLVM_FALLTHROUGH;
1708   }
1709   default:
1710     if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1711       if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
1712                                             Known, TLO, Depth))
1713         return true;
1714       break;
1715     }
1716 
1717     // Just use computeKnownBits to compute output bits.
1718     Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1719     break;
1720   }
1721 
1722   // If we know the value of all of the demanded bits, return this as a
1723   // constant.
1724   if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) {
1725     // Avoid folding to a constant if any OpaqueConstant is involved.
1726     const SDNode *N = Op.getNode();
1727     for (SDNodeIterator I = SDNodeIterator::begin(N),
1728                         E = SDNodeIterator::end(N);
1729          I != E; ++I) {
1730       SDNode *Op = *I;
1731       if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1732         if (C->isOpaque())
1733           return false;
1734     }
1735     // TODO: Handle float bits as well.
1736     if (VT.isInteger())
1737       return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
1738   }
1739 
1740   return false;
1741 }
1742 
1743 bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
1744                                                 const APInt &DemandedElts,
1745                                                 APInt &KnownUndef,
1746                                                 APInt &KnownZero,
1747                                                 DAGCombinerInfo &DCI) const {
1748   SelectionDAG &DAG = DCI.DAG;
1749   TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1750                         !DCI.isBeforeLegalizeOps());
1751 
1752   bool Simplified =
1753       SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
1754   if (Simplified) {
1755     DCI.AddToWorklist(Op.getNode());
1756     DCI.CommitTargetLoweringOpt(TLO);
1757   }
1758 
1759   return Simplified;
1760 }
1761 
1762 /// Given a vector binary operation and known undefined elements for each input
1763 /// operand, compute whether each element of the output is undefined.
1764 static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG,
1765                                          const APInt &UndefOp0,
1766                                          const APInt &UndefOp1) {
1767   EVT VT = BO.getValueType();
1768   assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&
1769          "Vector binop only");
1770 
1771   EVT EltVT = VT.getVectorElementType();
1772   unsigned NumElts = VT.getVectorNumElements();
1773   assert(UndefOp0.getBitWidth() == NumElts &&
1774          UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis");
1775 
1776   auto getUndefOrConstantElt = [&](SDValue V, unsigned Index,
1777                                    const APInt &UndefVals) {
1778     if (UndefVals[Index])
1779       return DAG.getUNDEF(EltVT);
1780 
1781     if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
1782       // Try hard to make sure that the getNode() call is not creating temporary
1783       // nodes. Ignore opaque integers because they do not constant fold.
1784       SDValue Elt = BV->getOperand(Index);
1785       auto *C = dyn_cast<ConstantSDNode>(Elt);
1786       if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque()))
1787         return Elt;
1788     }
1789 
1790     return SDValue();
1791   };
1792 
1793   APInt KnownUndef = APInt::getNullValue(NumElts);
1794   for (unsigned i = 0; i != NumElts; ++i) {
1795     // If both inputs for this element are either constant or undef and match
1796     // the element type, compute the constant/undef result for this element of
1797     // the vector.
1798     // TODO: Ideally we would use FoldConstantArithmetic() here, but that does
1799     // not handle FP constants. The code within getNode() should be refactored
1800     // to avoid the danger of creating a bogus temporary node here.
1801     SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0);
1802     SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1);
1803     if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT)
1804       if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef())
1805         KnownUndef.setBit(i);
1806   }
1807   return KnownUndef;
1808 }
1809 
1810 bool TargetLowering::SimplifyDemandedVectorElts(
1811     SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef,
1812     APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
1813     bool AssumeSingleUse) const {
1814   EVT VT = Op.getValueType();
1815   APInt DemandedElts = OriginalDemandedElts;
1816   unsigned NumElts = DemandedElts.getBitWidth();
1817   assert(VT.isVector() && "Expected vector op");
1818   assert(VT.getVectorNumElements() == NumElts &&
1819          "Mask size mismatches value type element count!");
1820 
1821   KnownUndef = KnownZero = APInt::getNullValue(NumElts);
1822 
1823   // Undef operand.
1824   if (Op.isUndef()) {
1825     KnownUndef.setAllBits();
1826     return false;
1827   }
1828 
1829   // If Op has other users, assume that all elements are needed.
1830   if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
1831     DemandedElts.setAllBits();
1832 
1833   // Not demanding any elements from Op.
1834   if (DemandedElts == 0) {
1835     KnownUndef.setAllBits();
1836     return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1837   }
1838 
1839   // Limit search depth.
1840   if (Depth >= 6)
1841     return false;
1842 
1843   SDLoc DL(Op);
1844   unsigned EltSizeInBits = VT.getScalarSizeInBits();
1845 
1846   switch (Op.getOpcode()) {
1847   case ISD::SCALAR_TO_VECTOR: {
1848     if (!DemandedElts[0]) {
1849       KnownUndef.setAllBits();
1850       return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1851     }
1852     KnownUndef.setHighBits(NumElts - 1);
1853     break;
1854   }
1855   case ISD::BITCAST: {
1856     SDValue Src = Op.getOperand(0);
1857     EVT SrcVT = Src.getValueType();
1858 
1859     // We only handle vectors here.
1860     // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits?
1861     if (!SrcVT.isVector())
1862       break;
1863 
1864     // Fast handling of 'identity' bitcasts.
1865     unsigned NumSrcElts = SrcVT.getVectorNumElements();
1866     if (NumSrcElts == NumElts)
1867       return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
1868                                         KnownZero, TLO, Depth + 1);
1869 
1870     APInt SrcZero, SrcUndef;
1871     APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts);
1872 
1873     // Bitcast from 'large element' src vector to 'small element' vector, we
1874     // must demand a source element if any DemandedElt maps to it.
1875     if ((NumElts % NumSrcElts) == 0) {
1876       unsigned Scale = NumElts / NumSrcElts;
1877       for (unsigned i = 0; i != NumElts; ++i)
1878         if (DemandedElts[i])
1879           SrcDemandedElts.setBit(i / Scale);
1880 
1881       if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
1882                                      TLO, Depth + 1))
1883         return true;
1884 
1885       // Try calling SimplifyDemandedBits, converting demanded elts to the bits
1886       // of the large element.
1887       // TODO - bigendian once we have test coverage.
1888       if (TLO.DAG.getDataLayout().isLittleEndian()) {
1889         unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits();
1890         APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits);
1891         for (unsigned i = 0; i != NumElts; ++i)
1892           if (DemandedElts[i]) {
1893             unsigned Ofs = (i % Scale) * EltSizeInBits;
1894             SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits);
1895           }
1896 
1897         KnownBits Known;
1898         if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1))
1899           return true;
1900       }
1901 
1902       // If the src element is zero/undef then all the output elements will be -
1903       // only demanded elements are guaranteed to be correct.
1904       for (unsigned i = 0; i != NumSrcElts; ++i) {
1905         if (SrcDemandedElts[i]) {
1906           if (SrcZero[i])
1907             KnownZero.setBits(i * Scale, (i + 1) * Scale);
1908           if (SrcUndef[i])
1909             KnownUndef.setBits(i * Scale, (i + 1) * Scale);
1910         }
1911       }
1912     }
1913 
1914     // Bitcast from 'small element' src vector to 'large element' vector, we
1915     // demand all smaller source elements covered by the larger demanded element
1916     // of this vector.
1917     if ((NumSrcElts % NumElts) == 0) {
1918       unsigned Scale = NumSrcElts / NumElts;
1919       for (unsigned i = 0; i != NumElts; ++i)
1920         if (DemandedElts[i])
1921           SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale);
1922 
1923       if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
1924                                      TLO, Depth + 1))
1925         return true;
1926 
1927       // If all the src elements covering an output element are zero/undef, then
1928       // the output element will be as well, assuming it was demanded.
1929       for (unsigned i = 0; i != NumElts; ++i) {
1930         if (DemandedElts[i]) {
1931           if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue())
1932             KnownZero.setBit(i);
1933           if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue())
1934             KnownUndef.setBit(i);
1935         }
1936       }
1937     }
1938     break;
1939   }
1940   case ISD::BUILD_VECTOR: {
1941     // Check all elements and simplify any unused elements with UNDEF.
1942     if (!DemandedElts.isAllOnesValue()) {
1943       // Don't simplify BROADCASTS.
1944       if (llvm::any_of(Op->op_values(),
1945                        [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
1946         SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
1947         bool Updated = false;
1948         for (unsigned i = 0; i != NumElts; ++i) {
1949           if (!DemandedElts[i] && !Ops[i].isUndef()) {
1950             Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
1951             KnownUndef.setBit(i);
1952             Updated = true;
1953           }
1954         }
1955         if (Updated)
1956           return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
1957       }
1958     }
1959     for (unsigned i = 0; i != NumElts; ++i) {
1960       SDValue SrcOp = Op.getOperand(i);
1961       if (SrcOp.isUndef()) {
1962         KnownUndef.setBit(i);
1963       } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
1964                  (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
1965         KnownZero.setBit(i);
1966       }
1967     }
1968     break;
1969   }
1970   case ISD::CONCAT_VECTORS: {
1971     EVT SubVT = Op.getOperand(0).getValueType();
1972     unsigned NumSubVecs = Op.getNumOperands();
1973     unsigned NumSubElts = SubVT.getVectorNumElements();
1974     for (unsigned i = 0; i != NumSubVecs; ++i) {
1975       SDValue SubOp = Op.getOperand(i);
1976       APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1977       APInt SubUndef, SubZero;
1978       if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
1979                                      Depth + 1))
1980         return true;
1981       KnownUndef.insertBits(SubUndef, i * NumSubElts);
1982       KnownZero.insertBits(SubZero, i * NumSubElts);
1983     }
1984     break;
1985   }
1986   case ISD::INSERT_SUBVECTOR: {
1987     if (!isa<ConstantSDNode>(Op.getOperand(2)))
1988       break;
1989     SDValue Base = Op.getOperand(0);
1990     SDValue Sub = Op.getOperand(1);
1991     EVT SubVT = Sub.getValueType();
1992     unsigned NumSubElts = SubVT.getVectorNumElements();
1993     const APInt &Idx = Op.getConstantOperandAPInt(2);
1994     if (Idx.ugt(NumElts - NumSubElts))
1995       break;
1996     unsigned SubIdx = Idx.getZExtValue();
1997     APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
1998     APInt SubUndef, SubZero;
1999     if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
2000                                    Depth + 1))
2001       return true;
2002     APInt BaseElts = DemandedElts;
2003     BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
2004     if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO,
2005                                    Depth + 1))
2006       return true;
2007     KnownUndef.insertBits(SubUndef, SubIdx);
2008     KnownZero.insertBits(SubZero, SubIdx);
2009     break;
2010   }
2011   case ISD::EXTRACT_SUBVECTOR: {
2012     SDValue Src = Op.getOperand(0);
2013     ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2014     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2015     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
2016       // Offset the demanded elts by the subvector index.
2017       uint64_t Idx = SubIdx->getZExtValue();
2018       APInt SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
2019       APInt SrcUndef, SrcZero;
2020       if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
2021                                      Depth + 1))
2022         return true;
2023       KnownUndef = SrcUndef.extractBits(NumElts, Idx);
2024       KnownZero = SrcZero.extractBits(NumElts, Idx);
2025     }
2026     break;
2027   }
2028   case ISD::INSERT_VECTOR_ELT: {
2029     SDValue Vec = Op.getOperand(0);
2030     SDValue Scl = Op.getOperand(1);
2031     auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2032 
2033     // For a legal, constant insertion index, if we don't need this insertion
2034     // then strip it, else remove it from the demanded elts.
2035     if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
2036       unsigned Idx = CIdx->getZExtValue();
2037       if (!DemandedElts[Idx])
2038         return TLO.CombineTo(Op, Vec);
2039 
2040       APInt DemandedVecElts(DemandedElts);
2041       DemandedVecElts.clearBit(Idx);
2042       if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
2043                                      KnownZero, TLO, Depth + 1))
2044         return true;
2045 
2046       KnownUndef.clearBit(Idx);
2047       if (Scl.isUndef())
2048         KnownUndef.setBit(Idx);
2049 
2050       KnownZero.clearBit(Idx);
2051       if (isNullConstant(Scl) || isNullFPConstant(Scl))
2052         KnownZero.setBit(Idx);
2053       break;
2054     }
2055 
2056     APInt VecUndef, VecZero;
2057     if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
2058                                    Depth + 1))
2059       return true;
2060     // Without knowing the insertion index we can't set KnownUndef/KnownZero.
2061     break;
2062   }
2063   case ISD::VSELECT: {
2064     // Try to transform the select condition based on the current demanded
2065     // elements.
2066     // TODO: If a condition element is undef, we can choose from one arm of the
2067     //       select (and if one arm is undef, then we can propagate that to the
2068     //       result).
2069     // TODO - add support for constant vselect masks (see IR version of this).
2070     APInt UnusedUndef, UnusedZero;
2071     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
2072                                    UnusedZero, TLO, Depth + 1))
2073       return true;
2074 
2075     // See if we can simplify either vselect operand.
2076     APInt DemandedLHS(DemandedElts);
2077     APInt DemandedRHS(DemandedElts);
2078     APInt UndefLHS, ZeroLHS;
2079     APInt UndefRHS, ZeroRHS;
2080     if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS,
2081                                    ZeroLHS, TLO, Depth + 1))
2082       return true;
2083     if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS,
2084                                    ZeroRHS, TLO, Depth + 1))
2085       return true;
2086 
2087     KnownUndef = UndefLHS & UndefRHS;
2088     KnownZero = ZeroLHS & ZeroRHS;
2089     break;
2090   }
2091   case ISD::VECTOR_SHUFFLE: {
2092     ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
2093 
2094     // Collect demanded elements from shuffle operands..
2095     APInt DemandedLHS(NumElts, 0);
2096     APInt DemandedRHS(NumElts, 0);
2097     for (unsigned i = 0; i != NumElts; ++i) {
2098       int M = ShuffleMask[i];
2099       if (M < 0 || !DemandedElts[i])
2100         continue;
2101       assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
2102       if (M < (int)NumElts)
2103         DemandedLHS.setBit(M);
2104       else
2105         DemandedRHS.setBit(M - NumElts);
2106     }
2107 
2108     // See if we can simplify either shuffle operand.
2109     APInt UndefLHS, ZeroLHS;
2110     APInt UndefRHS, ZeroRHS;
2111     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
2112                                    ZeroLHS, TLO, Depth + 1))
2113       return true;
2114     if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
2115                                    ZeroRHS, TLO, Depth + 1))
2116       return true;
2117 
2118     // Simplify mask using undef elements from LHS/RHS.
2119     bool Updated = false;
2120     bool IdentityLHS = true, IdentityRHS = true;
2121     SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
2122     for (unsigned i = 0; i != NumElts; ++i) {
2123       int &M = NewMask[i];
2124       if (M < 0)
2125         continue;
2126       if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
2127           (M >= (int)NumElts && UndefRHS[M - NumElts])) {
2128         Updated = true;
2129         M = -1;
2130       }
2131       IdentityLHS &= (M < 0) || (M == (int)i);
2132       IdentityRHS &= (M < 0) || ((M - NumElts) == i);
2133     }
2134 
2135     // Update legal shuffle masks based on demanded elements if it won't reduce
2136     // to Identity which can cause premature removal of the shuffle mask.
2137     if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps &&
2138         isShuffleMaskLegal(NewMask, VT))
2139       return TLO.CombineTo(Op,
2140                            TLO.DAG.getVectorShuffle(VT, DL, Op.getOperand(0),
2141                                                     Op.getOperand(1), NewMask));
2142 
2143     // Propagate undef/zero elements from LHS/RHS.
2144     for (unsigned i = 0; i != NumElts; ++i) {
2145       int M = ShuffleMask[i];
2146       if (M < 0) {
2147         KnownUndef.setBit(i);
2148       } else if (M < (int)NumElts) {
2149         if (UndefLHS[M])
2150           KnownUndef.setBit(i);
2151         if (ZeroLHS[M])
2152           KnownZero.setBit(i);
2153       } else {
2154         if (UndefRHS[M - NumElts])
2155           KnownUndef.setBit(i);
2156         if (ZeroRHS[M - NumElts])
2157           KnownZero.setBit(i);
2158       }
2159     }
2160     break;
2161   }
2162   case ISD::ANY_EXTEND_VECTOR_INREG:
2163   case ISD::SIGN_EXTEND_VECTOR_INREG:
2164   case ISD::ZERO_EXTEND_VECTOR_INREG: {
2165     APInt SrcUndef, SrcZero;
2166     SDValue Src = Op.getOperand(0);
2167     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2168     APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts);
2169     if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
2170                                    Depth + 1))
2171       return true;
2172     KnownZero = SrcZero.zextOrTrunc(NumElts);
2173     KnownUndef = SrcUndef.zextOrTrunc(NumElts);
2174 
2175     if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
2176         Op.getValueSizeInBits() == Src.getValueSizeInBits() &&
2177         DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) {
2178       // aext - if we just need the bottom element then we can bitcast.
2179       return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
2180     }
2181 
2182     if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
2183       // zext(undef) upper bits are guaranteed to be zero.
2184       if (DemandedElts.isSubsetOf(KnownUndef))
2185         return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2186       KnownUndef.clearAllBits();
2187     }
2188     break;
2189   }
2190 
2191   // TODO: There are more binop opcodes that could be handled here - MUL, MIN,
2192   // MAX, saturated math, etc.
2193   case ISD::OR:
2194   case ISD::XOR:
2195   case ISD::ADD:
2196   case ISD::SUB:
2197   case ISD::FADD:
2198   case ISD::FSUB:
2199   case ISD::FMUL:
2200   case ISD::FDIV:
2201   case ISD::FREM: {
2202     APInt UndefRHS, ZeroRHS;
2203     if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2204                                    ZeroRHS, TLO, Depth + 1))
2205       return true;
2206     APInt UndefLHS, ZeroLHS;
2207     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2208                                    ZeroLHS, TLO, Depth + 1))
2209       return true;
2210 
2211     KnownZero = ZeroLHS & ZeroRHS;
2212     KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS);
2213     break;
2214   }
2215   case ISD::SHL:
2216   case ISD::SRL:
2217   case ISD::SRA:
2218   case ISD::ROTL:
2219   case ISD::ROTR: {
2220     APInt UndefRHS, ZeroRHS;
2221     if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2222                                    ZeroRHS, TLO, Depth + 1))
2223       return true;
2224     APInt UndefLHS, ZeroLHS;
2225     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2226                                    ZeroLHS, TLO, Depth + 1))
2227       return true;
2228 
2229     KnownZero = ZeroLHS;
2230     KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop?
2231     break;
2232   }
2233   case ISD::MUL:
2234   case ISD::AND: {
2235     APInt SrcUndef, SrcZero;
2236     if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
2237                                    SrcZero, TLO, Depth + 1))
2238       return true;
2239     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2240                                    KnownZero, TLO, Depth + 1))
2241       return true;
2242 
2243     // If either side has a zero element, then the result element is zero, even
2244     // if the other is an UNDEF.
2245     // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros
2246     // and then handle 'and' nodes with the rest of the binop opcodes.
2247     KnownZero |= SrcZero;
2248     KnownUndef &= SrcUndef;
2249     KnownUndef &= ~KnownZero;
2250     break;
2251   }
2252   case ISD::TRUNCATE:
2253   case ISD::SIGN_EXTEND:
2254   case ISD::ZERO_EXTEND:
2255     if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2256                                    KnownZero, TLO, Depth + 1))
2257       return true;
2258 
2259     if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2260       // zext(undef) upper bits are guaranteed to be zero.
2261       if (DemandedElts.isSubsetOf(KnownUndef))
2262         return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2263       KnownUndef.clearAllBits();
2264     }
2265     break;
2266   default: {
2267     if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2268       if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
2269                                                   KnownZero, TLO, Depth))
2270         return true;
2271     } else {
2272       KnownBits Known;
2273       APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits);
2274       if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known,
2275                                TLO, Depth, AssumeSingleUse))
2276         return true;
2277     }
2278     break;
2279   }
2280   }
2281   assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero");
2282 
2283   // Constant fold all undef cases.
2284   // TODO: Handle zero cases as well.
2285   if (DemandedElts.isSubsetOf(KnownUndef))
2286     return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2287 
2288   return false;
2289 }
2290 
2291 /// Determine which of the bits specified in Mask are known to be either zero or
2292 /// one and return them in the Known.
2293 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
2294                                                    KnownBits &Known,
2295                                                    const APInt &DemandedElts,
2296                                                    const SelectionDAG &DAG,
2297                                                    unsigned Depth) const {
2298   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2299           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2300           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2301           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2302          "Should use MaskedValueIsZero if you don't know whether Op"
2303          " is a target node!");
2304   Known.resetAll();
2305 }
2306 
2307 void TargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
2308                                                    KnownBits &Known,
2309                                                    const APInt &DemandedElts,
2310                                                    const SelectionDAG &DAG,
2311                                                    unsigned Depth) const {
2312   assert(isa<FrameIndexSDNode>(Op) && "expected FrameIndex");
2313 
2314   if (unsigned Align = DAG.InferPtrAlignment(Op)) {
2315     // The low bits are known zero if the pointer is aligned.
2316     Known.Zero.setLowBits(Log2_32(Align));
2317   }
2318 }
2319 
2320 /// This method can be implemented by targets that want to expose additional
2321 /// information about sign bits to the DAG Combiner.
2322 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
2323                                                          const APInt &,
2324                                                          const SelectionDAG &,
2325                                                          unsigned Depth) const {
2326   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2327           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2328           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2329           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2330          "Should use ComputeNumSignBits if you don't know whether Op"
2331          " is a target node!");
2332   return 1;
2333 }
2334 
2335 bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
2336     SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
2337     TargetLoweringOpt &TLO, unsigned Depth) const {
2338   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2339           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2340           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2341           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2342          "Should use SimplifyDemandedVectorElts if you don't know whether Op"
2343          " is a target node!");
2344   return false;
2345 }
2346 
2347 bool TargetLowering::SimplifyDemandedBitsForTargetNode(
2348     SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2349     KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const {
2350   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2351           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2352           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2353           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2354          "Should use SimplifyDemandedBits if you don't know whether Op"
2355          " is a target node!");
2356   computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
2357   return false;
2358 }
2359 
2360 const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const {
2361   return nullptr;
2362 }
2363 
2364 bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
2365                                                   const SelectionDAG &DAG,
2366                                                   bool SNaN,
2367                                                   unsigned Depth) const {
2368   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2369           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2370           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2371           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2372          "Should use isKnownNeverNaN if you don't know whether Op"
2373          " is a target node!");
2374   return false;
2375 }
2376 
2377 // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
2378 // work with truncating build vectors and vectors with elements of less than
2379 // 8 bits.
2380 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
2381   if (!N)
2382     return false;
2383 
2384   APInt CVal;
2385   if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
2386     CVal = CN->getAPIntValue();
2387   } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) {
2388     auto *CN = BV->getConstantSplatNode();
2389     if (!CN)
2390       return false;
2391 
2392     // If this is a truncating build vector, truncate the splat value.
2393     // Otherwise, we may fail to match the expected values below.
2394     unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits();
2395     CVal = CN->getAPIntValue();
2396     if (BVEltWidth < CVal.getBitWidth())
2397       CVal = CVal.trunc(BVEltWidth);
2398   } else {
2399     return false;
2400   }
2401 
2402   switch (getBooleanContents(N->getValueType(0))) {
2403   case UndefinedBooleanContent:
2404     return CVal[0];
2405   case ZeroOrOneBooleanContent:
2406     return CVal.isOneValue();
2407   case ZeroOrNegativeOneBooleanContent:
2408     return CVal.isAllOnesValue();
2409   }
2410 
2411   llvm_unreachable("Invalid boolean contents");
2412 }
2413 
2414 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
2415   if (!N)
2416     return false;
2417 
2418   const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2419   if (!CN) {
2420     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
2421     if (!BV)
2422       return false;
2423 
2424     // Only interested in constant splats, we don't care about undef
2425     // elements in identifying boolean constants and getConstantSplatNode
2426     // returns NULL if all ops are undef;
2427     CN = BV->getConstantSplatNode();
2428     if (!CN)
2429       return false;
2430   }
2431 
2432   if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
2433     return !CN->getAPIntValue()[0];
2434 
2435   return CN->isNullValue();
2436 }
2437 
2438 bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT,
2439                                        bool SExt) const {
2440   if (VT == MVT::i1)
2441     return N->isOne();
2442 
2443   TargetLowering::BooleanContent Cnt = getBooleanContents(VT);
2444   switch (Cnt) {
2445   case TargetLowering::ZeroOrOneBooleanContent:
2446     // An extended value of 1 is always true, unless its original type is i1,
2447     // in which case it will be sign extended to -1.
2448     return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
2449   case TargetLowering::UndefinedBooleanContent:
2450   case TargetLowering::ZeroOrNegativeOneBooleanContent:
2451     return N->isAllOnesValue() && SExt;
2452   }
2453   llvm_unreachable("Unexpected enumeration.");
2454 }
2455 
2456 /// This helper function of SimplifySetCC tries to optimize the comparison when
2457 /// either operand of the SetCC node is a bitwise-and instruction.
2458 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
2459                                          ISD::CondCode Cond, const SDLoc &DL,
2460                                          DAGCombinerInfo &DCI) const {
2461   // Match these patterns in any of their permutations:
2462   // (X & Y) == Y
2463   // (X & Y) != Y
2464   if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2465     std::swap(N0, N1);
2466 
2467   EVT OpVT = N0.getValueType();
2468   if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
2469       (Cond != ISD::SETEQ && Cond != ISD::SETNE))
2470     return SDValue();
2471 
2472   SDValue X, Y;
2473   if (N0.getOperand(0) == N1) {
2474     X = N0.getOperand(1);
2475     Y = N0.getOperand(0);
2476   } else if (N0.getOperand(1) == N1) {
2477     X = N0.getOperand(0);
2478     Y = N0.getOperand(1);
2479   } else {
2480     return SDValue();
2481   }
2482 
2483   SelectionDAG &DAG = DCI.DAG;
2484   SDValue Zero = DAG.getConstant(0, DL, OpVT);
2485   if (DAG.isKnownToBeAPowerOfTwo(Y)) {
2486     // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set.
2487     // Note that where Y is variable and is known to have at most one bit set
2488     // (for example, if it is Z & 1) we cannot do this; the expressions are not
2489     // equivalent when Y == 0.
2490     Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2491     if (DCI.isBeforeLegalizeOps() ||
2492         isCondCodeLegal(Cond, N0.getSimpleValueType()))
2493       return DAG.getSetCC(DL, VT, N0, Zero, Cond);
2494   } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
2495     // If the target supports an 'and-not' or 'and-complement' logic operation,
2496     // try to use that to make a comparison operation more efficient.
2497     // But don't do this transform if the mask is a single bit because there are
2498     // more efficient ways to deal with that case (for example, 'bt' on x86 or
2499     // 'rlwinm' on PPC).
2500 
2501     // Bail out if the compare operand that we want to turn into a zero is
2502     // already a zero (otherwise, infinite loop).
2503     auto *YConst = dyn_cast<ConstantSDNode>(Y);
2504     if (YConst && YConst->isNullValue())
2505       return SDValue();
2506 
2507     // Transform this into: ~X & Y == 0.
2508     SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
2509     SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
2510     return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond);
2511   }
2512 
2513   return SDValue();
2514 }
2515 
2516 /// There are multiple IR patterns that could be checking whether certain
2517 /// truncation of a signed number would be lossy or not. The pattern which is
2518 /// best at IR level, may not lower optimally. Thus, we want to unfold it.
2519 /// We are looking for the following pattern: (KeptBits is a constant)
2520 ///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
2521 /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false.
2522 /// KeptBits also can't be 1, that would have been folded to  %x dstcond 0
2523 /// We will unfold it into the natural trunc+sext pattern:
2524 ///   ((%x << C) a>> C) dstcond %x
2525 /// Where  C = bitwidth(x) - KeptBits  and  C u< bitwidth(x)
2526 SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
2527     EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
2528     const SDLoc &DL) const {
2529   // We must be comparing with a constant.
2530   ConstantSDNode *C1;
2531   if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
2532     return SDValue();
2533 
2534   // N0 should be:  add %x, (1 << (KeptBits-1))
2535   if (N0->getOpcode() != ISD::ADD)
2536     return SDValue();
2537 
2538   // And we must be 'add'ing a constant.
2539   ConstantSDNode *C01;
2540   if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
2541     return SDValue();
2542 
2543   SDValue X = N0->getOperand(0);
2544   EVT XVT = X.getValueType();
2545 
2546   // Validate constants ...
2547 
2548   APInt I1 = C1->getAPIntValue();
2549 
2550   ISD::CondCode NewCond;
2551   if (Cond == ISD::CondCode::SETULT) {
2552     NewCond = ISD::CondCode::SETEQ;
2553   } else if (Cond == ISD::CondCode::SETULE) {
2554     NewCond = ISD::CondCode::SETEQ;
2555     // But need to 'canonicalize' the constant.
2556     I1 += 1;
2557   } else if (Cond == ISD::CondCode::SETUGT) {
2558     NewCond = ISD::CondCode::SETNE;
2559     // But need to 'canonicalize' the constant.
2560     I1 += 1;
2561   } else if (Cond == ISD::CondCode::SETUGE) {
2562     NewCond = ISD::CondCode::SETNE;
2563   } else
2564     return SDValue();
2565 
2566   APInt I01 = C01->getAPIntValue();
2567 
2568   auto checkConstants = [&I1, &I01]() -> bool {
2569     // Both of them must be power-of-two, and the constant from setcc is bigger.
2570     return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2();
2571   };
2572 
2573   if (checkConstants()) {
2574     // Great, e.g. got  icmp ult i16 (add i16 %x, 128), 256
2575   } else {
2576     // What if we invert constants? (and the target predicate)
2577     I1.negate();
2578     I01.negate();
2579     NewCond = getSetCCInverse(NewCond, /*isInteger=*/true);
2580     if (!checkConstants())
2581       return SDValue();
2582     // Great, e.g. got  icmp uge i16 (add i16 %x, -128), -256
2583   }
2584 
2585   // They are power-of-two, so which bit is set?
2586   const unsigned KeptBits = I1.logBase2();
2587   const unsigned KeptBitsMinusOne = I01.logBase2();
2588 
2589   // Magic!
2590   if (KeptBits != (KeptBitsMinusOne + 1))
2591     return SDValue();
2592   assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable");
2593 
2594   // We don't want to do this in every single case.
2595   SelectionDAG &DAG = DCI.DAG;
2596   if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
2597           XVT, KeptBits))
2598     return SDValue();
2599 
2600   const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
2601   assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable");
2602 
2603   // Unfold into:  ((%x << C) a>> C) cond %x
2604   // Where 'cond' will be either 'eq' or 'ne'.
2605   SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
2606   SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
2607   SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
2608   SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);
2609 
2610   return T2;
2611 }
2612 
2613 /// Try to fold an equality comparison with a {add/sub/xor} binary operation as
2614 /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to
2615 /// handle the commuted versions of these patterns.
2616 SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
2617                                            ISD::CondCode Cond, const SDLoc &DL,
2618                                            DAGCombinerInfo &DCI) const {
2619   unsigned BOpcode = N0.getOpcode();
2620   assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&
2621          "Unexpected binop");
2622   assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode");
2623 
2624   // (X + Y) == X --> Y == 0
2625   // (X - Y) == X --> Y == 0
2626   // (X ^ Y) == X --> Y == 0
2627   SelectionDAG &DAG = DCI.DAG;
2628   EVT OpVT = N0.getValueType();
2629   SDValue X = N0.getOperand(0);
2630   SDValue Y = N0.getOperand(1);
2631   if (X == N1)
2632     return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond);
2633 
2634   if (Y != N1)
2635     return SDValue();
2636 
2637   // (X + Y) == Y --> X == 0
2638   // (X ^ Y) == Y --> X == 0
2639   if (BOpcode == ISD::ADD || BOpcode == ISD::XOR)
2640     return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond);
2641 
2642   // The shift would not be valid if the operands are boolean (i1).
2643   if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
2644     return SDValue();
2645 
2646   // (X - Y) == Y --> X == Y << 1
2647   EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
2648                                  !DCI.isBeforeLegalize());
2649   SDValue One = DAG.getConstant(1, DL, ShiftVT);
2650   SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
2651   if (!DCI.isCalledByLegalizer())
2652     DCI.AddToWorklist(YShl1.getNode());
2653   return DAG.getSetCC(DL, VT, X, YShl1, Cond);
2654 }
2655 
2656 /// Try to simplify a setcc built with the specified operands and cc. If it is
2657 /// unable to simplify it, return a null SDValue.
2658 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2659                                       ISD::CondCode Cond, bool foldBooleans,
2660                                       DAGCombinerInfo &DCI,
2661                                       const SDLoc &dl) const {
2662   SelectionDAG &DAG = DCI.DAG;
2663   EVT OpVT = N0.getValueType();
2664 
2665   // Constant fold or commute setcc.
2666   if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
2667     return Fold;
2668 
2669   // Ensure that the constant occurs on the RHS and fold constant comparisons.
2670   // TODO: Handle non-splat vector constants. All undef causes trouble.
2671   ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
2672   if (isConstOrConstSplat(N0) &&
2673       (DCI.isBeforeLegalizeOps() ||
2674        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
2675     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
2676 
2677   // If we have a subtract with the same 2 non-constant operands as this setcc
2678   // -- but in reverse order -- then try to commute the operands of this setcc
2679   // to match. A matching pair of setcc (cmp) and sub may be combined into 1
2680   // instruction on some targets.
2681   if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
2682       (DCI.isBeforeLegalizeOps() ||
2683        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
2684       DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
2685       !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
2686     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
2687 
2688   if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
2689     const APInt &C1 = N1C->getAPIntValue();
2690 
2691     // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
2692     // equality comparison, then we're just comparing whether X itself is
2693     // zero.
2694     if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
2695         N0.getOperand(0).getOpcode() == ISD::CTLZ &&
2696         N0.getOperand(1).getOpcode() == ISD::Constant) {
2697       const APInt &ShAmt = N0.getConstantOperandAPInt(1);
2698       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2699           ShAmt == Log2_32(N0.getValueSizeInBits())) {
2700         if ((C1 == 0) == (Cond == ISD::SETEQ)) {
2701           // (srl (ctlz x), 5) == 0  -> X != 0
2702           // (srl (ctlz x), 5) != 1  -> X != 0
2703           Cond = ISD::SETNE;
2704         } else {
2705           // (srl (ctlz x), 5) != 0  -> X == 0
2706           // (srl (ctlz x), 5) == 1  -> X == 0
2707           Cond = ISD::SETEQ;
2708         }
2709         SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2710         return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
2711                             Zero, Cond);
2712       }
2713     }
2714 
2715     SDValue CTPOP = N0;
2716     // Look through truncs that don't change the value of a ctpop.
2717     if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
2718       CTPOP = N0.getOperand(0);
2719 
2720     if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
2721         (N0 == CTPOP ||
2722          N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) {
2723       EVT CTVT = CTPOP.getValueType();
2724       SDValue CTOp = CTPOP.getOperand(0);
2725 
2726       // (ctpop x) u< 2 -> (x & x-1) == 0
2727       // (ctpop x) u> 1 -> (x & x-1) != 0
2728       if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2729         SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2730                                   DAG.getConstant(1, dl, CTVT));
2731         SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2732         ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2733         return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
2734       }
2735 
2736       // If ctpop is not supported, expand a power-of-2 comparison based on it.
2737       if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) &&
2738           (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2739         // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0)
2740         // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
2741         SDValue Zero = DAG.getConstant(0, dl, CTVT);
2742         SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
2743         ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, true);
2744         SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
2745         SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
2746         SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
2747         SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond);
2748         unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
2749         return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);
2750       }
2751     }
2752 
2753     // (zext x) == C --> x == (trunc C)
2754     // (sext x) == C --> x == (trunc C)
2755     if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2756         DCI.isBeforeLegalize() && N0->hasOneUse()) {
2757       unsigned MinBits = N0.getValueSizeInBits();
2758       SDValue PreExt;
2759       bool Signed = false;
2760       if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2761         // ZExt
2762         MinBits = N0->getOperand(0).getValueSizeInBits();
2763         PreExt = N0->getOperand(0);
2764       } else if (N0->getOpcode() == ISD::AND) {
2765         // DAGCombine turns costly ZExts into ANDs
2766         if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2767           if ((C->getAPIntValue()+1).isPowerOf2()) {
2768             MinBits = C->getAPIntValue().countTrailingOnes();
2769             PreExt = N0->getOperand(0);
2770           }
2771       } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
2772         // SExt
2773         MinBits = N0->getOperand(0).getValueSizeInBits();
2774         PreExt = N0->getOperand(0);
2775         Signed = true;
2776       } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
2777         // ZEXTLOAD / SEXTLOAD
2778         if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2779           MinBits = LN0->getMemoryVT().getSizeInBits();
2780           PreExt = N0;
2781         } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
2782           Signed = true;
2783           MinBits = LN0->getMemoryVT().getSizeInBits();
2784           PreExt = N0;
2785         }
2786       }
2787 
2788       // Figure out how many bits we need to preserve this constant.
2789       unsigned ReqdBits = Signed ?
2790         C1.getBitWidth() - C1.getNumSignBits() + 1 :
2791         C1.getActiveBits();
2792 
2793       // Make sure we're not losing bits from the constant.
2794       if (MinBits > 0 &&
2795           MinBits < C1.getBitWidth() &&
2796           MinBits >= ReqdBits) {
2797         EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2798         if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2799           // Will get folded away.
2800           SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
2801           if (MinBits == 1 && C1 == 1)
2802             // Invert the condition.
2803             return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
2804                                 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2805           SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
2806           return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2807         }
2808 
2809         // If truncating the setcc operands is not desirable, we can still
2810         // simplify the expression in some cases:
2811         // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
2812         // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
2813         // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc))
2814         // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc)
2815         // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc))
2816         // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc)
2817         SDValue TopSetCC = N0->getOperand(0);
2818         unsigned N0Opc = N0->getOpcode();
2819         bool SExt = (N0Opc == ISD::SIGN_EXTEND);
2820         if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
2821             TopSetCC.getOpcode() == ISD::SETCC &&
2822             (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
2823             (isConstFalseVal(N1C) ||
2824              isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
2825 
2826           bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) ||
2827                          (!N1C->isNullValue() && Cond == ISD::SETNE);
2828 
2829           if (!Inverse)
2830             return TopSetCC;
2831 
2832           ISD::CondCode InvCond = ISD::getSetCCInverse(
2833               cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
2834               TopSetCC.getOperand(0).getValueType().isInteger());
2835           return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
2836                                       TopSetCC.getOperand(1),
2837                                       InvCond);
2838         }
2839       }
2840     }
2841 
2842     // If the LHS is '(and load, const)', the RHS is 0, the test is for
2843     // equality or unsigned, and all 1 bits of the const are in the same
2844     // partial word, see if we can shorten the load.
2845     if (DCI.isBeforeLegalize() &&
2846         !ISD::isSignedIntSetCC(Cond) &&
2847         N0.getOpcode() == ISD::AND && C1 == 0 &&
2848         N0.getNode()->hasOneUse() &&
2849         isa<LoadSDNode>(N0.getOperand(0)) &&
2850         N0.getOperand(0).getNode()->hasOneUse() &&
2851         isa<ConstantSDNode>(N0.getOperand(1))) {
2852       LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2853       APInt bestMask;
2854       unsigned bestWidth = 0, bestOffset = 0;
2855       if (!Lod->isVolatile() && Lod->isUnindexed()) {
2856         unsigned origWidth = N0.getValueSizeInBits();
2857         unsigned maskWidth = origWidth;
2858         // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2859         // 8 bits, but have to be careful...
2860         if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2861           origWidth = Lod->getMemoryVT().getSizeInBits();
2862         const APInt &Mask = N0.getConstantOperandAPInt(1);
2863         for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2864           APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2865           for (unsigned offset=0; offset<origWidth/width; offset++) {
2866             if (Mask.isSubsetOf(newMask)) {
2867               if (DAG.getDataLayout().isLittleEndian())
2868                 bestOffset = (uint64_t)offset * (width/8);
2869               else
2870                 bestOffset = (origWidth/width - offset - 1) * (width/8);
2871               bestMask = Mask.lshr(offset * (width/8) * 8);
2872               bestWidth = width;
2873               break;
2874             }
2875             newMask <<= width;
2876           }
2877         }
2878       }
2879       if (bestWidth) {
2880         EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2881         if (newVT.isRound() &&
2882             shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
2883           EVT PtrType = Lod->getOperand(1).getValueType();
2884           SDValue Ptr = Lod->getBasePtr();
2885           if (bestOffset != 0)
2886             Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2887                               DAG.getConstant(bestOffset, dl, PtrType));
2888           unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2889           SDValue NewLoad = DAG.getLoad(
2890               newVT, dl, Lod->getChain(), Ptr,
2891               Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign);
2892           return DAG.getSetCC(dl, VT,
2893                               DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2894                                       DAG.getConstant(bestMask.trunc(bestWidth),
2895                                                       dl, newVT)),
2896                               DAG.getConstant(0LL, dl, newVT), Cond);
2897         }
2898       }
2899     }
2900 
2901     // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2902     if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2903       unsigned InSize = N0.getOperand(0).getValueSizeInBits();
2904 
2905       // If the comparison constant has bits in the upper part, the
2906       // zero-extended value could never match.
2907       if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2908                                               C1.getBitWidth() - InSize))) {
2909         switch (Cond) {
2910         case ISD::SETUGT:
2911         case ISD::SETUGE:
2912         case ISD::SETEQ:
2913           return DAG.getConstant(0, dl, VT);
2914         case ISD::SETULT:
2915         case ISD::SETULE:
2916         case ISD::SETNE:
2917           return DAG.getConstant(1, dl, VT);
2918         case ISD::SETGT:
2919         case ISD::SETGE:
2920           // True if the sign bit of C1 is set.
2921           return DAG.getConstant(C1.isNegative(), dl, VT);
2922         case ISD::SETLT:
2923         case ISD::SETLE:
2924           // True if the sign bit of C1 isn't set.
2925           return DAG.getConstant(C1.isNonNegative(), dl, VT);
2926         default:
2927           break;
2928         }
2929       }
2930 
2931       // Otherwise, we can perform the comparison with the low bits.
2932       switch (Cond) {
2933       case ISD::SETEQ:
2934       case ISD::SETNE:
2935       case ISD::SETUGT:
2936       case ISD::SETUGE:
2937       case ISD::SETULT:
2938       case ISD::SETULE: {
2939         EVT newVT = N0.getOperand(0).getValueType();
2940         if (DCI.isBeforeLegalizeOps() ||
2941             (isOperationLegal(ISD::SETCC, newVT) &&
2942              isCondCodeLegal(Cond, newVT.getSimpleVT()))) {
2943           EVT NewSetCCVT =
2944               getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
2945           SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
2946 
2947           SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
2948                                           NewConst, Cond);
2949           return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
2950         }
2951         break;
2952       }
2953       default:
2954         break; // todo, be more careful with signed comparisons
2955       }
2956     } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2957                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2958       EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2959       unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2960       EVT ExtDstTy = N0.getValueType();
2961       unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2962 
2963       // If the constant doesn't fit into the number of bits for the source of
2964       // the sign extension, it is impossible for both sides to be equal.
2965       if (C1.getMinSignedBits() > ExtSrcTyBits)
2966         return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
2967 
2968       SDValue ZextOp;
2969       EVT Op0Ty = N0.getOperand(0).getValueType();
2970       if (Op0Ty == ExtSrcTy) {
2971         ZextOp = N0.getOperand(0);
2972       } else {
2973         APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2974         ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2975                              DAG.getConstant(Imm, dl, Op0Ty));
2976       }
2977       if (!DCI.isCalledByLegalizer())
2978         DCI.AddToWorklist(ZextOp.getNode());
2979       // Otherwise, make this a use of a zext.
2980       return DAG.getSetCC(dl, VT, ZextOp,
2981                           DAG.getConstant(C1 & APInt::getLowBitsSet(
2982                                                               ExtDstTyBits,
2983                                                               ExtSrcTyBits),
2984                                           dl, ExtDstTy),
2985                           Cond);
2986     } else if ((N1C->isNullValue() || N1C->isOne()) &&
2987                 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2988       // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2989       if (N0.getOpcode() == ISD::SETCC &&
2990           isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2991         bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne());
2992         if (TrueWhenTrue)
2993           return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2994         // Invert the condition.
2995         ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2996         CC = ISD::getSetCCInverse(CC,
2997                                   N0.getOperand(0).getValueType().isInteger());
2998         if (DCI.isBeforeLegalizeOps() ||
2999             isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
3000           return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
3001       }
3002 
3003       if ((N0.getOpcode() == ISD::XOR ||
3004            (N0.getOpcode() == ISD::AND &&
3005             N0.getOperand(0).getOpcode() == ISD::XOR &&
3006             N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3007           isa<ConstantSDNode>(N0.getOperand(1)) &&
3008           cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
3009         // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
3010         // can only do this if the top bits are known zero.
3011         unsigned BitWidth = N0.getValueSizeInBits();
3012         if (DAG.MaskedValueIsZero(N0,
3013                                   APInt::getHighBitsSet(BitWidth,
3014                                                         BitWidth-1))) {
3015           // Okay, get the un-inverted input value.
3016           SDValue Val;
3017           if (N0.getOpcode() == ISD::XOR) {
3018             Val = N0.getOperand(0);
3019           } else {
3020             assert(N0.getOpcode() == ISD::AND &&
3021                     N0.getOperand(0).getOpcode() == ISD::XOR);
3022             // ((X^1)&1)^1 -> X & 1
3023             Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
3024                               N0.getOperand(0).getOperand(0),
3025                               N0.getOperand(1));
3026           }
3027 
3028           return DAG.getSetCC(dl, VT, Val, N1,
3029                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3030         }
3031       } else if (N1C->isOne() &&
3032                  (VT == MVT::i1 ||
3033                   getBooleanContents(N0->getValueType(0)) ==
3034                       ZeroOrOneBooleanContent)) {
3035         SDValue Op0 = N0;
3036         if (Op0.getOpcode() == ISD::TRUNCATE)
3037           Op0 = Op0.getOperand(0);
3038 
3039         if ((Op0.getOpcode() == ISD::XOR) &&
3040             Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3041             Op0.getOperand(1).getOpcode() == ISD::SETCC) {
3042           // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
3043           Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
3044           return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
3045                               Cond);
3046         }
3047         if (Op0.getOpcode() == ISD::AND &&
3048             isa<ConstantSDNode>(Op0.getOperand(1)) &&
3049             cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
3050           // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
3051           if (Op0.getValueType().bitsGT(VT))
3052             Op0 = DAG.getNode(ISD::AND, dl, VT,
3053                           DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
3054                           DAG.getConstant(1, dl, VT));
3055           else if (Op0.getValueType().bitsLT(VT))
3056             Op0 = DAG.getNode(ISD::AND, dl, VT,
3057                         DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
3058                         DAG.getConstant(1, dl, VT));
3059 
3060           return DAG.getSetCC(dl, VT, Op0,
3061                               DAG.getConstant(0, dl, Op0.getValueType()),
3062                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3063         }
3064         if (Op0.getOpcode() == ISD::AssertZext &&
3065             cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
3066           return DAG.getSetCC(dl, VT, Op0,
3067                               DAG.getConstant(0, dl, Op0.getValueType()),
3068                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3069       }
3070     }
3071 
3072     // Given:
3073     //   icmp eq/ne (urem %x, %y), 0
3074     // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem':
3075     //   icmp eq/ne %x, 0
3076     if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3077         (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3078       KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0));
3079       KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1));
3080       if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2)
3081         return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
3082     }
3083 
3084     if (SDValue V =
3085             optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
3086       return V;
3087   }
3088 
3089   // These simplifications apply to splat vectors as well.
3090   // TODO: Handle more splat vector cases.
3091   if (auto *N1C = isConstOrConstSplat(N1)) {
3092     const APInt &C1 = N1C->getAPIntValue();
3093 
3094     APInt MinVal, MaxVal;
3095     unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits();
3096     if (ISD::isSignedIntSetCC(Cond)) {
3097       MinVal = APInt::getSignedMinValue(OperandBitSize);
3098       MaxVal = APInt::getSignedMaxValue(OperandBitSize);
3099     } else {
3100       MinVal = APInt::getMinValue(OperandBitSize);
3101       MaxVal = APInt::getMaxValue(OperandBitSize);
3102     }
3103 
3104     // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3105     if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3106       // X >= MIN --> true
3107       if (C1 == MinVal)
3108         return DAG.getBoolConstant(true, dl, VT, OpVT);
3109 
3110       if (!VT.isVector()) { // TODO: Support this for vectors.
3111         // X >= C0 --> X > (C0 - 1)
3112         APInt C = C1 - 1;
3113         ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
3114         if ((DCI.isBeforeLegalizeOps() ||
3115              isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3116             (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3117                                   isLegalICmpImmediate(C.getSExtValue())))) {
3118           return DAG.getSetCC(dl, VT, N0,
3119                               DAG.getConstant(C, dl, N1.getValueType()),
3120                               NewCC);
3121         }
3122       }
3123     }
3124 
3125     if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3126       // X <= MAX --> true
3127       if (C1 == MaxVal)
3128         return DAG.getBoolConstant(true, dl, VT, OpVT);
3129 
3130       // X <= C0 --> X < (C0 + 1)
3131       if (!VT.isVector()) { // TODO: Support this for vectors.
3132         APInt C = C1 + 1;
3133         ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3134         if ((DCI.isBeforeLegalizeOps() ||
3135              isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3136             (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3137                                   isLegalICmpImmediate(C.getSExtValue())))) {
3138           return DAG.getSetCC(dl, VT, N0,
3139                               DAG.getConstant(C, dl, N1.getValueType()),
3140                               NewCC);
3141         }
3142       }
3143     }
3144 
3145     if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3146       if (C1 == MinVal)
3147         return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false
3148 
3149       // TODO: Support this for vectors after legalize ops.
3150       if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3151         // Canonicalize setlt X, Max --> setne X, Max
3152         if (C1 == MaxVal)
3153           return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3154 
3155         // If we have setult X, 1, turn it into seteq X, 0
3156         if (C1 == MinVal+1)
3157           return DAG.getSetCC(dl, VT, N0,
3158                               DAG.getConstant(MinVal, dl, N0.getValueType()),
3159                               ISD::SETEQ);
3160       }
3161     }
3162 
3163     if (Cond == ISD::SETGT || Cond == ISD::SETUGT) {
3164       if (C1 == MaxVal)
3165         return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false
3166 
3167       // TODO: Support this for vectors after legalize ops.
3168       if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3169         // Canonicalize setgt X, Min --> setne X, Min
3170         if (C1 == MinVal)
3171           return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3172 
3173         // If we have setugt X, Max-1, turn it into seteq X, Max
3174         if (C1 == MaxVal-1)
3175           return DAG.getSetCC(dl, VT, N0,
3176                               DAG.getConstant(MaxVal, dl, N0.getValueType()),
3177                               ISD::SETEQ);
3178       }
3179     }
3180 
3181     // If we have "setcc X, C0", check to see if we can shrink the immediate
3182     // by changing cc.
3183     // TODO: Support this for vectors after legalize ops.
3184     if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3185       // SETUGT X, SINTMAX  -> SETLT X, 0
3186       if (Cond == ISD::SETUGT &&
3187           C1 == APInt::getSignedMaxValue(OperandBitSize))
3188         return DAG.getSetCC(dl, VT, N0,
3189                             DAG.getConstant(0, dl, N1.getValueType()),
3190                             ISD::SETLT);
3191 
3192       // SETULT X, SINTMIN  -> SETGT X, -1
3193       if (Cond == ISD::SETULT &&
3194           C1 == APInt::getSignedMinValue(OperandBitSize)) {
3195         SDValue ConstMinusOne =
3196             DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
3197                             N1.getValueType());
3198         return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
3199       }
3200     }
3201   }
3202 
3203   // Back to non-vector simplifications.
3204   // TODO: Can we do these for vector splats?
3205   if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
3206     const APInt &C1 = N1C->getAPIntValue();
3207 
3208     // Fold bit comparisons when we can.
3209     if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3210         (VT == N0.getValueType() ||
3211          (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
3212         N0.getOpcode() == ISD::AND) {
3213       auto &DL = DAG.getDataLayout();
3214       if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3215         EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3216                                        !DCI.isBeforeLegalize());
3217         if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
3218           // Perform the xform if the AND RHS is a single bit.
3219           if (AndRHS->getAPIntValue().isPowerOf2()) {
3220             return DAG.getNode(ISD::TRUNCATE, dl, VT,
3221                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
3222                    DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
3223                                    ShiftTy)));
3224           }
3225         } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
3226           // (X & 8) == 8  -->  (X & 8) >> 3
3227           // Perform the xform if C1 is a single bit.
3228           if (C1.isPowerOf2()) {
3229             return DAG.getNode(ISD::TRUNCATE, dl, VT,
3230                                DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
3231                                       DAG.getConstant(C1.logBase2(), dl,
3232                                                       ShiftTy)));
3233           }
3234         }
3235       }
3236     }
3237 
3238     if (C1.getMinSignedBits() <= 64 &&
3239         !isLegalICmpImmediate(C1.getSExtValue())) {
3240       // (X & -256) == 256 -> (X >> 8) == 1
3241       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3242           N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3243         if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3244           const APInt &AndRHSC = AndRHS->getAPIntValue();
3245           if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
3246             unsigned ShiftBits = AndRHSC.countTrailingZeros();
3247             auto &DL = DAG.getDataLayout();
3248             EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3249                                            !DCI.isBeforeLegalize());
3250             EVT CmpTy = N0.getValueType();
3251             SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
3252                                         DAG.getConstant(ShiftBits, dl,
3253                                                         ShiftTy));
3254             SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
3255             return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
3256           }
3257         }
3258       } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
3259                  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
3260         bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
3261         // X <  0x100000000 -> (X >> 32) <  1
3262         // X >= 0x100000000 -> (X >> 32) >= 1
3263         // X <= 0x0ffffffff -> (X >> 32) <  1
3264         // X >  0x0ffffffff -> (X >> 32) >= 1
3265         unsigned ShiftBits;
3266         APInt NewC = C1;
3267         ISD::CondCode NewCond = Cond;
3268         if (AdjOne) {
3269           ShiftBits = C1.countTrailingOnes();
3270           NewC = NewC + 1;
3271           NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3272         } else {
3273           ShiftBits = C1.countTrailingZeros();
3274         }
3275         NewC.lshrInPlace(ShiftBits);
3276         if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
3277           isLegalICmpImmediate(NewC.getSExtValue())) {
3278           auto &DL = DAG.getDataLayout();
3279           EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3280                                          !DCI.isBeforeLegalize());
3281           EVT CmpTy = N0.getValueType();
3282           SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
3283                                       DAG.getConstant(ShiftBits, dl, ShiftTy));
3284           SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
3285           return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
3286         }
3287       }
3288     }
3289   }
3290 
3291   if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) {
3292     auto *CFP = cast<ConstantFPSDNode>(N1);
3293     assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value");
3294 
3295     // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
3296     // constant if knowing that the operand is non-nan is enough.  We prefer to
3297     // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
3298     // materialize 0.0.
3299     if (Cond == ISD::SETO || Cond == ISD::SETUO)
3300       return DAG.getSetCC(dl, VT, N0, N0, Cond);
3301 
3302     // setcc (fneg x), C -> setcc swap(pred) x, -C
3303     if (N0.getOpcode() == ISD::FNEG) {
3304       ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
3305       if (DCI.isBeforeLegalizeOps() ||
3306           isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
3307         SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
3308         return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
3309       }
3310     }
3311 
3312     // If the condition is not legal, see if we can find an equivalent one
3313     // which is legal.
3314     if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
3315       // If the comparison was an awkward floating-point == or != and one of
3316       // the comparison operands is infinity or negative infinity, convert the
3317       // condition to a less-awkward <= or >=.
3318       if (CFP->getValueAPF().isInfinity()) {
3319         if (CFP->getValueAPF().isNegative()) {
3320           if (Cond == ISD::SETOEQ &&
3321               isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3322             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
3323           if (Cond == ISD::SETUEQ &&
3324               isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3325             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
3326           if (Cond == ISD::SETUNE &&
3327               isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3328             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
3329           if (Cond == ISD::SETONE &&
3330               isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3331             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
3332         } else {
3333           if (Cond == ISD::SETOEQ &&
3334               isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3335             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
3336           if (Cond == ISD::SETUEQ &&
3337               isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3338             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
3339           if (Cond == ISD::SETUNE &&
3340               isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3341             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
3342           if (Cond == ISD::SETONE &&
3343               isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3344             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
3345         }
3346       }
3347     }
3348   }
3349 
3350   if (N0 == N1) {
3351     // The sext(setcc()) => setcc() optimization relies on the appropriate
3352     // constant being emitted.
3353     assert(!N0.getValueType().isInteger() &&
3354            "Integer types should be handled by FoldSetCC");
3355 
3356     bool EqTrue = ISD::isTrueWhenEqual(Cond);
3357     unsigned UOF = ISD::getUnorderedFlavor(Cond);
3358     if (UOF == 2) // FP operators that are undefined on NaNs.
3359       return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
3360     if (UOF == unsigned(EqTrue))
3361       return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
3362     // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
3363     // if it is not already.
3364     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3365     if (NewCond != Cond &&
3366         (DCI.isBeforeLegalizeOps() ||
3367                             isCondCodeLegal(NewCond, N0.getSimpleValueType())))
3368       return DAG.getSetCC(dl, VT, N0, N1, NewCond);
3369   }
3370 
3371   if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3372       N0.getValueType().isInteger()) {
3373     if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3374         N0.getOpcode() == ISD::XOR) {
3375       // Simplify (X+Y) == (X+Z) -->  Y == Z
3376       if (N0.getOpcode() == N1.getOpcode()) {
3377         if (N0.getOperand(0) == N1.getOperand(0))
3378           return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
3379         if (N0.getOperand(1) == N1.getOperand(1))
3380           return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
3381         if (isCommutativeBinOp(N0.getOpcode())) {
3382           // If X op Y == Y op X, try other combinations.
3383           if (N0.getOperand(0) == N1.getOperand(1))
3384             return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
3385                                 Cond);
3386           if (N0.getOperand(1) == N1.getOperand(0))
3387             return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
3388                                 Cond);
3389         }
3390       }
3391 
3392       // If RHS is a legal immediate value for a compare instruction, we need
3393       // to be careful about increasing register pressure needlessly.
3394       bool LegalRHSImm = false;
3395 
3396       if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3397         if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3398           // Turn (X+C1) == C2 --> X == C2-C1
3399           if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
3400             return DAG.getSetCC(dl, VT, N0.getOperand(0),
3401                                 DAG.getConstant(RHSC->getAPIntValue()-
3402                                                 LHSR->getAPIntValue(),
3403                                 dl, N0.getValueType()), Cond);
3404           }
3405 
3406           // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3407           if (N0.getOpcode() == ISD::XOR)
3408             // If we know that all of the inverted bits are zero, don't bother
3409             // performing the inversion.
3410             if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
3411               return
3412                 DAG.getSetCC(dl, VT, N0.getOperand(0),
3413                              DAG.getConstant(LHSR->getAPIntValue() ^
3414                                                RHSC->getAPIntValue(),
3415                                              dl, N0.getValueType()),
3416                              Cond);
3417         }
3418 
3419         // Turn (C1-X) == C2 --> X == C1-C2
3420         if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3421           if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3422             return
3423               DAG.getSetCC(dl, VT, N0.getOperand(1),
3424                            DAG.getConstant(SUBC->getAPIntValue() -
3425                                              RHSC->getAPIntValue(),
3426                                            dl, N0.getValueType()),
3427                            Cond);
3428           }
3429         }
3430 
3431         // Could RHSC fold directly into a compare?
3432         if (RHSC->getValueType(0).getSizeInBits() <= 64)
3433           LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
3434       }
3435 
3436       // (X+Y) == X --> Y == 0 and similar folds.
3437       // Don't do this if X is an immediate that can fold into a cmp
3438       // instruction and X+Y has other uses. It could be an induction variable
3439       // chain, and the transform would increase register pressure.
3440       if (!LegalRHSImm || N0.hasOneUse())
3441         if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI))
3442           return V;
3443     }
3444 
3445     if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3446         N1.getOpcode() == ISD::XOR)
3447       if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI))
3448         return V;
3449 
3450     if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI))
3451       return V;
3452   }
3453 
3454   // Fold remainder of division by a constant.
3455   if (N0.getOpcode() == ISD::UREM && N0.hasOneUse() &&
3456       (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3457     AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3458 
3459     // When division is cheap or optimizing for minimum size,
3460     // fall through to DIVREM creation by skipping this fold.
3461     if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize))
3462       if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
3463         return Folded;
3464   }
3465 
3466   // Fold away ALL boolean setcc's.
3467   if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
3468     SDValue Temp;
3469     switch (Cond) {
3470     default: llvm_unreachable("Unknown integer setcc!");
3471     case ISD::SETEQ:  // X == Y  -> ~(X^Y)
3472       Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3473       N0 = DAG.getNOT(dl, Temp, OpVT);
3474       if (!DCI.isCalledByLegalizer())
3475         DCI.AddToWorklist(Temp.getNode());
3476       break;
3477     case ISD::SETNE:  // X != Y   -->  (X^Y)
3478       N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3479       break;
3480     case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
3481     case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
3482       Temp = DAG.getNOT(dl, N0, OpVT);
3483       N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
3484       if (!DCI.isCalledByLegalizer())
3485         DCI.AddToWorklist(Temp.getNode());
3486       break;
3487     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
3488     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
3489       Temp = DAG.getNOT(dl, N1, OpVT);
3490       N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
3491       if (!DCI.isCalledByLegalizer())
3492         DCI.AddToWorklist(Temp.getNode());
3493       break;
3494     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
3495     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
3496       Temp = DAG.getNOT(dl, N0, OpVT);
3497       N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
3498       if (!DCI.isCalledByLegalizer())
3499         DCI.AddToWorklist(Temp.getNode());
3500       break;
3501     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
3502     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
3503       Temp = DAG.getNOT(dl, N1, OpVT);
3504       N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
3505       break;
3506     }
3507     if (VT.getScalarType() != MVT::i1) {
3508       if (!DCI.isCalledByLegalizer())
3509         DCI.AddToWorklist(N0.getNode());
3510       // FIXME: If running after legalize, we probably can't do this.
3511       ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
3512       N0 = DAG.getNode(ExtendCode, dl, VT, N0);
3513     }
3514     return N0;
3515   }
3516 
3517   // Could not fold it.
3518   return SDValue();
3519 }
3520 
3521 /// Returns true (and the GlobalValue and the offset) if the node is a
3522 /// GlobalAddress + offset.
3523 bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA,
3524                                     int64_t &Offset) const {
3525 
3526   SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode();
3527 
3528   if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
3529     GA = GASD->getGlobal();
3530     Offset += GASD->getOffset();
3531     return true;
3532   }
3533 
3534   if (N->getOpcode() == ISD::ADD) {
3535     SDValue N1 = N->getOperand(0);
3536     SDValue N2 = N->getOperand(1);
3537     if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
3538       if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
3539         Offset += V->getSExtValue();
3540         return true;
3541       }
3542     } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
3543       if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
3544         Offset += V->getSExtValue();
3545         return true;
3546       }
3547     }
3548   }
3549 
3550   return false;
3551 }
3552 
3553 SDValue TargetLowering::PerformDAGCombine(SDNode *N,
3554                                           DAGCombinerInfo &DCI) const {
3555   // Default implementation: no optimization.
3556   return SDValue();
3557 }
3558 
3559 //===----------------------------------------------------------------------===//
3560 //  Inline Assembler Implementation Methods
3561 //===----------------------------------------------------------------------===//
3562 
3563 TargetLowering::ConstraintType
3564 TargetLowering::getConstraintType(StringRef Constraint) const {
3565   unsigned S = Constraint.size();
3566 
3567   if (S == 1) {
3568     switch (Constraint[0]) {
3569     default: break;
3570     case 'r':
3571       return C_RegisterClass;
3572     case 'm': // memory
3573     case 'o': // offsetable
3574     case 'V': // not offsetable
3575       return C_Memory;
3576     case 'n': // Simple Integer
3577     case 'E': // Floating Point Constant
3578     case 'F': // Floating Point Constant
3579       return C_Immediate;
3580     case 'i': // Simple Integer or Relocatable Constant
3581     case 's': // Relocatable Constant
3582     case 'p': // Address.
3583     case 'X': // Allow ANY value.
3584     case 'I': // Target registers.
3585     case 'J':
3586     case 'K':
3587     case 'L':
3588     case 'M':
3589     case 'N':
3590     case 'O':
3591     case 'P':
3592     case '<':
3593     case '>':
3594       return C_Other;
3595     }
3596   }
3597 
3598   if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') {
3599     if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
3600       return C_Memory;
3601     return C_Register;
3602   }
3603   return C_Unknown;
3604 }
3605 
3606 /// Try to replace an X constraint, which matches anything, with another that
3607 /// has more specific requirements based on the type of the corresponding
3608 /// operand.
3609 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
3610   if (ConstraintVT.isInteger())
3611     return "r";
3612   if (ConstraintVT.isFloatingPoint())
3613     return "f"; // works for many targets
3614   return nullptr;
3615 }
3616 
3617 SDValue TargetLowering::LowerAsmOutputForConstraint(
3618     SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo,
3619     SelectionDAG &DAG) const {
3620   return SDValue();
3621 }
3622 
3623 /// Lower the specified operand into the Ops vector.
3624 /// If it is invalid, don't add anything to Ops.
3625 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3626                                                   std::string &Constraint,
3627                                                   std::vector<SDValue> &Ops,
3628                                                   SelectionDAG &DAG) const {
3629 
3630   if (Constraint.length() > 1) return;
3631 
3632   char ConstraintLetter = Constraint[0];
3633   switch (ConstraintLetter) {
3634   default: break;
3635   case 'X':     // Allows any operand; labels (basic block) use this.
3636     if (Op.getOpcode() == ISD::BasicBlock ||
3637         Op.getOpcode() == ISD::TargetBlockAddress) {
3638       Ops.push_back(Op);
3639       return;
3640     }
3641     LLVM_FALLTHROUGH;
3642   case 'i':    // Simple Integer or Relocatable Constant
3643   case 'n':    // Simple Integer
3644   case 's': {  // Relocatable Constant
3645 
3646     GlobalAddressSDNode *GA;
3647     ConstantSDNode *C;
3648     BlockAddressSDNode *BA;
3649     uint64_t Offset = 0;
3650 
3651     // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C),
3652     // etc., since getelementpointer is variadic. We can't use
3653     // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible
3654     // while in this case the GA may be furthest from the root node which is
3655     // likely an ISD::ADD.
3656     while (1) {
3657       if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') {
3658         Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
3659                                                  GA->getValueType(0),
3660                                                  Offset + GA->getOffset()));
3661         return;
3662       } else if ((C = dyn_cast<ConstantSDNode>(Op)) &&
3663                  ConstraintLetter != 's') {
3664         // gcc prints these as sign extended.  Sign extend value to 64 bits
3665         // now; without this it would get ZExt'd later in
3666         // ScheduleDAGSDNodes::EmitNode, which is very generic.
3667         bool IsBool = C->getConstantIntValue()->getBitWidth() == 1;
3668         BooleanContent BCont = getBooleanContents(MVT::i64);
3669         ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont)
3670                                       : ISD::SIGN_EXTEND;
3671         int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue()
3672                                                     : C->getSExtValue();
3673         Ops.push_back(DAG.getTargetConstant(Offset + ExtVal,
3674                                             SDLoc(C), MVT::i64));
3675         return;
3676       } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) &&
3677                  ConstraintLetter != 'n') {
3678         Ops.push_back(DAG.getTargetBlockAddress(
3679             BA->getBlockAddress(), BA->getValueType(0),
3680             Offset + BA->getOffset(), BA->getTargetFlags()));
3681         return;
3682       } else {
3683         const unsigned OpCode = Op.getOpcode();
3684         if (OpCode == ISD::ADD || OpCode == ISD::SUB) {
3685           if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0))))
3686             Op = Op.getOperand(1);
3687           // Subtraction is not commutative.
3688           else if (OpCode == ISD::ADD &&
3689                    (C = dyn_cast<ConstantSDNode>(Op.getOperand(1))))
3690             Op = Op.getOperand(0);
3691           else
3692             return;
3693           Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue();
3694           continue;
3695         }
3696       }
3697       return;
3698     }
3699     break;
3700   }
3701   }
3702 }
3703 
3704 std::pair<unsigned, const TargetRegisterClass *>
3705 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
3706                                              StringRef Constraint,
3707                                              MVT VT) const {
3708   if (Constraint.empty() || Constraint[0] != '{')
3709     return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
3710   assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?");
3711 
3712   // Remove the braces from around the name.
3713   StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3714 
3715   std::pair<unsigned, const TargetRegisterClass *> R =
3716       std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr));
3717 
3718   // Figure out which register class contains this reg.
3719   for (const TargetRegisterClass *RC : RI->regclasses()) {
3720     // If none of the value types for this register class are valid, we
3721     // can't use it.  For example, 64-bit reg classes on 32-bit targets.
3722     if (!isLegalRC(*RI, *RC))
3723       continue;
3724 
3725     for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
3726          I != E; ++I) {
3727       if (RegName.equals_lower(RI->getRegAsmName(*I))) {
3728         std::pair<unsigned, const TargetRegisterClass *> S =
3729             std::make_pair(*I, RC);
3730 
3731         // If this register class has the requested value type, return it,
3732         // otherwise keep searching and return the first class found
3733         // if no other is found which explicitly has the requested type.
3734         if (RI->isTypeLegalForClass(*RC, VT))
3735           return S;
3736         if (!R.second)
3737           R = S;
3738       }
3739     }
3740   }
3741 
3742   return R;
3743 }
3744 
3745 //===----------------------------------------------------------------------===//
3746 // Constraint Selection.
3747 
3748 /// Return true of this is an input operand that is a matching constraint like
3749 /// "4".
3750 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
3751   assert(!ConstraintCode.empty() && "No known constraint!");
3752   return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
3753 }
3754 
3755 /// If this is an input matching constraint, this method returns the output
3756 /// operand it matches.
3757 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
3758   assert(!ConstraintCode.empty() && "No known constraint!");
3759   return atoi(ConstraintCode.c_str());
3760 }
3761 
3762 /// Split up the constraint string from the inline assembly value into the
3763 /// specific constraints and their prefixes, and also tie in the associated
3764 /// operand values.
3765 /// If this returns an empty vector, and if the constraint string itself
3766 /// isn't empty, there was an error parsing.
3767 TargetLowering::AsmOperandInfoVector
3768 TargetLowering::ParseConstraints(const DataLayout &DL,
3769                                  const TargetRegisterInfo *TRI,
3770                                  ImmutableCallSite CS) const {
3771   /// Information about all of the constraints.
3772   AsmOperandInfoVector ConstraintOperands;
3773   const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3774   unsigned maCount = 0; // Largest number of multiple alternative constraints.
3775 
3776   // Do a prepass over the constraints, canonicalizing them, and building up the
3777   // ConstraintOperands list.
3778   unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3779   unsigned ResNo = 0; // ResNo - The result number of the next output.
3780 
3781   for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
3782     ConstraintOperands.emplace_back(std::move(CI));
3783     AsmOperandInfo &OpInfo = ConstraintOperands.back();
3784 
3785     // Update multiple alternative constraint count.
3786     if (OpInfo.multipleAlternatives.size() > maCount)
3787       maCount = OpInfo.multipleAlternatives.size();
3788 
3789     OpInfo.ConstraintVT = MVT::Other;
3790 
3791     // Compute the value type for each operand.
3792     switch (OpInfo.Type) {
3793     case InlineAsm::isOutput:
3794       // Indirect outputs just consume an argument.
3795       if (OpInfo.isIndirect) {
3796         OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3797         break;
3798       }
3799 
3800       // The return value of the call is this value.  As such, there is no
3801       // corresponding argument.
3802       assert(!CS.getType()->isVoidTy() &&
3803              "Bad inline asm!");
3804       if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
3805         OpInfo.ConstraintVT =
3806             getSimpleValueType(DL, STy->getElementType(ResNo));
3807       } else {
3808         assert(ResNo == 0 && "Asm only has one result!");
3809         OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
3810       }
3811       ++ResNo;
3812       break;
3813     case InlineAsm::isInput:
3814       OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3815       break;
3816     case InlineAsm::isClobber:
3817       // Nothing to do.
3818       break;
3819     }
3820 
3821     if (OpInfo.CallOperandVal) {
3822       llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
3823       if (OpInfo.isIndirect) {
3824         llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
3825         if (!PtrTy)
3826           report_fatal_error("Indirect operand for inline asm not a pointer!");
3827         OpTy = PtrTy->getElementType();
3828       }
3829 
3830       // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
3831       if (StructType *STy = dyn_cast<StructType>(OpTy))
3832         if (STy->getNumElements() == 1)
3833           OpTy = STy->getElementType(0);
3834 
3835       // If OpTy is not a single value, it may be a struct/union that we
3836       // can tile with integers.
3837       if (!OpTy->isSingleValueType() && OpTy->isSized()) {
3838         unsigned BitSize = DL.getTypeSizeInBits(OpTy);
3839         switch (BitSize) {
3840         default: break;
3841         case 1:
3842         case 8:
3843         case 16:
3844         case 32:
3845         case 64:
3846         case 128:
3847           OpInfo.ConstraintVT =
3848               MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
3849           break;
3850         }
3851       } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
3852         unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
3853         OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
3854       } else {
3855         OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
3856       }
3857     }
3858   }
3859 
3860   // If we have multiple alternative constraints, select the best alternative.
3861   if (!ConstraintOperands.empty()) {
3862     if (maCount) {
3863       unsigned bestMAIndex = 0;
3864       int bestWeight = -1;
3865       // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
3866       int weight = -1;
3867       unsigned maIndex;
3868       // Compute the sums of the weights for each alternative, keeping track
3869       // of the best (highest weight) one so far.
3870       for (maIndex = 0; maIndex < maCount; ++maIndex) {
3871         int weightSum = 0;
3872         for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3873              cIndex != eIndex; ++cIndex) {
3874           AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
3875           if (OpInfo.Type == InlineAsm::isClobber)
3876             continue;
3877 
3878           // If this is an output operand with a matching input operand,
3879           // look up the matching input. If their types mismatch, e.g. one
3880           // is an integer, the other is floating point, or their sizes are
3881           // different, flag it as an maCantMatch.
3882           if (OpInfo.hasMatchingInput()) {
3883             AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3884             if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3885               if ((OpInfo.ConstraintVT.isInteger() !=
3886                    Input.ConstraintVT.isInteger()) ||
3887                   (OpInfo.ConstraintVT.getSizeInBits() !=
3888                    Input.ConstraintVT.getSizeInBits())) {
3889                 weightSum = -1; // Can't match.
3890                 break;
3891               }
3892             }
3893           }
3894           weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3895           if (weight == -1) {
3896             weightSum = -1;
3897             break;
3898           }
3899           weightSum += weight;
3900         }
3901         // Update best.
3902         if (weightSum > bestWeight) {
3903           bestWeight = weightSum;
3904           bestMAIndex = maIndex;
3905         }
3906       }
3907 
3908       // Now select chosen alternative in each constraint.
3909       for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3910            cIndex != eIndex; ++cIndex) {
3911         AsmOperandInfo &cInfo = ConstraintOperands[cIndex];
3912         if (cInfo.Type == InlineAsm::isClobber)
3913           continue;
3914         cInfo.selectAlternative(bestMAIndex);
3915       }
3916     }
3917   }
3918 
3919   // Check and hook up tied operands, choose constraint code to use.
3920   for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3921        cIndex != eIndex; ++cIndex) {
3922     AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
3923 
3924     // If this is an output operand with a matching input operand, look up the
3925     // matching input. If their types mismatch, e.g. one is an integer, the
3926     // other is floating point, or their sizes are different, flag it as an
3927     // error.
3928     if (OpInfo.hasMatchingInput()) {
3929       AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3930 
3931       if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3932         std::pair<unsigned, const TargetRegisterClass *> MatchRC =
3933             getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
3934                                          OpInfo.ConstraintVT);
3935         std::pair<unsigned, const TargetRegisterClass *> InputRC =
3936             getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
3937                                          Input.ConstraintVT);
3938         if ((OpInfo.ConstraintVT.isInteger() !=
3939              Input.ConstraintVT.isInteger()) ||
3940             (MatchRC.second != InputRC.second)) {
3941           report_fatal_error("Unsupported asm: input constraint"
3942                              " with a matching output constraint of"
3943                              " incompatible type!");
3944         }
3945       }
3946     }
3947   }
3948 
3949   return ConstraintOperands;
3950 }
3951 
3952 /// Return an integer indicating how general CT is.
3953 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3954   switch (CT) {
3955   case TargetLowering::C_Immediate:
3956   case TargetLowering::C_Other:
3957   case TargetLowering::C_Unknown:
3958     return 0;
3959   case TargetLowering::C_Register:
3960     return 1;
3961   case TargetLowering::C_RegisterClass:
3962     return 2;
3963   case TargetLowering::C_Memory:
3964     return 3;
3965   }
3966   llvm_unreachable("Invalid constraint type");
3967 }
3968 
3969 /// Examine constraint type and operand type and determine a weight value.
3970 /// This object must already have been set up with the operand type
3971 /// and the current alternative constraint selected.
3972 TargetLowering::ConstraintWeight
3973   TargetLowering::getMultipleConstraintMatchWeight(
3974     AsmOperandInfo &info, int maIndex) const {
3975   InlineAsm::ConstraintCodeVector *rCodes;
3976   if (maIndex >= (int)info.multipleAlternatives.size())
3977     rCodes = &info.Codes;
3978   else
3979     rCodes = &info.multipleAlternatives[maIndex].Codes;
3980   ConstraintWeight BestWeight = CW_Invalid;
3981 
3982   // Loop over the options, keeping track of the most general one.
3983   for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3984     ConstraintWeight weight =
3985       getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3986     if (weight > BestWeight)
3987       BestWeight = weight;
3988   }
3989 
3990   return BestWeight;
3991 }
3992 
3993 /// Examine constraint type and operand type and determine a weight value.
3994 /// This object must already have been set up with the operand type
3995 /// and the current alternative constraint selected.
3996 TargetLowering::ConstraintWeight
3997   TargetLowering::getSingleConstraintMatchWeight(
3998     AsmOperandInfo &info, const char *constraint) const {
3999   ConstraintWeight weight = CW_Invalid;
4000   Value *CallOperandVal = info.CallOperandVal;
4001     // If we don't have a value, we can't do a match,
4002     // but allow it at the lowest weight.
4003   if (!CallOperandVal)
4004     return CW_Default;
4005   // Look at the constraint type.
4006   switch (*constraint) {
4007     case 'i': // immediate integer.
4008     case 'n': // immediate integer with a known value.
4009       if (isa<ConstantInt>(CallOperandVal))
4010         weight = CW_Constant;
4011       break;
4012     case 's': // non-explicit intregal immediate.
4013       if (isa<GlobalValue>(CallOperandVal))
4014         weight = CW_Constant;
4015       break;
4016     case 'E': // immediate float if host format.
4017     case 'F': // immediate float.
4018       if (isa<ConstantFP>(CallOperandVal))
4019         weight = CW_Constant;
4020       break;
4021     case '<': // memory operand with autodecrement.
4022     case '>': // memory operand with autoincrement.
4023     case 'm': // memory operand.
4024     case 'o': // offsettable memory operand
4025     case 'V': // non-offsettable memory operand
4026       weight = CW_Memory;
4027       break;
4028     case 'r': // general register.
4029     case 'g': // general register, memory operand or immediate integer.
4030               // note: Clang converts "g" to "imr".
4031       if (CallOperandVal->getType()->isIntegerTy())
4032         weight = CW_Register;
4033       break;
4034     case 'X': // any operand.
4035   default:
4036     weight = CW_Default;
4037     break;
4038   }
4039   return weight;
4040 }
4041 
4042 /// If there are multiple different constraints that we could pick for this
4043 /// operand (e.g. "imr") try to pick the 'best' one.
4044 /// This is somewhat tricky: constraints fall into four classes:
4045 ///    Other         -> immediates and magic values
4046 ///    Register      -> one specific register
4047 ///    RegisterClass -> a group of regs
4048 ///    Memory        -> memory
4049 /// Ideally, we would pick the most specific constraint possible: if we have
4050 /// something that fits into a register, we would pick it.  The problem here
4051 /// is that if we have something that could either be in a register or in
4052 /// memory that use of the register could cause selection of *other*
4053 /// operands to fail: they might only succeed if we pick memory.  Because of
4054 /// this the heuristic we use is:
4055 ///
4056 ///  1) If there is an 'other' constraint, and if the operand is valid for
4057 ///     that constraint, use it.  This makes us take advantage of 'i'
4058 ///     constraints when available.
4059 ///  2) Otherwise, pick the most general constraint present.  This prefers
4060 ///     'm' over 'r', for example.
4061 ///
4062 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
4063                              const TargetLowering &TLI,
4064                              SDValue Op, SelectionDAG *DAG) {
4065   assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
4066   unsigned BestIdx = 0;
4067   TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
4068   int BestGenerality = -1;
4069 
4070   // Loop over the options, keeping track of the most general one.
4071   for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
4072     TargetLowering::ConstraintType CType =
4073       TLI.getConstraintType(OpInfo.Codes[i]);
4074 
4075     // If this is an 'other' or 'immediate' constraint, see if the operand is
4076     // valid for it. For example, on X86 we might have an 'rI' constraint. If
4077     // the operand is an integer in the range [0..31] we want to use I (saving a
4078     // load of a register), otherwise we must use 'r'.
4079     if ((CType == TargetLowering::C_Other ||
4080          CType == TargetLowering::C_Immediate) && Op.getNode()) {
4081       assert(OpInfo.Codes[i].size() == 1 &&
4082              "Unhandled multi-letter 'other' constraint");
4083       std::vector<SDValue> ResultOps;
4084       TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
4085                                        ResultOps, *DAG);
4086       if (!ResultOps.empty()) {
4087         BestType = CType;
4088         BestIdx = i;
4089         break;
4090       }
4091     }
4092 
4093     // Things with matching constraints can only be registers, per gcc
4094     // documentation.  This mainly affects "g" constraints.
4095     if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
4096       continue;
4097 
4098     // This constraint letter is more general than the previous one, use it.
4099     int Generality = getConstraintGenerality(CType);
4100     if (Generality > BestGenerality) {
4101       BestType = CType;
4102       BestIdx = i;
4103       BestGenerality = Generality;
4104     }
4105   }
4106 
4107   OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
4108   OpInfo.ConstraintType = BestType;
4109 }
4110 
4111 /// Determines the constraint code and constraint type to use for the specific
4112 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
4113 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
4114                                             SDValue Op,
4115                                             SelectionDAG *DAG) const {
4116   assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
4117 
4118   // Single-letter constraints ('r') are very common.
4119   if (OpInfo.Codes.size() == 1) {
4120     OpInfo.ConstraintCode = OpInfo.Codes[0];
4121     OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4122   } else {
4123     ChooseConstraint(OpInfo, *this, Op, DAG);
4124   }
4125 
4126   // 'X' matches anything.
4127   if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
4128     // Labels and constants are handled elsewhere ('X' is the only thing
4129     // that matches labels).  For Functions, the type here is the type of
4130     // the result, which is not what we want to look at; leave them alone.
4131     Value *v = OpInfo.CallOperandVal;
4132     if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
4133       OpInfo.CallOperandVal = v;
4134       return;
4135     }
4136 
4137     if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress)
4138       return;
4139 
4140     // Otherwise, try to resolve it to something we know about by looking at
4141     // the actual operand type.
4142     if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
4143       OpInfo.ConstraintCode = Repl;
4144       OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4145     }
4146   }
4147 }
4148 
4149 /// Given an exact SDIV by a constant, create a multiplication
4150 /// with the multiplicative inverse of the constant.
4151 static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
4152                               const SDLoc &dl, SelectionDAG &DAG,
4153                               SmallVectorImpl<SDNode *> &Created) {
4154   SDValue Op0 = N->getOperand(0);
4155   SDValue Op1 = N->getOperand(1);
4156   EVT VT = N->getValueType(0);
4157   EVT SVT = VT.getScalarType();
4158   EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
4159   EVT ShSVT = ShVT.getScalarType();
4160 
4161   bool UseSRA = false;
4162   SmallVector<SDValue, 16> Shifts, Factors;
4163 
4164   auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4165     if (C->isNullValue())
4166       return false;
4167     APInt Divisor = C->getAPIntValue();
4168     unsigned Shift = Divisor.countTrailingZeros();
4169     if (Shift) {
4170       Divisor.ashrInPlace(Shift);
4171       UseSRA = true;
4172     }
4173     // Calculate the multiplicative inverse, using Newton's method.
4174     APInt t;
4175     APInt Factor = Divisor;
4176     while ((t = Divisor * Factor) != 1)
4177       Factor *= APInt(Divisor.getBitWidth(), 2) - t;
4178     Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT));
4179     Factors.push_back(DAG.getConstant(Factor, dl, SVT));
4180     return true;
4181   };
4182 
4183   // Collect all magic values from the build vector.
4184   if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
4185     return SDValue();
4186 
4187   SDValue Shift, Factor;
4188   if (VT.isVector()) {
4189     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4190     Factor = DAG.getBuildVector(VT, dl, Factors);
4191   } else {
4192     Shift = Shifts[0];
4193     Factor = Factors[0];
4194   }
4195 
4196   SDValue Res = Op0;
4197 
4198   // Shift the value upfront if it is even, so the LSB is one.
4199   if (UseSRA) {
4200     // TODO: For UDIV use SRL instead of SRA.
4201     SDNodeFlags Flags;
4202     Flags.setExact(true);
4203     Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
4204     Created.push_back(Res.getNode());
4205   }
4206 
4207   return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
4208 }
4209 
4210 SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
4211                               SelectionDAG &DAG,
4212                               SmallVectorImpl<SDNode *> &Created) const {
4213   AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4214   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4215   if (TLI.isIntDivCheap(N->getValueType(0), Attr))
4216     return SDValue(N, 0); // Lower SDIV as SDIV
4217   return SDValue();
4218 }
4219 
4220 /// Given an ISD::SDIV node expressing a divide by constant,
4221 /// return a DAG expression to select that will generate the same value by
4222 /// multiplying by a magic number.
4223 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
4224 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
4225                                   bool IsAfterLegalization,
4226                                   SmallVectorImpl<SDNode *> &Created) const {
4227   SDLoc dl(N);
4228   EVT VT = N->getValueType(0);
4229   EVT SVT = VT.getScalarType();
4230   EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4231   EVT ShSVT = ShVT.getScalarType();
4232   unsigned EltBits = VT.getScalarSizeInBits();
4233 
4234   // Check to see if we can do this.
4235   // FIXME: We should be more aggressive here.
4236   if (!isTypeLegal(VT))
4237     return SDValue();
4238 
4239   // If the sdiv has an 'exact' bit we can use a simpler lowering.
4240   if (N->getFlags().hasExact())
4241     return BuildExactSDIV(*this, N, dl, DAG, Created);
4242 
4243   SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
4244 
4245   auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4246     if (C->isNullValue())
4247       return false;
4248 
4249     const APInt &Divisor = C->getAPIntValue();
4250     APInt::ms magics = Divisor.magic();
4251     int NumeratorFactor = 0;
4252     int ShiftMask = -1;
4253 
4254     if (Divisor.isOneValue() || Divisor.isAllOnesValue()) {
4255       // If d is +1/-1, we just multiply the numerator by +1/-1.
4256       NumeratorFactor = Divisor.getSExtValue();
4257       magics.m = 0;
4258       magics.s = 0;
4259       ShiftMask = 0;
4260     } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
4261       // If d > 0 and m < 0, add the numerator.
4262       NumeratorFactor = 1;
4263     } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
4264       // If d < 0 and m > 0, subtract the numerator.
4265       NumeratorFactor = -1;
4266     }
4267 
4268     MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
4269     Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
4270     Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT));
4271     ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
4272     return true;
4273   };
4274 
4275   SDValue N0 = N->getOperand(0);
4276   SDValue N1 = N->getOperand(1);
4277 
4278   // Collect the shifts / magic values from each element.
4279   if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
4280     return SDValue();
4281 
4282   SDValue MagicFactor, Factor, Shift, ShiftMask;
4283   if (VT.isVector()) {
4284     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
4285     Factor = DAG.getBuildVector(VT, dl, Factors);
4286     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4287     ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
4288   } else {
4289     MagicFactor = MagicFactors[0];
4290     Factor = Factors[0];
4291     Shift = Shifts[0];
4292     ShiftMask = ShiftMasks[0];
4293   }
4294 
4295   // Multiply the numerator (operand 0) by the magic value.
4296   // FIXME: We should support doing a MUL in a wider type.
4297   SDValue Q;
4298   if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
4299                           : isOperationLegalOrCustom(ISD::MULHS, VT))
4300     Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor);
4301   else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
4302                                : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
4303     SDValue LoHi =
4304         DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
4305     Q = SDValue(LoHi.getNode(), 1);
4306   } else
4307     return SDValue(); // No mulhs or equivalent.
4308   Created.push_back(Q.getNode());
4309 
4310   // (Optionally) Add/subtract the numerator using Factor.
4311   Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
4312   Created.push_back(Factor.getNode());
4313   Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor);
4314   Created.push_back(Q.getNode());
4315 
4316   // Shift right algebraic by shift value.
4317   Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
4318   Created.push_back(Q.getNode());
4319 
4320   // Extract the sign bit, mask it and add it to the quotient.
4321   SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
4322   SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
4323   Created.push_back(T.getNode());
4324   T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
4325   Created.push_back(T.getNode());
4326   return DAG.getNode(ISD::ADD, dl, VT, Q, T);
4327 }
4328 
4329 /// Given an ISD::UDIV node expressing a divide by constant,
4330 /// return a DAG expression to select that will generate the same value by
4331 /// multiplying by a magic number.
4332 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
4333 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
4334                                   bool IsAfterLegalization,
4335                                   SmallVectorImpl<SDNode *> &Created) const {
4336   SDLoc dl(N);
4337   EVT VT = N->getValueType(0);
4338   EVT SVT = VT.getScalarType();
4339   EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4340   EVT ShSVT = ShVT.getScalarType();
4341   unsigned EltBits = VT.getScalarSizeInBits();
4342 
4343   // Check to see if we can do this.
4344   // FIXME: We should be more aggressive here.
4345   if (!isTypeLegal(VT))
4346     return SDValue();
4347 
4348   bool UseNPQ = false;
4349   SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
4350 
4351   auto BuildUDIVPattern = [&](ConstantSDNode *C) {
4352     if (C->isNullValue())
4353       return false;
4354     // FIXME: We should use a narrower constant when the upper
4355     // bits are known to be zero.
4356     APInt Divisor = C->getAPIntValue();
4357     APInt::mu magics = Divisor.magicu();
4358     unsigned PreShift = 0, PostShift = 0;
4359 
4360     // If the divisor is even, we can avoid using the expensive fixup by
4361     // shifting the divided value upfront.
4362     if (magics.a != 0 && !Divisor[0]) {
4363       PreShift = Divisor.countTrailingZeros();
4364       // Get magic number for the shifted divisor.
4365       magics = Divisor.lshr(PreShift).magicu(PreShift);
4366       assert(magics.a == 0 && "Should use cheap fixup now");
4367     }
4368 
4369     APInt Magic = magics.m;
4370 
4371     unsigned SelNPQ;
4372     if (magics.a == 0 || Divisor.isOneValue()) {
4373       assert(magics.s < Divisor.getBitWidth() &&
4374              "We shouldn't generate an undefined shift!");
4375       PostShift = magics.s;
4376       SelNPQ = false;
4377     } else {
4378       PostShift = magics.s - 1;
4379       SelNPQ = true;
4380     }
4381 
4382     PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT));
4383     MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT));
4384     NPQFactors.push_back(
4385         DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1)
4386                                : APInt::getNullValue(EltBits),
4387                         dl, SVT));
4388     PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT));
4389     UseNPQ |= SelNPQ;
4390     return true;
4391   };
4392 
4393   SDValue N0 = N->getOperand(0);
4394   SDValue N1 = N->getOperand(1);
4395 
4396   // Collect the shifts/magic values from each element.
4397   if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern))
4398     return SDValue();
4399 
4400   SDValue PreShift, PostShift, MagicFactor, NPQFactor;
4401   if (VT.isVector()) {
4402     PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
4403     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
4404     NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
4405     PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
4406   } else {
4407     PreShift = PreShifts[0];
4408     MagicFactor = MagicFactors[0];
4409     PostShift = PostShifts[0];
4410   }
4411 
4412   SDValue Q = N0;
4413   Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift);
4414   Created.push_back(Q.getNode());
4415 
4416   // FIXME: We should support doing a MUL in a wider type.
4417   auto GetMULHU = [&](SDValue X, SDValue Y) {
4418     if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
4419                             : isOperationLegalOrCustom(ISD::MULHU, VT))
4420       return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
4421     if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
4422                             : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
4423       SDValue LoHi =
4424           DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
4425       return SDValue(LoHi.getNode(), 1);
4426     }
4427     return SDValue(); // No mulhu or equivalent
4428   };
4429 
4430   // Multiply the numerator (operand 0) by the magic value.
4431   Q = GetMULHU(Q, MagicFactor);
4432   if (!Q)
4433     return SDValue();
4434 
4435   Created.push_back(Q.getNode());
4436 
4437   if (UseNPQ) {
4438     SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
4439     Created.push_back(NPQ.getNode());
4440 
4441     // For vectors we might have a mix of non-NPQ/NPQ paths, so use
4442     // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
4443     if (VT.isVector())
4444       NPQ = GetMULHU(NPQ, NPQFactor);
4445     else
4446       NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT));
4447 
4448     Created.push_back(NPQ.getNode());
4449 
4450     Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
4451     Created.push_back(Q.getNode());
4452   }
4453 
4454   Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
4455   Created.push_back(Q.getNode());
4456 
4457   SDValue One = DAG.getConstant(1, dl, VT);
4458   SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
4459   return DAG.getSelect(dl, VT, IsOne, N0, Q);
4460 }
4461 
4462 /// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE
4463 /// where the divisor is constant and the comparison target is zero,
4464 /// return a DAG expression that will generate the same comparison result
4465 /// using only multiplications, additions and shifts/rotations.
4466 /// Ref: "Hacker's Delight" 10-17.
4467 SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode,
4468                                         SDValue CompTargetNode,
4469                                         ISD::CondCode Cond,
4470                                         DAGCombinerInfo &DCI,
4471                                         const SDLoc &DL) const {
4472   SmallVector<SDNode *, 2> Built;
4473   if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
4474                                          DCI, DL, Built)) {
4475     for (SDNode *N : Built)
4476       DCI.AddToWorklist(N);
4477     return Folded;
4478   }
4479 
4480   return SDValue();
4481 }
4482 
4483 SDValue
4484 TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4485                                   SDValue CompTargetNode, ISD::CondCode Cond,
4486                                   DAGCombinerInfo &DCI, const SDLoc &DL,
4487                                   SmallVectorImpl<SDNode *> &Created) const {
4488   // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q)
4489   // - D must be constant with D = D0 * 2^K where D0 is odd and D0 != 1
4490   // - P is the multiplicative inverse of D0 modulo 2^W
4491   // - Q = floor((2^W - 1) / D0)
4492   // where W is the width of the common type of N and D.
4493   assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4494          "Only applicable for (in)equality comparisons.");
4495 
4496   EVT VT = REMNode.getValueType();
4497 
4498   // If MUL is unavailable, we cannot proceed in any case.
4499   if (!isOperationLegalOrCustom(ISD::MUL, VT))
4500     return SDValue();
4501 
4502   // TODO: Add non-uniform constant support.
4503   ConstantSDNode *Divisor = isConstOrConstSplat(REMNode->getOperand(1));
4504   ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode);
4505   if (!Divisor || !CompTarget || Divisor->isNullValue() ||
4506       !CompTarget->isNullValue())
4507     return SDValue();
4508 
4509   const APInt &D = Divisor->getAPIntValue();
4510 
4511   // Decompose D into D0 * 2^K
4512   unsigned K = D.countTrailingZeros();
4513   bool DivisorIsEven = (K != 0);
4514   APInt D0 = D.lshr(K);
4515 
4516   // The fold is invalid when D0 == 1.
4517   // This is reachable because visitSetCC happens before visitREM.
4518   if (D0.isOneValue())
4519     return SDValue();
4520 
4521   // P = inv(D0, 2^W)
4522   // 2^W requires W + 1 bits, so we have to extend and then truncate.
4523   unsigned W = D.getBitWidth();
4524   APInt P = D0.zext(W + 1)
4525                 .multiplicativeInverse(APInt::getSignedMinValue(W + 1))
4526                 .trunc(W);
4527   assert(!P.isNullValue() && "No multiplicative inverse!"); // unreachable
4528   assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.");
4529 
4530   // Q = floor((2^W - 1) / D)
4531   APInt Q = APInt::getAllOnesValue(W).udiv(D);
4532 
4533   SelectionDAG &DAG = DCI.DAG;
4534 
4535   SDValue PVal = DAG.getConstant(P, DL, VT);
4536   SDValue QVal = DAG.getConstant(Q, DL, VT);
4537   // (mul N, P)
4538   SDValue Op1 = DAG.getNode(ISD::MUL, DL, VT, REMNode->getOperand(0), PVal);
4539   Created.push_back(Op1.getNode());
4540 
4541   // Rotate right only if D was even.
4542   if (DivisorIsEven) {
4543     // We need ROTR to do this.
4544     if (!isOperationLegalOrCustom(ISD::ROTR, VT))
4545       return SDValue();
4546     SDValue ShAmt =
4547         DAG.getConstant(K, DL, getShiftAmountTy(VT, DAG.getDataLayout()));
4548     SDNodeFlags Flags;
4549     Flags.setExact(true);
4550     // UREM: (rotr (mul N, P), K)
4551     Op1 = DAG.getNode(ISD::ROTR, DL, VT, Op1, ShAmt, Flags);
4552     Created.push_back(Op1.getNode());
4553   }
4554 
4555   // UREM: (setule/setugt (rotr (mul N, P), K), Q)
4556   return DAG.getSetCC(DL, SETCCVT, Op1, QVal,
4557                       ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
4558 }
4559 
4560 bool TargetLowering::
4561 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
4562   if (!isa<ConstantSDNode>(Op.getOperand(0))) {
4563     DAG.getContext()->emitError("argument to '__builtin_return_address' must "
4564                                 "be a constant integer");
4565     return true;
4566   }
4567 
4568   return false;
4569 }
4570 
4571 //===----------------------------------------------------------------------===//
4572 // Legalization Utilities
4573 //===----------------------------------------------------------------------===//
4574 
4575 bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl,
4576                                     SDValue LHS, SDValue RHS,
4577                                     SmallVectorImpl<SDValue> &Result,
4578                                     EVT HiLoVT, SelectionDAG &DAG,
4579                                     MulExpansionKind Kind, SDValue LL,
4580                                     SDValue LH, SDValue RL, SDValue RH) const {
4581   assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
4582          Opcode == ISD::SMUL_LOHI);
4583 
4584   bool HasMULHS = (Kind == MulExpansionKind::Always) ||
4585                   isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
4586   bool HasMULHU = (Kind == MulExpansionKind::Always) ||
4587                   isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
4588   bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) ||
4589                       isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
4590   bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) ||
4591                       isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
4592 
4593   if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
4594     return false;
4595 
4596   unsigned OuterBitSize = VT.getScalarSizeInBits();
4597   unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
4598   unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
4599   unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
4600 
4601   // LL, LH, RL, and RH must be either all NULL or all set to a value.
4602   assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
4603          (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
4604 
4605   SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
4606   auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi,
4607                           bool Signed) -> bool {
4608     if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) {
4609       Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
4610       Hi = SDValue(Lo.getNode(), 1);
4611       return true;
4612     }
4613     if ((Signed && HasMULHS) || (!Signed && HasMULHU)) {
4614       Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
4615       Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
4616       return true;
4617     }
4618     return false;
4619   };
4620 
4621   SDValue Lo, Hi;
4622 
4623   if (!LL.getNode() && !RL.getNode() &&
4624       isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
4625     LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
4626     RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
4627   }
4628 
4629   if (!LL.getNode())
4630     return false;
4631 
4632   APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
4633   if (DAG.MaskedValueIsZero(LHS, HighMask) &&
4634       DAG.MaskedValueIsZero(RHS, HighMask)) {
4635     // The inputs are both zero-extended.
4636     if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
4637       Result.push_back(Lo);
4638       Result.push_back(Hi);
4639       if (Opcode != ISD::MUL) {
4640         SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
4641         Result.push_back(Zero);
4642         Result.push_back(Zero);
4643       }
4644       return true;
4645     }
4646   }
4647 
4648   if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
4649       RHSSB > InnerBitSize) {
4650     // The input values are both sign-extended.
4651     // TODO non-MUL case?
4652     if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
4653       Result.push_back(Lo);
4654       Result.push_back(Hi);
4655       return true;
4656     }
4657   }
4658 
4659   unsigned ShiftAmount = OuterBitSize - InnerBitSize;
4660   EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
4661   if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
4662     // FIXME getShiftAmountTy does not always return a sensible result when VT
4663     // is an illegal type, and so the type may be too small to fit the shift
4664     // amount. Override it with i32. The shift will have to be legalized.
4665     ShiftAmountTy = MVT::i32;
4666   }
4667   SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
4668 
4669   if (!LH.getNode() && !RH.getNode() &&
4670       isOperationLegalOrCustom(ISD::SRL, VT) &&
4671       isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
4672     LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
4673     LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
4674     RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
4675     RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
4676   }
4677 
4678   if (!LH.getNode())
4679     return false;
4680 
4681   if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
4682     return false;
4683 
4684   Result.push_back(Lo);
4685 
4686   if (Opcode == ISD::MUL) {
4687     RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
4688     LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
4689     Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
4690     Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
4691     Result.push_back(Hi);
4692     return true;
4693   }
4694 
4695   // Compute the full width result.
4696   auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue {
4697     Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
4698     Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
4699     Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
4700     return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
4701   };
4702 
4703   SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
4704   if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
4705     return false;
4706 
4707   // This is effectively the add part of a multiply-add of half-sized operands,
4708   // so it cannot overflow.
4709   Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
4710 
4711   if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
4712     return false;
4713 
4714   SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
4715   EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
4716 
4717   bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&
4718                   isOperationLegalOrCustom(ISD::ADDE, VT));
4719   if (UseGlue)
4720     Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
4721                        Merge(Lo, Hi));
4722   else
4723     Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
4724                        Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType));
4725 
4726   SDValue Carry = Next.getValue(1);
4727   Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4728   Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
4729 
4730   if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
4731     return false;
4732 
4733   if (UseGlue)
4734     Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
4735                      Carry);
4736   else
4737     Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
4738                      Zero, Carry);
4739 
4740   Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
4741 
4742   if (Opcode == ISD::SMUL_LOHI) {
4743     SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
4744                                   DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
4745     Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
4746 
4747     NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
4748                           DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
4749     Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
4750   }
4751 
4752   Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4753   Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
4754   Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4755   return true;
4756 }
4757 
4758 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
4759                                SelectionDAG &DAG, MulExpansionKind Kind,
4760                                SDValue LL, SDValue LH, SDValue RL,
4761                                SDValue RH) const {
4762   SmallVector<SDValue, 2> Result;
4763   bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
4764                            N->getOperand(0), N->getOperand(1), Result, HiLoVT,
4765                            DAG, Kind, LL, LH, RL, RH);
4766   if (Ok) {
4767     assert(Result.size() == 2);
4768     Lo = Result[0];
4769     Hi = Result[1];
4770   }
4771   return Ok;
4772 }
4773 
4774 bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
4775                                        SelectionDAG &DAG) const {
4776   EVT VT = Node->getValueType(0);
4777 
4778   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
4779                         !isOperationLegalOrCustom(ISD::SRL, VT) ||
4780                         !isOperationLegalOrCustom(ISD::SUB, VT) ||
4781                         !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
4782     return false;
4783 
4784   // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
4785   // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
4786   SDValue X = Node->getOperand(0);
4787   SDValue Y = Node->getOperand(1);
4788   SDValue Z = Node->getOperand(2);
4789 
4790   unsigned EltSizeInBits = VT.getScalarSizeInBits();
4791   bool IsFSHL = Node->getOpcode() == ISD::FSHL;
4792   SDLoc DL(SDValue(Node, 0));
4793 
4794   EVT ShVT = Z.getValueType();
4795   SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT);
4796   SDValue Zero = DAG.getConstant(0, DL, ShVT);
4797 
4798   SDValue ShAmt;
4799   if (isPowerOf2_32(EltSizeInBits)) {
4800     SDValue Mask = DAG.getConstant(EltSizeInBits - 1, DL, ShVT);
4801     ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask);
4802   } else {
4803     ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC);
4804   }
4805 
4806   SDValue InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt);
4807   SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt);
4808   SDValue ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt);
4809   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
4810 
4811   // If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
4812   // and that is undefined. We must compare and select to avoid UB.
4813   EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ShVT);
4814 
4815   // For fshl, 0-shift returns the 1st arg (X).
4816   // For fshr, 0-shift returns the 2nd arg (Y).
4817   SDValue IsZeroShift = DAG.getSetCC(DL, CCVT, ShAmt, Zero, ISD::SETEQ);
4818   Result = DAG.getSelect(DL, VT, IsZeroShift, IsFSHL ? X : Y, Or);
4819   return true;
4820 }
4821 
4822 // TODO: Merge with expandFunnelShift.
4823 bool TargetLowering::expandROT(SDNode *Node, SDValue &Result,
4824                                SelectionDAG &DAG) const {
4825   EVT VT = Node->getValueType(0);
4826   unsigned EltSizeInBits = VT.getScalarSizeInBits();
4827   bool IsLeft = Node->getOpcode() == ISD::ROTL;
4828   SDValue Op0 = Node->getOperand(0);
4829   SDValue Op1 = Node->getOperand(1);
4830   SDLoc DL(SDValue(Node, 0));
4831 
4832   EVT ShVT = Op1.getValueType();
4833   SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT);
4834 
4835   // If a rotate in the other direction is legal, use it.
4836   unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
4837   if (isOperationLegal(RevRot, VT)) {
4838     SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
4839     Result = DAG.getNode(RevRot, DL, VT, Op0, Sub);
4840     return true;
4841   }
4842 
4843   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
4844                         !isOperationLegalOrCustom(ISD::SRL, VT) ||
4845                         !isOperationLegalOrCustom(ISD::SUB, VT) ||
4846                         !isOperationLegalOrCustomOrPromote(ISD::OR, VT) ||
4847                         !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
4848     return false;
4849 
4850   // Otherwise,
4851   //   (rotl x, c) -> (or (shl x, (and c, w-1)), (srl x, (and w-c, w-1)))
4852   //   (rotr x, c) -> (or (srl x, (and c, w-1)), (shl x, (and w-c, w-1)))
4853   //
4854   assert(isPowerOf2_32(EltSizeInBits) && EltSizeInBits > 1 &&
4855          "Expecting the type bitwidth to be a power of 2");
4856   unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
4857   unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
4858   SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT);
4859   SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
4860   SDValue And0 = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC);
4861   SDValue And1 = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC);
4862   Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
4863                        DAG.getNode(HsOpc, DL, VT, Op0, And1));
4864   return true;
4865 }
4866 
4867 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
4868                                       SelectionDAG &DAG) const {
4869   SDValue Src = Node->getOperand(0);
4870   EVT SrcVT = Src.getValueType();
4871   EVT DstVT = Node->getValueType(0);
4872   SDLoc dl(SDValue(Node, 0));
4873 
4874   // FIXME: Only f32 to i64 conversions are supported.
4875   if (SrcVT != MVT::f32 || DstVT != MVT::i64)
4876     return false;
4877 
4878   // Expand f32 -> i64 conversion
4879   // This algorithm comes from compiler-rt's implementation of fixsfdi:
4880   // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c
4881   unsigned SrcEltBits = SrcVT.getScalarSizeInBits();
4882   EVT IntVT = SrcVT.changeTypeToInteger();
4883   EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout());
4884 
4885   SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
4886   SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
4887   SDValue Bias = DAG.getConstant(127, dl, IntVT);
4888   SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT);
4889   SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT);
4890   SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
4891 
4892   SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src);
4893 
4894   SDValue ExponentBits = DAG.getNode(
4895       ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
4896       DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT));
4897   SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
4898 
4899   SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
4900                              DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
4901                              DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT));
4902   Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT);
4903 
4904   SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
4905                           DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
4906                           DAG.getConstant(0x00800000, dl, IntVT));
4907 
4908   R = DAG.getZExtOrTrunc(R, dl, DstVT);
4909 
4910   R = DAG.getSelectCC(
4911       dl, Exponent, ExponentLoBit,
4912       DAG.getNode(ISD::SHL, dl, DstVT, R,
4913                   DAG.getZExtOrTrunc(
4914                       DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
4915                       dl, IntShVT)),
4916       DAG.getNode(ISD::SRL, dl, DstVT, R,
4917                   DAG.getZExtOrTrunc(
4918                       DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
4919                       dl, IntShVT)),
4920       ISD::SETGT);
4921 
4922   SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT,
4923                             DAG.getNode(ISD::XOR, dl, DstVT, R, Sign), Sign);
4924 
4925   Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
4926                            DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT);
4927   return true;
4928 }
4929 
4930 bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result,
4931                                       SelectionDAG &DAG) const {
4932   SDLoc dl(SDValue(Node, 0));
4933   SDValue Src = Node->getOperand(0);
4934 
4935   EVT SrcVT = Src.getValueType();
4936   EVT DstVT = Node->getValueType(0);
4937   EVT SetCCVT =
4938       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
4939 
4940   // Only expand vector types if we have the appropriate vector bit operations.
4941   if (DstVT.isVector() && (!isOperationLegalOrCustom(ISD::FP_TO_SINT, DstVT) ||
4942                            !isOperationLegalOrCustomOrPromote(ISD::XOR, SrcVT)))
4943     return false;
4944 
4945   // If the maximum float value is smaller then the signed integer range,
4946   // the destination signmask can't be represented by the float, so we can
4947   // just use FP_TO_SINT directly.
4948   const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT);
4949   APFloat APF(APFSem, APInt::getNullValue(SrcVT.getScalarSizeInBits()));
4950   APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits());
4951   if (APFloat::opOverflow &
4952       APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) {
4953     Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
4954     return true;
4955   }
4956 
4957   SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT);
4958   SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT);
4959 
4960   bool Strict = shouldUseStrictFP_TO_INT(SrcVT, DstVT, /*IsSigned*/ false);
4961   if (Strict) {
4962     // Expand based on maximum range of FP_TO_SINT, if the value exceeds the
4963     // signmask then offset (the result of which should be fully representable).
4964     // Sel = Src < 0x8000000000000000
4965     // Val = select Sel, Src, Src - 0x8000000000000000
4966     // Ofs = select Sel, 0, 0x8000000000000000
4967     // Result = fp_to_sint(Val) ^ Ofs
4968 
4969     // TODO: Should any fast-math-flags be set for the FSUB?
4970     SDValue Val = DAG.getSelect(dl, SrcVT, Sel, Src,
4971                                 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
4972     SDValue Ofs = DAG.getSelect(dl, DstVT, Sel, DAG.getConstant(0, dl, DstVT),
4973                                 DAG.getConstant(SignMask, dl, DstVT));
4974     Result = DAG.getNode(ISD::XOR, dl, DstVT,
4975                          DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val), Ofs);
4976   } else {
4977     // Expand based on maximum range of FP_TO_SINT:
4978     // True = fp_to_sint(Src)
4979     // False = 0x8000000000000000 + fp_to_sint(Src - 0x8000000000000000)
4980     // Result = select (Src < 0x8000000000000000), True, False
4981 
4982     SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
4983     // TODO: Should any fast-math-flags be set for the FSUB?
4984     SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT,
4985                                 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
4986     False = DAG.getNode(ISD::XOR, dl, DstVT, False,
4987                         DAG.getConstant(SignMask, dl, DstVT));
4988     Result = DAG.getSelect(dl, DstVT, Sel, True, False);
4989   }
4990   return true;
4991 }
4992 
4993 bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
4994                                       SelectionDAG &DAG) const {
4995   SDValue Src = Node->getOperand(0);
4996   EVT SrcVT = Src.getValueType();
4997   EVT DstVT = Node->getValueType(0);
4998 
4999   if (SrcVT.getScalarType() != MVT::i64)
5000     return false;
5001 
5002   SDLoc dl(SDValue(Node, 0));
5003   EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout());
5004 
5005   if (DstVT.getScalarType() == MVT::f32) {
5006     // Only expand vector types if we have the appropriate vector bit
5007     // operations.
5008     if (SrcVT.isVector() &&
5009         (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||
5010          !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
5011          !isOperationLegalOrCustom(ISD::SINT_TO_FP, SrcVT) ||
5012          !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
5013          !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
5014       return false;
5015 
5016     // For unsigned conversions, convert them to signed conversions using the
5017     // algorithm from the x86_64 __floatundidf in compiler_rt.
5018     SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Src);
5019 
5020     SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
5021     SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Src, ShiftConst);
5022     SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
5023     SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Src, AndConst);
5024     SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
5025 
5026     SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Or);
5027     SDValue Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
5028 
5029     // TODO: This really should be implemented using a branch rather than a
5030     // select.  We happen to get lucky and machinesink does the right
5031     // thing most of the time.  This would be a good candidate for a
5032     // pseudo-op, or, even better, for whole-function isel.
5033     EVT SetCCVT =
5034         getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
5035 
5036     SDValue SignBitTest = DAG.getSetCC(
5037         dl, SetCCVT, Src, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
5038     Result = DAG.getSelect(dl, DstVT, SignBitTest, Slow, Fast);
5039     return true;
5040   }
5041 
5042   if (DstVT.getScalarType() == MVT::f64) {
5043     // Only expand vector types if we have the appropriate vector bit
5044     // operations.
5045     if (SrcVT.isVector() &&
5046         (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||
5047          !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
5048          !isOperationLegalOrCustom(ISD::FSUB, DstVT) ||
5049          !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
5050          !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
5051       return false;
5052 
5053     // Implementation of unsigned i64 to f64 following the algorithm in
5054     // __floatundidf in compiler_rt. This implementation has the advantage
5055     // of performing rounding correctly, both in the default rounding mode
5056     // and in all alternate rounding modes.
5057     SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, SrcVT);
5058     SDValue TwoP84PlusTwoP52 = DAG.getConstantFP(
5059         BitsToDouble(UINT64_C(0x4530000000100000)), dl, DstVT);
5060     SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000), dl, SrcVT);
5061     SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF), dl, SrcVT);
5062     SDValue HiShift = DAG.getConstant(32, dl, ShiftVT);
5063 
5064     SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask);
5065     SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift);
5066     SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52);
5067     SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84);
5068     SDValue LoFlt = DAG.getBitcast(DstVT, LoOr);
5069     SDValue HiFlt = DAG.getBitcast(DstVT, HiOr);
5070     SDValue HiSub = DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52);
5071     Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
5072     return true;
5073   }
5074 
5075   return false;
5076 }
5077 
5078 SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
5079                                               SelectionDAG &DAG) const {
5080   SDLoc dl(Node);
5081   unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
5082     ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
5083   EVT VT = Node->getValueType(0);
5084   if (isOperationLegalOrCustom(NewOp, VT)) {
5085     SDValue Quiet0 = Node->getOperand(0);
5086     SDValue Quiet1 = Node->getOperand(1);
5087 
5088     if (!Node->getFlags().hasNoNaNs()) {
5089       // Insert canonicalizes if it's possible we need to quiet to get correct
5090       // sNaN behavior.
5091       if (!DAG.isKnownNeverSNaN(Quiet0)) {
5092         Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0,
5093                              Node->getFlags());
5094       }
5095       if (!DAG.isKnownNeverSNaN(Quiet1)) {
5096         Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1,
5097                              Node->getFlags());
5098       }
5099     }
5100 
5101     return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags());
5102   }
5103 
5104   // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that
5105   // instead if there are no NaNs.
5106   if (Node->getFlags().hasNoNaNs()) {
5107     unsigned IEEE2018Op =
5108         Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
5109     if (isOperationLegalOrCustom(IEEE2018Op, VT)) {
5110       return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0),
5111                          Node->getOperand(1), Node->getFlags());
5112     }
5113   }
5114 
5115   return SDValue();
5116 }
5117 
5118 bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
5119                                  SelectionDAG &DAG) const {
5120   SDLoc dl(Node);
5121   EVT VT = Node->getValueType(0);
5122   EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5123   SDValue Op = Node->getOperand(0);
5124   unsigned Len = VT.getScalarSizeInBits();
5125   assert(VT.isInteger() && "CTPOP not implemented for this type.");
5126 
5127   // TODO: Add support for irregular type lengths.
5128   if (!(Len <= 128 && Len % 8 == 0))
5129     return false;
5130 
5131   // Only expand vector types if we have the appropriate vector bit operations.
5132   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) ||
5133                         !isOperationLegalOrCustom(ISD::SUB, VT) ||
5134                         !isOperationLegalOrCustom(ISD::SRL, VT) ||
5135                         (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) ||
5136                         !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
5137     return false;
5138 
5139   // This is the "best" algorithm from
5140   // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
5141   SDValue Mask55 =
5142       DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT);
5143   SDValue Mask33 =
5144       DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT);
5145   SDValue Mask0F =
5146       DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT);
5147   SDValue Mask01 =
5148       DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT);
5149 
5150   // v = v - ((v >> 1) & 0x55555555...)
5151   Op = DAG.getNode(ISD::SUB, dl, VT, Op,
5152                    DAG.getNode(ISD::AND, dl, VT,
5153                                DAG.getNode(ISD::SRL, dl, VT, Op,
5154                                            DAG.getConstant(1, dl, ShVT)),
5155                                Mask55));
5156   // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
5157   Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
5158                    DAG.getNode(ISD::AND, dl, VT,
5159                                DAG.getNode(ISD::SRL, dl, VT, Op,
5160                                            DAG.getConstant(2, dl, ShVT)),
5161                                Mask33));
5162   // v = (v + (v >> 4)) & 0x0F0F0F0F...
5163   Op = DAG.getNode(ISD::AND, dl, VT,
5164                    DAG.getNode(ISD::ADD, dl, VT, Op,
5165                                DAG.getNode(ISD::SRL, dl, VT, Op,
5166                                            DAG.getConstant(4, dl, ShVT))),
5167                    Mask0F);
5168   // v = (v * 0x01010101...) >> (Len - 8)
5169   if (Len > 8)
5170     Op =
5171         DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
5172                     DAG.getConstant(Len - 8, dl, ShVT));
5173 
5174   Result = Op;
5175   return true;
5176 }
5177 
5178 bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
5179                                 SelectionDAG &DAG) const {
5180   SDLoc dl(Node);
5181   EVT VT = Node->getValueType(0);
5182   EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5183   SDValue Op = Node->getOperand(0);
5184   unsigned NumBitsPerElt = VT.getScalarSizeInBits();
5185 
5186   // If the non-ZERO_UNDEF version is supported we can use that instead.
5187   if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
5188       isOperationLegalOrCustom(ISD::CTLZ, VT)) {
5189     Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
5190     return true;
5191   }
5192 
5193   // If the ZERO_UNDEF version is supported use that and handle the zero case.
5194   if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
5195     EVT SetCCVT =
5196         getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5197     SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
5198     SDValue Zero = DAG.getConstant(0, dl, VT);
5199     SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
5200     Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
5201                          DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
5202     return true;
5203   }
5204 
5205   // Only expand vector types if we have the appropriate vector bit operations.
5206   if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
5207                         !isOperationLegalOrCustom(ISD::CTPOP, VT) ||
5208                         !isOperationLegalOrCustom(ISD::SRL, VT) ||
5209                         !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
5210     return false;
5211 
5212   // for now, we do this:
5213   // x = x | (x >> 1);
5214   // x = x | (x >> 2);
5215   // ...
5216   // x = x | (x >>16);
5217   // x = x | (x >>32); // for 64-bit input
5218   // return popcount(~x);
5219   //
5220   // Ref: "Hacker's Delight" by Henry Warren
5221   for (unsigned i = 0; (1U << i) <= (NumBitsPerElt / 2); ++i) {
5222     SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT);
5223     Op = DAG.getNode(ISD::OR, dl, VT, Op,
5224                      DAG.getNode(ISD::SRL, dl, VT, Op, Tmp));
5225   }
5226   Op = DAG.getNOT(dl, Op, VT);
5227   Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
5228   return true;
5229 }
5230 
5231 bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
5232                                 SelectionDAG &DAG) const {
5233   SDLoc dl(Node);
5234   EVT VT = Node->getValueType(0);
5235   SDValue Op = Node->getOperand(0);
5236   unsigned NumBitsPerElt = VT.getScalarSizeInBits();
5237 
5238   // If the non-ZERO_UNDEF version is supported we can use that instead.
5239   if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
5240       isOperationLegalOrCustom(ISD::CTTZ, VT)) {
5241     Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
5242     return true;
5243   }
5244 
5245   // If the ZERO_UNDEF version is supported use that and handle the zero case.
5246   if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
5247     EVT SetCCVT =
5248         getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5249     SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
5250     SDValue Zero = DAG.getConstant(0, dl, VT);
5251     SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
5252     Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
5253                          DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
5254     return true;
5255   }
5256 
5257   // Only expand vector types if we have the appropriate vector bit operations.
5258   if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
5259                         (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&
5260                          !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
5261                         !isOperationLegalOrCustom(ISD::SUB, VT) ||
5262                         !isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
5263                         !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
5264     return false;
5265 
5266   // for now, we use: { return popcount(~x & (x - 1)); }
5267   // unless the target has ctlz but not ctpop, in which case we use:
5268   // { return 32 - nlz(~x & (x-1)); }
5269   // Ref: "Hacker's Delight" by Henry Warren
5270   SDValue Tmp = DAG.getNode(
5271       ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT),
5272       DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT)));
5273 
5274   // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5275   if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
5276     Result =
5277         DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
5278                     DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
5279     return true;
5280   }
5281 
5282   Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
5283   return true;
5284 }
5285 
5286 bool TargetLowering::expandABS(SDNode *N, SDValue &Result,
5287                                SelectionDAG &DAG) const {
5288   SDLoc dl(N);
5289   EVT VT = N->getValueType(0);
5290   EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5291   SDValue Op = N->getOperand(0);
5292 
5293   // Only expand vector types if we have the appropriate vector operations.
5294   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) ||
5295                         !isOperationLegalOrCustom(ISD::ADD, VT) ||
5296                         !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
5297     return false;
5298 
5299   SDValue Shift =
5300       DAG.getNode(ISD::SRA, dl, VT, Op,
5301                   DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT));
5302   SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift);
5303   Result = DAG.getNode(ISD::XOR, dl, VT, Add, Shift);
5304   return true;
5305 }
5306 
5307 SDValue TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
5308                                             SelectionDAG &DAG) const {
5309   SDLoc SL(LD);
5310   SDValue Chain = LD->getChain();
5311   SDValue BasePTR = LD->getBasePtr();
5312   EVT SrcVT = LD->getMemoryVT();
5313   ISD::LoadExtType ExtType = LD->getExtensionType();
5314 
5315   unsigned NumElem = SrcVT.getVectorNumElements();
5316 
5317   EVT SrcEltVT = SrcVT.getScalarType();
5318   EVT DstEltVT = LD->getValueType(0).getScalarType();
5319 
5320   unsigned Stride = SrcEltVT.getSizeInBits() / 8;
5321   assert(SrcEltVT.isByteSized());
5322 
5323   SmallVector<SDValue, 8> Vals;
5324   SmallVector<SDValue, 8> LoadChains;
5325 
5326   for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
5327     SDValue ScalarLoad =
5328         DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
5329                        LD->getPointerInfo().getWithOffset(Idx * Stride),
5330                        SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
5331                        LD->getMemOperand()->getFlags(), LD->getAAInfo());
5332 
5333     BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, Stride);
5334 
5335     Vals.push_back(ScalarLoad.getValue(0));
5336     LoadChains.push_back(ScalarLoad.getValue(1));
5337   }
5338 
5339   SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains);
5340   SDValue Value = DAG.getBuildVector(LD->getValueType(0), SL, Vals);
5341 
5342   return DAG.getMergeValues({Value, NewChain}, SL);
5343 }
5344 
5345 SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
5346                                              SelectionDAG &DAG) const {
5347   SDLoc SL(ST);
5348 
5349   SDValue Chain = ST->getChain();
5350   SDValue BasePtr = ST->getBasePtr();
5351   SDValue Value = ST->getValue();
5352   EVT StVT = ST->getMemoryVT();
5353 
5354   // The type of the data we want to save
5355   EVT RegVT = Value.getValueType();
5356   EVT RegSclVT = RegVT.getScalarType();
5357 
5358   // The type of data as saved in memory.
5359   EVT MemSclVT = StVT.getScalarType();
5360 
5361   EVT IdxVT = getVectorIdxTy(DAG.getDataLayout());
5362   unsigned NumElem = StVT.getVectorNumElements();
5363 
5364   // A vector must always be stored in memory as-is, i.e. without any padding
5365   // between the elements, since various code depend on it, e.g. in the
5366   // handling of a bitcast of a vector type to int, which may be done with a
5367   // vector store followed by an integer load. A vector that does not have
5368   // elements that are byte-sized must therefore be stored as an integer
5369   // built out of the extracted vector elements.
5370   if (!MemSclVT.isByteSized()) {
5371     unsigned NumBits = StVT.getSizeInBits();
5372     EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
5373 
5374     SDValue CurrVal = DAG.getConstant(0, SL, IntVT);
5375 
5376     for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
5377       SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
5378                                 DAG.getConstant(Idx, SL, IdxVT));
5379       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt);
5380       SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
5381       unsigned ShiftIntoIdx =
5382           (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
5383       SDValue ShiftAmount =
5384           DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT);
5385       SDValue ShiftedElt =
5386           DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
5387       CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
5388     }
5389 
5390     return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
5391                         ST->getAlignment(), ST->getMemOperand()->getFlags(),
5392                         ST->getAAInfo());
5393   }
5394 
5395   // Store Stride in bytes
5396   unsigned Stride = MemSclVT.getSizeInBits() / 8;
5397   assert(Stride && "Zero stride!");
5398   // Extract each of the elements from the original vector and save them into
5399   // memory individually.
5400   SmallVector<SDValue, 8> Stores;
5401   for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
5402     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
5403                               DAG.getConstant(Idx, SL, IdxVT));
5404 
5405     SDValue Ptr = DAG.getObjectPtrOffset(SL, BasePtr, Idx * Stride);
5406 
5407     // This scalar TruncStore may be illegal, but we legalize it later.
5408     SDValue Store = DAG.getTruncStore(
5409         Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
5410         MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride),
5411         ST->getMemOperand()->getFlags(), ST->getAAInfo());
5412 
5413     Stores.push_back(Store);
5414   }
5415 
5416   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores);
5417 }
5418 
5419 std::pair<SDValue, SDValue>
5420 TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
5421   assert(LD->getAddressingMode() == ISD::UNINDEXED &&
5422          "unaligned indexed loads not implemented!");
5423   SDValue Chain = LD->getChain();
5424   SDValue Ptr = LD->getBasePtr();
5425   EVT VT = LD->getValueType(0);
5426   EVT LoadedVT = LD->getMemoryVT();
5427   SDLoc dl(LD);
5428   auto &MF = DAG.getMachineFunction();
5429 
5430   if (VT.isFloatingPoint() || VT.isVector()) {
5431     EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
5432     if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) {
5433       if (!isOperationLegalOrCustom(ISD::LOAD, intVT) &&
5434           LoadedVT.isVector()) {
5435         // Scalarize the load and let the individual components be handled.
5436         SDValue Scalarized = scalarizeVectorLoad(LD, DAG);
5437         if (Scalarized->getOpcode() == ISD::MERGE_VALUES)
5438           return std::make_pair(Scalarized.getOperand(0), Scalarized.getOperand(1));
5439         return std::make_pair(Scalarized.getValue(0), Scalarized.getValue(1));
5440       }
5441 
5442       // Expand to a (misaligned) integer load of the same size,
5443       // then bitconvert to floating point or vector.
5444       SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
5445                                     LD->getMemOperand());
5446       SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
5447       if (LoadedVT != VT)
5448         Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
5449                              ISD::ANY_EXTEND, dl, VT, Result);
5450 
5451       return std::make_pair(Result, newLoad.getValue(1));
5452     }
5453 
5454     // Copy the value to a (aligned) stack slot using (unaligned) integer
5455     // loads and stores, then do a (aligned) load from the stack slot.
5456     MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
5457     unsigned LoadedBytes = LoadedVT.getStoreSize();
5458     unsigned RegBytes = RegVT.getSizeInBits() / 8;
5459     unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
5460 
5461     // Make sure the stack slot is also aligned for the register type.
5462     SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
5463     auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex();
5464     SmallVector<SDValue, 8> Stores;
5465     SDValue StackPtr = StackBase;
5466     unsigned Offset = 0;
5467 
5468     EVT PtrVT = Ptr.getValueType();
5469     EVT StackPtrVT = StackPtr.getValueType();
5470 
5471     SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
5472     SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
5473 
5474     // Do all but one copies using the full register width.
5475     for (unsigned i = 1; i < NumRegs; i++) {
5476       // Load one integer register's worth from the original location.
5477       SDValue Load = DAG.getLoad(
5478           RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
5479           MinAlign(LD->getAlignment(), Offset), LD->getMemOperand()->getFlags(),
5480           LD->getAAInfo());
5481       // Follow the load with a store to the stack slot.  Remember the store.
5482       Stores.push_back(DAG.getStore(
5483           Load.getValue(1), dl, Load, StackPtr,
5484           MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset)));
5485       // Increment the pointers.
5486       Offset += RegBytes;
5487 
5488       Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
5489       StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
5490     }
5491 
5492     // The last copy may be partial.  Do an extending load.
5493     EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
5494                                   8 * (LoadedBytes - Offset));
5495     SDValue Load =
5496         DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
5497                        LD->getPointerInfo().getWithOffset(Offset), MemVT,
5498                        MinAlign(LD->getAlignment(), Offset),
5499                        LD->getMemOperand()->getFlags(), LD->getAAInfo());
5500     // Follow the load with a store to the stack slot.  Remember the store.
5501     // On big-endian machines this requires a truncating store to ensure
5502     // that the bits end up in the right place.
5503     Stores.push_back(DAG.getTruncStore(
5504         Load.getValue(1), dl, Load, StackPtr,
5505         MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT));
5506 
5507     // The order of the stores doesn't matter - say it with a TokenFactor.
5508     SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
5509 
5510     // Finally, perform the original load only redirected to the stack slot.
5511     Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
5512                           MachinePointerInfo::getFixedStack(MF, FrameIndex, 0),
5513                           LoadedVT);
5514 
5515     // Callers expect a MERGE_VALUES node.
5516     return std::make_pair(Load, TF);
5517   }
5518 
5519   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
5520          "Unaligned load of unsupported type.");
5521 
5522   // Compute the new VT that is half the size of the old one.  This is an
5523   // integer MVT.
5524   unsigned NumBits = LoadedVT.getSizeInBits();
5525   EVT NewLoadedVT;
5526   NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
5527   NumBits >>= 1;
5528 
5529   unsigned Alignment = LD->getAlignment();
5530   unsigned IncrementSize = NumBits / 8;
5531   ISD::LoadExtType HiExtType = LD->getExtensionType();
5532 
5533   // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
5534   if (HiExtType == ISD::NON_EXTLOAD)
5535     HiExtType = ISD::ZEXTLOAD;
5536 
5537   // Load the value in two parts
5538   SDValue Lo, Hi;
5539   if (DAG.getDataLayout().isLittleEndian()) {
5540     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
5541                         NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
5542                         LD->getAAInfo());
5543 
5544     Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
5545     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
5546                         LD->getPointerInfo().getWithOffset(IncrementSize),
5547                         NewLoadedVT, MinAlign(Alignment, IncrementSize),
5548                         LD->getMemOperand()->getFlags(), LD->getAAInfo());
5549   } else {
5550     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
5551                         NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
5552                         LD->getAAInfo());
5553 
5554     Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
5555     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
5556                         LD->getPointerInfo().getWithOffset(IncrementSize),
5557                         NewLoadedVT, MinAlign(Alignment, IncrementSize),
5558                         LD->getMemOperand()->getFlags(), LD->getAAInfo());
5559   }
5560 
5561   // aggregate the two parts
5562   SDValue ShiftAmount =
5563       DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(),
5564                                                     DAG.getDataLayout()));
5565   SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
5566   Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
5567 
5568   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
5569                              Hi.getValue(1));
5570 
5571   return std::make_pair(Result, TF);
5572 }
5573 
5574 SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
5575                                              SelectionDAG &DAG) const {
5576   assert(ST->getAddressingMode() == ISD::UNINDEXED &&
5577          "unaligned indexed stores not implemented!");
5578   SDValue Chain = ST->getChain();
5579   SDValue Ptr = ST->getBasePtr();
5580   SDValue Val = ST->getValue();
5581   EVT VT = Val.getValueType();
5582   int Alignment = ST->getAlignment();
5583   auto &MF = DAG.getMachineFunction();
5584   EVT StoreMemVT = ST->getMemoryVT();
5585 
5586   SDLoc dl(ST);
5587   if (StoreMemVT.isFloatingPoint() || StoreMemVT.isVector()) {
5588     EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
5589     if (isTypeLegal(intVT)) {
5590       if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&
5591           StoreMemVT.isVector()) {
5592         // Scalarize the store and let the individual components be handled.
5593         SDValue Result = scalarizeVectorStore(ST, DAG);
5594         return Result;
5595       }
5596       // Expand to a bitconvert of the value to the integer type of the
5597       // same size, then a (misaligned) int store.
5598       // FIXME: Does not handle truncating floating point stores!
5599       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
5600       Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
5601                             Alignment, ST->getMemOperand()->getFlags());
5602       return Result;
5603     }
5604     // Do a (aligned) store to a stack slot, then copy from the stack slot
5605     // to the final destination using (unaligned) integer loads and stores.
5606     MVT RegVT = getRegisterType(
5607         *DAG.getContext(),
5608         EVT::getIntegerVT(*DAG.getContext(), StoreMemVT.getSizeInBits()));
5609     EVT PtrVT = Ptr.getValueType();
5610     unsigned StoredBytes = StoreMemVT.getStoreSize();
5611     unsigned RegBytes = RegVT.getSizeInBits() / 8;
5612     unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
5613 
5614     // Make sure the stack slot is also aligned for the register type.
5615     SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT);
5616     auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
5617 
5618     // Perform the original store, only redirected to the stack slot.
5619     SDValue Store = DAG.getTruncStore(
5620         Chain, dl, Val, StackPtr,
5621         MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoreMemVT);
5622 
5623     EVT StackPtrVT = StackPtr.getValueType();
5624 
5625     SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
5626     SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
5627     SmallVector<SDValue, 8> Stores;
5628     unsigned Offset = 0;
5629 
5630     // Do all but one copies using the full register width.
5631     for (unsigned i = 1; i < NumRegs; i++) {
5632       // Load one integer register's worth from the stack slot.
5633       SDValue Load = DAG.getLoad(
5634           RegVT, dl, Store, StackPtr,
5635           MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset));
5636       // Store it to the final location.  Remember the store.
5637       Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
5638                                     ST->getPointerInfo().getWithOffset(Offset),
5639                                     MinAlign(ST->getAlignment(), Offset),
5640                                     ST->getMemOperand()->getFlags()));
5641       // Increment the pointers.
5642       Offset += RegBytes;
5643       StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
5644       Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
5645     }
5646 
5647     // The last store may be partial.  Do a truncating store.  On big-endian
5648     // machines this requires an extending load from the stack slot to ensure
5649     // that the bits are in the right place.
5650     EVT LoadMemVT =
5651         EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
5652 
5653     // Load from the stack slot.
5654     SDValue Load = DAG.getExtLoad(
5655         ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
5656         MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), LoadMemVT);
5657 
5658     Stores.push_back(
5659         DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
5660                           ST->getPointerInfo().getWithOffset(Offset), LoadMemVT,
5661                           MinAlign(ST->getAlignment(), Offset),
5662                           ST->getMemOperand()->getFlags(), ST->getAAInfo()));
5663     // The order of the stores doesn't matter - say it with a TokenFactor.
5664     SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
5665     return Result;
5666   }
5667 
5668   assert(StoreMemVT.isInteger() && !StoreMemVT.isVector() &&
5669          "Unaligned store of unknown type.");
5670   // Get the half-size VT
5671   EVT NewStoredVT = StoreMemVT.getHalfSizedIntegerVT(*DAG.getContext());
5672   int NumBits = NewStoredVT.getSizeInBits();
5673   int IncrementSize = NumBits / 8;
5674 
5675   // Divide the stored value in two parts.
5676   SDValue ShiftAmount = DAG.getConstant(
5677       NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout()));
5678   SDValue Lo = Val;
5679   SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
5680 
5681   // Store the two parts
5682   SDValue Store1, Store2;
5683   Store1 = DAG.getTruncStore(Chain, dl,
5684                              DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
5685                              Ptr, ST->getPointerInfo(), NewStoredVT, Alignment,
5686                              ST->getMemOperand()->getFlags());
5687 
5688   Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
5689   Alignment = MinAlign(Alignment, IncrementSize);
5690   Store2 = DAG.getTruncStore(
5691       Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
5692       ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment,
5693       ST->getMemOperand()->getFlags(), ST->getAAInfo());
5694 
5695   SDValue Result =
5696       DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
5697   return Result;
5698 }
5699 
5700 SDValue
5701 TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask,
5702                                        const SDLoc &DL, EVT DataVT,
5703                                        SelectionDAG &DAG,
5704                                        bool IsCompressedMemory) const {
5705   SDValue Increment;
5706   EVT AddrVT = Addr.getValueType();
5707   EVT MaskVT = Mask.getValueType();
5708   assert(DataVT.getVectorNumElements() == MaskVT.getVectorNumElements() &&
5709          "Incompatible types of Data and Mask");
5710   if (IsCompressedMemory) {
5711     // Incrementing the pointer according to number of '1's in the mask.
5712     EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits());
5713     SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask);
5714     if (MaskIntVT.getSizeInBits() < 32) {
5715       MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg);
5716       MaskIntVT = MVT::i32;
5717     }
5718 
5719     // Count '1's with POPCNT.
5720     Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg);
5721     Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT);
5722     // Scale is an element size in bytes.
5723     SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL,
5724                                     AddrVT);
5725     Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale);
5726   } else
5727     Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT);
5728 
5729   return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment);
5730 }
5731 
5732 static SDValue clampDynamicVectorIndex(SelectionDAG &DAG,
5733                                        SDValue Idx,
5734                                        EVT VecVT,
5735                                        const SDLoc &dl) {
5736   if (isa<ConstantSDNode>(Idx))
5737     return Idx;
5738 
5739   EVT IdxVT = Idx.getValueType();
5740   unsigned NElts = VecVT.getVectorNumElements();
5741   if (isPowerOf2_32(NElts)) {
5742     APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(),
5743                                      Log2_32(NElts));
5744     return DAG.getNode(ISD::AND, dl, IdxVT, Idx,
5745                        DAG.getConstant(Imm, dl, IdxVT));
5746   }
5747 
5748   return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx,
5749                      DAG.getConstant(NElts - 1, dl, IdxVT));
5750 }
5751 
5752 SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG,
5753                                                 SDValue VecPtr, EVT VecVT,
5754                                                 SDValue Index) const {
5755   SDLoc dl(Index);
5756   // Make sure the index type is big enough to compute in.
5757   Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType());
5758 
5759   EVT EltVT = VecVT.getVectorElementType();
5760 
5761   // Calculate the element offset and add it to the pointer.
5762   unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
5763   assert(EltSize * 8 == EltVT.getSizeInBits() &&
5764          "Converting bits to bytes lost precision");
5765 
5766   Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl);
5767 
5768   EVT IdxVT = Index.getValueType();
5769 
5770   Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
5771                       DAG.getConstant(EltSize, dl, IdxVT));
5772   return DAG.getNode(ISD::ADD, dl, IdxVT, VecPtr, Index);
5773 }
5774 
5775 //===----------------------------------------------------------------------===//
5776 // Implementation of Emulated TLS Model
5777 //===----------------------------------------------------------------------===//
5778 
5779 SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
5780                                                 SelectionDAG &DAG) const {
5781   // Access to address of TLS varialbe xyz is lowered to a function call:
5782   //   __emutls_get_address( address of global variable named "__emutls_v.xyz" )
5783   EVT PtrVT = getPointerTy(DAG.getDataLayout());
5784   PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext());
5785   SDLoc dl(GA);
5786 
5787   ArgListTy Args;
5788   ArgListEntry Entry;
5789   std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str();
5790   Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent());
5791   StringRef EmuTlsVarName(NameString);
5792   GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName);
5793   assert(EmuTlsVar && "Cannot find EmuTlsVar ");
5794   Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT);
5795   Entry.Ty = VoidPtrType;
5796   Args.push_back(Entry);
5797 
5798   SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT);
5799 
5800   TargetLowering::CallLoweringInfo CLI(DAG);
5801   CLI.setDebugLoc(dl).setChain(DAG.getEntryNode());
5802   CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args));
5803   std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
5804 
5805   // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5806   // At last for X86 targets, maybe good for other targets too?
5807   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5808   MFI.setAdjustsStack(true); // Is this only for X86 target?
5809   MFI.setHasCalls(true);
5810 
5811   assert((GA->getOffset() == 0) &&
5812          "Emulated TLS must have zero offset in GlobalAddressSDNode");
5813   return CallResult.first;
5814 }
5815 
5816 SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
5817                                                 SelectionDAG &DAG) const {
5818   assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
5819   if (!isCtlzFast())
5820     return SDValue();
5821   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5822   SDLoc dl(Op);
5823   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
5824     if (C->isNullValue() && CC == ISD::SETEQ) {
5825       EVT VT = Op.getOperand(0).getValueType();
5826       SDValue Zext = Op.getOperand(0);
5827       if (VT.bitsLT(MVT::i32)) {
5828         VT = MVT::i32;
5829         Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
5830       }
5831       unsigned Log2b = Log2_32(VT.getSizeInBits());
5832       SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
5833       SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
5834                                 DAG.getConstant(Log2b, dl, MVT::i32));
5835       return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
5836     }
5837   }
5838   return SDValue();
5839 }
5840 
5841 SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
5842   unsigned Opcode = Node->getOpcode();
5843   SDValue LHS = Node->getOperand(0);
5844   SDValue RHS = Node->getOperand(1);
5845   EVT VT = LHS.getValueType();
5846   SDLoc dl(Node);
5847 
5848   assert(VT == RHS.getValueType() && "Expected operands to be the same type");
5849   assert(VT.isInteger() && "Expected operands to be integers");
5850 
5851   // usub.sat(a, b) -> umax(a, b) - b
5852   if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
5853     SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
5854     return DAG.getNode(ISD::SUB, dl, VT, Max, RHS);
5855   }
5856 
5857   if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) {
5858     SDValue InvRHS = DAG.getNOT(dl, RHS, VT);
5859     SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS);
5860     return DAG.getNode(ISD::ADD, dl, VT, Min, RHS);
5861   }
5862 
5863   unsigned OverflowOp;
5864   switch (Opcode) {
5865   case ISD::SADDSAT:
5866     OverflowOp = ISD::SADDO;
5867     break;
5868   case ISD::UADDSAT:
5869     OverflowOp = ISD::UADDO;
5870     break;
5871   case ISD::SSUBSAT:
5872     OverflowOp = ISD::SSUBO;
5873     break;
5874   case ISD::USUBSAT:
5875     OverflowOp = ISD::USUBO;
5876     break;
5877   default:
5878     llvm_unreachable("Expected method to receive signed or unsigned saturation "
5879                      "addition or subtraction node.");
5880   }
5881 
5882   unsigned BitWidth = LHS.getScalarValueSizeInBits();
5883   EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5884   SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT),
5885                                LHS, RHS);
5886   SDValue SumDiff = Result.getValue(0);
5887   SDValue Overflow = Result.getValue(1);
5888   SDValue Zero = DAG.getConstant(0, dl, VT);
5889   SDValue AllOnes = DAG.getAllOnesConstant(dl, VT);
5890 
5891   if (Opcode == ISD::UADDSAT) {
5892     if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
5893       // (LHS + RHS) | OverflowMask
5894       SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT);
5895       return DAG.getNode(ISD::OR, dl, VT, SumDiff, OverflowMask);
5896     }
5897     // Overflow ? 0xffff.... : (LHS + RHS)
5898     return DAG.getSelect(dl, VT, Overflow, AllOnes, SumDiff);
5899   } else if (Opcode == ISD::USUBSAT) {
5900     if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
5901       // (LHS - RHS) & ~OverflowMask
5902       SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT);
5903       SDValue Not = DAG.getNOT(dl, OverflowMask, VT);
5904       return DAG.getNode(ISD::AND, dl, VT, SumDiff, Not);
5905     }
5906     // Overflow ? 0 : (LHS - RHS)
5907     return DAG.getSelect(dl, VT, Overflow, Zero, SumDiff);
5908   } else {
5909     // SatMax -> Overflow && SumDiff < 0
5910     // SatMin -> Overflow && SumDiff >= 0
5911     APInt MinVal = APInt::getSignedMinValue(BitWidth);
5912     APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
5913     SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
5914     SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
5915     SDValue SumNeg = DAG.getSetCC(dl, BoolVT, SumDiff, Zero, ISD::SETLT);
5916     Result = DAG.getSelect(dl, VT, SumNeg, SatMax, SatMin);
5917     return DAG.getSelect(dl, VT, Overflow, Result, SumDiff);
5918   }
5919 }
5920 
5921 SDValue
5922 TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
5923   assert((Node->getOpcode() == ISD::SMULFIX ||
5924           Node->getOpcode() == ISD::UMULFIX ||
5925           Node->getOpcode() == ISD::SMULFIXSAT) &&
5926          "Expected a fixed point multiplication opcode");
5927 
5928   SDLoc dl(Node);
5929   SDValue LHS = Node->getOperand(0);
5930   SDValue RHS = Node->getOperand(1);
5931   EVT VT = LHS.getValueType();
5932   unsigned Scale = Node->getConstantOperandVal(2);
5933   bool Saturating = Node->getOpcode() == ISD::SMULFIXSAT;
5934   EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5935   unsigned VTSize = VT.getScalarSizeInBits();
5936 
5937   if (!Scale) {
5938     // [us]mul.fix(a, b, 0) -> mul(a, b)
5939     if (!Saturating && isOperationLegalOrCustom(ISD::MUL, VT)) {
5940       return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
5941     } else if (Saturating && isOperationLegalOrCustom(ISD::SMULO, VT)) {
5942       SDValue Result =
5943           DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
5944       SDValue Product = Result.getValue(0);
5945       SDValue Overflow = Result.getValue(1);
5946       SDValue Zero = DAG.getConstant(0, dl, VT);
5947 
5948       APInt MinVal = APInt::getSignedMinValue(VTSize);
5949       APInt MaxVal = APInt::getSignedMaxValue(VTSize);
5950       SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
5951       SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
5952       SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
5953       Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
5954       return DAG.getSelect(dl, VT, Overflow, Result, Product);
5955     }
5956   }
5957 
5958   bool Signed =
5959       Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::SMULFIXSAT;
5960   assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) &&
5961          "Expected scale to be less than the number of bits if signed or at "
5962          "most the number of bits if unsigned.");
5963   assert(LHS.getValueType() == RHS.getValueType() &&
5964          "Expected both operands to be the same type");
5965 
5966   // Get the upper and lower bits of the result.
5967   SDValue Lo, Hi;
5968   unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
5969   unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
5970   if (isOperationLegalOrCustom(LoHiOp, VT)) {
5971     SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS);
5972     Lo = Result.getValue(0);
5973     Hi = Result.getValue(1);
5974   } else if (isOperationLegalOrCustom(HiOp, VT)) {
5975     Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
5976     Hi = DAG.getNode(HiOp, dl, VT, LHS, RHS);
5977   } else if (VT.isVector()) {
5978     return SDValue();
5979   } else {
5980     report_fatal_error("Unable to expand fixed point multiplication.");
5981   }
5982 
5983   if (Scale == VTSize)
5984     // Result is just the top half since we'd be shifting by the width of the
5985     // operand.
5986     return Hi;
5987 
5988   // The result will need to be shifted right by the scale since both operands
5989   // are scaled. The result is given to us in 2 halves, so we only want part of
5990   // both in the result.
5991   EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
5992   SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,
5993                                DAG.getConstant(Scale, dl, ShiftTy));
5994   if (!Saturating)
5995     return Result;
5996 
5997   unsigned OverflowBits = VTSize - Scale + 1; // +1 for the sign
5998   SDValue HiMask =
5999       DAG.getConstant(APInt::getHighBitsSet(VTSize, OverflowBits), dl, VT);
6000   SDValue LoMask = DAG.getConstant(
6001       APInt::getLowBitsSet(VTSize, VTSize - OverflowBits), dl, VT);
6002   APInt MaxVal = APInt::getSignedMaxValue(VTSize);
6003   APInt MinVal = APInt::getSignedMinValue(VTSize);
6004 
6005   Result = DAG.getSelectCC(dl, Hi, LoMask,
6006                            DAG.getConstant(MaxVal, dl, VT), Result,
6007                            ISD::SETGT);
6008   return DAG.getSelectCC(dl, Hi, HiMask,
6009                          DAG.getConstant(MinVal, dl, VT), Result,
6010                          ISD::SETLT);
6011 }
6012 
6013 void TargetLowering::expandUADDSUBO(
6014     SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const {
6015   SDLoc dl(Node);
6016   SDValue LHS = Node->getOperand(0);
6017   SDValue RHS = Node->getOperand(1);
6018   bool IsAdd = Node->getOpcode() == ISD::UADDO;
6019 
6020   // If ADD/SUBCARRY is legal, use that instead.
6021   unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
6022   if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
6023     SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
6024     SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
6025                                     { LHS, RHS, CarryIn });
6026     Result = SDValue(NodeCarry.getNode(), 0);
6027     Overflow = SDValue(NodeCarry.getNode(), 1);
6028     return;
6029   }
6030 
6031   Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
6032                             LHS.getValueType(), LHS, RHS);
6033 
6034   EVT ResultType = Node->getValueType(1);
6035   EVT SetCCType = getSetCCResultType(
6036       DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0));
6037   ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
6038   SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC);
6039   Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
6040 }
6041 
6042 void TargetLowering::expandSADDSUBO(
6043     SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const {
6044   SDLoc dl(Node);
6045   SDValue LHS = Node->getOperand(0);
6046   SDValue RHS = Node->getOperand(1);
6047   bool IsAdd = Node->getOpcode() == ISD::SADDO;
6048 
6049   Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
6050                             LHS.getValueType(), LHS, RHS);
6051 
6052   EVT ResultType = Node->getValueType(1);
6053   EVT OType = getSetCCResultType(
6054       DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0));
6055 
6056   // If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
6057   unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
6058   if (isOperationLegalOrCustom(OpcSat, LHS.getValueType())) {
6059     SDValue Sat = DAG.getNode(OpcSat, dl, LHS.getValueType(), LHS, RHS);
6060     SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE);
6061     Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
6062     return;
6063   }
6064 
6065   SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
6066 
6067   //   LHSSign -> LHS >= 0
6068   //   RHSSign -> RHS >= 0
6069   //   SumSign -> Result >= 0
6070   //
6071   //   Add:
6072   //   Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
6073   //   Sub:
6074   //   Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
6075   SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
6076   SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
6077   SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
6078                                     IsAdd ? ISD::SETEQ : ISD::SETNE);
6079 
6080   SDValue SumSign = DAG.getSetCC(dl, OType, Result, Zero, ISD::SETGE);
6081   SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
6082 
6083   SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
6084   Overflow = DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType);
6085 }
6086 
6087 bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result,
6088                                 SDValue &Overflow, SelectionDAG &DAG) const {
6089   SDLoc dl(Node);
6090   EVT VT = Node->getValueType(0);
6091   EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
6092   SDValue LHS = Node->getOperand(0);
6093   SDValue RHS = Node->getOperand(1);
6094   bool isSigned = Node->getOpcode() == ISD::SMULO;
6095 
6096   // For power-of-two multiplications we can use a simpler shift expansion.
6097   if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) {
6098     const APInt &C = RHSC->getAPIntValue();
6099     // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X }
6100     if (C.isPowerOf2()) {
6101       // smulo(x, signed_min) is same as umulo(x, signed_min).
6102       bool UseArithShift = isSigned && !C.isMinSignedValue();
6103       EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout());
6104       SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy);
6105       Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt);
6106       Overflow = DAG.getSetCC(dl, SetCCVT,
6107           DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
6108                       dl, VT, Result, ShiftAmt),
6109           LHS, ISD::SETNE);
6110       return true;
6111     }
6112   }
6113 
6114   EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
6115   if (VT.isVector())
6116     WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
6117                               VT.getVectorNumElements());
6118 
6119   SDValue BottomHalf;
6120   SDValue TopHalf;
6121   static const unsigned Ops[2][3] =
6122       { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
6123         { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
6124   if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
6125     BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
6126     TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
6127   } else if (isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
6128     BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
6129                              RHS);
6130     TopHalf = BottomHalf.getValue(1);
6131   } else if (isTypeLegal(WideVT)) {
6132     LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
6133     RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
6134     SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
6135     BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Mul);
6136     SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl,
6137         getShiftAmountTy(WideVT, DAG.getDataLayout()));
6138     TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT,
6139                           DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt));
6140   } else {
6141     if (VT.isVector())
6142       return false;
6143 
6144     // We can fall back to a libcall with an illegal type for the MUL if we
6145     // have a libcall big enough.
6146     // Also, we can fall back to a division in some cases, but that's a big
6147     // performance hit in the general case.
6148     RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6149     if (WideVT == MVT::i16)
6150       LC = RTLIB::MUL_I16;
6151     else if (WideVT == MVT::i32)
6152       LC = RTLIB::MUL_I32;
6153     else if (WideVT == MVT::i64)
6154       LC = RTLIB::MUL_I64;
6155     else if (WideVT == MVT::i128)
6156       LC = RTLIB::MUL_I128;
6157     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
6158 
6159     SDValue HiLHS;
6160     SDValue HiRHS;
6161     if (isSigned) {
6162       // The high part is obtained by SRA'ing all but one of the bits of low
6163       // part.
6164       unsigned LoSize = VT.getSizeInBits();
6165       HiLHS =
6166           DAG.getNode(ISD::SRA, dl, VT, LHS,
6167                       DAG.getConstant(LoSize - 1, dl,
6168                                       getPointerTy(DAG.getDataLayout())));
6169       HiRHS =
6170           DAG.getNode(ISD::SRA, dl, VT, RHS,
6171                       DAG.getConstant(LoSize - 1, dl,
6172                                       getPointerTy(DAG.getDataLayout())));
6173     } else {
6174         HiLHS = DAG.getConstant(0, dl, VT);
6175         HiRHS = DAG.getConstant(0, dl, VT);
6176     }
6177 
6178     // Here we're passing the 2 arguments explicitly as 4 arguments that are
6179     // pre-lowered to the correct types. This all depends upon WideVT not
6180     // being a legal type for the architecture and thus has to be split to
6181     // two arguments.
6182     SDValue Ret;
6183     if (shouldSplitFunctionArgumentsAsLittleEndian(DAG.getDataLayout())) {
6184       // Halves of WideVT are packed into registers in different order
6185       // depending on platform endianness. This is usually handled by
6186       // the C calling convention, but we can't defer to it in
6187       // the legalizer.
6188       SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
6189       Ret = makeLibCall(DAG, LC, WideVT, Args, isSigned, dl,
6190           /* doesNotReturn */ false, /* isReturnValueUsed */ true,
6191           /* isPostTypeLegalization */ true).first;
6192     } else {
6193       SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
6194       Ret = makeLibCall(DAG, LC, WideVT, Args, isSigned, dl,
6195           /* doesNotReturn */ false, /* isReturnValueUsed */ true,
6196           /* isPostTypeLegalization */ true).first;
6197     }
6198     assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
6199            "Ret value is a collection of constituent nodes holding result.");
6200     if (DAG.getDataLayout().isLittleEndian()) {
6201       // Same as above.
6202       BottomHalf = Ret.getOperand(0);
6203       TopHalf = Ret.getOperand(1);
6204     } else {
6205       BottomHalf = Ret.getOperand(1);
6206       TopHalf = Ret.getOperand(0);
6207     }
6208   }
6209 
6210   Result = BottomHalf;
6211   if (isSigned) {
6212     SDValue ShiftAmt = DAG.getConstant(
6213         VT.getScalarSizeInBits() - 1, dl,
6214         getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
6215     SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
6216     Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE);
6217   } else {
6218     Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf,
6219                             DAG.getConstant(0, dl, VT), ISD::SETNE);
6220   }
6221 
6222   // Truncate the result if SetCC returns a larger type than needed.
6223   EVT RType = Node->getValueType(1);
6224   if (RType.getSizeInBits() < Overflow.getValueSizeInBits())
6225     Overflow = DAG.getNode(ISD::TRUNCATE, dl, RType, Overflow);
6226 
6227   assert(RType.getSizeInBits() == Overflow.getValueSizeInBits() &&
6228          "Unexpected result type for S/UMULO legalization");
6229   return true;
6230 }
6231 
6232 SDValue TargetLowering::expandVecReduce(SDNode *Node, SelectionDAG &DAG) const {
6233   SDLoc dl(Node);
6234   bool NoNaN = Node->getFlags().hasNoNaNs();
6235   unsigned BaseOpcode = 0;
6236   switch (Node->getOpcode()) {
6237   default: llvm_unreachable("Expected VECREDUCE opcode");
6238   case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
6239   case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
6240   case ISD::VECREDUCE_ADD:  BaseOpcode = ISD::ADD; break;
6241   case ISD::VECREDUCE_MUL:  BaseOpcode = ISD::MUL; break;
6242   case ISD::VECREDUCE_AND:  BaseOpcode = ISD::AND; break;
6243   case ISD::VECREDUCE_OR:   BaseOpcode = ISD::OR; break;
6244   case ISD::VECREDUCE_XOR:  BaseOpcode = ISD::XOR; break;
6245   case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
6246   case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
6247   case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
6248   case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
6249   case ISD::VECREDUCE_FMAX:
6250     BaseOpcode = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
6251     break;
6252   case ISD::VECREDUCE_FMIN:
6253     BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
6254     break;
6255   }
6256 
6257   SDValue Op = Node->getOperand(0);
6258   EVT VT = Op.getValueType();
6259 
6260   // Try to use a shuffle reduction for power of two vectors.
6261   if (VT.isPow2VectorType()) {
6262     while (VT.getVectorNumElements() > 1) {
6263       EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
6264       if (!isOperationLegalOrCustom(BaseOpcode, HalfVT))
6265         break;
6266 
6267       SDValue Lo, Hi;
6268       std::tie(Lo, Hi) = DAG.SplitVector(Op, dl);
6269       Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi);
6270       VT = HalfVT;
6271     }
6272   }
6273 
6274   EVT EltVT = VT.getVectorElementType();
6275   unsigned NumElts = VT.getVectorNumElements();
6276 
6277   SmallVector<SDValue, 8> Ops;
6278   DAG.ExtractVectorElements(Op, Ops, 0, NumElts);
6279 
6280   SDValue Res = Ops[0];
6281   for (unsigned i = 1; i < NumElts; i++)
6282     Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags());
6283 
6284   // Result type may be wider than element type.
6285   if (EltVT != Node->getValueType(0))
6286     Res = DAG.getNode(ISD::ANY_EXTEND, dl, Node->getValueType(0), Res);
6287   return Res;
6288 }
6289