1 //===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating from LLVM IR into SelectionDAG IR. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 14 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 15 16 #include "StatepointLowering.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/MapVector.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/CodeGen/AssignmentTrackingAnalysis.h" 22 #include "llvm/CodeGen/CodeGenCommonISel.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineValueType.h" 25 #include "llvm/CodeGen/SelectionDAGNodes.h" 26 #include "llvm/CodeGen/SwitchLoweringUtils.h" 27 #include "llvm/CodeGen/TargetLowering.h" 28 #include "llvm/CodeGen/ValueTypes.h" 29 #include "llvm/IR/DebugLoc.h" 30 #include "llvm/IR/Instruction.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/CodeGen.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include <algorithm> 35 #include <cassert> 36 #include <cstdint> 37 #include <optional> 38 #include <utility> 39 #include <vector> 40 41 namespace llvm { 42 43 class AAResults; 44 class AllocaInst; 45 class AtomicCmpXchgInst; 46 class AtomicRMWInst; 47 class AssumptionCache; 48 class BasicBlock; 49 class BranchInst; 50 class CallInst; 51 class CallBrInst; 52 class CatchPadInst; 53 class CatchReturnInst; 54 class CatchSwitchInst; 55 class CleanupPadInst; 56 class CleanupReturnInst; 57 class Constant; 58 class ConstrainedFPIntrinsic; 59 class DbgValueInst; 60 class DataLayout; 61 class DIExpression; 62 class DILocalVariable; 63 class DILocation; 64 class FenceInst; 65 class FunctionLoweringInfo; 66 class GCFunctionInfo; 67 class GCRelocateInst; 68 class GCResultInst; 69 class GCStatepointInst; 70 class IndirectBrInst; 71 class InvokeInst; 72 class LandingPadInst; 73 class LLVMContext; 74 class LoadInst; 75 class MachineBasicBlock; 76 class PHINode; 77 class ResumeInst; 78 class ReturnInst; 79 class SDDbgValue; 80 class SelectionDAG; 81 class StoreInst; 82 class SwiftErrorValueTracking; 83 class SwitchInst; 84 class TargetLibraryInfo; 85 class TargetMachine; 86 class Type; 87 class VAArgInst; 88 class UnreachableInst; 89 class Use; 90 class User; 91 class Value; 92 93 //===----------------------------------------------------------------------===// 94 /// SelectionDAGBuilder - This is the common target-independent lowering 95 /// implementation that is parameterized by a TargetLowering object. 96 /// 97 class SelectionDAGBuilder { 98 /// The current instruction being visited. 99 const Instruction *CurInst = nullptr; 100 101 DenseMap<const Value*, SDValue> NodeMap; 102 103 /// Maps argument value for unused arguments. This is used 104 /// to preserve debug information for incoming arguments. 105 DenseMap<const Value*, SDValue> UnusedArgNodeMap; 106 107 /// Helper type for DanglingDebugInfoMap. 108 class DanglingDebugInfo { 109 using DbgValTy = const DbgValueInst *; 110 using VarLocTy = const VarLocInfo *; 111 PointerUnion<DbgValTy, VarLocTy> Info; 112 unsigned SDNodeOrder = 0; 113 114 public: 115 DanglingDebugInfo() = default; 116 DanglingDebugInfo(const DbgValueInst *DI, unsigned SDNO) 117 : Info(DI), SDNodeOrder(SDNO) {} 118 DanglingDebugInfo(const VarLocInfo *VarLoc, unsigned SDNO) 119 : Info(VarLoc), SDNodeOrder(SDNO) {} 120 121 DILocalVariable *getVariable(const FunctionVarLocs *Locs) const { 122 if (isa<VarLocTy>(Info)) 123 return Locs->getDILocalVariable(cast<VarLocTy>(Info)->VariableID); 124 return cast<DbgValTy>(Info)->getVariable(); 125 } 126 DIExpression *getExpression() const { 127 if (isa<VarLocTy>(Info)) 128 return cast<VarLocTy>(Info)->Expr; 129 return cast<DbgValTy>(Info)->getExpression(); 130 } 131 Value *getVariableLocationOp(unsigned Idx) const { 132 assert(Idx == 0 && "Dangling variadic debug values not supported yet"); 133 if (isa<VarLocTy>(Info)) 134 return cast<VarLocTy>(Info)->Values.getVariableLocationOp(Idx); 135 return cast<DbgValTy>(Info)->getVariableLocationOp(Idx); 136 } 137 DebugLoc getDebugLoc() const { 138 if (isa<VarLocTy>(Info)) 139 return cast<VarLocTy>(Info)->DL; 140 return cast<DbgValTy>(Info)->getDebugLoc(); 141 } 142 unsigned getSDNodeOrder() const { return SDNodeOrder; } 143 144 /// Helper for printing DanglingDebugInfo. This hoop-jumping is to 145 /// accommodate the fact that an argument is required for getVariable. 146 /// Call SelectionDAGBuilder::printDDI instead of using directly. 147 struct Print { 148 Print(const DanglingDebugInfo &DDI, const FunctionVarLocs *VarLocs) 149 : DDI(DDI), VarLocs(VarLocs) {} 150 const DanglingDebugInfo &DDI; 151 const FunctionVarLocs *VarLocs; 152 friend raw_ostream &operator<<(raw_ostream &OS, 153 const DanglingDebugInfo::Print &P) { 154 OS << "DDI(var=" << *P.DDI.getVariable(P.VarLocs) 155 << ", val= " << *P.DDI.getVariableLocationOp(0) 156 << ", expr=" << *P.DDI.getExpression() 157 << ", order=" << P.DDI.getSDNodeOrder() 158 << ", loc=" << P.DDI.getDebugLoc() << ")"; 159 return OS; 160 } 161 }; 162 }; 163 164 /// Returns an object that defines `raw_ostream &operator<<` for printing. 165 /// Usage example: 166 //// errs() << printDDI(MyDanglingInfo) << " is dangling\n"; 167 DanglingDebugInfo::Print printDDI(const DanglingDebugInfo &DDI) { 168 return DanglingDebugInfo::Print(DDI, DAG.getFunctionVarLocs()); 169 } 170 171 /// Helper type for DanglingDebugInfoMap. 172 typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector; 173 174 /// Keeps track of dbg_values for which we have not yet seen the referent. 175 /// We defer handling these until we do see it. 176 MapVector<const Value*, DanglingDebugInfoVector> DanglingDebugInfoMap; 177 178 /// Cache the module flag for whether we should use debug-info assignment 179 /// tracking. 180 bool AssignmentTrackingEnabled = false; 181 182 public: 183 /// Loads are not emitted to the program immediately. We bunch them up and 184 /// then emit token factor nodes when possible. This allows us to get simple 185 /// disambiguation between loads without worrying about alias analysis. 186 SmallVector<SDValue, 8> PendingLoads; 187 188 /// State used while lowering a statepoint sequence (gc_statepoint, 189 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details. 190 StatepointLoweringState StatepointLowering; 191 192 private: 193 /// CopyToReg nodes that copy values to virtual registers for export to other 194 /// blocks need to be emitted before any terminator instruction, but they have 195 /// no other ordering requirements. We bunch them up and the emit a single 196 /// tokenfactor for them just before terminator instructions. 197 SmallVector<SDValue, 8> PendingExports; 198 199 /// Similar to loads, nodes corresponding to constrained FP intrinsics are 200 /// bunched up and emitted when necessary. These can be moved across each 201 /// other and any (normal) memory operation (load or store), but not across 202 /// calls or instructions having unspecified side effects. As a special 203 /// case, constrained FP intrinsics using fpexcept.strict may not be deleted 204 /// even if otherwise unused, so they need to be chained before any 205 /// terminator instruction (like PendingExports). We track the latter 206 /// set of nodes in a separate list. 207 SmallVector<SDValue, 8> PendingConstrainedFP; 208 SmallVector<SDValue, 8> PendingConstrainedFPStrict; 209 210 /// Update root to include all chains from the Pending list. 211 SDValue updateRoot(SmallVectorImpl<SDValue> &Pending); 212 213 /// A unique monotonically increasing number used to order the SDNodes we 214 /// create. 215 unsigned SDNodeOrder; 216 217 /// Determine the rank by weight of CC in [First,Last]. If CC has more weight 218 /// than each cluster in the range, its rank is 0. 219 unsigned caseClusterRank(const SwitchCG::CaseCluster &CC, 220 SwitchCG::CaseClusterIt First, 221 SwitchCG::CaseClusterIt Last); 222 223 /// Emit comparison and split W into two subtrees. 224 void splitWorkItem(SwitchCG::SwitchWorkList &WorkList, 225 const SwitchCG::SwitchWorkListItem &W, Value *Cond, 226 MachineBasicBlock *SwitchMBB); 227 228 /// Lower W. 229 void lowerWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond, 230 MachineBasicBlock *SwitchMBB, 231 MachineBasicBlock *DefaultMBB); 232 233 /// Peel the top probability case if it exceeds the threshold 234 MachineBasicBlock * 235 peelDominantCaseCluster(const SwitchInst &SI, 236 SwitchCG::CaseClusterVector &Clusters, 237 BranchProbability &PeeledCaseProb); 238 239 private: 240 const TargetMachine &TM; 241 242 public: 243 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling 244 /// nodes without a corresponding SDNode. 245 static const unsigned LowestSDNodeOrder = 1; 246 247 SelectionDAG &DAG; 248 AAResults *AA = nullptr; 249 AssumptionCache *AC = nullptr; 250 const TargetLibraryInfo *LibInfo = nullptr; 251 252 class SDAGSwitchLowering : public SwitchCG::SwitchLowering { 253 public: 254 SDAGSwitchLowering(SelectionDAGBuilder *sdb, FunctionLoweringInfo &funcinfo) 255 : SwitchCG::SwitchLowering(funcinfo), SDB(sdb) {} 256 257 void addSuccessorWithProb( 258 MachineBasicBlock *Src, MachineBasicBlock *Dst, 259 BranchProbability Prob = BranchProbability::getUnknown()) override { 260 SDB->addSuccessorWithProb(Src, Dst, Prob); 261 } 262 263 private: 264 SelectionDAGBuilder *SDB = nullptr; 265 }; 266 267 // Data related to deferred switch lowerings. Used to construct additional 268 // Basic Blocks in SelectionDAGISel::FinishBasicBlock. 269 std::unique_ptr<SDAGSwitchLowering> SL; 270 271 /// A StackProtectorDescriptor structure used to communicate stack protector 272 /// information in between SelectBasicBlock and FinishBasicBlock. 273 StackProtectorDescriptor SPDescriptor; 274 275 // Emit PHI-node-operand constants only once even if used by multiple 276 // PHI nodes. 277 DenseMap<const Constant *, unsigned> ConstantsOut; 278 279 /// Information about the function as a whole. 280 FunctionLoweringInfo &FuncInfo; 281 282 /// Information about the swifterror values used throughout the function. 283 SwiftErrorValueTracking &SwiftError; 284 285 /// Garbage collection metadata for the function. 286 GCFunctionInfo *GFI = nullptr; 287 288 /// Map a landing pad to the call site indexes. 289 DenseMap<MachineBasicBlock *, SmallVector<unsigned, 4>> LPadToCallSiteMap; 290 291 /// This is set to true if a call in the current block has been translated as 292 /// a tail call. In this case, no subsequent DAG nodes should be created. 293 bool HasTailCall = false; 294 295 LLVMContext *Context = nullptr; 296 297 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, 298 SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol) 299 : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag), 300 SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)), FuncInfo(funcinfo), 301 SwiftError(swifterror) {} 302 303 void init(GCFunctionInfo *gfi, AAResults *AA, AssumptionCache *AC, 304 const TargetLibraryInfo *li); 305 306 /// Clear out the current SelectionDAG and the associated state and prepare 307 /// this SelectionDAGBuilder object to be used for a new block. This doesn't 308 /// clear out information about additional blocks that are needed to complete 309 /// switch lowering or PHI node updating; that information is cleared out as 310 /// it is consumed. 311 void clear(); 312 313 /// Clear the dangling debug information map. This function is separated from 314 /// the clear so that debug information that is dangling in a basic block can 315 /// be properly resolved in a different basic block. This allows the 316 /// SelectionDAG to resolve dangling debug information attached to PHI nodes. 317 void clearDanglingDebugInfo(); 318 319 /// Return the current virtual root of the Selection DAG, flushing any 320 /// PendingLoad items. This must be done before emitting a store or any other 321 /// memory node that may need to be ordered after any prior load instructions. 322 SDValue getMemoryRoot(); 323 324 /// Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) 325 /// items. This must be done before emitting any call other any other node 326 /// that may need to be ordered after FP instructions due to other side 327 /// effects. 328 SDValue getRoot(); 329 330 /// Similar to getRoot, but instead of flushing all the PendingLoad items, 331 /// flush all the PendingExports (and PendingConstrainedFPStrict) items. 332 /// It is necessary to do this before emitting a terminator instruction. 333 SDValue getControlRoot(); 334 335 SDLoc getCurSDLoc() const { 336 return SDLoc(CurInst, SDNodeOrder); 337 } 338 339 DebugLoc getCurDebugLoc() const { 340 return CurInst ? CurInst->getDebugLoc() : DebugLoc(); 341 } 342 343 void CopyValueToVirtualRegister(const Value *V, unsigned Reg, 344 ISD::NodeType ExtendType = ISD::ANY_EXTEND); 345 346 void visit(const Instruction &I); 347 348 void visit(unsigned Opcode, const User &I); 349 350 /// If there was virtual register allocated for the value V emit CopyFromReg 351 /// of the specified type Ty. Return empty SDValue() otherwise. 352 SDValue getCopyFromRegs(const Value *V, Type *Ty); 353 354 /// Register a dbg_value which relies on a Value which we have not yet seen. 355 void addDanglingDebugInfo(const DbgValueInst *DI, unsigned Order); 356 void addDanglingDebugInfo(const VarLocInfo *VarLoc, unsigned Order); 357 358 /// If we have dangling debug info that describes \p Variable, or an 359 /// overlapping part of variable considering the \p Expr, then this method 360 /// will drop that debug info as it isn't valid any longer. 361 void dropDanglingDebugInfo(const DILocalVariable *Variable, 362 const DIExpression *Expr); 363 364 /// If we saw an earlier dbg_value referring to V, generate the debug data 365 /// structures now that we've seen its definition. 366 void resolveDanglingDebugInfo(const Value *V, SDValue Val); 367 368 /// For the given dangling debuginfo record, perform last-ditch efforts to 369 /// resolve the debuginfo to something that is represented in this DAG. If 370 /// this cannot be done, produce an Undef debug value record. 371 void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI); 372 373 /// For a given list of Values, attempt to create and record a SDDbgValue in 374 /// the SelectionDAG. 375 bool handleDebugValue(ArrayRef<const Value *> Values, DILocalVariable *Var, 376 DIExpression *Expr, DebugLoc DbgLoc, unsigned Order, 377 bool IsVariadic); 378 379 /// Create a record for a kill location debug intrinsic. 380 void handleKillDebugValue(DILocalVariable *Var, DIExpression *Expr, 381 DebugLoc DbgLoc, unsigned Order); 382 383 /// Evict any dangling debug information, attempting to salvage it first. 384 void resolveOrClearDbgInfo(); 385 386 SDValue getValue(const Value *V); 387 388 SDValue getNonRegisterValue(const Value *V); 389 SDValue getValueImpl(const Value *V); 390 391 void setValue(const Value *V, SDValue NewN) { 392 SDValue &N = NodeMap[V]; 393 assert(!N.getNode() && "Already set a value for this node!"); 394 N = NewN; 395 } 396 397 void setUnusedArgValue(const Value *V, SDValue NewN) { 398 SDValue &N = UnusedArgNodeMap[V]; 399 assert(!N.getNode() && "Already set a value for this node!"); 400 N = NewN; 401 } 402 403 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, 404 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 405 MachineBasicBlock *SwitchBB, 406 Instruction::BinaryOps Opc, BranchProbability TProb, 407 BranchProbability FProb, bool InvertCond); 408 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, 409 MachineBasicBlock *FBB, 410 MachineBasicBlock *CurBB, 411 MachineBasicBlock *SwitchBB, 412 BranchProbability TProb, BranchProbability FProb, 413 bool InvertCond); 414 bool ShouldEmitAsBranches(const std::vector<SwitchCG::CaseBlock> &Cases); 415 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); 416 void CopyToExportRegsIfNeeded(const Value *V); 417 void ExportFromCurrentBlock(const Value *V); 418 void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, 419 bool IsMustTailCall, const BasicBlock *EHPadBB = nullptr); 420 421 // Lower range metadata from 0 to N to assert zext to an integer of nearest 422 // floor power of two. 423 SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, 424 SDValue Op); 425 426 void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, 427 const CallBase *Call, unsigned ArgIdx, 428 unsigned NumArgs, SDValue Callee, 429 Type *ReturnTy, bool IsPatchPoint); 430 431 std::pair<SDValue, SDValue> 432 lowerInvokable(TargetLowering::CallLoweringInfo &CLI, 433 const BasicBlock *EHPadBB = nullptr); 434 435 /// When an MBB was split during scheduling, update the 436 /// references that need to refer to the last resulting block. 437 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last); 438 439 /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes 440 /// of lowering into a STATEPOINT node. 441 struct StatepointLoweringInfo { 442 /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set 443 /// of gc pointers this STATEPOINT has to relocate. 444 SmallVector<const Value *, 16> Bases; 445 SmallVector<const Value *, 16> Ptrs; 446 447 /// The set of gc.relocate calls associated with this gc.statepoint. 448 SmallVector<const GCRelocateInst *, 16> GCRelocates; 449 450 /// The full list of gc arguments to the gc.statepoint being lowered. 451 ArrayRef<const Use> GCArgs; 452 453 /// The gc.statepoint instruction. 454 const Instruction *StatepointInstr = nullptr; 455 456 /// The list of gc transition arguments present in the gc.statepoint being 457 /// lowered. 458 ArrayRef<const Use> GCTransitionArgs; 459 460 /// The ID that the resulting STATEPOINT instruction has to report. 461 unsigned ID = -1; 462 463 /// Information regarding the underlying call instruction. 464 TargetLowering::CallLoweringInfo CLI; 465 466 /// The deoptimization state associated with this gc.statepoint call, if 467 /// any. 468 ArrayRef<const Use> DeoptState; 469 470 /// Flags associated with the meta arguments being lowered. 471 uint64_t StatepointFlags = -1; 472 473 /// The number of patchable bytes the call needs to get lowered into. 474 unsigned NumPatchBytes = -1; 475 476 /// The exception handling unwind destination, in case this represents an 477 /// invoke of gc.statepoint. 478 const BasicBlock *EHPadBB = nullptr; 479 480 explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {} 481 }; 482 483 /// Lower \p SLI into a STATEPOINT instruction. 484 SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI); 485 486 // This function is responsible for the whole statepoint lowering process. 487 // It uniformly handles invoke and call statepoints. 488 void LowerStatepoint(const GCStatepointInst &I, 489 const BasicBlock *EHPadBB = nullptr); 490 491 void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, 492 const BasicBlock *EHPadBB); 493 494 void LowerDeoptimizeCall(const CallInst *CI); 495 void LowerDeoptimizingReturn(); 496 497 void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee, 498 const BasicBlock *EHPadBB, 499 bool VarArgDisallowed, 500 bool ForceVoidReturnTy); 501 502 /// Returns the type of FrameIndex and TargetFrameIndex nodes. 503 MVT getFrameIndexTy() { 504 return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()); 505 } 506 507 private: 508 // Terminator instructions. 509 void visitRet(const ReturnInst &I); 510 void visitBr(const BranchInst &I); 511 void visitSwitch(const SwitchInst &I); 512 void visitIndirectBr(const IndirectBrInst &I); 513 void visitUnreachable(const UnreachableInst &I); 514 void visitCleanupRet(const CleanupReturnInst &I); 515 void visitCatchSwitch(const CatchSwitchInst &I); 516 void visitCatchRet(const CatchReturnInst &I); 517 void visitCatchPad(const CatchPadInst &I); 518 void visitCleanupPad(const CleanupPadInst &CPI); 519 520 BranchProbability getEdgeProbability(const MachineBasicBlock *Src, 521 const MachineBasicBlock *Dst) const; 522 void addSuccessorWithProb( 523 MachineBasicBlock *Src, MachineBasicBlock *Dst, 524 BranchProbability Prob = BranchProbability::getUnknown()); 525 526 public: 527 void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB); 528 void visitSPDescriptorParent(StackProtectorDescriptor &SPD, 529 MachineBasicBlock *ParentBB); 530 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD); 531 void visitBitTestHeader(SwitchCG::BitTestBlock &B, 532 MachineBasicBlock *SwitchBB); 533 void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, 534 BranchProbability BranchProbToNext, unsigned Reg, 535 SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB); 536 void visitJumpTable(SwitchCG::JumpTable &JT); 537 void visitJumpTableHeader(SwitchCG::JumpTable &JT, 538 SwitchCG::JumpTableHeader &JTH, 539 MachineBasicBlock *SwitchBB); 540 541 private: 542 // These all get lowered before this pass. 543 void visitInvoke(const InvokeInst &I); 544 void visitCallBr(const CallBrInst &I); 545 void visitCallBrLandingPad(const CallInst &I); 546 void visitResume(const ResumeInst &I); 547 548 void visitUnary(const User &I, unsigned Opcode); 549 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } 550 551 void visitBinary(const User &I, unsigned Opcode); 552 void visitShift(const User &I, unsigned Opcode); 553 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); } 554 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } 555 void visitSub(const User &I) { visitBinary(I, ISD::SUB); } 556 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); } 557 void visitMul(const User &I) { visitBinary(I, ISD::MUL); } 558 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } 559 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } 560 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } 561 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } 562 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } 563 void visitSDiv(const User &I); 564 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } 565 void visitAnd (const User &I) { visitBinary(I, ISD::AND); } 566 void visitOr (const User &I) { visitBinary(I, ISD::OR); } 567 void visitXor (const User &I) { visitBinary(I, ISD::XOR); } 568 void visitShl (const User &I) { visitShift(I, ISD::SHL); } 569 void visitLShr(const User &I) { visitShift(I, ISD::SRL); } 570 void visitAShr(const User &I) { visitShift(I, ISD::SRA); } 571 void visitICmp(const User &I); 572 void visitFCmp(const User &I); 573 // Visit the conversion instructions 574 void visitTrunc(const User &I); 575 void visitZExt(const User &I); 576 void visitSExt(const User &I); 577 void visitFPTrunc(const User &I); 578 void visitFPExt(const User &I); 579 void visitFPToUI(const User &I); 580 void visitFPToSI(const User &I); 581 void visitUIToFP(const User &I); 582 void visitSIToFP(const User &I); 583 void visitPtrToInt(const User &I); 584 void visitIntToPtr(const User &I); 585 void visitBitCast(const User &I); 586 void visitAddrSpaceCast(const User &I); 587 588 void visitExtractElement(const User &I); 589 void visitInsertElement(const User &I); 590 void visitShuffleVector(const User &I); 591 592 void visitExtractValue(const ExtractValueInst &I); 593 void visitInsertValue(const InsertValueInst &I); 594 void visitLandingPad(const LandingPadInst &LP); 595 596 void visitGetElementPtr(const User &I); 597 void visitSelect(const User &I); 598 599 void visitAlloca(const AllocaInst &I); 600 void visitLoad(const LoadInst &I); 601 void visitStore(const StoreInst &I); 602 void visitMaskedLoad(const CallInst &I, bool IsExpanding = false); 603 void visitMaskedStore(const CallInst &I, bool IsCompressing = false); 604 void visitMaskedGather(const CallInst &I); 605 void visitMaskedScatter(const CallInst &I); 606 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I); 607 void visitAtomicRMW(const AtomicRMWInst &I); 608 void visitFence(const FenceInst &I); 609 void visitPHI(const PHINode &I); 610 void visitCall(const CallInst &I); 611 bool visitMemCmpBCmpCall(const CallInst &I); 612 bool visitMemPCpyCall(const CallInst &I); 613 bool visitMemChrCall(const CallInst &I); 614 bool visitStrCpyCall(const CallInst &I, bool isStpcpy); 615 bool visitStrCmpCall(const CallInst &I); 616 bool visitStrLenCall(const CallInst &I); 617 bool visitStrNLenCall(const CallInst &I); 618 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode); 619 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode); 620 void visitAtomicLoad(const LoadInst &I); 621 void visitAtomicStore(const StoreInst &I); 622 void visitLoadFromSwiftError(const LoadInst &I); 623 void visitStoreToSwiftError(const StoreInst &I); 624 void visitFreeze(const FreezeInst &I); 625 626 void visitInlineAsm(const CallBase &Call, 627 const BasicBlock *EHPadBB = nullptr); 628 void visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); 629 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); 630 void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI); 631 void visitVPLoad(const VPIntrinsic &VPIntrin, EVT VT, 632 const SmallVectorImpl<SDValue> &OpValues); 633 void visitVPStore(const VPIntrinsic &VPIntrin, 634 const SmallVectorImpl<SDValue> &OpValues); 635 void visitVPGather(const VPIntrinsic &VPIntrin, EVT VT, 636 const SmallVectorImpl<SDValue> &OpValues); 637 void visitVPScatter(const VPIntrinsic &VPIntrin, 638 const SmallVectorImpl<SDValue> &OpValues); 639 void visitVPStridedLoad(const VPIntrinsic &VPIntrin, EVT VT, 640 const SmallVectorImpl<SDValue> &OpValues); 641 void visitVPStridedStore(const VPIntrinsic &VPIntrin, 642 const SmallVectorImpl<SDValue> &OpValues); 643 void visitVPCmp(const VPCmpIntrinsic &VPIntrin); 644 void visitVectorPredicationIntrinsic(const VPIntrinsic &VPIntrin); 645 646 void visitVAStart(const CallInst &I); 647 void visitVAArg(const VAArgInst &I); 648 void visitVAEnd(const CallInst &I); 649 void visitVACopy(const CallInst &I); 650 void visitStackmap(const CallInst &I); 651 void visitPatchpoint(const CallBase &CB, const BasicBlock *EHPadBB = nullptr); 652 653 // These two are implemented in StatepointLowering.cpp 654 void visitGCRelocate(const GCRelocateInst &Relocate); 655 void visitGCResult(const GCResultInst &I); 656 657 void visitVectorReduce(const CallInst &I, unsigned Intrinsic); 658 void visitVectorReverse(const CallInst &I); 659 void visitVectorSplice(const CallInst &I); 660 void visitVectorInterleave(const CallInst &I); 661 void visitVectorDeinterleave(const CallInst &I); 662 void visitStepVector(const CallInst &I); 663 664 void visitUserOp1(const Instruction &I) { 665 llvm_unreachable("UserOp1 should not exist at instruction selection time!"); 666 } 667 void visitUserOp2(const Instruction &I) { 668 llvm_unreachable("UserOp2 should not exist at instruction selection time!"); 669 } 670 671 void processIntegerCallValue(const Instruction &I, 672 SDValue Value, bool IsSigned); 673 674 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 675 676 void emitInlineAsmError(const CallBase &Call, const Twine &Message); 677 678 /// An enum that states to emit func argument dbg value the kind of intrinsic 679 /// it originally had. This controls the internal behavior of 680 /// EmitFuncArgumentDbgValue. 681 enum class FuncArgumentDbgValueKind { 682 Value, // This was originally a llvm.dbg.value. 683 Declare, // This was originally a llvm.dbg.declare. 684 }; 685 686 /// If V is an function argument then create corresponding DBG_VALUE machine 687 /// instruction for it now. At the end of instruction selection, they will be 688 /// inserted to the entry BB. 689 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable, 690 DIExpression *Expr, DILocation *DL, 691 FuncArgumentDbgValueKind Kind, 692 const SDValue &N); 693 694 /// Return the next block after MBB, or nullptr if there is none. 695 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB); 696 697 /// Update the DAG and DAG builder with the relevant information after 698 /// a new root node has been created which could be a tail call. 699 void updateDAGForMaybeTailCall(SDValue MaybeTC); 700 701 /// Return the appropriate SDDbgValue based on N. 702 SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable, 703 DIExpression *Expr, const DebugLoc &dl, 704 unsigned DbgSDNodeOrder); 705 706 /// Lowers CallInst to an external symbol. 707 void lowerCallToExternalSymbol(const CallInst &I, const char *FunctionName); 708 709 SDValue lowerStartEH(SDValue Chain, const BasicBlock *EHPadBB, 710 MCSymbol *&BeginLabel); 711 SDValue lowerEndEH(SDValue Chain, const InvokeInst *II, 712 const BasicBlock *EHPadBB, MCSymbol *BeginLabel); 713 }; 714 715 /// This struct represents the registers (physical or virtual) 716 /// that a particular set of values is assigned, and the type information about 717 /// the value. The most common situation is to represent one value at a time, 718 /// but struct or array values are handled element-wise as multiple values. The 719 /// splitting of aggregates is performed recursively, so that we never have 720 /// aggregate-typed registers. The values at this point do not necessarily have 721 /// legal types, so each value may require one or more registers of some legal 722 /// type. 723 /// 724 struct RegsForValue { 725 /// The value types of the values, which may not be legal, and 726 /// may need be promoted or synthesized from one or more registers. 727 SmallVector<EVT, 4> ValueVTs; 728 729 /// The value types of the registers. This is the same size as ValueVTs and it 730 /// records, for each value, what the type of the assigned register or 731 /// registers are. (Individual values are never synthesized from more than one 732 /// type of register.) 733 /// 734 /// With virtual registers, the contents of RegVTs is redundant with TLI's 735 /// getRegisterType member function, however when with physical registers 736 /// it is necessary to have a separate record of the types. 737 SmallVector<MVT, 4> RegVTs; 738 739 /// This list holds the registers assigned to the values. 740 /// Each legal or promoted value requires one register, and each 741 /// expanded value requires multiple registers. 742 SmallVector<unsigned, 4> Regs; 743 744 /// This list holds the number of registers for each value. 745 SmallVector<unsigned, 4> RegCount; 746 747 /// Records if this value needs to be treated in an ABI dependant manner, 748 /// different to normal type legalization. 749 std::optional<CallingConv::ID> CallConv; 750 751 RegsForValue() = default; 752 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt, 753 std::optional<CallingConv::ID> CC = std::nullopt); 754 RegsForValue(LLVMContext &Context, const TargetLowering &TLI, 755 const DataLayout &DL, unsigned Reg, Type *Ty, 756 std::optional<CallingConv::ID> CC); 757 758 bool isABIMangled() const { return CallConv.has_value(); } 759 760 /// Add the specified values to this one. 761 void append(const RegsForValue &RHS) { 762 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 763 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 764 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 765 RegCount.push_back(RHS.Regs.size()); 766 } 767 768 /// Emit a series of CopyFromReg nodes that copies from this value and returns 769 /// the result as a ValueVTs value. This uses Chain/Flag as the input and 770 /// updates them for the output Chain/Flag. If the Flag pointer is NULL, no 771 /// flag is used. 772 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 773 const SDLoc &dl, SDValue &Chain, SDValue *Glue, 774 const Value *V = nullptr) const; 775 776 /// Emit a series of CopyToReg nodes that copies the specified value into the 777 /// registers specified by this object. This uses Chain/Flag as the input and 778 /// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no 779 /// flag is used. If V is not nullptr, then it is used in printing better 780 /// diagnostic messages on error. 781 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, 782 SDValue &Chain, SDValue *Glue, const Value *V = nullptr, 783 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const; 784 785 /// Add this value to the specified inlineasm node operand list. This adds the 786 /// code marker, matching input operand index (if applicable), and includes 787 /// the number of values added into it. 788 void AddInlineAsmOperands(unsigned Code, bool HasMatching, 789 unsigned MatchingIdx, const SDLoc &dl, 790 SelectionDAG &DAG, std::vector<SDValue> &Ops) const; 791 792 /// Check if the total RegCount is greater than one. 793 bool occupiesMultipleRegs() const { 794 return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1; 795 } 796 797 /// Return a list of registers and their sizes. 798 SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const; 799 }; 800 801 } // end namespace llvm 802 803 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 804