xref: /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (revision a4a491e2238b12ccd64d3faf9e6401487f6f1f1b)
1 //===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the SelectionDAG class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/SelectionDAG.h"
14 #include "SDNodeDbgValue.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/APSInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/FoldingSet.h"
21 #include "llvm/ADT/None.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/Analysis/AliasAnalysis.h"
28 #include "llvm/Analysis/MemoryLocation.h"
29 #include "llvm/Analysis/ValueTracking.h"
30 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/ISDOpcodes.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/RuntimeLibcalls.h"
39 #include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
40 #include "llvm/CodeGen/SelectionDAGNodes.h"
41 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
42 #include "llvm/CodeGen/TargetFrameLowering.h"
43 #include "llvm/CodeGen/TargetLowering.h"
44 #include "llvm/CodeGen/TargetRegisterInfo.h"
45 #include "llvm/CodeGen/TargetSubtargetInfo.h"
46 #include "llvm/CodeGen/ValueTypes.h"
47 #include "llvm/IR/Constant.h"
48 #include "llvm/IR/Constants.h"
49 #include "llvm/IR/DataLayout.h"
50 #include "llvm/IR/DebugInfoMetadata.h"
51 #include "llvm/IR/DebugLoc.h"
52 #include "llvm/IR/DerivedTypes.h"
53 #include "llvm/IR/Function.h"
54 #include "llvm/IR/GlobalValue.h"
55 #include "llvm/IR/Metadata.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CodeGen.h"
59 #include "llvm/Support/Compiler.h"
60 #include "llvm/Support/Debug.h"
61 #include "llvm/Support/ErrorHandling.h"
62 #include "llvm/Support/KnownBits.h"
63 #include "llvm/Support/MachineValueType.h"
64 #include "llvm/Support/MathExtras.h"
65 #include "llvm/Support/Mutex.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetOptions.h"
69 #include "llvm/Transforms/Utils/SizeOpts.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cstdint>
73 #include <cstdlib>
74 #include <limits>
75 #include <set>
76 #include <string>
77 #include <utility>
78 #include <vector>
79 
80 using namespace llvm;
81 
82 /// makeVTList - Return an instance of the SDVTList struct initialized with the
83 /// specified members.
84 static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
85   SDVTList Res = {VTs, NumVTs};
86   return Res;
87 }
88 
89 // Default null implementations of the callbacks.
90 void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode*, SDNode*) {}
91 void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {}
92 void SelectionDAG::DAGUpdateListener::NodeInserted(SDNode *) {}
93 
94 void SelectionDAG::DAGNodeDeletedListener::anchor() {}
95 
96 #define DEBUG_TYPE "selectiondag"
97 
98 static cl::opt<bool> EnableMemCpyDAGOpt("enable-memcpy-dag-opt",
99        cl::Hidden, cl::init(true),
100        cl::desc("Gang up loads and stores generated by inlining of memcpy"));
101 
102 static cl::opt<int> MaxLdStGlue("ldstmemcpy-glue-max",
103        cl::desc("Number limit for gluing ld/st of memcpy."),
104        cl::Hidden, cl::init(0));
105 
106 static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G) {
107   LLVM_DEBUG(dbgs() << Msg; V.getNode()->dump(G););
108 }
109 
110 //===----------------------------------------------------------------------===//
111 //                              ConstantFPSDNode Class
112 //===----------------------------------------------------------------------===//
113 
114 /// isExactlyValue - We don't rely on operator== working on double values, as
115 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
116 /// As such, this method can be used to do an exact bit-for-bit comparison of
117 /// two floating point values.
118 bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
119   return getValueAPF().bitwiseIsEqual(V);
120 }
121 
122 bool ConstantFPSDNode::isValueValidForType(EVT VT,
123                                            const APFloat& Val) {
124   assert(VT.isFloatingPoint() && "Can only convert between FP types");
125 
126   // convert modifies in place, so make a copy.
127   APFloat Val2 = APFloat(Val);
128   bool losesInfo;
129   (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
130                       APFloat::rmNearestTiesToEven,
131                       &losesInfo);
132   return !losesInfo;
133 }
134 
135 //===----------------------------------------------------------------------===//
136 //                              ISD Namespace
137 //===----------------------------------------------------------------------===//
138 
139 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) {
140   if (N->getOpcode() == ISD::SPLAT_VECTOR) {
141     unsigned EltSize =
142         N->getValueType(0).getVectorElementType().getSizeInBits();
143     if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
144       SplatVal = Op0->getAPIntValue().trunc(EltSize);
145       return true;
146     }
147     if (auto *Op0 = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) {
148       SplatVal = Op0->getValueAPF().bitcastToAPInt().trunc(EltSize);
149       return true;
150     }
151   }
152 
153   auto *BV = dyn_cast<BuildVectorSDNode>(N);
154   if (!BV)
155     return false;
156 
157   APInt SplatUndef;
158   unsigned SplatBitSize;
159   bool HasUndefs;
160   unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits();
161   return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
162                              EltSize) &&
163          EltSize == SplatBitSize;
164 }
165 
166 // FIXME: AllOnes and AllZeros duplicate a lot of code. Could these be
167 // specializations of the more general isConstantSplatVector()?
168 
169 bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
170   // Look through a bit convert.
171   while (N->getOpcode() == ISD::BITCAST)
172     N = N->getOperand(0).getNode();
173 
174   if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) {
175     APInt SplatVal;
176     return isConstantSplatVector(N, SplatVal) && SplatVal.isAllOnes();
177   }
178 
179   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
180 
181   unsigned i = 0, e = N->getNumOperands();
182 
183   // Skip over all of the undef values.
184   while (i != e && N->getOperand(i).isUndef())
185     ++i;
186 
187   // Do not accept an all-undef vector.
188   if (i == e) return false;
189 
190   // Do not accept build_vectors that aren't all constants or which have non-~0
191   // elements. We have to be a bit careful here, as the type of the constant
192   // may not be the same as the type of the vector elements due to type
193   // legalization (the elements are promoted to a legal type for the target and
194   // a vector of a type may be legal when the base element type is not).
195   // We only want to check enough bits to cover the vector elements, because
196   // we care if the resultant vector is all ones, not whether the individual
197   // constants are.
198   SDValue NotZero = N->getOperand(i);
199   unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
200   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(NotZero)) {
201     if (CN->getAPIntValue().countTrailingOnes() < EltSize)
202       return false;
203   } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(NotZero)) {
204     if (CFPN->getValueAPF().bitcastToAPInt().countTrailingOnes() < EltSize)
205       return false;
206   } else
207     return false;
208 
209   // Okay, we have at least one ~0 value, check to see if the rest match or are
210   // undefs. Even with the above element type twiddling, this should be OK, as
211   // the same type legalization should have applied to all the elements.
212   for (++i; i != e; ++i)
213     if (N->getOperand(i) != NotZero && !N->getOperand(i).isUndef())
214       return false;
215   return true;
216 }
217 
218 bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) {
219   // Look through a bit convert.
220   while (N->getOpcode() == ISD::BITCAST)
221     N = N->getOperand(0).getNode();
222 
223   if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) {
224     APInt SplatVal;
225     return isConstantSplatVector(N, SplatVal) && SplatVal.isZero();
226   }
227 
228   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
229 
230   bool IsAllUndef = true;
231   for (const SDValue &Op : N->op_values()) {
232     if (Op.isUndef())
233       continue;
234     IsAllUndef = false;
235     // Do not accept build_vectors that aren't all constants or which have non-0
236     // elements. We have to be a bit careful here, as the type of the constant
237     // may not be the same as the type of the vector elements due to type
238     // legalization (the elements are promoted to a legal type for the target
239     // and a vector of a type may be legal when the base element type is not).
240     // We only want to check enough bits to cover the vector elements, because
241     // we care if the resultant vector is all zeros, not whether the individual
242     // constants are.
243     unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
244     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op)) {
245       if (CN->getAPIntValue().countTrailingZeros() < EltSize)
246         return false;
247     } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Op)) {
248       if (CFPN->getValueAPF().bitcastToAPInt().countTrailingZeros() < EltSize)
249         return false;
250     } else
251       return false;
252   }
253 
254   // Do not accept an all-undef vector.
255   if (IsAllUndef)
256     return false;
257   return true;
258 }
259 
260 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
261   return isConstantSplatVectorAllOnes(N, /*BuildVectorOnly*/ true);
262 }
263 
264 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
265   return isConstantSplatVectorAllZeros(N, /*BuildVectorOnly*/ true);
266 }
267 
268 bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) {
269   if (N->getOpcode() != ISD::BUILD_VECTOR)
270     return false;
271 
272   for (const SDValue &Op : N->op_values()) {
273     if (Op.isUndef())
274       continue;
275     if (!isa<ConstantSDNode>(Op))
276       return false;
277   }
278   return true;
279 }
280 
281 bool ISD::isBuildVectorOfConstantFPSDNodes(const SDNode *N) {
282   if (N->getOpcode() != ISD::BUILD_VECTOR)
283     return false;
284 
285   for (const SDValue &Op : N->op_values()) {
286     if (Op.isUndef())
287       continue;
288     if (!isa<ConstantFPSDNode>(Op))
289       return false;
290   }
291   return true;
292 }
293 
294 bool ISD::allOperandsUndef(const SDNode *N) {
295   // Return false if the node has no operands.
296   // This is "logically inconsistent" with the definition of "all" but
297   // is probably the desired behavior.
298   if (N->getNumOperands() == 0)
299     return false;
300   return all_of(N->op_values(), [](SDValue Op) { return Op.isUndef(); });
301 }
302 
303 bool ISD::matchUnaryPredicate(SDValue Op,
304                               std::function<bool(ConstantSDNode *)> Match,
305                               bool AllowUndefs) {
306   // FIXME: Add support for scalar UNDEF cases?
307   if (auto *Cst = dyn_cast<ConstantSDNode>(Op))
308     return Match(Cst);
309 
310   // FIXME: Add support for vector UNDEF cases?
311   if (ISD::BUILD_VECTOR != Op.getOpcode() &&
312       ISD::SPLAT_VECTOR != Op.getOpcode())
313     return false;
314 
315   EVT SVT = Op.getValueType().getScalarType();
316   for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
317     if (AllowUndefs && Op.getOperand(i).isUndef()) {
318       if (!Match(nullptr))
319         return false;
320       continue;
321     }
322 
323     auto *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(i));
324     if (!Cst || Cst->getValueType(0) != SVT || !Match(Cst))
325       return false;
326   }
327   return true;
328 }
329 
330 bool ISD::matchBinaryPredicate(
331     SDValue LHS, SDValue RHS,
332     std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
333     bool AllowUndefs, bool AllowTypeMismatch) {
334   if (!AllowTypeMismatch && LHS.getValueType() != RHS.getValueType())
335     return false;
336 
337   // TODO: Add support for scalar UNDEF cases?
338   if (auto *LHSCst = dyn_cast<ConstantSDNode>(LHS))
339     if (auto *RHSCst = dyn_cast<ConstantSDNode>(RHS))
340       return Match(LHSCst, RHSCst);
341 
342   // TODO: Add support for vector UNDEF cases?
343   if (LHS.getOpcode() != RHS.getOpcode() ||
344       (LHS.getOpcode() != ISD::BUILD_VECTOR &&
345        LHS.getOpcode() != ISD::SPLAT_VECTOR))
346     return false;
347 
348   EVT SVT = LHS.getValueType().getScalarType();
349   for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
350     SDValue LHSOp = LHS.getOperand(i);
351     SDValue RHSOp = RHS.getOperand(i);
352     bool LHSUndef = AllowUndefs && LHSOp.isUndef();
353     bool RHSUndef = AllowUndefs && RHSOp.isUndef();
354     auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
355     auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
356     if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
357       return false;
358     if (!AllowTypeMismatch && (LHSOp.getValueType() != SVT ||
359                                LHSOp.getValueType() != RHSOp.getValueType()))
360       return false;
361     if (!Match(LHSCst, RHSCst))
362       return false;
363   }
364   return true;
365 }
366 
367 ISD::NodeType ISD::getVecReduceBaseOpcode(unsigned VecReduceOpcode) {
368   switch (VecReduceOpcode) {
369   default:
370     llvm_unreachable("Expected VECREDUCE opcode");
371   case ISD::VECREDUCE_FADD:
372   case ISD::VECREDUCE_SEQ_FADD:
373   case ISD::VP_REDUCE_FADD:
374   case ISD::VP_REDUCE_SEQ_FADD:
375     return ISD::FADD;
376   case ISD::VECREDUCE_FMUL:
377   case ISD::VECREDUCE_SEQ_FMUL:
378   case ISD::VP_REDUCE_FMUL:
379   case ISD::VP_REDUCE_SEQ_FMUL:
380     return ISD::FMUL;
381   case ISD::VECREDUCE_ADD:
382   case ISD::VP_REDUCE_ADD:
383     return ISD::ADD;
384   case ISD::VECREDUCE_MUL:
385   case ISD::VP_REDUCE_MUL:
386     return ISD::MUL;
387   case ISD::VECREDUCE_AND:
388   case ISD::VP_REDUCE_AND:
389     return ISD::AND;
390   case ISD::VECREDUCE_OR:
391   case ISD::VP_REDUCE_OR:
392     return ISD::OR;
393   case ISD::VECREDUCE_XOR:
394   case ISD::VP_REDUCE_XOR:
395     return ISD::XOR;
396   case ISD::VECREDUCE_SMAX:
397   case ISD::VP_REDUCE_SMAX:
398     return ISD::SMAX;
399   case ISD::VECREDUCE_SMIN:
400   case ISD::VP_REDUCE_SMIN:
401     return ISD::SMIN;
402   case ISD::VECREDUCE_UMAX:
403   case ISD::VP_REDUCE_UMAX:
404     return ISD::UMAX;
405   case ISD::VECREDUCE_UMIN:
406   case ISD::VP_REDUCE_UMIN:
407     return ISD::UMIN;
408   case ISD::VECREDUCE_FMAX:
409   case ISD::VP_REDUCE_FMAX:
410     return ISD::FMAXNUM;
411   case ISD::VECREDUCE_FMIN:
412   case ISD::VP_REDUCE_FMIN:
413     return ISD::FMINNUM;
414   }
415 }
416 
417 bool ISD::isVPOpcode(unsigned Opcode) {
418   switch (Opcode) {
419   default:
420     return false;
421 #define BEGIN_REGISTER_VP_SDNODE(VPSD, ...)                                    \
422   case ISD::VPSD:                                                              \
423     return true;
424 #include "llvm/IR/VPIntrinsics.def"
425   }
426 }
427 
428 bool ISD::isVPBinaryOp(unsigned Opcode) {
429   switch (Opcode) {
430   default:
431     break;
432 #define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
433 #define VP_PROPERTY_BINARYOP return true;
434 #define END_REGISTER_VP_SDNODE(VPSD) break;
435 #include "llvm/IR/VPIntrinsics.def"
436   }
437   return false;
438 }
439 
440 bool ISD::isVPReduction(unsigned Opcode) {
441   switch (Opcode) {
442   default:
443     break;
444 #define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
445 #define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
446 #define END_REGISTER_VP_SDNODE(VPSD) break;
447 #include "llvm/IR/VPIntrinsics.def"
448   }
449   return false;
450 }
451 
452 /// The operand position of the vector mask.
453 Optional<unsigned> ISD::getVPMaskIdx(unsigned Opcode) {
454   switch (Opcode) {
455   default:
456     return None;
457 #define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...)         \
458   case ISD::VPSD:                                                              \
459     return MASKPOS;
460 #include "llvm/IR/VPIntrinsics.def"
461   }
462 }
463 
464 /// The operand position of the explicit vector length parameter.
465 Optional<unsigned> ISD::getVPExplicitVectorLengthIdx(unsigned Opcode) {
466   switch (Opcode) {
467   default:
468     return None;
469 #define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS)      \
470   case ISD::VPSD:                                                              \
471     return EVLPOS;
472 #include "llvm/IR/VPIntrinsics.def"
473   }
474 }
475 
476 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
477   switch (ExtType) {
478   case ISD::EXTLOAD:
479     return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
480   case ISD::SEXTLOAD:
481     return ISD::SIGN_EXTEND;
482   case ISD::ZEXTLOAD:
483     return ISD::ZERO_EXTEND;
484   default:
485     break;
486   }
487 
488   llvm_unreachable("Invalid LoadExtType");
489 }
490 
491 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
492   // To perform this operation, we just need to swap the L and G bits of the
493   // operation.
494   unsigned OldL = (Operation >> 2) & 1;
495   unsigned OldG = (Operation >> 1) & 1;
496   return ISD::CondCode((Operation & ~6) |  // Keep the N, U, E bits
497                        (OldL << 1) |       // New G bit
498                        (OldG << 2));       // New L bit.
499 }
500 
501 static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike) {
502   unsigned Operation = Op;
503   if (isIntegerLike)
504     Operation ^= 7;   // Flip L, G, E bits, but not U.
505   else
506     Operation ^= 15;  // Flip all of the condition bits.
507 
508   if (Operation > ISD::SETTRUE2)
509     Operation &= ~8;  // Don't let N and U bits get set.
510 
511   return ISD::CondCode(Operation);
512 }
513 
514 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) {
515   return getSetCCInverseImpl(Op, Type.isInteger());
516 }
517 
518 ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op,
519                                                bool isIntegerLike) {
520   return getSetCCInverseImpl(Op, isIntegerLike);
521 }
522 
523 /// For an integer comparison, return 1 if the comparison is a signed operation
524 /// and 2 if the result is an unsigned comparison. Return zero if the operation
525 /// does not depend on the sign of the input (setne and seteq).
526 static int isSignedOp(ISD::CondCode Opcode) {
527   switch (Opcode) {
528   default: llvm_unreachable("Illegal integer setcc operation!");
529   case ISD::SETEQ:
530   case ISD::SETNE: return 0;
531   case ISD::SETLT:
532   case ISD::SETLE:
533   case ISD::SETGT:
534   case ISD::SETGE: return 1;
535   case ISD::SETULT:
536   case ISD::SETULE:
537   case ISD::SETUGT:
538   case ISD::SETUGE: return 2;
539   }
540 }
541 
542 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
543                                        EVT Type) {
544   bool IsInteger = Type.isInteger();
545   if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
546     // Cannot fold a signed integer setcc with an unsigned integer setcc.
547     return ISD::SETCC_INVALID;
548 
549   unsigned Op = Op1 | Op2;  // Combine all of the condition bits.
550 
551   // If the N and U bits get set, then the resultant comparison DOES suddenly
552   // care about orderedness, and it is true when ordered.
553   if (Op > ISD::SETTRUE2)
554     Op &= ~16;     // Clear the U bit if the N bit is set.
555 
556   // Canonicalize illegal integer setcc's.
557   if (IsInteger && Op == ISD::SETUNE)  // e.g. SETUGT | SETULT
558     Op = ISD::SETNE;
559 
560   return ISD::CondCode(Op);
561 }
562 
563 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
564                                         EVT Type) {
565   bool IsInteger = Type.isInteger();
566   if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
567     // Cannot fold a signed setcc with an unsigned setcc.
568     return ISD::SETCC_INVALID;
569 
570   // Combine all of the condition bits.
571   ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
572 
573   // Canonicalize illegal integer setcc's.
574   if (IsInteger) {
575     switch (Result) {
576     default: break;
577     case ISD::SETUO : Result = ISD::SETFALSE; break;  // SETUGT & SETULT
578     case ISD::SETOEQ:                                 // SETEQ  & SETU[LG]E
579     case ISD::SETUEQ: Result = ISD::SETEQ   ; break;  // SETUGE & SETULE
580     case ISD::SETOLT: Result = ISD::SETULT  ; break;  // SETULT & SETNE
581     case ISD::SETOGT: Result = ISD::SETUGT  ; break;  // SETUGT & SETNE
582     }
583   }
584 
585   return Result;
586 }
587 
588 //===----------------------------------------------------------------------===//
589 //                           SDNode Profile Support
590 //===----------------------------------------------------------------------===//
591 
592 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
593 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)  {
594   ID.AddInteger(OpC);
595 }
596 
597 /// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
598 /// solely with their pointer.
599 static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
600   ID.AddPointer(VTList.VTs);
601 }
602 
603 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
604 static void AddNodeIDOperands(FoldingSetNodeID &ID,
605                               ArrayRef<SDValue> Ops) {
606   for (const auto &Op : Ops) {
607     ID.AddPointer(Op.getNode());
608     ID.AddInteger(Op.getResNo());
609   }
610 }
611 
612 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
613 static void AddNodeIDOperands(FoldingSetNodeID &ID,
614                               ArrayRef<SDUse> Ops) {
615   for (const auto &Op : Ops) {
616     ID.AddPointer(Op.getNode());
617     ID.AddInteger(Op.getResNo());
618   }
619 }
620 
621 static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned short OpC,
622                           SDVTList VTList, ArrayRef<SDValue> OpList) {
623   AddNodeIDOpcode(ID, OpC);
624   AddNodeIDValueTypes(ID, VTList);
625   AddNodeIDOperands(ID, OpList);
626 }
627 
628 /// If this is an SDNode with special info, add this info to the NodeID data.
629 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
630   switch (N->getOpcode()) {
631   case ISD::TargetExternalSymbol:
632   case ISD::ExternalSymbol:
633   case ISD::MCSymbol:
634     llvm_unreachable("Should only be used on nodes with operands");
635   default: break;  // Normal nodes don't need extra info.
636   case ISD::TargetConstant:
637   case ISD::Constant: {
638     const ConstantSDNode *C = cast<ConstantSDNode>(N);
639     ID.AddPointer(C->getConstantIntValue());
640     ID.AddBoolean(C->isOpaque());
641     break;
642   }
643   case ISD::TargetConstantFP:
644   case ISD::ConstantFP:
645     ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue());
646     break;
647   case ISD::TargetGlobalAddress:
648   case ISD::GlobalAddress:
649   case ISD::TargetGlobalTLSAddress:
650   case ISD::GlobalTLSAddress: {
651     const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
652     ID.AddPointer(GA->getGlobal());
653     ID.AddInteger(GA->getOffset());
654     ID.AddInteger(GA->getTargetFlags());
655     break;
656   }
657   case ISD::BasicBlock:
658     ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
659     break;
660   case ISD::Register:
661     ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
662     break;
663   case ISD::RegisterMask:
664     ID.AddPointer(cast<RegisterMaskSDNode>(N)->getRegMask());
665     break;
666   case ISD::SRCVALUE:
667     ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
668     break;
669   case ISD::FrameIndex:
670   case ISD::TargetFrameIndex:
671     ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
672     break;
673   case ISD::LIFETIME_START:
674   case ISD::LIFETIME_END:
675     if (cast<LifetimeSDNode>(N)->hasOffset()) {
676       ID.AddInteger(cast<LifetimeSDNode>(N)->getSize());
677       ID.AddInteger(cast<LifetimeSDNode>(N)->getOffset());
678     }
679     break;
680   case ISD::PSEUDO_PROBE:
681     ID.AddInteger(cast<PseudoProbeSDNode>(N)->getGuid());
682     ID.AddInteger(cast<PseudoProbeSDNode>(N)->getIndex());
683     ID.AddInteger(cast<PseudoProbeSDNode>(N)->getAttributes());
684     break;
685   case ISD::JumpTable:
686   case ISD::TargetJumpTable:
687     ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex());
688     ID.AddInteger(cast<JumpTableSDNode>(N)->getTargetFlags());
689     break;
690   case ISD::ConstantPool:
691   case ISD::TargetConstantPool: {
692     const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
693     ID.AddInteger(CP->getAlign().value());
694     ID.AddInteger(CP->getOffset());
695     if (CP->isMachineConstantPoolEntry())
696       CP->getMachineCPVal()->addSelectionDAGCSEId(ID);
697     else
698       ID.AddPointer(CP->getConstVal());
699     ID.AddInteger(CP->getTargetFlags());
700     break;
701   }
702   case ISD::TargetIndex: {
703     const TargetIndexSDNode *TI = cast<TargetIndexSDNode>(N);
704     ID.AddInteger(TI->getIndex());
705     ID.AddInteger(TI->getOffset());
706     ID.AddInteger(TI->getTargetFlags());
707     break;
708   }
709   case ISD::LOAD: {
710     const LoadSDNode *LD = cast<LoadSDNode>(N);
711     ID.AddInteger(LD->getMemoryVT().getRawBits());
712     ID.AddInteger(LD->getRawSubclassData());
713     ID.AddInteger(LD->getPointerInfo().getAddrSpace());
714     ID.AddInteger(LD->getMemOperand()->getFlags());
715     break;
716   }
717   case ISD::STORE: {
718     const StoreSDNode *ST = cast<StoreSDNode>(N);
719     ID.AddInteger(ST->getMemoryVT().getRawBits());
720     ID.AddInteger(ST->getRawSubclassData());
721     ID.AddInteger(ST->getPointerInfo().getAddrSpace());
722     ID.AddInteger(ST->getMemOperand()->getFlags());
723     break;
724   }
725   case ISD::VP_LOAD: {
726     const VPLoadSDNode *ELD = cast<VPLoadSDNode>(N);
727     ID.AddInteger(ELD->getMemoryVT().getRawBits());
728     ID.AddInteger(ELD->getRawSubclassData());
729     ID.AddInteger(ELD->getPointerInfo().getAddrSpace());
730     ID.AddInteger(ELD->getMemOperand()->getFlags());
731     break;
732   }
733   case ISD::VP_STORE: {
734     const VPStoreSDNode *EST = cast<VPStoreSDNode>(N);
735     ID.AddInteger(EST->getMemoryVT().getRawBits());
736     ID.AddInteger(EST->getRawSubclassData());
737     ID.AddInteger(EST->getPointerInfo().getAddrSpace());
738     ID.AddInteger(EST->getMemOperand()->getFlags());
739     break;
740   }
741   case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
742     const VPStridedLoadSDNode *SLD = cast<VPStridedLoadSDNode>(N);
743     ID.AddInteger(SLD->getMemoryVT().getRawBits());
744     ID.AddInteger(SLD->getRawSubclassData());
745     ID.AddInteger(SLD->getPointerInfo().getAddrSpace());
746     break;
747   }
748   case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
749     const VPStridedStoreSDNode *SST = cast<VPStridedStoreSDNode>(N);
750     ID.AddInteger(SST->getMemoryVT().getRawBits());
751     ID.AddInteger(SST->getRawSubclassData());
752     ID.AddInteger(SST->getPointerInfo().getAddrSpace());
753     break;
754   }
755   case ISD::VP_GATHER: {
756     const VPGatherSDNode *EG = cast<VPGatherSDNode>(N);
757     ID.AddInteger(EG->getMemoryVT().getRawBits());
758     ID.AddInteger(EG->getRawSubclassData());
759     ID.AddInteger(EG->getPointerInfo().getAddrSpace());
760     ID.AddInteger(EG->getMemOperand()->getFlags());
761     break;
762   }
763   case ISD::VP_SCATTER: {
764     const VPScatterSDNode *ES = cast<VPScatterSDNode>(N);
765     ID.AddInteger(ES->getMemoryVT().getRawBits());
766     ID.AddInteger(ES->getRawSubclassData());
767     ID.AddInteger(ES->getPointerInfo().getAddrSpace());
768     ID.AddInteger(ES->getMemOperand()->getFlags());
769     break;
770   }
771   case ISD::MLOAD: {
772     const MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N);
773     ID.AddInteger(MLD->getMemoryVT().getRawBits());
774     ID.AddInteger(MLD->getRawSubclassData());
775     ID.AddInteger(MLD->getPointerInfo().getAddrSpace());
776     ID.AddInteger(MLD->getMemOperand()->getFlags());
777     break;
778   }
779   case ISD::MSTORE: {
780     const MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
781     ID.AddInteger(MST->getMemoryVT().getRawBits());
782     ID.AddInteger(MST->getRawSubclassData());
783     ID.AddInteger(MST->getPointerInfo().getAddrSpace());
784     ID.AddInteger(MST->getMemOperand()->getFlags());
785     break;
786   }
787   case ISD::MGATHER: {
788     const MaskedGatherSDNode *MG = cast<MaskedGatherSDNode>(N);
789     ID.AddInteger(MG->getMemoryVT().getRawBits());
790     ID.AddInteger(MG->getRawSubclassData());
791     ID.AddInteger(MG->getPointerInfo().getAddrSpace());
792     ID.AddInteger(MG->getMemOperand()->getFlags());
793     break;
794   }
795   case ISD::MSCATTER: {
796     const MaskedScatterSDNode *MS = cast<MaskedScatterSDNode>(N);
797     ID.AddInteger(MS->getMemoryVT().getRawBits());
798     ID.AddInteger(MS->getRawSubclassData());
799     ID.AddInteger(MS->getPointerInfo().getAddrSpace());
800     ID.AddInteger(MS->getMemOperand()->getFlags());
801     break;
802   }
803   case ISD::ATOMIC_CMP_SWAP:
804   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
805   case ISD::ATOMIC_SWAP:
806   case ISD::ATOMIC_LOAD_ADD:
807   case ISD::ATOMIC_LOAD_SUB:
808   case ISD::ATOMIC_LOAD_AND:
809   case ISD::ATOMIC_LOAD_CLR:
810   case ISD::ATOMIC_LOAD_OR:
811   case ISD::ATOMIC_LOAD_XOR:
812   case ISD::ATOMIC_LOAD_NAND:
813   case ISD::ATOMIC_LOAD_MIN:
814   case ISD::ATOMIC_LOAD_MAX:
815   case ISD::ATOMIC_LOAD_UMIN:
816   case ISD::ATOMIC_LOAD_UMAX:
817   case ISD::ATOMIC_LOAD:
818   case ISD::ATOMIC_STORE: {
819     const AtomicSDNode *AT = cast<AtomicSDNode>(N);
820     ID.AddInteger(AT->getMemoryVT().getRawBits());
821     ID.AddInteger(AT->getRawSubclassData());
822     ID.AddInteger(AT->getPointerInfo().getAddrSpace());
823     ID.AddInteger(AT->getMemOperand()->getFlags());
824     break;
825   }
826   case ISD::PREFETCH: {
827     const MemSDNode *PF = cast<MemSDNode>(N);
828     ID.AddInteger(PF->getPointerInfo().getAddrSpace());
829     ID.AddInteger(PF->getMemOperand()->getFlags());
830     break;
831   }
832   case ISD::VECTOR_SHUFFLE: {
833     const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
834     for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements();
835          i != e; ++i)
836       ID.AddInteger(SVN->getMaskElt(i));
837     break;
838   }
839   case ISD::TargetBlockAddress:
840   case ISD::BlockAddress: {
841     const BlockAddressSDNode *BA = cast<BlockAddressSDNode>(N);
842     ID.AddPointer(BA->getBlockAddress());
843     ID.AddInteger(BA->getOffset());
844     ID.AddInteger(BA->getTargetFlags());
845     break;
846   }
847   case ISD::AssertAlign:
848     ID.AddInteger(cast<AssertAlignSDNode>(N)->getAlign().value());
849     break;
850   } // end switch (N->getOpcode())
851 
852   // Target specific memory nodes could also have address spaces and flags
853   // to check.
854   if (N->isTargetMemoryOpcode()) {
855     const MemSDNode *MN = cast<MemSDNode>(N);
856     ID.AddInteger(MN->getPointerInfo().getAddrSpace());
857     ID.AddInteger(MN->getMemOperand()->getFlags());
858   }
859 }
860 
861 /// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID
862 /// data.
863 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
864   AddNodeIDOpcode(ID, N->getOpcode());
865   // Add the return value info.
866   AddNodeIDValueTypes(ID, N->getVTList());
867   // Add the operand info.
868   AddNodeIDOperands(ID, N->ops());
869 
870   // Handle SDNode leafs with special info.
871   AddNodeIDCustom(ID, N);
872 }
873 
874 //===----------------------------------------------------------------------===//
875 //                              SelectionDAG Class
876 //===----------------------------------------------------------------------===//
877 
878 /// doNotCSE - Return true if CSE should not be performed for this node.
879 static bool doNotCSE(SDNode *N) {
880   if (N->getValueType(0) == MVT::Glue)
881     return true; // Never CSE anything that produces a flag.
882 
883   switch (N->getOpcode()) {
884   default: break;
885   case ISD::HANDLENODE:
886   case ISD::EH_LABEL:
887     return true;   // Never CSE these nodes.
888   }
889 
890   // Check that remaining values produced are not flags.
891   for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
892     if (N->getValueType(i) == MVT::Glue)
893       return true; // Never CSE anything that produces a flag.
894 
895   return false;
896 }
897 
898 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
899 /// SelectionDAG.
900 void SelectionDAG::RemoveDeadNodes() {
901   // Create a dummy node (which is not added to allnodes), that adds a reference
902   // to the root node, preventing it from being deleted.
903   HandleSDNode Dummy(getRoot());
904 
905   SmallVector<SDNode*, 128> DeadNodes;
906 
907   // Add all obviously-dead nodes to the DeadNodes worklist.
908   for (SDNode &Node : allnodes())
909     if (Node.use_empty())
910       DeadNodes.push_back(&Node);
911 
912   RemoveDeadNodes(DeadNodes);
913 
914   // If the root changed (e.g. it was a dead load, update the root).
915   setRoot(Dummy.getValue());
916 }
917 
918 /// RemoveDeadNodes - This method deletes the unreachable nodes in the
919 /// given list, and any nodes that become unreachable as a result.
920 void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes) {
921 
922   // Process the worklist, deleting the nodes and adding their uses to the
923   // worklist.
924   while (!DeadNodes.empty()) {
925     SDNode *N = DeadNodes.pop_back_val();
926     // Skip to next node if we've already managed to delete the node. This could
927     // happen if replacing a node causes a node previously added to the node to
928     // be deleted.
929     if (N->getOpcode() == ISD::DELETED_NODE)
930       continue;
931 
932     for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
933       DUL->NodeDeleted(N, nullptr);
934 
935     // Take the node out of the appropriate CSE map.
936     RemoveNodeFromCSEMaps(N);
937 
938     // Next, brutally remove the operand list.  This is safe to do, as there are
939     // no cycles in the graph.
940     for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
941       SDUse &Use = *I++;
942       SDNode *Operand = Use.getNode();
943       Use.set(SDValue());
944 
945       // Now that we removed this operand, see if there are no uses of it left.
946       if (Operand->use_empty())
947         DeadNodes.push_back(Operand);
948     }
949 
950     DeallocateNode(N);
951   }
952 }
953 
954 void SelectionDAG::RemoveDeadNode(SDNode *N){
955   SmallVector<SDNode*, 16> DeadNodes(1, N);
956 
957   // Create a dummy node that adds a reference to the root node, preventing
958   // it from being deleted.  (This matters if the root is an operand of the
959   // dead node.)
960   HandleSDNode Dummy(getRoot());
961 
962   RemoveDeadNodes(DeadNodes);
963 }
964 
965 void SelectionDAG::DeleteNode(SDNode *N) {
966   // First take this out of the appropriate CSE map.
967   RemoveNodeFromCSEMaps(N);
968 
969   // Finally, remove uses due to operands of this node, remove from the
970   // AllNodes list, and delete the node.
971   DeleteNodeNotInCSEMaps(N);
972 }
973 
974 void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
975   assert(N->getIterator() != AllNodes.begin() &&
976          "Cannot delete the entry node!");
977   assert(N->use_empty() && "Cannot delete a node that is not dead!");
978 
979   // Drop all of the operands and decrement used node's use counts.
980   N->DropOperands();
981 
982   DeallocateNode(N);
983 }
984 
985 void SDDbgInfo::add(SDDbgValue *V, bool isParameter) {
986   assert(!(V->isVariadic() && isParameter));
987   if (isParameter)
988     ByvalParmDbgValues.push_back(V);
989   else
990     DbgValues.push_back(V);
991   for (const SDNode *Node : V->getSDNodes())
992     if (Node)
993       DbgValMap[Node].push_back(V);
994 }
995 
996 void SDDbgInfo::erase(const SDNode *Node) {
997   DbgValMapType::iterator I = DbgValMap.find(Node);
998   if (I == DbgValMap.end())
999     return;
1000   for (auto &Val: I->second)
1001     Val->setIsInvalidated();
1002   DbgValMap.erase(I);
1003 }
1004 
1005 void SelectionDAG::DeallocateNode(SDNode *N) {
1006   // If we have operands, deallocate them.
1007   removeOperands(N);
1008 
1009   NodeAllocator.Deallocate(AllNodes.remove(N));
1010 
1011   // Set the opcode to DELETED_NODE to help catch bugs when node
1012   // memory is reallocated.
1013   // FIXME: There are places in SDag that have grown a dependency on the opcode
1014   // value in the released node.
1015   __asan_unpoison_memory_region(&N->NodeType, sizeof(N->NodeType));
1016   N->NodeType = ISD::DELETED_NODE;
1017 
1018   // If any of the SDDbgValue nodes refer to this SDNode, invalidate
1019   // them and forget about that node.
1020   DbgInfo->erase(N);
1021 }
1022 
1023 #ifndef NDEBUG
1024 /// VerifySDNode - Check the given SDNode.  Aborts if it is invalid.
1025 static void VerifySDNode(SDNode *N) {
1026   switch (N->getOpcode()) {
1027   default:
1028     break;
1029   case ISD::BUILD_PAIR: {
1030     EVT VT = N->getValueType(0);
1031     assert(N->getNumValues() == 1 && "Too many results!");
1032     assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
1033            "Wrong return type!");
1034     assert(N->getNumOperands() == 2 && "Wrong number of operands!");
1035     assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
1036            "Mismatched operand types!");
1037     assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() &&
1038            "Wrong operand type!");
1039     assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() &&
1040            "Wrong return type size");
1041     break;
1042   }
1043   case ISD::BUILD_VECTOR: {
1044     assert(N->getNumValues() == 1 && "Too many results!");
1045     assert(N->getValueType(0).isVector() && "Wrong return type!");
1046     assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
1047            "Wrong number of operands!");
1048     EVT EltVT = N->getValueType(0).getVectorElementType();
1049     for (const SDUse &Op : N->ops()) {
1050       assert((Op.getValueType() == EltVT ||
1051               (EltVT.isInteger() && Op.getValueType().isInteger() &&
1052                EltVT.bitsLE(Op.getValueType()))) &&
1053              "Wrong operand type!");
1054       assert(Op.getValueType() == N->getOperand(0).getValueType() &&
1055              "Operands must all have the same type");
1056     }
1057     break;
1058   }
1059   }
1060 }
1061 #endif // NDEBUG
1062 
1063 /// Insert a newly allocated node into the DAG.
1064 ///
1065 /// Handles insertion into the all nodes list and CSE map, as well as
1066 /// verification and other common operations when a new node is allocated.
1067 void SelectionDAG::InsertNode(SDNode *N) {
1068   AllNodes.push_back(N);
1069 #ifndef NDEBUG
1070   N->PersistentId = NextPersistentId++;
1071   VerifySDNode(N);
1072 #endif
1073   for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1074     DUL->NodeInserted(N);
1075 }
1076 
1077 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
1078 /// correspond to it.  This is useful when we're about to delete or repurpose
1079 /// the node.  We don't want future request for structurally identical nodes
1080 /// to return N anymore.
1081 bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
1082   bool Erased = false;
1083   switch (N->getOpcode()) {
1084   case ISD::HANDLENODE: return false;  // noop.
1085   case ISD::CONDCODE:
1086     assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
1087            "Cond code doesn't exist!");
1088     Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != nullptr;
1089     CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = nullptr;
1090     break;
1091   case ISD::ExternalSymbol:
1092     Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
1093     break;
1094   case ISD::TargetExternalSymbol: {
1095     ExternalSymbolSDNode *ESN = cast<ExternalSymbolSDNode>(N);
1096     Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1097         ESN->getSymbol(), ESN->getTargetFlags()));
1098     break;
1099   }
1100   case ISD::MCSymbol: {
1101     auto *MCSN = cast<MCSymbolSDNode>(N);
1102     Erased = MCSymbols.erase(MCSN->getMCSymbol());
1103     break;
1104   }
1105   case ISD::VALUETYPE: {
1106     EVT VT = cast<VTSDNode>(N)->getVT();
1107     if (VT.isExtended()) {
1108       Erased = ExtendedValueTypeNodes.erase(VT);
1109     } else {
1110       Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != nullptr;
1111       ValueTypeNodes[VT.getSimpleVT().SimpleTy] = nullptr;
1112     }
1113     break;
1114   }
1115   default:
1116     // Remove it from the CSE Map.
1117     assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
1118     assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
1119     Erased = CSEMap.RemoveNode(N);
1120     break;
1121   }
1122 #ifndef NDEBUG
1123   // Verify that the node was actually in one of the CSE maps, unless it has a
1124   // flag result (which cannot be CSE'd) or is one of the special cases that are
1125   // not subject to CSE.
1126   if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue &&
1127       !N->isMachineOpcode() && !doNotCSE(N)) {
1128     N->dump(this);
1129     dbgs() << "\n";
1130     llvm_unreachable("Node is not in map!");
1131   }
1132 #endif
1133   return Erased;
1134 }
1135 
1136 /// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE
1137 /// maps and modified in place. Add it back to the CSE maps, unless an identical
1138 /// node already exists, in which case transfer all its users to the existing
1139 /// node. This transfer can potentially trigger recursive merging.
1140 void
1141 SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N) {
1142   // For node types that aren't CSE'd, just act as if no identical node
1143   // already exists.
1144   if (!doNotCSE(N)) {
1145     SDNode *Existing = CSEMap.GetOrInsertNode(N);
1146     if (Existing != N) {
1147       // If there was already an existing matching node, use ReplaceAllUsesWith
1148       // to replace the dead one with the existing one.  This can cause
1149       // recursive merging of other unrelated nodes down the line.
1150       ReplaceAllUsesWith(N, Existing);
1151 
1152       // N is now dead. Inform the listeners and delete it.
1153       for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1154         DUL->NodeDeleted(N, Existing);
1155       DeleteNodeNotInCSEMaps(N);
1156       return;
1157     }
1158   }
1159 
1160   // If the node doesn't already exist, we updated it.  Inform listeners.
1161   for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1162     DUL->NodeUpdated(N);
1163 }
1164 
1165 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
1166 /// were replaced with those specified.  If this node is never memoized,
1167 /// return null, otherwise return a pointer to the slot it would take.  If a
1168 /// node already exists with these operands, the slot will be non-null.
1169 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
1170                                            void *&InsertPos) {
1171   if (doNotCSE(N))
1172     return nullptr;
1173 
1174   SDValue Ops[] = { Op };
1175   FoldingSetNodeID ID;
1176   AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
1177   AddNodeIDCustom(ID, N);
1178   SDNode *Node = FindNodeOrInsertPos(ID, SDLoc(N), InsertPos);
1179   if (Node)
1180     Node->intersectFlagsWith(N->getFlags());
1181   return Node;
1182 }
1183 
1184 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
1185 /// were replaced with those specified.  If this node is never memoized,
1186 /// return null, otherwise return a pointer to the slot it would take.  If a
1187 /// node already exists with these operands, the slot will be non-null.
1188 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
1189                                            SDValue Op1, SDValue Op2,
1190                                            void *&InsertPos) {
1191   if (doNotCSE(N))
1192     return nullptr;
1193 
1194   SDValue Ops[] = { Op1, Op2 };
1195   FoldingSetNodeID ID;
1196   AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
1197   AddNodeIDCustom(ID, N);
1198   SDNode *Node = FindNodeOrInsertPos(ID, SDLoc(N), InsertPos);
1199   if (Node)
1200     Node->intersectFlagsWith(N->getFlags());
1201   return Node;
1202 }
1203 
1204 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
1205 /// were replaced with those specified.  If this node is never memoized,
1206 /// return null, otherwise return a pointer to the slot it would take.  If a
1207 /// node already exists with these operands, the slot will be non-null.
1208 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
1209                                            void *&InsertPos) {
1210   if (doNotCSE(N))
1211     return nullptr;
1212 
1213   FoldingSetNodeID ID;
1214   AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
1215   AddNodeIDCustom(ID, N);
1216   SDNode *Node = FindNodeOrInsertPos(ID, SDLoc(N), InsertPos);
1217   if (Node)
1218     Node->intersectFlagsWith(N->getFlags());
1219   return Node;
1220 }
1221 
1222 Align SelectionDAG::getEVTAlign(EVT VT) const {
1223   Type *Ty = VT == MVT::iPTR ?
1224                    PointerType::get(Type::getInt8Ty(*getContext()), 0) :
1225                    VT.getTypeForEVT(*getContext());
1226 
1227   return getDataLayout().getABITypeAlign(Ty);
1228 }
1229 
1230 // EntryNode could meaningfully have debug info if we can find it...
1231 SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOpt::Level OL)
1232     : TM(tm), OptLevel(OL),
1233       EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)),
1234       Root(getEntryNode()) {
1235   InsertNode(&EntryNode);
1236   DbgInfo = new SDDbgInfo();
1237 }
1238 
1239 void SelectionDAG::init(MachineFunction &NewMF,
1240                         OptimizationRemarkEmitter &NewORE,
1241                         Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
1242                         LegacyDivergenceAnalysis * Divergence,
1243                         ProfileSummaryInfo *PSIin,
1244                         BlockFrequencyInfo *BFIin) {
1245   MF = &NewMF;
1246   SDAGISelPass = PassPtr;
1247   ORE = &NewORE;
1248   TLI = getSubtarget().getTargetLowering();
1249   TSI = getSubtarget().getSelectionDAGInfo();
1250   LibInfo = LibraryInfo;
1251   Context = &MF->getFunction().getContext();
1252   DA = Divergence;
1253   PSI = PSIin;
1254   BFI = BFIin;
1255 }
1256 
1257 SelectionDAG::~SelectionDAG() {
1258   assert(!UpdateListeners && "Dangling registered DAGUpdateListeners");
1259   allnodes_clear();
1260   OperandRecycler.clear(OperandAllocator);
1261   delete DbgInfo;
1262 }
1263 
1264 bool SelectionDAG::shouldOptForSize() const {
1265   return MF->getFunction().hasOptSize() ||
1266       llvm::shouldOptimizeForSize(FLI->MBB->getBasicBlock(), PSI, BFI);
1267 }
1268 
1269 void SelectionDAG::allnodes_clear() {
1270   assert(&*AllNodes.begin() == &EntryNode);
1271   AllNodes.remove(AllNodes.begin());
1272   while (!AllNodes.empty())
1273     DeallocateNode(&AllNodes.front());
1274 #ifndef NDEBUG
1275   NextPersistentId = 0;
1276 #endif
1277 }
1278 
1279 SDNode *SelectionDAG::FindNodeOrInsertPos(const FoldingSetNodeID &ID,
1280                                           void *&InsertPos) {
1281   SDNode *N = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
1282   if (N) {
1283     switch (N->getOpcode()) {
1284     default: break;
1285     case ISD::Constant:
1286     case ISD::ConstantFP:
1287       llvm_unreachable("Querying for Constant and ConstantFP nodes requires "
1288                        "debug location.  Use another overload.");
1289     }
1290   }
1291   return N;
1292 }
1293 
1294 SDNode *SelectionDAG::FindNodeOrInsertPos(const FoldingSetNodeID &ID,
1295                                           const SDLoc &DL, void *&InsertPos) {
1296   SDNode *N = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
1297   if (N) {
1298     switch (N->getOpcode()) {
1299     case ISD::Constant:
1300     case ISD::ConstantFP:
1301       // Erase debug location from the node if the node is used at several
1302       // different places. Do not propagate one location to all uses as it
1303       // will cause a worse single stepping debugging experience.
1304       if (N->getDebugLoc() != DL.getDebugLoc())
1305         N->setDebugLoc(DebugLoc());
1306       break;
1307     default:
1308       // When the node's point of use is located earlier in the instruction
1309       // sequence than its prior point of use, update its debug info to the
1310       // earlier location.
1311       if (DL.getIROrder() && DL.getIROrder() < N->getIROrder())
1312         N->setDebugLoc(DL.getDebugLoc());
1313       break;
1314     }
1315   }
1316   return N;
1317 }
1318 
1319 void SelectionDAG::clear() {
1320   allnodes_clear();
1321   OperandRecycler.clear(OperandAllocator);
1322   OperandAllocator.Reset();
1323   CSEMap.clear();
1324 
1325   ExtendedValueTypeNodes.clear();
1326   ExternalSymbols.clear();
1327   TargetExternalSymbols.clear();
1328   MCSymbols.clear();
1329   SDCallSiteDbgInfo.clear();
1330   std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
1331             static_cast<CondCodeSDNode*>(nullptr));
1332   std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
1333             static_cast<SDNode*>(nullptr));
1334 
1335   EntryNode.UseList = nullptr;
1336   InsertNode(&EntryNode);
1337   Root = getEntryNode();
1338   DbgInfo->clear();
1339 }
1340 
1341 SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) {
1342   return VT.bitsGT(Op.getValueType())
1343              ? getNode(ISD::FP_EXTEND, DL, VT, Op)
1344              : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL));
1345 }
1346 
1347 std::pair<SDValue, SDValue>
1348 SelectionDAG::getStrictFPExtendOrRound(SDValue Op, SDValue Chain,
1349                                        const SDLoc &DL, EVT VT) {
1350   assert(!VT.bitsEq(Op.getValueType()) &&
1351          "Strict no-op FP extend/round not allowed.");
1352   SDValue Res =
1353       VT.bitsGT(Op.getValueType())
1354           ? getNode(ISD::STRICT_FP_EXTEND, DL, {VT, MVT::Other}, {Chain, Op})
1355           : getNode(ISD::STRICT_FP_ROUND, DL, {VT, MVT::Other},
1356                     {Chain, Op, getIntPtrConstant(0, DL)});
1357 
1358   return std::pair<SDValue, SDValue>(Res, SDValue(Res.getNode(), 1));
1359 }
1360 
1361 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
1362   return VT.bitsGT(Op.getValueType()) ?
1363     getNode(ISD::ANY_EXTEND, DL, VT, Op) :
1364     getNode(ISD::TRUNCATE, DL, VT, Op);
1365 }
1366 
1367 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
1368   return VT.bitsGT(Op.getValueType()) ?
1369     getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
1370     getNode(ISD::TRUNCATE, DL, VT, Op);
1371 }
1372 
1373 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
1374   return VT.bitsGT(Op.getValueType()) ?
1375     getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
1376     getNode(ISD::TRUNCATE, DL, VT, Op);
1377 }
1378 
1379 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT,
1380                                         EVT OpVT) {
1381   if (VT.bitsLE(Op.getValueType()))
1382     return getNode(ISD::TRUNCATE, SL, VT, Op);
1383 
1384   TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT);
1385   return getNode(TLI->getExtendForContent(BType), SL, VT, Op);
1386 }
1387 
1388 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
1389   EVT OpVT = Op.getValueType();
1390   assert(VT.isInteger() && OpVT.isInteger() &&
1391          "Cannot getZeroExtendInReg FP types");
1392   assert(VT.isVector() == OpVT.isVector() &&
1393          "getZeroExtendInReg type should be vector iff the operand "
1394          "type is vector!");
1395   assert((!VT.isVector() ||
1396           VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
1397          "Vector element counts must match in getZeroExtendInReg");
1398   assert(VT.bitsLE(OpVT) && "Not extending!");
1399   if (OpVT == VT)
1400     return Op;
1401   APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
1402                                    VT.getScalarSizeInBits());
1403   return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
1404 }
1405 
1406 SDValue SelectionDAG::getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
1407   // Only unsigned pointer semantics are supported right now. In the future this
1408   // might delegate to TLI to check pointer signedness.
1409   return getZExtOrTrunc(Op, DL, VT);
1410 }
1411 
1412 SDValue SelectionDAG::getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
1413   // Only unsigned pointer semantics are supported right now. In the future this
1414   // might delegate to TLI to check pointer signedness.
1415   return getZeroExtendInReg(Op, DL, VT);
1416 }
1417 
1418 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
1419 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) {
1420   return getNode(ISD::XOR, DL, VT, Val, getAllOnesConstant(DL, VT));
1421 }
1422 
1423 SDValue SelectionDAG::getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT) {
1424   SDValue TrueValue = getBoolConstant(true, DL, VT, VT);
1425   return getNode(ISD::XOR, DL, VT, Val, TrueValue);
1426 }
1427 
1428 SDValue SelectionDAG::getVPLogicalNOT(const SDLoc &DL, SDValue Val,
1429                                       SDValue Mask, SDValue EVL, EVT VT) {
1430   SDValue TrueValue = getBoolConstant(true, DL, VT, VT);
1431   return getNode(ISD::VP_XOR, DL, VT, Val, TrueValue, Mask, EVL);
1432 }
1433 
1434 SDValue SelectionDAG::getBoolConstant(bool V, const SDLoc &DL, EVT VT,
1435                                       EVT OpVT) {
1436   if (!V)
1437     return getConstant(0, DL, VT);
1438 
1439   switch (TLI->getBooleanContents(OpVT)) {
1440   case TargetLowering::ZeroOrOneBooleanContent:
1441   case TargetLowering::UndefinedBooleanContent:
1442     return getConstant(1, DL, VT);
1443   case TargetLowering::ZeroOrNegativeOneBooleanContent:
1444     return getAllOnesConstant(DL, VT);
1445   }
1446   llvm_unreachable("Unexpected boolean content enum!");
1447 }
1448 
1449 SDValue SelectionDAG::getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
1450                                   bool isT, bool isO) {
1451   EVT EltVT = VT.getScalarType();
1452   assert((EltVT.getSizeInBits() >= 64 ||
1453           (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
1454          "getConstant with a uint64_t value that doesn't fit in the type!");
1455   return getConstant(APInt(EltVT.getSizeInBits(), Val), DL, VT, isT, isO);
1456 }
1457 
1458 SDValue SelectionDAG::getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
1459                                   bool isT, bool isO) {
1460   return getConstant(*ConstantInt::get(*Context, Val), DL, VT, isT, isO);
1461 }
1462 
1463 SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
1464                                   EVT VT, bool isT, bool isO) {
1465   assert(VT.isInteger() && "Cannot create FP integer constant!");
1466 
1467   EVT EltVT = VT.getScalarType();
1468   const ConstantInt *Elt = &Val;
1469 
1470   // In some cases the vector type is legal but the element type is illegal and
1471   // needs to be promoted, for example v8i8 on ARM.  In this case, promote the
1472   // inserted value (the type does not need to match the vector element type).
1473   // Any extra bits introduced will be truncated away.
1474   if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) ==
1475                            TargetLowering::TypePromoteInteger) {
1476     EltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
1477     APInt NewVal = Elt->getValue().zextOrTrunc(EltVT.getSizeInBits());
1478     Elt = ConstantInt::get(*getContext(), NewVal);
1479   }
1480   // In other cases the element type is illegal and needs to be expanded, for
1481   // example v2i64 on MIPS32. In this case, find the nearest legal type, split
1482   // the value into n parts and use a vector type with n-times the elements.
1483   // Then bitcast to the type requested.
1484   // Legalizing constants too early makes the DAGCombiner's job harder so we
1485   // only legalize if the DAG tells us we must produce legal types.
1486   else if (NewNodesMustHaveLegalTypes && VT.isVector() &&
1487            TLI->getTypeAction(*getContext(), EltVT) ==
1488                TargetLowering::TypeExpandInteger) {
1489     const APInt &NewVal = Elt->getValue();
1490     EVT ViaEltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
1491     unsigned ViaEltSizeInBits = ViaEltVT.getSizeInBits();
1492 
1493     // For scalable vectors, try to use a SPLAT_VECTOR_PARTS node.
1494     if (VT.isScalableVector()) {
1495       assert(EltVT.getSizeInBits() % ViaEltSizeInBits == 0 &&
1496              "Can only handle an even split!");
1497       unsigned Parts = EltVT.getSizeInBits() / ViaEltSizeInBits;
1498 
1499       SmallVector<SDValue, 2> ScalarParts;
1500       for (unsigned i = 0; i != Parts; ++i)
1501         ScalarParts.push_back(getConstant(
1502             NewVal.extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits), DL,
1503             ViaEltVT, isT, isO));
1504 
1505       return getNode(ISD::SPLAT_VECTOR_PARTS, DL, VT, ScalarParts);
1506     }
1507 
1508     unsigned ViaVecNumElts = VT.getSizeInBits() / ViaEltSizeInBits;
1509     EVT ViaVecVT = EVT::getVectorVT(*getContext(), ViaEltVT, ViaVecNumElts);
1510 
1511     // Check the temporary vector is the correct size. If this fails then
1512     // getTypeToTransformTo() probably returned a type whose size (in bits)
1513     // isn't a power-of-2 factor of the requested type size.
1514     assert(ViaVecVT.getSizeInBits() == VT.getSizeInBits());
1515 
1516     SmallVector<SDValue, 2> EltParts;
1517     for (unsigned i = 0; i < ViaVecNumElts / VT.getVectorNumElements(); ++i)
1518       EltParts.push_back(getConstant(
1519           NewVal.extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits), DL,
1520           ViaEltVT, isT, isO));
1521 
1522     // EltParts is currently in little endian order. If we actually want
1523     // big-endian order then reverse it now.
1524     if (getDataLayout().isBigEndian())
1525       std::reverse(EltParts.begin(), EltParts.end());
1526 
1527     // The elements must be reversed when the element order is different
1528     // to the endianness of the elements (because the BITCAST is itself a
1529     // vector shuffle in this situation). However, we do not need any code to
1530     // perform this reversal because getConstant() is producing a vector
1531     // splat.
1532     // This situation occurs in MIPS MSA.
1533 
1534     SmallVector<SDValue, 8> Ops;
1535     for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1536       llvm::append_range(Ops, EltParts);
1537 
1538     SDValue V =
1539         getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops));
1540     return V;
1541   }
1542 
1543   assert(Elt->getBitWidth() == EltVT.getSizeInBits() &&
1544          "APInt size does not match type size!");
1545   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
1546   FoldingSetNodeID ID;
1547   AddNodeIDNode(ID, Opc, getVTList(EltVT), None);
1548   ID.AddPointer(Elt);
1549   ID.AddBoolean(isO);
1550   void *IP = nullptr;
1551   SDNode *N = nullptr;
1552   if ((N = FindNodeOrInsertPos(ID, DL, IP)))
1553     if (!VT.isVector())
1554       return SDValue(N, 0);
1555 
1556   if (!N) {
1557     N = newSDNode<ConstantSDNode>(isT, isO, Elt, EltVT);
1558     CSEMap.InsertNode(N, IP);
1559     InsertNode(N);
1560     NewSDValueDbgMsg(SDValue(N, 0), "Creating constant: ", this);
1561   }
1562 
1563   SDValue Result(N, 0);
1564   if (VT.isScalableVector())
1565     Result = getSplatVector(VT, DL, Result);
1566   else if (VT.isVector())
1567     Result = getSplatBuildVector(VT, DL, Result);
1568 
1569   return Result;
1570 }
1571 
1572 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, const SDLoc &DL,
1573                                         bool isTarget) {
1574   return getConstant(Val, DL, TLI->getPointerTy(getDataLayout()), isTarget);
1575 }
1576 
1577 SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
1578                                              const SDLoc &DL, bool LegalTypes) {
1579   assert(VT.isInteger() && "Shift amount is not an integer type!");
1580   EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout(), LegalTypes);
1581   return getConstant(Val, DL, ShiftVT);
1582 }
1583 
1584 SDValue SelectionDAG::getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
1585                                            bool isTarget) {
1586   return getConstant(Val, DL, TLI->getVectorIdxTy(getDataLayout()), isTarget);
1587 }
1588 
1589 SDValue SelectionDAG::getConstantFP(const APFloat &V, const SDLoc &DL, EVT VT,
1590                                     bool isTarget) {
1591   return getConstantFP(*ConstantFP::get(*getContext(), V), DL, VT, isTarget);
1592 }
1593 
1594 SDValue SelectionDAG::getConstantFP(const ConstantFP &V, const SDLoc &DL,
1595                                     EVT VT, bool isTarget) {
1596   assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
1597 
1598   EVT EltVT = VT.getScalarType();
1599 
1600   // Do the map lookup using the actual bit pattern for the floating point
1601   // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
1602   // we don't have issues with SNANs.
1603   unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
1604   FoldingSetNodeID ID;
1605   AddNodeIDNode(ID, Opc, getVTList(EltVT), None);
1606   ID.AddPointer(&V);
1607   void *IP = nullptr;
1608   SDNode *N = nullptr;
1609   if ((N = FindNodeOrInsertPos(ID, DL, IP)))
1610     if (!VT.isVector())
1611       return SDValue(N, 0);
1612 
1613   if (!N) {
1614     N = newSDNode<ConstantFPSDNode>(isTarget, &V, EltVT);
1615     CSEMap.InsertNode(N, IP);
1616     InsertNode(N);
1617   }
1618 
1619   SDValue Result(N, 0);
1620   if (VT.isScalableVector())
1621     Result = getSplatVector(VT, DL, Result);
1622   else if (VT.isVector())
1623     Result = getSplatBuildVector(VT, DL, Result);
1624   NewSDValueDbgMsg(Result, "Creating fp constant: ", this);
1625   return Result;
1626 }
1627 
1628 SDValue SelectionDAG::getConstantFP(double Val, const SDLoc &DL, EVT VT,
1629                                     bool isTarget) {
1630   EVT EltVT = VT.getScalarType();
1631   if (EltVT == MVT::f32)
1632     return getConstantFP(APFloat((float)Val), DL, VT, isTarget);
1633   if (EltVT == MVT::f64)
1634     return getConstantFP(APFloat(Val), DL, VT, isTarget);
1635   if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1636       EltVT == MVT::f16 || EltVT == MVT::bf16) {
1637     bool Ignored;
1638     APFloat APF = APFloat(Val);
1639     APF.convert(EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven,
1640                 &Ignored);
1641     return getConstantFP(APF, DL, VT, isTarget);
1642   }
1643   llvm_unreachable("Unsupported type in getConstantFP");
1644 }
1645 
1646 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
1647                                        EVT VT, int64_t Offset, bool isTargetGA,
1648                                        unsigned TargetFlags) {
1649   assert((TargetFlags == 0 || isTargetGA) &&
1650          "Cannot set target flags on target-independent globals");
1651 
1652   // Truncate (with sign-extension) the offset value to the pointer size.
1653   unsigned BitWidth = getDataLayout().getPointerTypeSizeInBits(GV->getType());
1654   if (BitWidth < 64)
1655     Offset = SignExtend64(Offset, BitWidth);
1656 
1657   unsigned Opc;
1658   if (GV->isThreadLocal())
1659     Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
1660   else
1661     Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
1662 
1663   FoldingSetNodeID ID;
1664   AddNodeIDNode(ID, Opc, getVTList(VT), None);
1665   ID.AddPointer(GV);
1666   ID.AddInteger(Offset);
1667   ID.AddInteger(TargetFlags);
1668   void *IP = nullptr;
1669   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
1670     return SDValue(E, 0);
1671 
1672   auto *N = newSDNode<GlobalAddressSDNode>(
1673       Opc, DL.getIROrder(), DL.getDebugLoc(), GV, VT, Offset, TargetFlags);
1674   CSEMap.InsertNode(N, IP);
1675     InsertNode(N);
1676   return SDValue(N, 0);
1677 }
1678 
1679 SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) {
1680   unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
1681   FoldingSetNodeID ID;
1682   AddNodeIDNode(ID, Opc, getVTList(VT), None);
1683   ID.AddInteger(FI);
1684   void *IP = nullptr;
1685   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1686     return SDValue(E, 0);
1687 
1688   auto *N = newSDNode<FrameIndexSDNode>(FI, VT, isTarget);
1689   CSEMap.InsertNode(N, IP);
1690   InsertNode(N);
1691   return SDValue(N, 0);
1692 }
1693 
1694 SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget,
1695                                    unsigned TargetFlags) {
1696   assert((TargetFlags == 0 || isTarget) &&
1697          "Cannot set target flags on target-independent jump tables");
1698   unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1699   FoldingSetNodeID ID;
1700   AddNodeIDNode(ID, Opc, getVTList(VT), None);
1701   ID.AddInteger(JTI);
1702   ID.AddInteger(TargetFlags);
1703   void *IP = nullptr;
1704   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1705     return SDValue(E, 0);
1706 
1707   auto *N = newSDNode<JumpTableSDNode>(JTI, VT, isTarget, TargetFlags);
1708   CSEMap.InsertNode(N, IP);
1709   InsertNode(N);
1710   return SDValue(N, 0);
1711 }
1712 
1713 SDValue SelectionDAG::getConstantPool(const Constant *C, EVT VT,
1714                                       MaybeAlign Alignment, int Offset,
1715                                       bool isTarget, unsigned TargetFlags) {
1716   assert((TargetFlags == 0 || isTarget) &&
1717          "Cannot set target flags on target-independent globals");
1718   if (!Alignment)
1719     Alignment = shouldOptForSize()
1720                     ? getDataLayout().getABITypeAlign(C->getType())
1721                     : getDataLayout().getPrefTypeAlign(C->getType());
1722   unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1723   FoldingSetNodeID ID;
1724   AddNodeIDNode(ID, Opc, getVTList(VT), None);
1725   ID.AddInteger(Alignment->value());
1726   ID.AddInteger(Offset);
1727   ID.AddPointer(C);
1728   ID.AddInteger(TargetFlags);
1729   void *IP = nullptr;
1730   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1731     return SDValue(E, 0);
1732 
1733   auto *N = newSDNode<ConstantPoolSDNode>(isTarget, C, VT, Offset, *Alignment,
1734                                           TargetFlags);
1735   CSEMap.InsertNode(N, IP);
1736   InsertNode(N);
1737   SDValue V = SDValue(N, 0);
1738   NewSDValueDbgMsg(V, "Creating new constant pool: ", this);
1739   return V;
1740 }
1741 
1742 SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT,
1743                                       MaybeAlign Alignment, int Offset,
1744                                       bool isTarget, unsigned TargetFlags) {
1745   assert((TargetFlags == 0 || isTarget) &&
1746          "Cannot set target flags on target-independent globals");
1747   if (!Alignment)
1748     Alignment = getDataLayout().getPrefTypeAlign(C->getType());
1749   unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1750   FoldingSetNodeID ID;
1751   AddNodeIDNode(ID, Opc, getVTList(VT), None);
1752   ID.AddInteger(Alignment->value());
1753   ID.AddInteger(Offset);
1754   C->addSelectionDAGCSEId(ID);
1755   ID.AddInteger(TargetFlags);
1756   void *IP = nullptr;
1757   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1758     return SDValue(E, 0);
1759 
1760   auto *N = newSDNode<ConstantPoolSDNode>(isTarget, C, VT, Offset, *Alignment,
1761                                           TargetFlags);
1762   CSEMap.InsertNode(N, IP);
1763   InsertNode(N);
1764   return SDValue(N, 0);
1765 }
1766 
1767 SDValue SelectionDAG::getTargetIndex(int Index, EVT VT, int64_t Offset,
1768                                      unsigned TargetFlags) {
1769   FoldingSetNodeID ID;
1770   AddNodeIDNode(ID, ISD::TargetIndex, getVTList(VT), None);
1771   ID.AddInteger(Index);
1772   ID.AddInteger(Offset);
1773   ID.AddInteger(TargetFlags);
1774   void *IP = nullptr;
1775   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1776     return SDValue(E, 0);
1777 
1778   auto *N = newSDNode<TargetIndexSDNode>(Index, VT, Offset, TargetFlags);
1779   CSEMap.InsertNode(N, IP);
1780   InsertNode(N);
1781   return SDValue(N, 0);
1782 }
1783 
1784 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
1785   FoldingSetNodeID ID;
1786   AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), None);
1787   ID.AddPointer(MBB);
1788   void *IP = nullptr;
1789   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
1790     return SDValue(E, 0);
1791 
1792   auto *N = newSDNode<BasicBlockSDNode>(MBB);
1793   CSEMap.InsertNode(N, IP);
1794   InsertNode(N);
1795   return SDValue(N, 0);
1796 }
1797 
1798 SDValue SelectionDAG::getValueType(EVT VT) {
1799   if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
1800       ValueTypeNodes.size())
1801     ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
1802 
1803   SDNode *&N = VT.isExtended() ?
1804     ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
1805 
1806   if (N) return SDValue(N, 0);
1807   N = newSDNode<VTSDNode>(VT);
1808   InsertNode(N);
1809   return SDValue(N, 0);
1810 }
1811 
1812 SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) {
1813   SDNode *&N = ExternalSymbols[Sym];
1814   if (N) return SDValue(N, 0);
1815   N = newSDNode<ExternalSymbolSDNode>(false, Sym, 0, VT);
1816   InsertNode(N);
1817   return SDValue(N, 0);
1818 }
1819 
1820 SDValue SelectionDAG::getMCSymbol(MCSymbol *Sym, EVT VT) {
1821   SDNode *&N = MCSymbols[Sym];
1822   if (N)
1823     return SDValue(N, 0);
1824   N = newSDNode<MCSymbolSDNode>(Sym, VT);
1825   InsertNode(N);
1826   return SDValue(N, 0);
1827 }
1828 
1829 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT,
1830                                               unsigned TargetFlags) {
1831   SDNode *&N =
1832       TargetExternalSymbols[std::pair<std::string, unsigned>(Sym, TargetFlags)];
1833   if (N) return SDValue(N, 0);
1834   N = newSDNode<ExternalSymbolSDNode>(true, Sym, TargetFlags, VT);
1835   InsertNode(N);
1836   return SDValue(N, 0);
1837 }
1838 
1839 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1840   if ((unsigned)Cond >= CondCodeNodes.size())
1841     CondCodeNodes.resize(Cond+1);
1842 
1843   if (!CondCodeNodes[Cond]) {
1844     auto *N = newSDNode<CondCodeSDNode>(Cond);
1845     CondCodeNodes[Cond] = N;
1846     InsertNode(N);
1847   }
1848 
1849   return SDValue(CondCodeNodes[Cond], 0);
1850 }
1851 
1852 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT) {
1853   APInt One(ResVT.getScalarSizeInBits(), 1);
1854   return getStepVector(DL, ResVT, One);
1855 }
1856 
1857 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal) {
1858   assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth());
1859   if (ResVT.isScalableVector())
1860     return getNode(
1861         ISD::STEP_VECTOR, DL, ResVT,
1862         getTargetConstant(StepVal, DL, ResVT.getVectorElementType()));
1863 
1864   SmallVector<SDValue, 16> OpsStepConstants;
1865   for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++)
1866     OpsStepConstants.push_back(
1867         getConstant(StepVal * i, DL, ResVT.getVectorElementType()));
1868   return getBuildVector(ResVT, DL, OpsStepConstants);
1869 }
1870 
1871 /// Swaps the values of N1 and N2. Swaps all indices in the shuffle mask M that
1872 /// point at N1 to point at N2 and indices that point at N2 to point at N1.
1873 static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef<int> M) {
1874   std::swap(N1, N2);
1875   ShuffleVectorSDNode::commuteMask(M);
1876 }
1877 
1878 SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
1879                                        SDValue N2, ArrayRef<int> Mask) {
1880   assert(VT.getVectorNumElements() == Mask.size() &&
1881          "Must have the same number of vector elements as mask elements!");
1882   assert(VT == N1.getValueType() && VT == N2.getValueType() &&
1883          "Invalid VECTOR_SHUFFLE");
1884 
1885   // Canonicalize shuffle undef, undef -> undef
1886   if (N1.isUndef() && N2.isUndef())
1887     return getUNDEF(VT);
1888 
1889   // Validate that all indices in Mask are within the range of the elements
1890   // input to the shuffle.
1891   int NElts = Mask.size();
1892   assert(llvm::all_of(Mask,
1893                       [&](int M) { return M < (NElts * 2) && M >= -1; }) &&
1894          "Index out of range");
1895 
1896   // Copy the mask so we can do any needed cleanup.
1897   SmallVector<int, 8> MaskVec(Mask.begin(), Mask.end());
1898 
1899   // Canonicalize shuffle v, v -> v, undef
1900   if (N1 == N2) {
1901     N2 = getUNDEF(VT);
1902     for (int i = 0; i != NElts; ++i)
1903       if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
1904   }
1905 
1906   // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
1907   if (N1.isUndef())
1908     commuteShuffle(N1, N2, MaskVec);
1909 
1910   if (TLI->hasVectorBlend()) {
1911     // If shuffling a splat, try to blend the splat instead. We do this here so
1912     // that even when this arises during lowering we don't have to re-handle it.
1913     auto BlendSplat = [&](BuildVectorSDNode *BV, int Offset) {
1914       BitVector UndefElements;
1915       SDValue Splat = BV->getSplatValue(&UndefElements);
1916       if (!Splat)
1917         return;
1918 
1919       for (int i = 0; i < NElts; ++i) {
1920         if (MaskVec[i] < Offset || MaskVec[i] >= (Offset + NElts))
1921           continue;
1922 
1923         // If this input comes from undef, mark it as such.
1924         if (UndefElements[MaskVec[i] - Offset]) {
1925           MaskVec[i] = -1;
1926           continue;
1927         }
1928 
1929         // If we can blend a non-undef lane, use that instead.
1930         if (!UndefElements[i])
1931           MaskVec[i] = i + Offset;
1932       }
1933     };
1934     if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
1935       BlendSplat(N1BV, 0);
1936     if (auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
1937       BlendSplat(N2BV, NElts);
1938   }
1939 
1940   // Canonicalize all index into lhs, -> shuffle lhs, undef
1941   // Canonicalize all index into rhs, -> shuffle rhs, undef
1942   bool AllLHS = true, AllRHS = true;
1943   bool N2Undef = N2.isUndef();
1944   for (int i = 0; i != NElts; ++i) {
1945     if (MaskVec[i] >= NElts) {
1946       if (N2Undef)
1947         MaskVec[i] = -1;
1948       else
1949         AllLHS = false;
1950     } else if (MaskVec[i] >= 0) {
1951       AllRHS = false;
1952     }
1953   }
1954   if (AllLHS && AllRHS)
1955     return getUNDEF(VT);
1956   if (AllLHS && !N2Undef)
1957     N2 = getUNDEF(VT);
1958   if (AllRHS) {
1959     N1 = getUNDEF(VT);
1960     commuteShuffle(N1, N2, MaskVec);
1961   }
1962   // Reset our undef status after accounting for the mask.
1963   N2Undef = N2.isUndef();
1964   // Re-check whether both sides ended up undef.
1965   if (N1.isUndef() && N2Undef)
1966     return getUNDEF(VT);
1967 
1968   // If Identity shuffle return that node.
1969   bool Identity = true, AllSame = true;
1970   for (int i = 0; i != NElts; ++i) {
1971     if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
1972     if (MaskVec[i] != MaskVec[0]) AllSame = false;
1973   }
1974   if (Identity && NElts)
1975     return N1;
1976 
1977   // Shuffling a constant splat doesn't change the result.
1978   if (N2Undef) {
1979     SDValue V = N1;
1980 
1981     // Look through any bitcasts. We check that these don't change the number
1982     // (and size) of elements and just changes their types.
1983     while (V.getOpcode() == ISD::BITCAST)
1984       V = V->getOperand(0);
1985 
1986     // A splat should always show up as a build vector node.
1987     if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
1988       BitVector UndefElements;
1989       SDValue Splat = BV->getSplatValue(&UndefElements);
1990       // If this is a splat of an undef, shuffling it is also undef.
1991       if (Splat && Splat.isUndef())
1992         return getUNDEF(VT);
1993 
1994       bool SameNumElts =
1995           V.getValueType().getVectorNumElements() == VT.getVectorNumElements();
1996 
1997       // We only have a splat which can skip shuffles if there is a splatted
1998       // value and no undef lanes rearranged by the shuffle.
1999       if (Splat && UndefElements.none()) {
2000         // Splat of <x, x, ..., x>, return <x, x, ..., x>, provided that the
2001         // number of elements match or the value splatted is a zero constant.
2002         if (SameNumElts)
2003           return N1;
2004         if (auto *C = dyn_cast<ConstantSDNode>(Splat))
2005           if (C->isZero())
2006             return N1;
2007       }
2008 
2009       // If the shuffle itself creates a splat, build the vector directly.
2010       if (AllSame && SameNumElts) {
2011         EVT BuildVT = BV->getValueType(0);
2012         const SDValue &Splatted = BV->getOperand(MaskVec[0]);
2013         SDValue NewBV = getSplatBuildVector(BuildVT, dl, Splatted);
2014 
2015         // We may have jumped through bitcasts, so the type of the
2016         // BUILD_VECTOR may not match the type of the shuffle.
2017         if (BuildVT != VT)
2018           NewBV = getNode(ISD::BITCAST, dl, VT, NewBV);
2019         return NewBV;
2020       }
2021     }
2022   }
2023 
2024   FoldingSetNodeID ID;
2025   SDValue Ops[2] = { N1, N2 };
2026   AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops);
2027   for (int i = 0; i != NElts; ++i)
2028     ID.AddInteger(MaskVec[i]);
2029 
2030   void* IP = nullptr;
2031   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
2032     return SDValue(E, 0);
2033 
2034   // Allocate the mask array for the node out of the BumpPtrAllocator, since
2035   // SDNode doesn't have access to it.  This memory will be "leaked" when
2036   // the node is deallocated, but recovered when the NodeAllocator is released.
2037   int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
2038   llvm::copy(MaskVec, MaskAlloc);
2039 
2040   auto *N = newSDNode<ShuffleVectorSDNode>(VT, dl.getIROrder(),
2041                                            dl.getDebugLoc(), MaskAlloc);
2042   createOperands(N, Ops);
2043 
2044   CSEMap.InsertNode(N, IP);
2045   InsertNode(N);
2046   SDValue V = SDValue(N, 0);
2047   NewSDValueDbgMsg(V, "Creating new node: ", this);
2048   return V;
2049 }
2050 
2051 SDValue SelectionDAG::getCommutedVectorShuffle(const ShuffleVectorSDNode &SV) {
2052   EVT VT = SV.getValueType(0);
2053   SmallVector<int, 8> MaskVec(SV.getMask().begin(), SV.getMask().end());
2054   ShuffleVectorSDNode::commuteMask(MaskVec);
2055 
2056   SDValue Op0 = SV.getOperand(0);
2057   SDValue Op1 = SV.getOperand(1);
2058   return getVectorShuffle(VT, SDLoc(&SV), Op1, Op0, MaskVec);
2059 }
2060 
2061 SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) {
2062   FoldingSetNodeID ID;
2063   AddNodeIDNode(ID, ISD::Register, getVTList(VT), None);
2064   ID.AddInteger(RegNo);
2065   void *IP = nullptr;
2066   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2067     return SDValue(E, 0);
2068 
2069   auto *N = newSDNode<RegisterSDNode>(RegNo, VT);
2070   N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(N, FLI, DA);
2071   CSEMap.InsertNode(N, IP);
2072   InsertNode(N);
2073   return SDValue(N, 0);
2074 }
2075 
2076 SDValue SelectionDAG::getRegisterMask(const uint32_t *RegMask) {
2077   FoldingSetNodeID ID;
2078   AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None);
2079   ID.AddPointer(RegMask);
2080   void *IP = nullptr;
2081   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2082     return SDValue(E, 0);
2083 
2084   auto *N = newSDNode<RegisterMaskSDNode>(RegMask);
2085   CSEMap.InsertNode(N, IP);
2086   InsertNode(N);
2087   return SDValue(N, 0);
2088 }
2089 
2090 SDValue SelectionDAG::getEHLabel(const SDLoc &dl, SDValue Root,
2091                                  MCSymbol *Label) {
2092   return getLabelNode(ISD::EH_LABEL, dl, Root, Label);
2093 }
2094 
2095 SDValue SelectionDAG::getLabelNode(unsigned Opcode, const SDLoc &dl,
2096                                    SDValue Root, MCSymbol *Label) {
2097   FoldingSetNodeID ID;
2098   SDValue Ops[] = { Root };
2099   AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), Ops);
2100   ID.AddPointer(Label);
2101   void *IP = nullptr;
2102   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2103     return SDValue(E, 0);
2104 
2105   auto *N =
2106       newSDNode<LabelSDNode>(Opcode, dl.getIROrder(), dl.getDebugLoc(), Label);
2107   createOperands(N, Ops);
2108 
2109   CSEMap.InsertNode(N, IP);
2110   InsertNode(N);
2111   return SDValue(N, 0);
2112 }
2113 
2114 SDValue SelectionDAG::getBlockAddress(const BlockAddress *BA, EVT VT,
2115                                       int64_t Offset, bool isTarget,
2116                                       unsigned TargetFlags) {
2117   unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress;
2118 
2119   FoldingSetNodeID ID;
2120   AddNodeIDNode(ID, Opc, getVTList(VT), None);
2121   ID.AddPointer(BA);
2122   ID.AddInteger(Offset);
2123   ID.AddInteger(TargetFlags);
2124   void *IP = nullptr;
2125   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2126     return SDValue(E, 0);
2127 
2128   auto *N = newSDNode<BlockAddressSDNode>(Opc, VT, BA, Offset, TargetFlags);
2129   CSEMap.InsertNode(N, IP);
2130   InsertNode(N);
2131   return SDValue(N, 0);
2132 }
2133 
2134 SDValue SelectionDAG::getSrcValue(const Value *V) {
2135   FoldingSetNodeID ID;
2136   AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), None);
2137   ID.AddPointer(V);
2138 
2139   void *IP = nullptr;
2140   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2141     return SDValue(E, 0);
2142 
2143   auto *N = newSDNode<SrcValueSDNode>(V);
2144   CSEMap.InsertNode(N, IP);
2145   InsertNode(N);
2146   return SDValue(N, 0);
2147 }
2148 
2149 SDValue SelectionDAG::getMDNode(const MDNode *MD) {
2150   FoldingSetNodeID ID;
2151   AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), None);
2152   ID.AddPointer(MD);
2153 
2154   void *IP = nullptr;
2155   if (SDNode *E = FindNodeOrInsertPos(ID, IP))
2156     return SDValue(E, 0);
2157 
2158   auto *N = newSDNode<MDNodeSDNode>(MD);
2159   CSEMap.InsertNode(N, IP);
2160   InsertNode(N);
2161   return SDValue(N, 0);
2162 }
2163 
2164 SDValue SelectionDAG::getBitcast(EVT VT, SDValue V) {
2165   if (VT == V.getValueType())
2166     return V;
2167 
2168   return getNode(ISD::BITCAST, SDLoc(V), VT, V);
2169 }
2170 
2171 SDValue SelectionDAG::getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr,
2172                                        unsigned SrcAS, unsigned DestAS) {
2173   SDValue Ops[] = {Ptr};
2174   FoldingSetNodeID ID;
2175   AddNodeIDNode(ID, ISD::ADDRSPACECAST, getVTList(VT), Ops);
2176   ID.AddInteger(SrcAS);
2177   ID.AddInteger(DestAS);
2178 
2179   void *IP = nullptr;
2180   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
2181     return SDValue(E, 0);
2182 
2183   auto *N = newSDNode<AddrSpaceCastSDNode>(dl.getIROrder(), dl.getDebugLoc(),
2184                                            VT, SrcAS, DestAS);
2185   createOperands(N, Ops);
2186 
2187   CSEMap.InsertNode(N, IP);
2188   InsertNode(N);
2189   return SDValue(N, 0);
2190 }
2191 
2192 SDValue SelectionDAG::getFreeze(SDValue V) {
2193   return getNode(ISD::FREEZE, SDLoc(V), V.getValueType(), V);
2194 }
2195 
2196 /// getShiftAmountOperand - Return the specified value casted to
2197 /// the target's desired shift amount type.
2198 SDValue SelectionDAG::getShiftAmountOperand(EVT LHSTy, SDValue Op) {
2199   EVT OpTy = Op.getValueType();
2200   EVT ShTy = TLI->getShiftAmountTy(LHSTy, getDataLayout());
2201   if (OpTy == ShTy || OpTy.isVector()) return Op;
2202 
2203   return getZExtOrTrunc(Op, SDLoc(Op), ShTy);
2204 }
2205 
2206 SDValue SelectionDAG::expandVAArg(SDNode *Node) {
2207   SDLoc dl(Node);
2208   const TargetLowering &TLI = getTargetLoweringInfo();
2209   const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2210   EVT VT = Node->getValueType(0);
2211   SDValue Tmp1 = Node->getOperand(0);
2212   SDValue Tmp2 = Node->getOperand(1);
2213   const MaybeAlign MA(Node->getConstantOperandVal(3));
2214 
2215   SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1,
2216                                Tmp2, MachinePointerInfo(V));
2217   SDValue VAList = VAListLoad;
2218 
2219   if (MA && *MA > TLI.getMinStackArgumentAlignment()) {
2220     VAList = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
2221                      getConstant(MA->value() - 1, dl, VAList.getValueType()));
2222 
2223     VAList =
2224         getNode(ISD::AND, dl, VAList.getValueType(), VAList,
2225                 getConstant(-(int64_t)MA->value(), dl, VAList.getValueType()));
2226   }
2227 
2228   // Increment the pointer, VAList, to the next vaarg
2229   Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
2230                  getConstant(getDataLayout().getTypeAllocSize(
2231                                                VT.getTypeForEVT(*getContext())),
2232                              dl, VAList.getValueType()));
2233   // Store the incremented VAList to the legalized pointer
2234   Tmp1 =
2235       getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V));
2236   // Load the actual argument out of the pointer VAList
2237   return getLoad(VT, dl, Tmp1, VAList, MachinePointerInfo());
2238 }
2239 
2240 SDValue SelectionDAG::expandVACopy(SDNode *Node) {
2241   SDLoc dl(Node);
2242   const TargetLowering &TLI = getTargetLoweringInfo();
2243   // This defaults to loading a pointer from the input and storing it to the
2244   // output, returning the chain.
2245   const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2246   const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2247   SDValue Tmp1 =
2248       getLoad(TLI.getPointerTy(getDataLayout()), dl, Node->getOperand(0),
2249               Node->getOperand(2), MachinePointerInfo(VS));
2250   return getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2251                   MachinePointerInfo(VD));
2252 }
2253 
2254 Align SelectionDAG::getReducedAlign(EVT VT, bool UseABI) {
2255   const DataLayout &DL = getDataLayout();
2256   Type *Ty = VT.getTypeForEVT(*getContext());
2257   Align RedAlign = UseABI ? DL.getABITypeAlign(Ty) : DL.getPrefTypeAlign(Ty);
2258 
2259   if (TLI->isTypeLegal(VT) || !VT.isVector())
2260     return RedAlign;
2261 
2262   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2263   const Align StackAlign = TFI->getStackAlign();
2264 
2265   // See if we can choose a smaller ABI alignment in cases where it's an
2266   // illegal vector type that will get broken down.
2267   if (RedAlign > StackAlign) {
2268     EVT IntermediateVT;
2269     MVT RegisterVT;
2270     unsigned NumIntermediates;
2271     TLI->getVectorTypeBreakdown(*getContext(), VT, IntermediateVT,
2272                                 NumIntermediates, RegisterVT);
2273     Ty = IntermediateVT.getTypeForEVT(*getContext());
2274     Align RedAlign2 = UseABI ? DL.getABITypeAlign(Ty) : DL.getPrefTypeAlign(Ty);
2275     if (RedAlign2 < RedAlign)
2276       RedAlign = RedAlign2;
2277   }
2278 
2279   return RedAlign;
2280 }
2281 
2282 SDValue SelectionDAG::CreateStackTemporary(TypeSize Bytes, Align Alignment) {
2283   MachineFrameInfo &MFI = MF->getFrameInfo();
2284   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2285   int StackID = 0;
2286   if (Bytes.isScalable())
2287     StackID = TFI->getStackIDForScalableVectors();
2288   // The stack id gives an indication of whether the object is scalable or
2289   // not, so it's safe to pass in the minimum size here.
2290   int FrameIdx = MFI.CreateStackObject(Bytes.getKnownMinSize(), Alignment,
2291                                        false, nullptr, StackID);
2292   return getFrameIndex(FrameIdx, TLI->getFrameIndexTy(getDataLayout()));
2293 }
2294 
2295 SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
2296   Type *Ty = VT.getTypeForEVT(*getContext());
2297   Align StackAlign =
2298       std::max(getDataLayout().getPrefTypeAlign(Ty), Align(minAlign));
2299   return CreateStackTemporary(VT.getStoreSize(), StackAlign);
2300 }
2301 
2302 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
2303   TypeSize VT1Size = VT1.getStoreSize();
2304   TypeSize VT2Size = VT2.getStoreSize();
2305   assert(VT1Size.isScalable() == VT2Size.isScalable() &&
2306          "Don't know how to choose the maximum size when creating a stack "
2307          "temporary");
2308   TypeSize Bytes =
2309       VT1Size.getKnownMinSize() > VT2Size.getKnownMinSize() ? VT1Size : VT2Size;
2310 
2311   Type *Ty1 = VT1.getTypeForEVT(*getContext());
2312   Type *Ty2 = VT2.getTypeForEVT(*getContext());
2313   const DataLayout &DL = getDataLayout();
2314   Align Align = std::max(DL.getPrefTypeAlign(Ty1), DL.getPrefTypeAlign(Ty2));
2315   return CreateStackTemporary(Bytes, Align);
2316 }
2317 
2318 SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
2319                                 ISD::CondCode Cond, const SDLoc &dl) {
2320   EVT OpVT = N1.getValueType();
2321 
2322   // These setcc operations always fold.
2323   switch (Cond) {
2324   default: break;
2325   case ISD::SETFALSE:
2326   case ISD::SETFALSE2: return getBoolConstant(false, dl, VT, OpVT);
2327   case ISD::SETTRUE:
2328   case ISD::SETTRUE2: return getBoolConstant(true, dl, VT, OpVT);
2329 
2330   case ISD::SETOEQ:
2331   case ISD::SETOGT:
2332   case ISD::SETOGE:
2333   case ISD::SETOLT:
2334   case ISD::SETOLE:
2335   case ISD::SETONE:
2336   case ISD::SETO:
2337   case ISD::SETUO:
2338   case ISD::SETUEQ:
2339   case ISD::SETUNE:
2340     assert(!OpVT.isInteger() && "Illegal setcc for integer!");
2341     break;
2342   }
2343 
2344   if (OpVT.isInteger()) {
2345     // For EQ and NE, we can always pick a value for the undef to make the
2346     // predicate pass or fail, so we can return undef.
2347     // Matches behavior in llvm::ConstantFoldCompareInstruction.
2348     // icmp eq/ne X, undef -> undef.
2349     if ((N1.isUndef() || N2.isUndef()) &&
2350         (Cond == ISD::SETEQ || Cond == ISD::SETNE))
2351       return getUNDEF(VT);
2352 
2353     // If both operands are undef, we can return undef for int comparison.
2354     // icmp undef, undef -> undef.
2355     if (N1.isUndef() && N2.isUndef())
2356       return getUNDEF(VT);
2357 
2358     // icmp X, X -> true/false
2359     // icmp X, undef -> true/false because undef could be X.
2360     if (N1 == N2)
2361       return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT);
2362   }
2363 
2364   if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2)) {
2365     const APInt &C2 = N2C->getAPIntValue();
2366     if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
2367       const APInt &C1 = N1C->getAPIntValue();
2368 
2369       return getBoolConstant(ICmpInst::compare(C1, C2, getICmpCondCode(Cond)),
2370                              dl, VT, OpVT);
2371     }
2372   }
2373 
2374   auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2375   auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2376 
2377   if (N1CFP && N2CFP) {
2378     APFloat::cmpResult R = N1CFP->getValueAPF().compare(N2CFP->getValueAPF());
2379     switch (Cond) {
2380     default: break;
2381     case ISD::SETEQ:  if (R==APFloat::cmpUnordered)
2382                         return getUNDEF(VT);
2383                       LLVM_FALLTHROUGH;
2384     case ISD::SETOEQ: return getBoolConstant(R==APFloat::cmpEqual, dl, VT,
2385                                              OpVT);
2386     case ISD::SETNE:  if (R==APFloat::cmpUnordered)
2387                         return getUNDEF(VT);
2388                       LLVM_FALLTHROUGH;
2389     case ISD::SETONE: return getBoolConstant(R==APFloat::cmpGreaterThan ||
2390                                              R==APFloat::cmpLessThan, dl, VT,
2391                                              OpVT);
2392     case ISD::SETLT:  if (R==APFloat::cmpUnordered)
2393                         return getUNDEF(VT);
2394                       LLVM_FALLTHROUGH;
2395     case ISD::SETOLT: return getBoolConstant(R==APFloat::cmpLessThan, dl, VT,
2396                                              OpVT);
2397     case ISD::SETGT:  if (R==APFloat::cmpUnordered)
2398                         return getUNDEF(VT);
2399                       LLVM_FALLTHROUGH;
2400     case ISD::SETOGT: return getBoolConstant(R==APFloat::cmpGreaterThan, dl,
2401                                              VT, OpVT);
2402     case ISD::SETLE:  if (R==APFloat::cmpUnordered)
2403                         return getUNDEF(VT);
2404                       LLVM_FALLTHROUGH;
2405     case ISD::SETOLE: return getBoolConstant(R==APFloat::cmpLessThan ||
2406                                              R==APFloat::cmpEqual, dl, VT,
2407                                              OpVT);
2408     case ISD::SETGE:  if (R==APFloat::cmpUnordered)
2409                         return getUNDEF(VT);
2410                       LLVM_FALLTHROUGH;
2411     case ISD::SETOGE: return getBoolConstant(R==APFloat::cmpGreaterThan ||
2412                                          R==APFloat::cmpEqual, dl, VT, OpVT);
2413     case ISD::SETO:   return getBoolConstant(R!=APFloat::cmpUnordered, dl, VT,
2414                                              OpVT);
2415     case ISD::SETUO:  return getBoolConstant(R==APFloat::cmpUnordered, dl, VT,
2416                                              OpVT);
2417     case ISD::SETUEQ: return getBoolConstant(R==APFloat::cmpUnordered ||
2418                                              R==APFloat::cmpEqual, dl, VT,
2419                                              OpVT);
2420     case ISD::SETUNE: return getBoolConstant(R!=APFloat::cmpEqual, dl, VT,
2421                                              OpVT);
2422     case ISD::SETULT: return getBoolConstant(R==APFloat::cmpUnordered ||
2423                                              R==APFloat::cmpLessThan, dl, VT,
2424                                              OpVT);
2425     case ISD::SETUGT: return getBoolConstant(R==APFloat::cmpGreaterThan ||
2426                                              R==APFloat::cmpUnordered, dl, VT,
2427                                              OpVT);
2428     case ISD::SETULE: return getBoolConstant(R!=APFloat::cmpGreaterThan, dl,
2429                                              VT, OpVT);
2430     case ISD::SETUGE: return getBoolConstant(R!=APFloat::cmpLessThan, dl, VT,
2431                                              OpVT);
2432     }
2433   } else if (N1CFP && OpVT.isSimple() && !N2.isUndef()) {
2434     // Ensure that the constant occurs on the RHS.
2435     ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond);
2436     if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT()))
2437       return SDValue();
2438     return getSetCC(dl, VT, N2, N1, SwappedCond);
2439   } else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2440              (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) {
2441     // If an operand is known to be a nan (or undef that could be a nan), we can
2442     // fold it.
2443     // Choosing NaN for the undef will always make unordered comparison succeed
2444     // and ordered comparison fails.
2445     // Matches behavior in llvm::ConstantFoldCompareInstruction.
2446     switch (ISD::getUnorderedFlavor(Cond)) {
2447     default:
2448       llvm_unreachable("Unknown flavor!");
2449     case 0: // Known false.
2450       return getBoolConstant(false, dl, VT, OpVT);
2451     case 1: // Known true.
2452       return getBoolConstant(true, dl, VT, OpVT);
2453     case 2: // Undefined.
2454       return getUNDEF(VT);
2455     }
2456   }
2457 
2458   // Could not fold it.
2459   return SDValue();
2460 }
2461 
2462 /// See if the specified operand can be simplified with the knowledge that only
2463 /// the bits specified by DemandedBits are used.
2464 /// TODO: really we should be making this into the DAG equivalent of
2465 /// SimplifyMultipleUseDemandedBits and not generate any new nodes.
2466 SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &DemandedBits) {
2467   EVT VT = V.getValueType();
2468 
2469   if (VT.isScalableVector())
2470     return SDValue();
2471 
2472   switch (V.getOpcode()) {
2473   default:
2474     return TLI->SimplifyMultipleUseDemandedBits(V, DemandedBits, *this);
2475   case ISD::Constant: {
2476     const APInt &CVal = cast<ConstantSDNode>(V)->getAPIntValue();
2477     APInt NewVal = CVal & DemandedBits;
2478     if (NewVal != CVal)
2479       return getConstant(NewVal, SDLoc(V), V.getValueType());
2480     break;
2481   }
2482   case ISD::SRL:
2483     // Only look at single-use SRLs.
2484     if (!V.getNode()->hasOneUse())
2485       break;
2486     if (auto *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
2487       // See if we can recursively simplify the LHS.
2488       unsigned Amt = RHSC->getZExtValue();
2489 
2490       // Watch out for shift count overflow though.
2491       if (Amt >= DemandedBits.getBitWidth())
2492         break;
2493       APInt SrcDemandedBits = DemandedBits << Amt;
2494       if (SDValue SimplifyLHS = TLI->SimplifyMultipleUseDemandedBits(
2495               V.getOperand(0), SrcDemandedBits, *this))
2496         return getNode(ISD::SRL, SDLoc(V), V.getValueType(), SimplifyLHS,
2497                        V.getOperand(1));
2498     }
2499     break;
2500   }
2501   return SDValue();
2502 }
2503 
2504 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero.  We
2505 /// use this predicate to simplify operations downstream.
2506 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
2507   unsigned BitWidth = Op.getScalarValueSizeInBits();
2508   return MaskedValueIsZero(Op, APInt::getSignMask(BitWidth), Depth);
2509 }
2510 
2511 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero.  We use
2512 /// this predicate to simplify operations downstream.  Mask is known to be zero
2513 /// for bits that V cannot have.
2514 bool SelectionDAG::MaskedValueIsZero(SDValue V, const APInt &Mask,
2515                                      unsigned Depth) const {
2516   return Mask.isSubsetOf(computeKnownBits(V, Depth).Zero);
2517 }
2518 
2519 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero in
2520 /// DemandedElts.  We use this predicate to simplify operations downstream.
2521 /// Mask is known to be zero for bits that V cannot have.
2522 bool SelectionDAG::MaskedValueIsZero(SDValue V, const APInt &Mask,
2523                                      const APInt &DemandedElts,
2524                                      unsigned Depth) const {
2525   return Mask.isSubsetOf(computeKnownBits(V, DemandedElts, Depth).Zero);
2526 }
2527 
2528 /// MaskedVectorIsZero - Return true if 'Op' is known to be zero in
2529 /// DemandedElts.  We use this predicate to simplify operations downstream.
2530 bool SelectionDAG::MaskedVectorIsZero(SDValue V, const APInt &DemandedElts,
2531                                       unsigned Depth /* = 0 */) const {
2532   return computeKnownBits(V, DemandedElts, Depth).isZero();
2533 }
2534 
2535 /// MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.
2536 bool SelectionDAG::MaskedValueIsAllOnes(SDValue V, const APInt &Mask,
2537                                         unsigned Depth) const {
2538   return Mask.isSubsetOf(computeKnownBits(V, Depth).One);
2539 }
2540 
2541 /// isSplatValue - Return true if the vector V has the same value
2542 /// across all DemandedElts. For scalable vectors it does not make
2543 /// sense to specify which elements are demanded or undefined, therefore
2544 /// they are simply ignored.
2545 bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
2546                                 APInt &UndefElts, unsigned Depth) const {
2547   unsigned Opcode = V.getOpcode();
2548   EVT VT = V.getValueType();
2549   assert(VT.isVector() && "Vector type expected");
2550 
2551   if (!VT.isScalableVector() && !DemandedElts)
2552     return false; // No demanded elts, better to assume we don't know anything.
2553 
2554   if (Depth >= MaxRecursionDepth)
2555     return false; // Limit search depth.
2556 
2557   // Deal with some common cases here that work for both fixed and scalable
2558   // vector types.
2559   switch (Opcode) {
2560   case ISD::SPLAT_VECTOR:
2561     UndefElts = V.getOperand(0).isUndef()
2562                     ? APInt::getAllOnes(DemandedElts.getBitWidth())
2563                     : APInt(DemandedElts.getBitWidth(), 0);
2564     return true;
2565   case ISD::ADD:
2566   case ISD::SUB:
2567   case ISD::AND:
2568   case ISD::XOR:
2569   case ISD::OR: {
2570     APInt UndefLHS, UndefRHS;
2571     SDValue LHS = V.getOperand(0);
2572     SDValue RHS = V.getOperand(1);
2573     if (isSplatValue(LHS, DemandedElts, UndefLHS, Depth + 1) &&
2574         isSplatValue(RHS, DemandedElts, UndefRHS, Depth + 1)) {
2575       UndefElts = UndefLHS | UndefRHS;
2576       return true;
2577     }
2578     return false;
2579   }
2580   case ISD::ABS:
2581   case ISD::TRUNCATE:
2582   case ISD::SIGN_EXTEND:
2583   case ISD::ZERO_EXTEND:
2584     return isSplatValue(V.getOperand(0), DemandedElts, UndefElts, Depth + 1);
2585   default:
2586     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
2587         Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID)
2588       return TLI->isSplatValueForTargetNode(V, DemandedElts, UndefElts, Depth);
2589     break;
2590 }
2591 
2592   // We don't support other cases than those above for scalable vectors at
2593   // the moment.
2594   if (VT.isScalableVector())
2595     return false;
2596 
2597   unsigned NumElts = VT.getVectorNumElements();
2598   assert(NumElts == DemandedElts.getBitWidth() && "Vector size mismatch");
2599   UndefElts = APInt::getZero(NumElts);
2600 
2601   switch (Opcode) {
2602   case ISD::BUILD_VECTOR: {
2603     SDValue Scl;
2604     for (unsigned i = 0; i != NumElts; ++i) {
2605       SDValue Op = V.getOperand(i);
2606       if (Op.isUndef()) {
2607         UndefElts.setBit(i);
2608         continue;
2609       }
2610       if (!DemandedElts[i])
2611         continue;
2612       if (Scl && Scl != Op)
2613         return false;
2614       Scl = Op;
2615     }
2616     return true;
2617   }
2618   case ISD::VECTOR_SHUFFLE: {
2619     // Check if this is a shuffle node doing a splat or a shuffle of a splat.
2620     APInt DemandedLHS = APInt::getNullValue(NumElts);
2621     APInt DemandedRHS = APInt::getNullValue(NumElts);
2622     ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2623     for (int i = 0; i != (int)NumElts; ++i) {
2624       int M = Mask[i];
2625       if (M < 0) {
2626         UndefElts.setBit(i);
2627         continue;
2628       }
2629       if (!DemandedElts[i])
2630         continue;
2631       if (M < (int)NumElts)
2632         DemandedLHS.setBit(M);
2633       else
2634         DemandedRHS.setBit(M - NumElts);
2635     }
2636 
2637     // If we aren't demanding either op, assume there's no splat.
2638     // If we are demanding both ops, assume there's no splat.
2639     if ((DemandedLHS.isZero() && DemandedRHS.isZero()) ||
2640         (!DemandedLHS.isZero() && !DemandedRHS.isZero()))
2641       return false;
2642 
2643     // See if the demanded elts of the source op is a splat or we only demand
2644     // one element, which should always be a splat.
2645     // TODO: Handle source ops splats with undefs.
2646     auto CheckSplatSrc = [&](SDValue Src, const APInt &SrcElts) {
2647       APInt SrcUndefs;
2648       return (SrcElts.countPopulation() == 1) ||
2649              (isSplatValue(Src, SrcElts, SrcUndefs, Depth + 1) &&
2650               (SrcElts & SrcUndefs).isZero());
2651     };
2652     if (!DemandedLHS.isZero())
2653       return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2654     return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2655   }
2656   case ISD::EXTRACT_SUBVECTOR: {
2657     // Offset the demanded elts by the subvector index.
2658     SDValue Src = V.getOperand(0);
2659     // We don't support scalable vectors at the moment.
2660     if (Src.getValueType().isScalableVector())
2661       return false;
2662     uint64_t Idx = V.getConstantOperandVal(1);
2663     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2664     APInt UndefSrcElts;
2665     APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
2666     if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) {
2667       UndefElts = UndefSrcElts.extractBits(NumElts, Idx);
2668       return true;
2669     }
2670     break;
2671   }
2672   case ISD::ANY_EXTEND_VECTOR_INREG:
2673   case ISD::SIGN_EXTEND_VECTOR_INREG:
2674   case ISD::ZERO_EXTEND_VECTOR_INREG: {
2675     // Widen the demanded elts by the src element count.
2676     SDValue Src = V.getOperand(0);
2677     // We don't support scalable vectors at the moment.
2678     if (Src.getValueType().isScalableVector())
2679       return false;
2680     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2681     APInt UndefSrcElts;
2682     APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts);
2683     if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) {
2684       UndefElts = UndefSrcElts.trunc(NumElts);
2685       return true;
2686     }
2687     break;
2688   }
2689   case ISD::BITCAST: {
2690     SDValue Src = V.getOperand(0);
2691     EVT SrcVT = Src.getValueType();
2692     unsigned SrcBitWidth = SrcVT.getScalarSizeInBits();
2693     unsigned BitWidth = VT.getScalarSizeInBits();
2694 
2695     // Ignore bitcasts from unsupported types.
2696     // TODO: Add fp support?
2697     if (!SrcVT.isVector() || !SrcVT.isInteger() || !VT.isInteger())
2698       break;
2699 
2700     // Bitcast 'small element' vector to 'large element' vector.
2701     if ((BitWidth % SrcBitWidth) == 0) {
2702       // See if each sub element is a splat.
2703       unsigned Scale = BitWidth / SrcBitWidth;
2704       unsigned NumSrcElts = SrcVT.getVectorNumElements();
2705       APInt ScaledDemandedElts =
2706           APIntOps::ScaleBitMask(DemandedElts, NumSrcElts);
2707       for (unsigned I = 0; I != Scale; ++I) {
2708         APInt SubUndefElts;
2709         APInt SubDemandedElt = APInt::getOneBitSet(Scale, I);
2710         APInt SubDemandedElts = APInt::getSplat(NumSrcElts, SubDemandedElt);
2711         SubDemandedElts &= ScaledDemandedElts;
2712         if (!isSplatValue(Src, SubDemandedElts, SubUndefElts, Depth + 1))
2713           return false;
2714         // TODO: Add support for merging sub undef elements.
2715         if (!SubUndefElts.isZero())
2716           return false;
2717       }
2718       return true;
2719     }
2720     break;
2721   }
2722   }
2723 
2724   return false;
2725 }
2726 
2727 /// Helper wrapper to main isSplatValue function.
2728 bool SelectionDAG::isSplatValue(SDValue V, bool AllowUndefs) const {
2729   EVT VT = V.getValueType();
2730   assert(VT.isVector() && "Vector type expected");
2731 
2732   APInt UndefElts;
2733   APInt DemandedElts;
2734 
2735   // For now we don't support this with scalable vectors.
2736   if (!VT.isScalableVector())
2737     DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
2738   return isSplatValue(V, DemandedElts, UndefElts) &&
2739          (AllowUndefs || !UndefElts);
2740 }
2741 
2742 SDValue SelectionDAG::getSplatSourceVector(SDValue V, int &SplatIdx) {
2743   V = peekThroughExtractSubvectors(V);
2744 
2745   EVT VT = V.getValueType();
2746   unsigned Opcode = V.getOpcode();
2747   switch (Opcode) {
2748   default: {
2749     APInt UndefElts;
2750     APInt DemandedElts;
2751 
2752     if (!VT.isScalableVector())
2753       DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
2754 
2755     if (isSplatValue(V, DemandedElts, UndefElts)) {
2756       if (VT.isScalableVector()) {
2757         // DemandedElts and UndefElts are ignored for scalable vectors, since
2758         // the only supported cases are SPLAT_VECTOR nodes.
2759         SplatIdx = 0;
2760       } else {
2761         // Handle case where all demanded elements are UNDEF.
2762         if (DemandedElts.isSubsetOf(UndefElts)) {
2763           SplatIdx = 0;
2764           return getUNDEF(VT);
2765         }
2766         SplatIdx = (UndefElts & DemandedElts).countTrailingOnes();
2767       }
2768       return V;
2769     }
2770     break;
2771   }
2772   case ISD::SPLAT_VECTOR:
2773     SplatIdx = 0;
2774     return V;
2775   case ISD::VECTOR_SHUFFLE: {
2776     if (VT.isScalableVector())
2777       return SDValue();
2778 
2779     // Check if this is a shuffle node doing a splat.
2780     // TODO - remove this and rely purely on SelectionDAG::isSplatValue,
2781     // getTargetVShiftNode currently struggles without the splat source.
2782     auto *SVN = cast<ShuffleVectorSDNode>(V);
2783     if (!SVN->isSplat())
2784       break;
2785     int Idx = SVN->getSplatIndex();
2786     int NumElts = V.getValueType().getVectorNumElements();
2787     SplatIdx = Idx % NumElts;
2788     return V.getOperand(Idx / NumElts);
2789   }
2790   }
2791 
2792   return SDValue();
2793 }
2794 
2795 SDValue SelectionDAG::getSplatValue(SDValue V, bool LegalTypes) {
2796   int SplatIdx;
2797   if (SDValue SrcVector = getSplatSourceVector(V, SplatIdx)) {
2798     EVT SVT = SrcVector.getValueType().getScalarType();
2799     EVT LegalSVT = SVT;
2800     if (LegalTypes && !TLI->isTypeLegal(SVT)) {
2801       if (!SVT.isInteger())
2802         return SDValue();
2803       LegalSVT = TLI->getTypeToTransformTo(*getContext(), LegalSVT);
2804       if (LegalSVT.bitsLT(SVT))
2805         return SDValue();
2806     }
2807     return getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(V), LegalSVT, SrcVector,
2808                    getVectorIdxConstant(SplatIdx, SDLoc(V)));
2809   }
2810   return SDValue();
2811 }
2812 
2813 const APInt *
2814 SelectionDAG::getValidShiftAmountConstant(SDValue V,
2815                                           const APInt &DemandedElts) const {
2816   assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
2817           V.getOpcode() == ISD::SRA) &&
2818          "Unknown shift node");
2819   unsigned BitWidth = V.getScalarValueSizeInBits();
2820   if (ConstantSDNode *SA = isConstOrConstSplat(V.getOperand(1), DemandedElts)) {
2821     // Shifting more than the bitwidth is not valid.
2822     const APInt &ShAmt = SA->getAPIntValue();
2823     if (ShAmt.ult(BitWidth))
2824       return &ShAmt;
2825   }
2826   return nullptr;
2827 }
2828 
2829 const APInt *SelectionDAG::getValidMinimumShiftAmountConstant(
2830     SDValue V, const APInt &DemandedElts) const {
2831   assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
2832           V.getOpcode() == ISD::SRA) &&
2833          "Unknown shift node");
2834   if (const APInt *ValidAmt = getValidShiftAmountConstant(V, DemandedElts))
2835     return ValidAmt;
2836   unsigned BitWidth = V.getScalarValueSizeInBits();
2837   auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
2838   if (!BV)
2839     return nullptr;
2840   const APInt *MinShAmt = nullptr;
2841   for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2842     if (!DemandedElts[i])
2843       continue;
2844     auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
2845     if (!SA)
2846       return nullptr;
2847     // Shifting more than the bitwidth is not valid.
2848     const APInt &ShAmt = SA->getAPIntValue();
2849     if (ShAmt.uge(BitWidth))
2850       return nullptr;
2851     if (MinShAmt && MinShAmt->ule(ShAmt))
2852       continue;
2853     MinShAmt = &ShAmt;
2854   }
2855   return MinShAmt;
2856 }
2857 
2858 const APInt *SelectionDAG::getValidMaximumShiftAmountConstant(
2859     SDValue V, const APInt &DemandedElts) const {
2860   assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
2861           V.getOpcode() == ISD::SRA) &&
2862          "Unknown shift node");
2863   if (const APInt *ValidAmt = getValidShiftAmountConstant(V, DemandedElts))
2864     return ValidAmt;
2865   unsigned BitWidth = V.getScalarValueSizeInBits();
2866   auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
2867   if (!BV)
2868     return nullptr;
2869   const APInt *MaxShAmt = nullptr;
2870   for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2871     if (!DemandedElts[i])
2872       continue;
2873     auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
2874     if (!SA)
2875       return nullptr;
2876     // Shifting more than the bitwidth is not valid.
2877     const APInt &ShAmt = SA->getAPIntValue();
2878     if (ShAmt.uge(BitWidth))
2879       return nullptr;
2880     if (MaxShAmt && MaxShAmt->uge(ShAmt))
2881       continue;
2882     MaxShAmt = &ShAmt;
2883   }
2884   return MaxShAmt;
2885 }
2886 
2887 /// Determine which bits of Op are known to be either zero or one and return
2888 /// them in Known. For vectors, the known bits are those that are shared by
2889 /// every vector element.
2890 KnownBits SelectionDAG::computeKnownBits(SDValue Op, unsigned Depth) const {
2891   EVT VT = Op.getValueType();
2892 
2893   // TOOD: Until we have a plan for how to represent demanded elements for
2894   // scalable vectors, we can just bail out for now.
2895   if (Op.getValueType().isScalableVector()) {
2896     unsigned BitWidth = Op.getScalarValueSizeInBits();
2897     return KnownBits(BitWidth);
2898   }
2899 
2900   APInt DemandedElts = VT.isVector()
2901                            ? APInt::getAllOnes(VT.getVectorNumElements())
2902                            : APInt(1, 1);
2903   return computeKnownBits(Op, DemandedElts, Depth);
2904 }
2905 
2906 /// Determine which bits of Op are known to be either zero or one and return
2907 /// them in Known. The DemandedElts argument allows us to only collect the known
2908 /// bits that are shared by the requested vector elements.
2909 KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
2910                                          unsigned Depth) const {
2911   unsigned BitWidth = Op.getScalarValueSizeInBits();
2912 
2913   KnownBits Known(BitWidth);   // Don't know anything.
2914 
2915   // TOOD: Until we have a plan for how to represent demanded elements for
2916   // scalable vectors, we can just bail out for now.
2917   if (Op.getValueType().isScalableVector())
2918     return Known;
2919 
2920   if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2921     // We know all of the bits for a constant!
2922     return KnownBits::makeConstant(C->getAPIntValue());
2923   }
2924   if (auto *C = dyn_cast<ConstantFPSDNode>(Op)) {
2925     // We know all of the bits for a constant fp!
2926     return KnownBits::makeConstant(C->getValueAPF().bitcastToAPInt());
2927   }
2928 
2929   if (Depth >= MaxRecursionDepth)
2930     return Known;  // Limit search depth.
2931 
2932   KnownBits Known2;
2933   unsigned NumElts = DemandedElts.getBitWidth();
2934   assert((!Op.getValueType().isVector() ||
2935           NumElts == Op.getValueType().getVectorNumElements()) &&
2936          "Unexpected vector size");
2937 
2938   if (!DemandedElts)
2939     return Known;  // No demanded elts, better to assume we don't know anything.
2940 
2941   unsigned Opcode = Op.getOpcode();
2942   switch (Opcode) {
2943   case ISD::MERGE_VALUES:
2944     return computeKnownBits(Op.getOperand(Op.getResNo()), DemandedElts,
2945                             Depth + 1);
2946   case ISD::BUILD_VECTOR:
2947     // Collect the known bits that are shared by every demanded vector element.
2948     Known.Zero.setAllBits(); Known.One.setAllBits();
2949     for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
2950       if (!DemandedElts[i])
2951         continue;
2952 
2953       SDValue SrcOp = Op.getOperand(i);
2954       Known2 = computeKnownBits(SrcOp, Depth + 1);
2955 
2956       // BUILD_VECTOR can implicitly truncate sources, we must handle this.
2957       if (SrcOp.getValueSizeInBits() != BitWidth) {
2958         assert(SrcOp.getValueSizeInBits() > BitWidth &&
2959                "Expected BUILD_VECTOR implicit truncation");
2960         Known2 = Known2.trunc(BitWidth);
2961       }
2962 
2963       // Known bits are the values that are shared by every demanded element.
2964       Known = KnownBits::commonBits(Known, Known2);
2965 
2966       // If we don't know any bits, early out.
2967       if (Known.isUnknown())
2968         break;
2969     }
2970     break;
2971   case ISD::VECTOR_SHUFFLE: {
2972     // Collect the known bits that are shared by every vector element referenced
2973     // by the shuffle.
2974     APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0);
2975     Known.Zero.setAllBits(); Known.One.setAllBits();
2976     const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2977     assert(NumElts == SVN->getMask().size() && "Unexpected vector size");
2978     for (unsigned i = 0; i != NumElts; ++i) {
2979       if (!DemandedElts[i])
2980         continue;
2981 
2982       int M = SVN->getMaskElt(i);
2983       if (M < 0) {
2984         // For UNDEF elements, we don't know anything about the common state of
2985         // the shuffle result.
2986         Known.resetAll();
2987         DemandedLHS.clearAllBits();
2988         DemandedRHS.clearAllBits();
2989         break;
2990       }
2991 
2992       if ((unsigned)M < NumElts)
2993         DemandedLHS.setBit((unsigned)M % NumElts);
2994       else
2995         DemandedRHS.setBit((unsigned)M % NumElts);
2996     }
2997     // Known bits are the values that are shared by every demanded element.
2998     if (!!DemandedLHS) {
2999       SDValue LHS = Op.getOperand(0);
3000       Known2 = computeKnownBits(LHS, DemandedLHS, Depth + 1);
3001       Known = KnownBits::commonBits(Known, Known2);
3002     }
3003     // If we don't know any bits, early out.
3004     if (Known.isUnknown())
3005       break;
3006     if (!!DemandedRHS) {
3007       SDValue RHS = Op.getOperand(1);
3008       Known2 = computeKnownBits(RHS, DemandedRHS, Depth + 1);
3009       Known = KnownBits::commonBits(Known, Known2);
3010     }
3011     break;
3012   }
3013   case ISD::CONCAT_VECTORS: {
3014     // Split DemandedElts and test each of the demanded subvectors.
3015     Known.Zero.setAllBits(); Known.One.setAllBits();
3016     EVT SubVectorVT = Op.getOperand(0).getValueType();
3017     unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
3018     unsigned NumSubVectors = Op.getNumOperands();
3019     for (unsigned i = 0; i != NumSubVectors; ++i) {
3020       APInt DemandedSub =
3021           DemandedElts.extractBits(NumSubVectorElts, i * NumSubVectorElts);
3022       if (!!DemandedSub) {
3023         SDValue Sub = Op.getOperand(i);
3024         Known2 = computeKnownBits(Sub, DemandedSub, Depth + 1);
3025         Known = KnownBits::commonBits(Known, Known2);
3026       }
3027       // If we don't know any bits, early out.
3028       if (Known.isUnknown())
3029         break;
3030     }
3031     break;
3032   }
3033   case ISD::INSERT_SUBVECTOR: {
3034     // Demand any elements from the subvector and the remainder from the src its
3035     // inserted into.
3036     SDValue Src = Op.getOperand(0);
3037     SDValue Sub = Op.getOperand(1);
3038     uint64_t Idx = Op.getConstantOperandVal(2);
3039     unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
3040     APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
3041     APInt DemandedSrcElts = DemandedElts;
3042     DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx);
3043 
3044     Known.One.setAllBits();
3045     Known.Zero.setAllBits();
3046     if (!!DemandedSubElts) {
3047       Known = computeKnownBits(Sub, DemandedSubElts, Depth + 1);
3048       if (Known.isUnknown())
3049         break; // early-out.
3050     }
3051     if (!!DemandedSrcElts) {
3052       Known2 = computeKnownBits(Src, DemandedSrcElts, Depth + 1);
3053       Known = KnownBits::commonBits(Known, Known2);
3054     }
3055     break;
3056   }
3057   case ISD::EXTRACT_SUBVECTOR: {
3058     // Offset the demanded elts by the subvector index.
3059     SDValue Src = Op.getOperand(0);
3060     // Bail until we can represent demanded elements for scalable vectors.
3061     if (Src.getValueType().isScalableVector())
3062       break;
3063     uint64_t Idx = Op.getConstantOperandVal(1);
3064     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3065     APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
3066     Known = computeKnownBits(Src, DemandedSrcElts, Depth + 1);
3067     break;
3068   }
3069   case ISD::SCALAR_TO_VECTOR: {
3070     // We know about scalar_to_vector as much as we know about it source,
3071     // which becomes the first element of otherwise unknown vector.
3072     if (DemandedElts != 1)
3073       break;
3074 
3075     SDValue N0 = Op.getOperand(0);
3076     Known = computeKnownBits(N0, Depth + 1);
3077     if (N0.getValueSizeInBits() != BitWidth)
3078       Known = Known.trunc(BitWidth);
3079 
3080     break;
3081   }
3082   case ISD::BITCAST: {
3083     SDValue N0 = Op.getOperand(0);
3084     EVT SubVT = N0.getValueType();
3085     unsigned SubBitWidth = SubVT.getScalarSizeInBits();
3086 
3087     // Ignore bitcasts from unsupported types.
3088     if (!(SubVT.isInteger() || SubVT.isFloatingPoint()))
3089       break;
3090 
3091     // Fast handling of 'identity' bitcasts.
3092     if (BitWidth == SubBitWidth) {
3093       Known = computeKnownBits(N0, DemandedElts, Depth + 1);
3094       break;
3095     }
3096 
3097     bool IsLE = getDataLayout().isLittleEndian();
3098 
3099     // Bitcast 'small element' vector to 'large element' scalar/vector.
3100     if ((BitWidth % SubBitWidth) == 0) {
3101       assert(N0.getValueType().isVector() && "Expected bitcast from vector");
3102 
3103       // Collect known bits for the (larger) output by collecting the known
3104       // bits from each set of sub elements and shift these into place.
3105       // We need to separately call computeKnownBits for each set of
3106       // sub elements as the knownbits for each is likely to be different.
3107       unsigned SubScale = BitWidth / SubBitWidth;
3108       APInt SubDemandedElts(NumElts * SubScale, 0);
3109       for (unsigned i = 0; i != NumElts; ++i)
3110         if (DemandedElts[i])
3111           SubDemandedElts.setBit(i * SubScale);
3112 
3113       for (unsigned i = 0; i != SubScale; ++i) {
3114         Known2 = computeKnownBits(N0, SubDemandedElts.shl(i),
3115                          Depth + 1);
3116         unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3117         Known.insertBits(Known2, SubBitWidth * Shifts);
3118       }
3119     }
3120 
3121     // Bitcast 'large element' scalar/vector to 'small element' vector.
3122     if ((SubBitWidth % BitWidth) == 0) {
3123       assert(Op.getValueType().isVector() && "Expected bitcast to vector");
3124 
3125       // Collect known bits for the (smaller) output by collecting the known
3126       // bits from the overlapping larger input elements and extracting the
3127       // sub sections we actually care about.
3128       unsigned SubScale = SubBitWidth / BitWidth;
3129       APInt SubDemandedElts =
3130           APIntOps::ScaleBitMask(DemandedElts, NumElts / SubScale);
3131       Known2 = computeKnownBits(N0, SubDemandedElts, Depth + 1);
3132 
3133       Known.Zero.setAllBits(); Known.One.setAllBits();
3134       for (unsigned i = 0; i != NumElts; ++i)
3135         if (DemandedElts[i]) {
3136           unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3137           unsigned Offset = (Shifts % SubScale) * BitWidth;
3138           Known = KnownBits::commonBits(Known,
3139                                         Known2.extractBits(BitWidth, Offset));
3140           // If we don't know any bits, early out.
3141           if (Known.isUnknown())
3142             break;
3143         }
3144     }
3145     break;
3146   }
3147   case ISD::AND:
3148     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3149     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3150 
3151     Known &= Known2;
3152     break;
3153   case ISD::OR:
3154     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3155     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3156 
3157     Known |= Known2;
3158     break;
3159   case ISD::XOR:
3160     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3161     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3162 
3163     Known ^= Known2;
3164     break;
3165   case ISD::MUL: {
3166     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3167     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3168     bool SelfMultiply = Op.getOperand(0) == Op.getOperand(1);
3169     // TODO: SelfMultiply can be poison, but not undef.
3170     if (SelfMultiply)
3171       SelfMultiply &= isGuaranteedNotToBeUndefOrPoison(
3172           Op.getOperand(0), DemandedElts, false, Depth + 1);
3173     Known = KnownBits::mul(Known, Known2, SelfMultiply);
3174 
3175     // If the multiplication is known not to overflow, the product of a number
3176     // with itself is non-negative. Only do this if we didn't already computed
3177     // the opposite value for the sign bit.
3178     if (Op->getFlags().hasNoSignedWrap() &&
3179         Op.getOperand(0) == Op.getOperand(1) &&
3180         !Known.isNegative())
3181       Known.makeNonNegative();
3182     break;
3183   }
3184   case ISD::MULHU: {
3185     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3186     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3187     Known = KnownBits::mulhu(Known, Known2);
3188     break;
3189   }
3190   case ISD::MULHS: {
3191     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3192     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3193     Known = KnownBits::mulhs(Known, Known2);
3194     break;
3195   }
3196   case ISD::UMUL_LOHI: {
3197     assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result");
3198     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3199     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3200     bool SelfMultiply = Op.getOperand(0) == Op.getOperand(1);
3201     if (Op.getResNo() == 0)
3202       Known = KnownBits::mul(Known, Known2, SelfMultiply);
3203     else
3204       Known = KnownBits::mulhu(Known, Known2);
3205     break;
3206   }
3207   case ISD::SMUL_LOHI: {
3208     assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result");
3209     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3210     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3211     bool SelfMultiply = Op.getOperand(0) == Op.getOperand(1);
3212     if (Op.getResNo() == 0)
3213       Known = KnownBits::mul(Known, Known2, SelfMultiply);
3214     else
3215       Known = KnownBits::mulhs(Known, Known2);
3216     break;
3217   }
3218   case ISD::AVGCEILU: {
3219     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3220     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3221     Known = Known.zext(BitWidth + 1);
3222     Known2 = Known2.zext(BitWidth + 1);
3223     KnownBits One = KnownBits::makeConstant(APInt(1, 1));
3224     Known = KnownBits::computeForAddCarry(Known, Known2, One);
3225     Known = Known.extractBits(BitWidth, 1);
3226     break;
3227   }
3228   case ISD::SELECT:
3229   case ISD::VSELECT:
3230     Known = computeKnownBits(Op.getOperand(2), DemandedElts, Depth+1);
3231     // If we don't know any bits, early out.
3232     if (Known.isUnknown())
3233       break;
3234     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth+1);
3235 
3236     // Only known if known in both the LHS and RHS.
3237     Known = KnownBits::commonBits(Known, Known2);
3238     break;
3239   case ISD::SELECT_CC:
3240     Known = computeKnownBits(Op.getOperand(3), DemandedElts, Depth+1);
3241     // If we don't know any bits, early out.
3242     if (Known.isUnknown())
3243       break;
3244     Known2 = computeKnownBits(Op.getOperand(2), DemandedElts, Depth+1);
3245 
3246     // Only known if known in both the LHS and RHS.
3247     Known = KnownBits::commonBits(Known, Known2);
3248     break;
3249   case ISD::SMULO:
3250   case ISD::UMULO:
3251     if (Op.getResNo() != 1)
3252       break;
3253     // The boolean result conforms to getBooleanContents.
3254     // If we know the result of a setcc has the top bits zero, use this info.
3255     // We know that we have an integer-based boolean since these operations
3256     // are only available for integer.
3257     if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
3258             TargetLowering::ZeroOrOneBooleanContent &&
3259         BitWidth > 1)
3260       Known.Zero.setBitsFrom(1);
3261     break;
3262   case ISD::SETCC:
3263   case ISD::SETCCCARRY:
3264   case ISD::STRICT_FSETCC:
3265   case ISD::STRICT_FSETCCS: {
3266     unsigned OpNo = Op->isStrictFPOpcode() ? 1 : 0;
3267     // If we know the result of a setcc has the top bits zero, use this info.
3268     if (TLI->getBooleanContents(Op.getOperand(OpNo).getValueType()) ==
3269             TargetLowering::ZeroOrOneBooleanContent &&
3270         BitWidth > 1)
3271       Known.Zero.setBitsFrom(1);
3272     break;
3273   }
3274   case ISD::SHL:
3275     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3276     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3277     Known = KnownBits::shl(Known, Known2);
3278 
3279     // Minimum shift low bits are known zero.
3280     if (const APInt *ShMinAmt =
3281             getValidMinimumShiftAmountConstant(Op, DemandedElts))
3282       Known.Zero.setLowBits(ShMinAmt->getZExtValue());
3283     break;
3284   case ISD::SRL:
3285     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3286     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3287     Known = KnownBits::lshr(Known, Known2);
3288 
3289     // Minimum shift high bits are known zero.
3290     if (const APInt *ShMinAmt =
3291             getValidMinimumShiftAmountConstant(Op, DemandedElts))
3292       Known.Zero.setHighBits(ShMinAmt->getZExtValue());
3293     break;
3294   case ISD::SRA:
3295     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3296     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3297     Known = KnownBits::ashr(Known, Known2);
3298     // TODO: Add minimum shift high known sign bits.
3299     break;
3300   case ISD::FSHL:
3301   case ISD::FSHR:
3302     if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(2), DemandedElts)) {
3303       unsigned Amt = C->getAPIntValue().urem(BitWidth);
3304 
3305       // For fshl, 0-shift returns the 1st arg.
3306       // For fshr, 0-shift returns the 2nd arg.
3307       if (Amt == 0) {
3308         Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1),
3309                                  DemandedElts, Depth + 1);
3310         break;
3311       }
3312 
3313       // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
3314       // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
3315       Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3316       Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3317       if (Opcode == ISD::FSHL) {
3318         Known.One <<= Amt;
3319         Known.Zero <<= Amt;
3320         Known2.One.lshrInPlace(BitWidth - Amt);
3321         Known2.Zero.lshrInPlace(BitWidth - Amt);
3322       } else {
3323         Known.One <<= BitWidth - Amt;
3324         Known.Zero <<= BitWidth - Amt;
3325         Known2.One.lshrInPlace(Amt);
3326         Known2.Zero.lshrInPlace(Amt);
3327       }
3328       Known.One |= Known2.One;
3329       Known.Zero |= Known2.Zero;
3330     }
3331     break;
3332   case ISD::SHL_PARTS:
3333   case ISD::SRA_PARTS:
3334   case ISD::SRL_PARTS: {
3335     assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result");
3336 
3337     // Collect lo/hi source values and concatenate.
3338     // TODO: Would a KnownBits::concatBits helper be useful?
3339     unsigned LoBits = Op.getOperand(0).getScalarValueSizeInBits();
3340     unsigned HiBits = Op.getOperand(1).getScalarValueSizeInBits();
3341     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3342     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3343     Known = Known.anyext(LoBits + HiBits);
3344     Known.insertBits(Known2, LoBits);
3345 
3346     // Collect shift amount.
3347     Known2 = computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1);
3348 
3349     if (Opcode == ISD::SHL_PARTS)
3350       Known = KnownBits::shl(Known, Known2);
3351     else if (Opcode == ISD::SRA_PARTS)
3352       Known = KnownBits::ashr(Known, Known2);
3353     else // if (Opcode == ISD::SRL_PARTS)
3354       Known = KnownBits::lshr(Known, Known2);
3355 
3356     // TODO: Minimum shift low/high bits are known zero.
3357 
3358     if (Op.getResNo() == 0)
3359       Known = Known.extractBits(LoBits, 0);
3360     else
3361       Known = Known.extractBits(HiBits, LoBits);
3362     break;
3363   }
3364   case ISD::SIGN_EXTEND_INREG: {
3365     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3366     EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
3367     Known = Known.sextInReg(EVT.getScalarSizeInBits());
3368     break;
3369   }
3370   case ISD::CTTZ:
3371   case ISD::CTTZ_ZERO_UNDEF: {
3372     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3373     // If we have a known 1, its position is our upper bound.
3374     unsigned PossibleTZ = Known2.countMaxTrailingZeros();
3375     unsigned LowBits = Log2_32(PossibleTZ) + 1;
3376     Known.Zero.setBitsFrom(LowBits);
3377     break;
3378   }
3379   case ISD::CTLZ:
3380   case ISD::CTLZ_ZERO_UNDEF: {
3381     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3382     // If we have a known 1, its position is our upper bound.
3383     unsigned PossibleLZ = Known2.countMaxLeadingZeros();
3384     unsigned LowBits = Log2_32(PossibleLZ) + 1;
3385     Known.Zero.setBitsFrom(LowBits);
3386     break;
3387   }
3388   case ISD::CTPOP: {
3389     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3390     // If we know some of the bits are zero, they can't be one.
3391     unsigned PossibleOnes = Known2.countMaxPopulation();
3392     Known.Zero.setBitsFrom(Log2_32(PossibleOnes) + 1);
3393     break;
3394   }
3395   case ISD::PARITY: {
3396     // Parity returns 0 everywhere but the LSB.
3397     Known.Zero.setBitsFrom(1);
3398     break;
3399   }
3400   case ISD::LOAD: {
3401     LoadSDNode *LD = cast<LoadSDNode>(Op);
3402     const Constant *Cst = TLI->getTargetConstantFromLoad(LD);
3403     if (ISD::isNON_EXTLoad(LD) && Cst) {
3404       // Determine any common known bits from the loaded constant pool value.
3405       Type *CstTy = Cst->getType();
3406       if ((NumElts * BitWidth) == CstTy->getPrimitiveSizeInBits()) {
3407         // If its a vector splat, then we can (quickly) reuse the scalar path.
3408         // NOTE: We assume all elements match and none are UNDEF.
3409         if (CstTy->isVectorTy()) {
3410           if (const Constant *Splat = Cst->getSplatValue()) {
3411             Cst = Splat;
3412             CstTy = Cst->getType();
3413           }
3414         }
3415         // TODO - do we need to handle different bitwidths?
3416         if (CstTy->isVectorTy() && BitWidth == CstTy->getScalarSizeInBits()) {
3417           // Iterate across all vector elements finding common known bits.
3418           Known.One.setAllBits();
3419           Known.Zero.setAllBits();
3420           for (unsigned i = 0; i != NumElts; ++i) {
3421             if (!DemandedElts[i])
3422               continue;
3423             if (Constant *Elt = Cst->getAggregateElement(i)) {
3424               if (auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3425                 const APInt &Value = CInt->getValue();
3426                 Known.One &= Value;
3427                 Known.Zero &= ~Value;
3428                 continue;
3429               }
3430               if (auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3431                 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3432                 Known.One &= Value;
3433                 Known.Zero &= ~Value;
3434                 continue;
3435               }
3436             }
3437             Known.One.clearAllBits();
3438             Known.Zero.clearAllBits();
3439             break;
3440           }
3441         } else if (BitWidth == CstTy->getPrimitiveSizeInBits()) {
3442           if (auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3443             Known = KnownBits::makeConstant(CInt->getValue());
3444           } else if (auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3445             Known =
3446                 KnownBits::makeConstant(CFP->getValueAPF().bitcastToAPInt());
3447           }
3448         }
3449       }
3450     } else if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) {
3451       // If this is a ZEXTLoad and we are looking at the loaded value.
3452       EVT VT = LD->getMemoryVT();
3453       unsigned MemBits = VT.getScalarSizeInBits();
3454       Known.Zero.setBitsFrom(MemBits);
3455     } else if (const MDNode *Ranges = LD->getRanges()) {
3456       if (LD->getExtensionType() == ISD::NON_EXTLOAD)
3457         computeKnownBitsFromRangeMetadata(*Ranges, Known);
3458     }
3459     break;
3460   }
3461   case ISD::ZERO_EXTEND_VECTOR_INREG: {
3462     EVT InVT = Op.getOperand(0).getValueType();
3463     APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
3464     Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
3465     Known = Known.zext(BitWidth);
3466     break;
3467   }
3468   case ISD::ZERO_EXTEND: {
3469     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3470     Known = Known.zext(BitWidth);
3471     break;
3472   }
3473   case ISD::SIGN_EXTEND_VECTOR_INREG: {
3474     EVT InVT = Op.getOperand(0).getValueType();
3475     APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
3476     Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
3477     // If the sign bit is known to be zero or one, then sext will extend
3478     // it to the top bits, else it will just zext.
3479     Known = Known.sext(BitWidth);
3480     break;
3481   }
3482   case ISD::SIGN_EXTEND: {
3483     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3484     // If the sign bit is known to be zero or one, then sext will extend
3485     // it to the top bits, else it will just zext.
3486     Known = Known.sext(BitWidth);
3487     break;
3488   }
3489   case ISD::ANY_EXTEND_VECTOR_INREG: {
3490     EVT InVT = Op.getOperand(0).getValueType();
3491     APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
3492     Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
3493     Known = Known.anyext(BitWidth);
3494     break;
3495   }
3496   case ISD::ANY_EXTEND: {
3497     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3498     Known = Known.anyext(BitWidth);
3499     break;
3500   }
3501   case ISD::TRUNCATE: {
3502     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3503     Known = Known.trunc(BitWidth);
3504     break;
3505   }
3506   case ISD::AssertZext: {
3507     EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
3508     APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
3509     Known = computeKnownBits(Op.getOperand(0), Depth+1);
3510     Known.Zero |= (~InMask);
3511     Known.One  &= (~Known.Zero);
3512     break;
3513   }
3514   case ISD::AssertAlign: {
3515     unsigned LogOfAlign = Log2(cast<AssertAlignSDNode>(Op)->getAlign());
3516     assert(LogOfAlign != 0);
3517 
3518     // TODO: Should use maximum with source
3519     // If a node is guaranteed to be aligned, set low zero bits accordingly as
3520     // well as clearing one bits.
3521     Known.Zero.setLowBits(LogOfAlign);
3522     Known.One.clearLowBits(LogOfAlign);
3523     break;
3524   }
3525   case ISD::FGETSIGN:
3526     // All bits are zero except the low bit.
3527     Known.Zero.setBitsFrom(1);
3528     break;
3529   case ISD::USUBO:
3530   case ISD::SSUBO:
3531   case ISD::SUBCARRY:
3532   case ISD::SSUBO_CARRY:
3533     if (Op.getResNo() == 1) {
3534       // If we know the result of a setcc has the top bits zero, use this info.
3535       if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
3536               TargetLowering::ZeroOrOneBooleanContent &&
3537           BitWidth > 1)
3538         Known.Zero.setBitsFrom(1);
3539       break;
3540     }
3541     LLVM_FALLTHROUGH;
3542   case ISD::SUB:
3543   case ISD::SUBC: {
3544     assert(Op.getResNo() == 0 &&
3545            "We only compute knownbits for the difference here.");
3546 
3547     // TODO: Compute influence of the carry operand.
3548     if (Opcode == ISD::SUBCARRY || Opcode == ISD::SSUBO_CARRY)
3549       break;
3550 
3551     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3552     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3553     Known = KnownBits::computeForAddSub(/* Add */ false, /* NSW */ false,
3554                                         Known, Known2);
3555     break;
3556   }
3557   case ISD::UADDO:
3558   case ISD::SADDO:
3559   case ISD::ADDCARRY:
3560   case ISD::SADDO_CARRY:
3561     if (Op.getResNo() == 1) {
3562       // If we know the result of a setcc has the top bits zero, use this info.
3563       if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
3564               TargetLowering::ZeroOrOneBooleanContent &&
3565           BitWidth > 1)
3566         Known.Zero.setBitsFrom(1);
3567       break;
3568     }
3569     LLVM_FALLTHROUGH;
3570   case ISD::ADD:
3571   case ISD::ADDC:
3572   case ISD::ADDE: {
3573     assert(Op.getResNo() == 0 && "We only compute knownbits for the sum here.");
3574 
3575     // With ADDE and ADDCARRY, a carry bit may be added in.
3576     KnownBits Carry(1);
3577     if (Opcode == ISD::ADDE)
3578       // Can't track carry from glue, set carry to unknown.
3579       Carry.resetAll();
3580     else if (Opcode == ISD::ADDCARRY || Opcode == ISD::SADDO_CARRY)
3581       // TODO: Compute known bits for the carry operand. Not sure if it is worth
3582       // the trouble (how often will we find a known carry bit). And I haven't
3583       // tested this very much yet, but something like this might work:
3584       //   Carry = computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1);
3585       //   Carry = Carry.zextOrTrunc(1, false);
3586       Carry.resetAll();
3587     else
3588       Carry.setAllZero();
3589 
3590     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3591     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3592     Known = KnownBits::computeForAddCarry(Known, Known2, Carry);
3593     break;
3594   }
3595   case ISD::UDIV: {
3596     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3597     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3598     Known = KnownBits::udiv(Known, Known2);
3599     break;
3600   }
3601   case ISD::SREM: {
3602     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3603     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3604     Known = KnownBits::srem(Known, Known2);
3605     break;
3606   }
3607   case ISD::UREM: {
3608     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3609     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3610     Known = KnownBits::urem(Known, Known2);
3611     break;
3612   }
3613   case ISD::EXTRACT_ELEMENT: {
3614     Known = computeKnownBits(Op.getOperand(0), Depth+1);
3615     const unsigned Index = Op.getConstantOperandVal(1);
3616     const unsigned EltBitWidth = Op.getValueSizeInBits();
3617 
3618     // Remove low part of known bits mask
3619     Known.Zero = Known.Zero.getHiBits(Known.getBitWidth() - Index * EltBitWidth);
3620     Known.One = Known.One.getHiBits(Known.getBitWidth() - Index * EltBitWidth);
3621 
3622     // Remove high part of known bit mask
3623     Known = Known.trunc(EltBitWidth);
3624     break;
3625   }
3626   case ISD::EXTRACT_VECTOR_ELT: {
3627     SDValue InVec = Op.getOperand(0);
3628     SDValue EltNo = Op.getOperand(1);
3629     EVT VecVT = InVec.getValueType();
3630     // computeKnownBits not yet implemented for scalable vectors.
3631     if (VecVT.isScalableVector())
3632       break;
3633     const unsigned EltBitWidth = VecVT.getScalarSizeInBits();
3634     const unsigned NumSrcElts = VecVT.getVectorNumElements();
3635 
3636     // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
3637     // anything about the extended bits.
3638     if (BitWidth > EltBitWidth)
3639       Known = Known.trunc(EltBitWidth);
3640 
3641     // If we know the element index, just demand that vector element, else for
3642     // an unknown element index, ignore DemandedElts and demand them all.
3643     APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts);
3644     auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
3645     if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
3646       DemandedSrcElts =
3647           APInt::getOneBitSet(NumSrcElts, ConstEltNo->getZExtValue());
3648 
3649     Known = computeKnownBits(InVec, DemandedSrcElts, Depth + 1);
3650     if (BitWidth > EltBitWidth)
3651       Known = Known.anyext(BitWidth);
3652     break;
3653   }
3654   case ISD::INSERT_VECTOR_ELT: {
3655     // If we know the element index, split the demand between the
3656     // source vector and the inserted element, otherwise assume we need
3657     // the original demanded vector elements and the value.
3658     SDValue InVec = Op.getOperand(0);
3659     SDValue InVal = Op.getOperand(1);
3660     SDValue EltNo = Op.getOperand(2);
3661     bool DemandedVal = true;
3662     APInt DemandedVecElts = DemandedElts;
3663     auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
3664     if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
3665       unsigned EltIdx = CEltNo->getZExtValue();
3666       DemandedVal = !!DemandedElts[EltIdx];
3667       DemandedVecElts.clearBit(EltIdx);
3668     }
3669     Known.One.setAllBits();
3670     Known.Zero.setAllBits();
3671     if (DemandedVal) {
3672       Known2 = computeKnownBits(InVal, Depth + 1);
3673       Known = KnownBits::commonBits(Known, Known2.zextOrTrunc(BitWidth));
3674     }
3675     if (!!DemandedVecElts) {
3676       Known2 = computeKnownBits(InVec, DemandedVecElts, Depth + 1);
3677       Known = KnownBits::commonBits(Known, Known2);
3678     }
3679     break;
3680   }
3681   case ISD::BITREVERSE: {
3682     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3683     Known = Known2.reverseBits();
3684     break;
3685   }
3686   case ISD::BSWAP: {
3687     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3688     Known = Known2.byteSwap();
3689     break;
3690   }
3691   case ISD::ABS: {
3692     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3693     Known = Known2.abs();
3694     break;
3695   }
3696   case ISD::USUBSAT: {
3697     // The result of usubsat will never be larger than the LHS.
3698     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3699     Known.Zero.setHighBits(Known2.countMinLeadingZeros());
3700     break;
3701   }
3702   case ISD::UMIN: {
3703     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3704     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3705     Known = KnownBits::umin(Known, Known2);
3706     break;
3707   }
3708   case ISD::UMAX: {
3709     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3710     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3711     Known = KnownBits::umax(Known, Known2);
3712     break;
3713   }
3714   case ISD::SMIN:
3715   case ISD::SMAX: {
3716     // If we have a clamp pattern, we know that the number of sign bits will be
3717     // the minimum of the clamp min/max range.
3718     bool IsMax = (Opcode == ISD::SMAX);
3719     ConstantSDNode *CstLow = nullptr, *CstHigh = nullptr;
3720     if ((CstLow = isConstOrConstSplat(Op.getOperand(1), DemandedElts)))
3721       if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3722         CstHigh =
3723             isConstOrConstSplat(Op.getOperand(0).getOperand(1), DemandedElts);
3724     if (CstLow && CstHigh) {
3725       if (!IsMax)
3726         std::swap(CstLow, CstHigh);
3727 
3728       const APInt &ValueLow = CstLow->getAPIntValue();
3729       const APInt &ValueHigh = CstHigh->getAPIntValue();
3730       if (ValueLow.sle(ValueHigh)) {
3731         unsigned LowSignBits = ValueLow.getNumSignBits();
3732         unsigned HighSignBits = ValueHigh.getNumSignBits();
3733         unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
3734         if (ValueLow.isNegative() && ValueHigh.isNegative()) {
3735           Known.One.setHighBits(MinSignBits);
3736           break;
3737         }
3738         if (ValueLow.isNonNegative() && ValueHigh.isNonNegative()) {
3739           Known.Zero.setHighBits(MinSignBits);
3740           break;
3741         }
3742       }
3743     }
3744 
3745     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3746     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3747     if (IsMax)
3748       Known = KnownBits::smax(Known, Known2);
3749     else
3750       Known = KnownBits::smin(Known, Known2);
3751 
3752     // For SMAX, if CstLow is non-negative we know the result will be
3753     // non-negative and thus all sign bits are 0.
3754     // TODO: There's an equivalent of this for smin with negative constant for
3755     // known ones.
3756     if (IsMax && CstLow) {
3757       const APInt &ValueLow = CstLow->getAPIntValue();
3758       if (ValueLow.isNonNegative()) {
3759         unsigned SignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
3760         Known.Zero.setHighBits(std::min(SignBits, ValueLow.getNumSignBits()));
3761       }
3762     }
3763 
3764     break;
3765   }
3766   case ISD::FP_TO_UINT_SAT: {
3767     // FP_TO_UINT_SAT produces an unsigned value that fits in the saturating VT.
3768     EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
3769     Known.Zero |= APInt::getBitsSetFrom(BitWidth, VT.getScalarSizeInBits());
3770     break;
3771   }
3772   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
3773     if (Op.getResNo() == 1) {
3774       // The boolean result conforms to getBooleanContents.
3775       // If we know the result of a setcc has the top bits zero, use this info.
3776       // We know that we have an integer-based boolean since these operations
3777       // are only available for integer.
3778       if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
3779               TargetLowering::ZeroOrOneBooleanContent &&
3780           BitWidth > 1)
3781         Known.Zero.setBitsFrom(1);
3782       break;
3783     }
3784     LLVM_FALLTHROUGH;
3785   case ISD::ATOMIC_CMP_SWAP:
3786   case ISD::ATOMIC_SWAP:
3787   case ISD::ATOMIC_LOAD_ADD:
3788   case ISD::ATOMIC_LOAD_SUB:
3789   case ISD::ATOMIC_LOAD_AND:
3790   case ISD::ATOMIC_LOAD_CLR:
3791   case ISD::ATOMIC_LOAD_OR:
3792   case ISD::ATOMIC_LOAD_XOR:
3793   case ISD::ATOMIC_LOAD_NAND:
3794   case ISD::ATOMIC_LOAD_MIN:
3795   case ISD::ATOMIC_LOAD_MAX:
3796   case ISD::ATOMIC_LOAD_UMIN:
3797   case ISD::ATOMIC_LOAD_UMAX:
3798   case ISD::ATOMIC_LOAD: {
3799     unsigned MemBits =
3800         cast<AtomicSDNode>(Op)->getMemoryVT().getScalarSizeInBits();
3801     // If we are looking at the loaded value.
3802     if (Op.getResNo() == 0) {
3803       if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
3804         Known.Zero.setBitsFrom(MemBits);
3805     }
3806     break;
3807   }
3808   case ISD::FrameIndex:
3809   case ISD::TargetFrameIndex:
3810     TLI->computeKnownBitsForFrameIndex(cast<FrameIndexSDNode>(Op)->getIndex(),
3811                                        Known, getMachineFunction());
3812     break;
3813 
3814   default:
3815     if (Opcode < ISD::BUILTIN_OP_END)
3816       break;
3817     LLVM_FALLTHROUGH;
3818   case ISD::INTRINSIC_WO_CHAIN:
3819   case ISD::INTRINSIC_W_CHAIN:
3820   case ISD::INTRINSIC_VOID:
3821     // Allow the target to implement this method for its nodes.
3822     TLI->computeKnownBitsForTargetNode(Op, Known, DemandedElts, *this, Depth);
3823     break;
3824   }
3825 
3826   assert(!Known.hasConflict() && "Bits known to be one AND zero?");
3827   return Known;
3828 }
3829 
3830 SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind(SDValue N0,
3831                                                              SDValue N1) const {
3832   // X + 0 never overflow
3833   if (isNullConstant(N1))
3834     return OFK_Never;
3835 
3836   KnownBits N1Known = computeKnownBits(N1);
3837   if (N1Known.Zero.getBoolValue()) {
3838     KnownBits N0Known = computeKnownBits(N0);
3839 
3840     bool overflow;
3841     (void)N0Known.getMaxValue().uadd_ov(N1Known.getMaxValue(), overflow);
3842     if (!overflow)
3843       return OFK_Never;
3844   }
3845 
3846   // mulhi + 1 never overflow
3847   if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 &&
3848       (N1Known.getMaxValue() & 0x01) == N1Known.getMaxValue())
3849     return OFK_Never;
3850 
3851   if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) {
3852     KnownBits N0Known = computeKnownBits(N0);
3853 
3854     if ((N0Known.getMaxValue() & 0x01) == N0Known.getMaxValue())
3855       return OFK_Never;
3856   }
3857 
3858   return OFK_Sometime;
3859 }
3860 
3861 bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
3862   EVT OpVT = Val.getValueType();
3863   unsigned BitWidth = OpVT.getScalarSizeInBits();
3864 
3865   // Is the constant a known power of 2?
3866   if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val))
3867     return Const->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
3868 
3869   // A left-shift of a constant one will have exactly one bit set because
3870   // shifting the bit off the end is undefined.
3871   if (Val.getOpcode() == ISD::SHL) {
3872     auto *C = isConstOrConstSplat(Val.getOperand(0));
3873     if (C && C->getAPIntValue() == 1)
3874       return true;
3875   }
3876 
3877   // Similarly, a logical right-shift of a constant sign-bit will have exactly
3878   // one bit set.
3879   if (Val.getOpcode() == ISD::SRL) {
3880     auto *C = isConstOrConstSplat(Val.getOperand(0));
3881     if (C && C->getAPIntValue().isSignMask())
3882       return true;
3883   }
3884 
3885   // Are all operands of a build vector constant powers of two?
3886   if (Val.getOpcode() == ISD::BUILD_VECTOR)
3887     if (llvm::all_of(Val->ops(), [BitWidth](SDValue E) {
3888           if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
3889             return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
3890           return false;
3891         }))
3892       return true;
3893 
3894   // Is the operand of a splat vector a constant power of two?
3895   if (Val.getOpcode() == ISD::SPLAT_VECTOR)
3896     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val->getOperand(0)))
3897       if (C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2())
3898         return true;
3899 
3900   // vscale(power-of-two) is a power-of-two for some targets
3901   if (Val.getOpcode() == ISD::VSCALE &&
3902       getTargetLoweringInfo().isVScaleKnownToBeAPowerOfTwo() &&
3903       isKnownToBeAPowerOfTwo(Val.getOperand(0)))
3904     return true;
3905 
3906   // More could be done here, though the above checks are enough
3907   // to handle some common cases.
3908 
3909   // Fall back to computeKnownBits to catch other known cases.
3910   KnownBits Known = computeKnownBits(Val);
3911   return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
3912 }
3913 
3914 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
3915   EVT VT = Op.getValueType();
3916 
3917   // TODO: Assume we don't know anything for now.
3918   if (VT.isScalableVector())
3919     return 1;
3920 
3921   APInt DemandedElts = VT.isVector()
3922                            ? APInt::getAllOnes(VT.getVectorNumElements())
3923                            : APInt(1, 1);
3924   return ComputeNumSignBits(Op, DemandedElts, Depth);
3925 }
3926 
3927 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
3928                                           unsigned Depth) const {
3929   EVT VT = Op.getValueType();
3930   assert((VT.isInteger() || VT.isFloatingPoint()) && "Invalid VT!");
3931   unsigned VTBits = VT.getScalarSizeInBits();
3932   unsigned NumElts = DemandedElts.getBitWidth();
3933   unsigned Tmp, Tmp2;
3934   unsigned FirstAnswer = 1;
3935 
3936   if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
3937     const APInt &Val = C->getAPIntValue();
3938     return Val.getNumSignBits();
3939   }
3940 
3941   if (Depth >= MaxRecursionDepth)
3942     return 1;  // Limit search depth.
3943 
3944   if (!DemandedElts || VT.isScalableVector())
3945     return 1;  // No demanded elts, better to assume we don't know anything.
3946 
3947   unsigned Opcode = Op.getOpcode();
3948   switch (Opcode) {
3949   default: break;
3950   case ISD::AssertSext:
3951     Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
3952     return VTBits-Tmp+1;
3953   case ISD::AssertZext:
3954     Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
3955     return VTBits-Tmp;
3956   case ISD::MERGE_VALUES:
3957     return ComputeNumSignBits(Op.getOperand(Op.getResNo()), DemandedElts,
3958                               Depth + 1);
3959   case ISD::BUILD_VECTOR:
3960     Tmp = VTBits;
3961     for (unsigned i = 0, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
3962       if (!DemandedElts[i])
3963         continue;
3964 
3965       SDValue SrcOp = Op.getOperand(i);
3966       Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1);
3967 
3968       // BUILD_VECTOR can implicitly truncate sources, we must handle this.
3969       if (SrcOp.getValueSizeInBits() != VTBits) {
3970         assert(SrcOp.getValueSizeInBits() > VTBits &&
3971                "Expected BUILD_VECTOR implicit truncation");
3972         unsigned ExtraBits = SrcOp.getValueSizeInBits() - VTBits;
3973         Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
3974       }
3975       Tmp = std::min(Tmp, Tmp2);
3976     }
3977     return Tmp;
3978 
3979   case ISD::VECTOR_SHUFFLE: {
3980     // Collect the minimum number of sign bits that are shared by every vector
3981     // element referenced by the shuffle.
3982     APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0);
3983     const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
3984     assert(NumElts == SVN->getMask().size() && "Unexpected vector size");
3985     for (unsigned i = 0; i != NumElts; ++i) {
3986       int M = SVN->getMaskElt(i);
3987       if (!DemandedElts[i])
3988         continue;
3989       // For UNDEF elements, we don't know anything about the common state of
3990       // the shuffle result.
3991       if (M < 0)
3992         return 1;
3993       if ((unsigned)M < NumElts)
3994         DemandedLHS.setBit((unsigned)M % NumElts);
3995       else
3996         DemandedRHS.setBit((unsigned)M % NumElts);
3997     }
3998     Tmp = std::numeric_limits<unsigned>::max();
3999     if (!!DemandedLHS)
4000       Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedLHS, Depth + 1);
4001     if (!!DemandedRHS) {
4002       Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1);
4003       Tmp = std::min(Tmp, Tmp2);
4004     }
4005     // If we don't know anything, early out and try computeKnownBits fall-back.
4006     if (Tmp == 1)
4007       break;
4008     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
4009     return Tmp;
4010   }
4011 
4012   case ISD::BITCAST: {
4013     SDValue N0 = Op.getOperand(0);
4014     EVT SrcVT = N0.getValueType();
4015     unsigned SrcBits = SrcVT.getScalarSizeInBits();
4016 
4017     // Ignore bitcasts from unsupported types..
4018     if (!(SrcVT.isInteger() || SrcVT.isFloatingPoint()))
4019       break;
4020 
4021     // Fast handling of 'identity' bitcasts.
4022     if (VTBits == SrcBits)
4023       return ComputeNumSignBits(N0, DemandedElts, Depth + 1);
4024 
4025     bool IsLE = getDataLayout().isLittleEndian();
4026 
4027     // Bitcast 'large element' scalar/vector to 'small element' vector.
4028     if ((SrcBits % VTBits) == 0) {
4029       assert(VT.isVector() && "Expected bitcast to vector");
4030 
4031       unsigned Scale = SrcBits / VTBits;
4032       APInt SrcDemandedElts =
4033           APIntOps::ScaleBitMask(DemandedElts, NumElts / Scale);
4034 
4035       // Fast case - sign splat can be simply split across the small elements.
4036       Tmp = ComputeNumSignBits(N0, SrcDemandedElts, Depth + 1);
4037       if (Tmp == SrcBits)
4038         return VTBits;
4039 
4040       // Slow case - determine how far the sign extends into each sub-element.
4041       Tmp2 = VTBits;
4042       for (unsigned i = 0; i != NumElts; ++i)
4043         if (DemandedElts[i]) {
4044           unsigned SubOffset = i % Scale;
4045           SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4046           SubOffset = SubOffset * VTBits;
4047           if (Tmp <= SubOffset)
4048             return 1;
4049           Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4050         }
4051       return Tmp2;
4052     }
4053     break;
4054   }
4055 
4056   case ISD::FP_TO_SINT_SAT:
4057     // FP_TO_SINT_SAT produces a signed value that fits in the saturating VT.
4058     Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits();
4059     return VTBits - Tmp + 1;
4060   case ISD::SIGN_EXTEND:
4061     Tmp = VTBits - Op.getOperand(0).getScalarValueSizeInBits();
4062     return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1) + Tmp;
4063   case ISD::SIGN_EXTEND_INREG:
4064     // Max of the input and what this extends.
4065     Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits();
4066     Tmp = VTBits-Tmp+1;
4067     Tmp2 = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1);
4068     return std::max(Tmp, Tmp2);
4069   case ISD::SIGN_EXTEND_VECTOR_INREG: {
4070     SDValue Src = Op.getOperand(0);
4071     EVT SrcVT = Src.getValueType();
4072     APInt DemandedSrcElts = DemandedElts.zext(SrcVT.getVectorNumElements());
4073     Tmp = VTBits - SrcVT.getScalarSizeInBits();
4074     return ComputeNumSignBits(Src, DemandedSrcElts, Depth+1) + Tmp;
4075   }
4076   case ISD::SRA:
4077     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4078     // SRA X, C -> adds C sign bits.
4079     if (const APInt *ShAmt =
4080             getValidMinimumShiftAmountConstant(Op, DemandedElts))
4081       Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
4082     return Tmp;
4083   case ISD::SHL:
4084     if (const APInt *ShAmt =
4085             getValidMaximumShiftAmountConstant(Op, DemandedElts)) {
4086       // shl destroys sign bits, ensure it doesn't shift out all sign bits.
4087       Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4088       if (ShAmt->ult(Tmp))
4089         return Tmp - ShAmt->getZExtValue();
4090     }
4091     break;
4092   case ISD::AND:
4093   case ISD::OR:
4094   case ISD::XOR:    // NOT is handled here.
4095     // Logical binary ops preserve the number of sign bits at the worst.
4096     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1);
4097     if (Tmp != 1) {
4098       Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth+1);
4099       FirstAnswer = std::min(Tmp, Tmp2);
4100       // We computed what we know about the sign bits as our first
4101       // answer. Now proceed to the generic code that uses
4102       // computeKnownBits, and pick whichever answer is better.
4103     }
4104     break;
4105 
4106   case ISD::SELECT:
4107   case ISD::VSELECT:
4108     Tmp = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth+1);
4109     if (Tmp == 1) return 1;  // Early out.
4110     Tmp2 = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth+1);
4111     return std::min(Tmp, Tmp2);
4112   case ISD::SELECT_CC:
4113     Tmp = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth+1);
4114     if (Tmp == 1) return 1;  // Early out.
4115     Tmp2 = ComputeNumSignBits(Op.getOperand(3), DemandedElts, Depth+1);
4116     return std::min(Tmp, Tmp2);
4117 
4118   case ISD::SMIN:
4119   case ISD::SMAX: {
4120     // If we have a clamp pattern, we know that the number of sign bits will be
4121     // the minimum of the clamp min/max range.
4122     bool IsMax = (Opcode == ISD::SMAX);
4123     ConstantSDNode *CstLow = nullptr, *CstHigh = nullptr;
4124     if ((CstLow = isConstOrConstSplat(Op.getOperand(1), DemandedElts)))
4125       if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
4126         CstHigh =
4127             isConstOrConstSplat(Op.getOperand(0).getOperand(1), DemandedElts);
4128     if (CstLow && CstHigh) {
4129       if (!IsMax)
4130         std::swap(CstLow, CstHigh);
4131       if (CstLow->getAPIntValue().sle(CstHigh->getAPIntValue())) {
4132         Tmp = CstLow->getAPIntValue().getNumSignBits();
4133         Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4134         return std::min(Tmp, Tmp2);
4135       }
4136     }
4137 
4138     // Fallback - just get the minimum number of sign bits of the operands.
4139     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4140     if (Tmp == 1)
4141       return 1;  // Early out.
4142     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
4143     return std::min(Tmp, Tmp2);
4144   }
4145   case ISD::UMIN:
4146   case ISD::UMAX:
4147     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4148     if (Tmp == 1)
4149       return 1;  // Early out.
4150     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
4151     return std::min(Tmp, Tmp2);
4152   case ISD::SADDO:
4153   case ISD::UADDO:
4154   case ISD::SADDO_CARRY:
4155   case ISD::ADDCARRY:
4156   case ISD::SSUBO:
4157   case ISD::USUBO:
4158   case ISD::SSUBO_CARRY:
4159   case ISD::SUBCARRY:
4160   case ISD::SMULO:
4161   case ISD::UMULO:
4162     if (Op.getResNo() != 1)
4163       break;
4164     // The boolean result conforms to getBooleanContents.  Fall through.
4165     // If setcc returns 0/-1, all bits are sign bits.
4166     // We know that we have an integer-based boolean since these operations
4167     // are only available for integer.
4168     if (TLI->getBooleanContents(VT.isVector(), false) ==
4169         TargetLowering::ZeroOrNegativeOneBooleanContent)
4170       return VTBits;
4171     break;
4172   case ISD::SETCC:
4173   case ISD::SETCCCARRY:
4174   case ISD::STRICT_FSETCC:
4175   case ISD::STRICT_FSETCCS: {
4176     unsigned OpNo = Op->isStrictFPOpcode() ? 1 : 0;
4177     // If setcc returns 0/-1, all bits are sign bits.
4178     if (TLI->getBooleanContents(Op.getOperand(OpNo).getValueType()) ==
4179         TargetLowering::ZeroOrNegativeOneBooleanContent)
4180       return VTBits;
4181     break;
4182   }
4183   case ISD::ROTL:
4184   case ISD::ROTR:
4185     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4186 
4187     // If we're rotating an 0/-1 value, then it stays an 0/-1 value.
4188     if (Tmp == VTBits)
4189       return VTBits;
4190 
4191     if (ConstantSDNode *C =
4192             isConstOrConstSplat(Op.getOperand(1), DemandedElts)) {
4193       unsigned RotAmt = C->getAPIntValue().urem(VTBits);
4194 
4195       // Handle rotate right by N like a rotate left by 32-N.
4196       if (Opcode == ISD::ROTR)
4197         RotAmt = (VTBits - RotAmt) % VTBits;
4198 
4199       // If we aren't rotating out all of the known-in sign bits, return the
4200       // number that are left.  This handles rotl(sext(x), 1) for example.
4201       if (Tmp > (RotAmt + 1)) return (Tmp - RotAmt);
4202     }
4203     break;
4204   case ISD::ADD:
4205   case ISD::ADDC:
4206     // Add can have at most one carry bit.  Thus we know that the output
4207     // is, at worst, one more bit than the inputs.
4208     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4209     if (Tmp == 1) return 1; // Early out.
4210 
4211     // Special case decrementing a value (ADD X, -1):
4212     if (ConstantSDNode *CRHS =
4213             isConstOrConstSplat(Op.getOperand(1), DemandedElts))
4214       if (CRHS->isAllOnes()) {
4215         KnownBits Known =
4216             computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
4217 
4218         // If the input is known to be 0 or 1, the output is 0/-1, which is all
4219         // sign bits set.
4220         if ((Known.Zero | 1).isAllOnes())
4221           return VTBits;
4222 
4223         // If we are subtracting one from a positive number, there is no carry
4224         // out of the result.
4225         if (Known.isNonNegative())
4226           return Tmp;
4227       }
4228 
4229     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
4230     if (Tmp2 == 1) return 1; // Early out.
4231     return std::min(Tmp, Tmp2) - 1;
4232   case ISD::SUB:
4233     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
4234     if (Tmp2 == 1) return 1; // Early out.
4235 
4236     // Handle NEG.
4237     if (ConstantSDNode *CLHS =
4238             isConstOrConstSplat(Op.getOperand(0), DemandedElts))
4239       if (CLHS->isZero()) {
4240         KnownBits Known =
4241             computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
4242         // If the input is known to be 0 or 1, the output is 0/-1, which is all
4243         // sign bits set.
4244         if ((Known.Zero | 1).isAllOnes())
4245           return VTBits;
4246 
4247         // If the input is known to be positive (the sign bit is known clear),
4248         // the output of the NEG has the same number of sign bits as the input.
4249         if (Known.isNonNegative())
4250           return Tmp2;
4251 
4252         // Otherwise, we treat this like a SUB.
4253       }
4254 
4255     // Sub can have at most one carry bit.  Thus we know that the output
4256     // is, at worst, one more bit than the inputs.
4257     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4258     if (Tmp == 1) return 1; // Early out.
4259     return std::min(Tmp, Tmp2) - 1;
4260   case ISD::MUL: {
4261     // The output of the Mul can be at most twice the valid bits in the inputs.
4262     unsigned SignBitsOp0 = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4263     if (SignBitsOp0 == 1)
4264       break;
4265     unsigned SignBitsOp1 = ComputeNumSignBits(Op.getOperand(1), Depth + 1);
4266     if (SignBitsOp1 == 1)
4267       break;
4268     unsigned OutValidBits =
4269         (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4270     return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4271   }
4272   case ISD::SREM:
4273     // The sign bit is the LHS's sign bit, except when the result of the
4274     // remainder is zero. The magnitude of the result should be less than or
4275     // equal to the magnitude of the LHS. Therefore, the result should have
4276     // at least as many sign bits as the left hand side.
4277     return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
4278   case ISD::TRUNCATE: {
4279     // Check if the sign bits of source go down as far as the truncated value.
4280     unsigned NumSrcBits = Op.getOperand(0).getScalarValueSizeInBits();
4281     unsigned NumSrcSignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4282     if (NumSrcSignBits > (NumSrcBits - VTBits))
4283       return NumSrcSignBits - (NumSrcBits - VTBits);
4284     break;
4285   }
4286   case ISD::EXTRACT_ELEMENT: {
4287     const int KnownSign = ComputeNumSignBits(Op.getOperand(0), Depth+1);
4288     const int BitWidth = Op.getValueSizeInBits();
4289     const int Items = Op.getOperand(0).getValueSizeInBits() / BitWidth;
4290 
4291     // Get reverse index (starting from 1), Op1 value indexes elements from
4292     // little end. Sign starts at big end.
4293     const int rIndex = Items - 1 - Op.getConstantOperandVal(1);
4294 
4295     // If the sign portion ends in our element the subtraction gives correct
4296     // result. Otherwise it gives either negative or > bitwidth result
4297     return std::max(std::min(KnownSign - rIndex * BitWidth, BitWidth), 0);
4298   }
4299   case ISD::INSERT_VECTOR_ELT: {
4300     // If we know the element index, split the demand between the
4301     // source vector and the inserted element, otherwise assume we need
4302     // the original demanded vector elements and the value.
4303     SDValue InVec = Op.getOperand(0);
4304     SDValue InVal = Op.getOperand(1);
4305     SDValue EltNo = Op.getOperand(2);
4306     bool DemandedVal = true;
4307     APInt DemandedVecElts = DemandedElts;
4308     auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4309     if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4310       unsigned EltIdx = CEltNo->getZExtValue();
4311       DemandedVal = !!DemandedElts[EltIdx];
4312       DemandedVecElts.clearBit(EltIdx);
4313     }
4314     Tmp = std::numeric_limits<unsigned>::max();
4315     if (DemandedVal) {
4316       // TODO - handle implicit truncation of inserted elements.
4317       if (InVal.getScalarValueSizeInBits() != VTBits)
4318         break;
4319       Tmp2 = ComputeNumSignBits(InVal, Depth + 1);
4320       Tmp = std::min(Tmp, Tmp2);
4321     }
4322     if (!!DemandedVecElts) {
4323       Tmp2 = ComputeNumSignBits(InVec, DemandedVecElts, Depth + 1);
4324       Tmp = std::min(Tmp, Tmp2);
4325     }
4326     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
4327     return Tmp;
4328   }
4329   case ISD::EXTRACT_VECTOR_ELT: {
4330     SDValue InVec = Op.getOperand(0);
4331     SDValue EltNo = Op.getOperand(1);
4332     EVT VecVT = InVec.getValueType();
4333     // ComputeNumSignBits not yet implemented for scalable vectors.
4334     if (VecVT.isScalableVector())
4335       break;
4336     const unsigned BitWidth = Op.getValueSizeInBits();
4337     const unsigned EltBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
4338     const unsigned NumSrcElts = VecVT.getVectorNumElements();
4339 
4340     // If BitWidth > EltBitWidth the value is anyext:ed, and we do not know
4341     // anything about sign bits. But if the sizes match we can derive knowledge
4342     // about sign bits from the vector operand.
4343     if (BitWidth != EltBitWidth)
4344       break;
4345 
4346     // If we know the element index, just demand that vector element, else for
4347     // an unknown element index, ignore DemandedElts and demand them all.
4348     APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts);
4349     auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4350     if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4351       DemandedSrcElts =
4352           APInt::getOneBitSet(NumSrcElts, ConstEltNo->getZExtValue());
4353 
4354     return ComputeNumSignBits(InVec, DemandedSrcElts, Depth + 1);
4355   }
4356   case ISD::EXTRACT_SUBVECTOR: {
4357     // Offset the demanded elts by the subvector index.
4358     SDValue Src = Op.getOperand(0);
4359     // Bail until we can represent demanded elements for scalable vectors.
4360     if (Src.getValueType().isScalableVector())
4361       break;
4362     uint64_t Idx = Op.getConstantOperandVal(1);
4363     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4364     APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
4365     return ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
4366   }
4367   case ISD::CONCAT_VECTORS: {
4368     // Determine the minimum number of sign bits across all demanded
4369     // elts of the input vectors. Early out if the result is already 1.
4370     Tmp = std::numeric_limits<unsigned>::max();
4371     EVT SubVectorVT = Op.getOperand(0).getValueType();
4372     unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
4373     unsigned NumSubVectors = Op.getNumOperands();
4374     for (unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4375       APInt DemandedSub =
4376           DemandedElts.extractBits(NumSubVectorElts, i * NumSubVectorElts);
4377       if (!DemandedSub)
4378         continue;
4379       Tmp2 = ComputeNumSignBits(Op.getOperand(i), DemandedSub, Depth + 1);
4380       Tmp = std::min(Tmp, Tmp2);
4381     }
4382     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
4383     return Tmp;
4384   }
4385   case ISD::INSERT_SUBVECTOR: {
4386     // Demand any elements from the subvector and the remainder from the src its
4387     // inserted into.
4388     SDValue Src = Op.getOperand(0);
4389     SDValue Sub = Op.getOperand(1);
4390     uint64_t Idx = Op.getConstantOperandVal(2);
4391     unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
4392     APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
4393     APInt DemandedSrcElts = DemandedElts;
4394     DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx);
4395 
4396     Tmp = std::numeric_limits<unsigned>::max();
4397     if (!!DemandedSubElts) {
4398       Tmp = ComputeNumSignBits(Sub, DemandedSubElts, Depth + 1);
4399       if (Tmp == 1)
4400         return 1; // early-out
4401     }
4402     if (!!DemandedSrcElts) {
4403       Tmp2 = ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
4404       Tmp = std::min(Tmp, Tmp2);
4405     }
4406     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
4407     return Tmp;
4408   }
4409   case ISD::ATOMIC_CMP_SWAP:
4410   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
4411   case ISD::ATOMIC_SWAP:
4412   case ISD::ATOMIC_LOAD_ADD:
4413   case ISD::ATOMIC_LOAD_SUB:
4414   case ISD::ATOMIC_LOAD_AND:
4415   case ISD::ATOMIC_LOAD_CLR:
4416   case ISD::ATOMIC_LOAD_OR:
4417   case ISD::ATOMIC_LOAD_XOR:
4418   case ISD::ATOMIC_LOAD_NAND:
4419   case ISD::ATOMIC_LOAD_MIN:
4420   case ISD::ATOMIC_LOAD_MAX:
4421   case ISD::ATOMIC_LOAD_UMIN:
4422   case ISD::ATOMIC_LOAD_UMAX:
4423   case ISD::ATOMIC_LOAD: {
4424     Tmp = cast<AtomicSDNode>(Op)->getMemoryVT().getScalarSizeInBits();
4425     // If we are looking at the loaded value.
4426     if (Op.getResNo() == 0) {
4427       if (Tmp == VTBits)
4428         return 1; // early-out
4429       if (TLI->getExtendForAtomicOps() == ISD::SIGN_EXTEND)
4430         return VTBits - Tmp + 1;
4431       if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
4432         return VTBits - Tmp;
4433     }
4434     break;
4435   }
4436   }
4437 
4438   // If we are looking at the loaded value of the SDNode.
4439   if (Op.getResNo() == 0) {
4440     // Handle LOADX separately here. EXTLOAD case will fallthrough.
4441     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
4442       unsigned ExtType = LD->getExtensionType();
4443       switch (ExtType) {
4444       default: break;
4445       case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known.
4446         Tmp = LD->getMemoryVT().getScalarSizeInBits();
4447         return VTBits - Tmp + 1;
4448       case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known.
4449         Tmp = LD->getMemoryVT().getScalarSizeInBits();
4450         return VTBits - Tmp;
4451       case ISD::NON_EXTLOAD:
4452         if (const Constant *Cst = TLI->getTargetConstantFromLoad(LD)) {
4453           // We only need to handle vectors - computeKnownBits should handle
4454           // scalar cases.
4455           Type *CstTy = Cst->getType();
4456           if (CstTy->isVectorTy() &&
4457               (NumElts * VTBits) == CstTy->getPrimitiveSizeInBits() &&
4458               VTBits == CstTy->getScalarSizeInBits()) {
4459             Tmp = VTBits;
4460             for (unsigned i = 0; i != NumElts; ++i) {
4461               if (!DemandedElts[i])
4462                 continue;
4463               if (Constant *Elt = Cst->getAggregateElement(i)) {
4464                 if (auto *CInt = dyn_cast<ConstantInt>(Elt)) {
4465                   const APInt &Value = CInt->getValue();
4466                   Tmp = std::min(Tmp, Value.getNumSignBits());
4467                   continue;
4468                 }
4469                 if (auto *CFP = dyn_cast<ConstantFP>(Elt)) {
4470                   APInt Value = CFP->getValueAPF().bitcastToAPInt();
4471                   Tmp = std::min(Tmp, Value.getNumSignBits());
4472                   continue;
4473                 }
4474               }
4475               // Unknown type. Conservatively assume no bits match sign bit.
4476               return 1;
4477             }
4478             return Tmp;
4479           }
4480         }
4481         break;
4482       }
4483     }
4484   }
4485 
4486   // Allow the target to implement this method for its nodes.
4487   if (Opcode >= ISD::BUILTIN_OP_END ||
4488       Opcode == ISD::INTRINSIC_WO_CHAIN ||
4489       Opcode == ISD::INTRINSIC_W_CHAIN ||
4490       Opcode == ISD::INTRINSIC_VOID) {
4491     unsigned NumBits =
4492         TLI->ComputeNumSignBitsForTargetNode(Op, DemandedElts, *this, Depth);
4493     if (NumBits > 1)
4494       FirstAnswer = std::max(FirstAnswer, NumBits);
4495   }
4496 
4497   // Finally, if we can prove that the top bits of the result are 0's or 1's,
4498   // use this information.
4499   KnownBits Known = computeKnownBits(Op, DemandedElts, Depth);
4500   return std::max(FirstAnswer, Known.countMinSignBits());
4501 }
4502 
4503 unsigned SelectionDAG::ComputeMaxSignificantBits(SDValue Op,
4504                                                  unsigned Depth) const {
4505   unsigned SignBits = ComputeNumSignBits(Op, Depth);
4506   return Op.getScalarValueSizeInBits() - SignBits + 1;
4507 }
4508 
4509 unsigned SelectionDAG::ComputeMaxSignificantBits(SDValue Op,
4510                                                  const APInt &DemandedElts,
4511                                                  unsigned Depth) const {
4512   unsigned SignBits = ComputeNumSignBits(Op, DemandedElts, Depth);
4513   return Op.getScalarValueSizeInBits() - SignBits + 1;
4514 }
4515 
4516 bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly,
4517                                                     unsigned Depth) const {
4518   // Early out for FREEZE.
4519   if (Op.getOpcode() == ISD::FREEZE)
4520     return true;
4521 
4522   // TODO: Assume we don't know anything for now.
4523   EVT VT = Op.getValueType();
4524   if (VT.isScalableVector())
4525     return false;
4526 
4527   APInt DemandedElts = VT.isVector()
4528                            ? APInt::getAllOnes(VT.getVectorNumElements())
4529                            : APInt(1, 1);
4530   return isGuaranteedNotToBeUndefOrPoison(Op, DemandedElts, PoisonOnly, Depth);
4531 }
4532 
4533 bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
4534                                                     const APInt &DemandedElts,
4535                                                     bool PoisonOnly,
4536                                                     unsigned Depth) const {
4537   unsigned Opcode = Op.getOpcode();
4538 
4539   // Early out for FREEZE.
4540   if (Opcode == ISD::FREEZE)
4541     return true;
4542 
4543   if (Depth >= MaxRecursionDepth)
4544     return false; // Limit search depth.
4545 
4546   if (isIntOrFPConstant(Op))
4547     return true;
4548 
4549   switch (Opcode) {
4550   case ISD::UNDEF:
4551     return PoisonOnly;
4552 
4553   case ISD::BUILD_VECTOR:
4554     // NOTE: BUILD_VECTOR has implicit truncation of wider scalar elements -
4555     // this shouldn't affect the result.
4556     for (unsigned i = 0, e = Op.getNumOperands(); i < e; ++i) {
4557       if (!DemandedElts[i])
4558         continue;
4559       if (!isGuaranteedNotToBeUndefOrPoison(Op.getOperand(i), PoisonOnly,
4560                                             Depth + 1))
4561         return false;
4562     }
4563     return true;
4564 
4565   // TODO: Search for noundef attributes from library functions.
4566 
4567   // TODO: Pointers dereferenced by ISD::LOAD/STORE ops are noundef.
4568 
4569   default:
4570     // Allow the target to implement this method for its nodes.
4571     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
4572         Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID)
4573       return TLI->isGuaranteedNotToBeUndefOrPoisonForTargetNode(
4574           Op, DemandedElts, *this, PoisonOnly, Depth);
4575     break;
4576   }
4577 
4578   return false;
4579 }
4580 
4581 bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
4582   if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
4583       !isa<ConstantSDNode>(Op.getOperand(1)))
4584     return false;
4585 
4586   if (Op.getOpcode() == ISD::OR &&
4587       !MaskedValueIsZero(Op.getOperand(0), Op.getConstantOperandAPInt(1)))
4588     return false;
4589 
4590   return true;
4591 }
4592 
4593 bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const {
4594   // If we're told that NaNs won't happen, assume they won't.
4595   if (getTarget().Options.NoNaNsFPMath || Op->getFlags().hasNoNaNs())
4596     return true;
4597 
4598   if (Depth >= MaxRecursionDepth)
4599     return false; // Limit search depth.
4600 
4601   // TODO: Handle vectors.
4602   // If the value is a constant, we can obviously see if it is a NaN or not.
4603   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
4604     return !C->getValueAPF().isNaN() ||
4605            (SNaN && !C->getValueAPF().isSignaling());
4606   }
4607 
4608   unsigned Opcode = Op.getOpcode();
4609   switch (Opcode) {
4610   case ISD::FADD:
4611   case ISD::FSUB:
4612   case ISD::FMUL:
4613   case ISD::FDIV:
4614   case ISD::FREM:
4615   case ISD::FSIN:
4616   case ISD::FCOS: {
4617     if (SNaN)
4618       return true;
4619     // TODO: Need isKnownNeverInfinity
4620     return false;
4621   }
4622   case ISD::FCANONICALIZE:
4623   case ISD::FEXP:
4624   case ISD::FEXP2:
4625   case ISD::FTRUNC:
4626   case ISD::FFLOOR:
4627   case ISD::FCEIL:
4628   case ISD::FROUND:
4629   case ISD::FROUNDEVEN:
4630   case ISD::FRINT:
4631   case ISD::FNEARBYINT: {
4632     if (SNaN)
4633       return true;
4634     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4635   }
4636   case ISD::FABS:
4637   case ISD::FNEG:
4638   case ISD::FCOPYSIGN: {
4639     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4640   }
4641   case ISD::SELECT:
4642     return isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4643            isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4644   case ISD::FP_EXTEND:
4645   case ISD::FP_ROUND: {
4646     if (SNaN)
4647       return true;
4648     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4649   }
4650   case ISD::SINT_TO_FP:
4651   case ISD::UINT_TO_FP:
4652     return true;
4653   case ISD::FMA:
4654   case ISD::FMAD: {
4655     if (SNaN)
4656       return true;
4657     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4658            isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4659            isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4660   }
4661   case ISD::FSQRT: // Need is known positive
4662   case ISD::FLOG:
4663   case ISD::FLOG2:
4664   case ISD::FLOG10:
4665   case ISD::FPOWI:
4666   case ISD::FPOW: {
4667     if (SNaN)
4668       return true;
4669     // TODO: Refine on operand
4670     return false;
4671   }
4672   case ISD::FMINNUM:
4673   case ISD::FMAXNUM: {
4674     // Only one needs to be known not-nan, since it will be returned if the
4675     // other ends up being one.
4676     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) ||
4677            isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4678   }
4679   case ISD::FMINNUM_IEEE:
4680   case ISD::FMAXNUM_IEEE: {
4681     if (SNaN)
4682       return true;
4683     // This can return a NaN if either operand is an sNaN, or if both operands
4684     // are NaN.
4685     return (isKnownNeverNaN(Op.getOperand(0), false, Depth + 1) &&
4686             isKnownNeverSNaN(Op.getOperand(1), Depth + 1)) ||
4687            (isKnownNeverNaN(Op.getOperand(1), false, Depth + 1) &&
4688             isKnownNeverSNaN(Op.getOperand(0), Depth + 1));
4689   }
4690   case ISD::FMINIMUM:
4691   case ISD::FMAXIMUM: {
4692     // TODO: Does this quiet or return the origina NaN as-is?
4693     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4694            isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4695   }
4696   case ISD::EXTRACT_VECTOR_ELT: {
4697     return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4698   }
4699   default:
4700     if (Opcode >= ISD::BUILTIN_OP_END ||
4701         Opcode == ISD::INTRINSIC_WO_CHAIN ||
4702         Opcode == ISD::INTRINSIC_W_CHAIN ||
4703         Opcode == ISD::INTRINSIC_VOID) {
4704       return TLI->isKnownNeverNaNForTargetNode(Op, *this, SNaN, Depth);
4705     }
4706 
4707     return false;
4708   }
4709 }
4710 
4711 bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const {
4712   assert(Op.getValueType().isFloatingPoint() &&
4713          "Floating point type expected");
4714 
4715   // If the value is a constant, we can obviously see if it is a zero or not.
4716   // TODO: Add BuildVector support.
4717   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
4718     return !C->isZero();
4719   return false;
4720 }
4721 
4722 bool SelectionDAG::isKnownNeverZero(SDValue Op) const {
4723   assert(!Op.getValueType().isFloatingPoint() &&
4724          "Floating point types unsupported - use isKnownNeverZeroFloat");
4725 
4726   // If the value is a constant, we can obviously see if it is a zero or not.
4727   if (ISD::matchUnaryPredicate(Op,
4728                                [](ConstantSDNode *C) { return !C->isZero(); }))
4729     return true;
4730 
4731   // TODO: Recognize more cases here.
4732   switch (Op.getOpcode()) {
4733   default: break;
4734   case ISD::OR:
4735     if (isKnownNeverZero(Op.getOperand(1)) ||
4736         isKnownNeverZero(Op.getOperand(0)))
4737       return true;
4738     break;
4739   }
4740 
4741   return false;
4742 }
4743 
4744 bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const {
4745   // Check the obvious case.
4746   if (A == B) return true;
4747 
4748   // For for negative and positive zero.
4749   if (const ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A))
4750     if (const ConstantFPSDNode *CB = dyn_cast<ConstantFPSDNode>(B))
4751       if (CA->isZero() && CB->isZero()) return true;
4752 
4753   // Otherwise they may not be equal.
4754   return false;
4755 }
4756 
4757 // Only bits set in Mask must be negated, other bits may be arbitrary.
4758 SDValue llvm::getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs) {
4759   if (isBitwiseNot(V, AllowUndefs))
4760     return V.getOperand(0);
4761 
4762   // Handle any_extend (not (truncate X)) pattern, where Mask only sets
4763   // bits in the non-extended part.
4764   ConstantSDNode *MaskC = isConstOrConstSplat(Mask);
4765   if (!MaskC || V.getOpcode() != ISD::ANY_EXTEND)
4766     return SDValue();
4767   SDValue ExtArg = V.getOperand(0);
4768   if (ExtArg.getScalarValueSizeInBits() >=
4769           MaskC->getAPIntValue().getActiveBits() &&
4770       isBitwiseNot(ExtArg, AllowUndefs) &&
4771       ExtArg.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4772       ExtArg.getOperand(0).getOperand(0).getValueType() == V.getValueType())
4773     return ExtArg.getOperand(0).getOperand(0);
4774   return SDValue();
4775 }
4776 
4777 static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B) {
4778   // Match masked merge pattern (X & ~M) op (Y & M)
4779   // Including degenerate case (X & ~M) op M
4780   auto MatchNoCommonBitsPattern = [&](SDValue Not, SDValue Mask,
4781                                       SDValue Other) {
4782     if (SDValue NotOperand =
4783             getBitwiseNotOperand(Not, Mask, /* AllowUndefs */ true)) {
4784       if (Other == NotOperand)
4785         return true;
4786       if (Other->getOpcode() == ISD::AND)
4787         return NotOperand == Other->getOperand(0) ||
4788                NotOperand == Other->getOperand(1);
4789     }
4790     return false;
4791   };
4792   if (A->getOpcode() == ISD::AND)
4793     return MatchNoCommonBitsPattern(A->getOperand(0), A->getOperand(1), B) ||
4794            MatchNoCommonBitsPattern(A->getOperand(1), A->getOperand(0), B);
4795   return false;
4796 }
4797 
4798 // FIXME: unify with llvm::haveNoCommonBitsSet.
4799 bool SelectionDAG::haveNoCommonBitsSet(SDValue A, SDValue B) const {
4800   assert(A.getValueType() == B.getValueType() &&
4801          "Values must have the same type");
4802   if (haveNoCommonBitsSetCommutative(A, B) ||
4803       haveNoCommonBitsSetCommutative(B, A))
4804     return true;
4805   return KnownBits::haveNoCommonBitsSet(computeKnownBits(A),
4806                                         computeKnownBits(B));
4807 }
4808 
4809 static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step,
4810                                SelectionDAG &DAG) {
4811   if (cast<ConstantSDNode>(Step)->isZero())
4812     return DAG.getConstant(0, DL, VT);
4813 
4814   return SDValue();
4815 }
4816 
4817 static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT,
4818                                 ArrayRef<SDValue> Ops,
4819                                 SelectionDAG &DAG) {
4820   int NumOps = Ops.size();
4821   assert(NumOps != 0 && "Can't build an empty vector!");
4822   assert(!VT.isScalableVector() &&
4823          "BUILD_VECTOR cannot be used with scalable types");
4824   assert(VT.getVectorNumElements() == (unsigned)NumOps &&
4825          "Incorrect element count in BUILD_VECTOR!");
4826 
4827   // BUILD_VECTOR of UNDEFs is UNDEF.
4828   if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); }))
4829     return DAG.getUNDEF(VT);
4830 
4831   // BUILD_VECTOR of seq extract/insert from the same vector + type is Identity.
4832   SDValue IdentitySrc;
4833   bool IsIdentity = true;
4834   for (int i = 0; i != NumOps; ++i) {
4835     if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4836         Ops[i].getOperand(0).getValueType() != VT ||
4837         (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
4838         !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
4839         cast<ConstantSDNode>(Ops[i].getOperand(1))->getAPIntValue() != i) {
4840       IsIdentity = false;
4841       break;
4842     }
4843     IdentitySrc = Ops[i].getOperand(0);
4844   }
4845   if (IsIdentity)
4846     return IdentitySrc;
4847 
4848   return SDValue();
4849 }
4850 
4851 /// Try to simplify vector concatenation to an input value, undef, or build
4852 /// vector.
4853 static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
4854                                   ArrayRef<SDValue> Ops,
4855                                   SelectionDAG &DAG) {
4856   assert(!Ops.empty() && "Can't concatenate an empty list of vectors!");
4857   assert(llvm::all_of(Ops,
4858                       [Ops](SDValue Op) {
4859                         return Ops[0].getValueType() == Op.getValueType();
4860                       }) &&
4861          "Concatenation of vectors with inconsistent value types!");
4862   assert((Ops[0].getValueType().getVectorElementCount() * Ops.size()) ==
4863              VT.getVectorElementCount() &&
4864          "Incorrect element count in vector concatenation!");
4865 
4866   if (Ops.size() == 1)
4867     return Ops[0];
4868 
4869   // Concat of UNDEFs is UNDEF.
4870   if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); }))
4871     return DAG.getUNDEF(VT);
4872 
4873   // Scan the operands and look for extract operations from a single source
4874   // that correspond to insertion at the same location via this concatenation:
4875   // concat (extract X, 0*subvec_elts), (extract X, 1*subvec_elts), ...
4876   SDValue IdentitySrc;
4877   bool IsIdentity = true;
4878   for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
4879     SDValue Op = Ops[i];
4880     unsigned IdentityIndex = i * Op.getValueType().getVectorMinNumElements();
4881     if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
4882         Op.getOperand(0).getValueType() != VT ||
4883         (IdentitySrc && Op.getOperand(0) != IdentitySrc) ||
4884         Op.getConstantOperandVal(1) != IdentityIndex) {
4885       IsIdentity = false;
4886       break;
4887     }
4888     assert((!IdentitySrc || IdentitySrc == Op.getOperand(0)) &&
4889            "Unexpected identity source vector for concat of extracts");
4890     IdentitySrc = Op.getOperand(0);
4891   }
4892   if (IsIdentity) {
4893     assert(IdentitySrc && "Failed to set source vector of extracts");
4894     return IdentitySrc;
4895   }
4896 
4897   // The code below this point is only designed to work for fixed width
4898   // vectors, so we bail out for now.
4899   if (VT.isScalableVector())
4900     return SDValue();
4901 
4902   // A CONCAT_VECTOR with all UNDEF/BUILD_VECTOR operands can be
4903   // simplified to one big BUILD_VECTOR.
4904   // FIXME: Add support for SCALAR_TO_VECTOR as well.
4905   EVT SVT = VT.getScalarType();
4906   SmallVector<SDValue, 16> Elts;
4907   for (SDValue Op : Ops) {
4908     EVT OpVT = Op.getValueType();
4909     if (Op.isUndef())
4910       Elts.append(OpVT.getVectorNumElements(), DAG.getUNDEF(SVT));
4911     else if (Op.getOpcode() == ISD::BUILD_VECTOR)
4912       Elts.append(Op->op_begin(), Op->op_end());
4913     else
4914       return SDValue();
4915   }
4916 
4917   // BUILD_VECTOR requires all inputs to be of the same type, find the
4918   // maximum type and extend them all.
4919   for (SDValue Op : Elts)
4920     SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
4921 
4922   if (SVT.bitsGT(VT.getScalarType())) {
4923     for (SDValue &Op : Elts) {
4924       if (Op.isUndef())
4925         Op = DAG.getUNDEF(SVT);
4926       else
4927         Op = DAG.getTargetLoweringInfo().isZExtFree(Op.getValueType(), SVT)
4928                  ? DAG.getZExtOrTrunc(Op, DL, SVT)
4929                  : DAG.getSExtOrTrunc(Op, DL, SVT);
4930     }
4931   }
4932 
4933   SDValue V = DAG.getBuildVector(VT, DL, Elts);
4934   NewSDValueDbgMsg(V, "New node fold concat vectors: ", &DAG);
4935   return V;
4936 }
4937 
4938 /// Gets or creates the specified node.
4939 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT) {
4940   FoldingSetNodeID ID;
4941   AddNodeIDNode(ID, Opcode, getVTList(VT), None);
4942   void *IP = nullptr;
4943   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
4944     return SDValue(E, 0);
4945 
4946   auto *N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(),
4947                               getVTList(VT));
4948   CSEMap.InsertNode(N, IP);
4949 
4950   InsertNode(N);
4951   SDValue V = SDValue(N, 0);
4952   NewSDValueDbgMsg(V, "Creating new node: ", this);
4953   return V;
4954 }
4955 
4956 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
4957                               SDValue Operand) {
4958   SDNodeFlags Flags;
4959   if (Inserter)
4960     Flags = Inserter->getFlags();
4961   return getNode(Opcode, DL, VT, Operand, Flags);
4962 }
4963 
4964 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
4965                               SDValue Operand, const SDNodeFlags Flags) {
4966   assert(Operand.getOpcode() != ISD::DELETED_NODE &&
4967          "Operand is DELETED_NODE!");
4968   // Constant fold unary operations with an integer constant operand. Even
4969   // opaque constant will be folded, because the folding of unary operations
4970   // doesn't create new constants with different values. Nevertheless, the
4971   // opaque flag is preserved during folding to prevent future folding with
4972   // other constants.
4973   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand)) {
4974     const APInt &Val = C->getAPIntValue();
4975     switch (Opcode) {
4976     default: break;
4977     case ISD::SIGN_EXTEND:
4978       return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT,
4979                          C->isTargetOpcode(), C->isOpaque());
4980     case ISD::TRUNCATE:
4981       if (C->isOpaque())
4982         break;
4983       LLVM_FALLTHROUGH;
4984     case ISD::ZERO_EXTEND:
4985       return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,
4986                          C->isTargetOpcode(), C->isOpaque());
4987     case ISD::ANY_EXTEND:
4988       // Some targets like RISCV prefer to sign extend some types.
4989       if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT))
4990         return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT,
4991                            C->isTargetOpcode(), C->isOpaque());
4992       return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,
4993                          C->isTargetOpcode(), C->isOpaque());
4994     case ISD::UINT_TO_FP:
4995     case ISD::SINT_TO_FP: {
4996       APFloat apf(EVTToAPFloatSemantics(VT),
4997                   APInt::getZero(VT.getSizeInBits()));
4998       (void)apf.convertFromAPInt(Val,
4999                                  Opcode==ISD::SINT_TO_FP,
5000                                  APFloat::rmNearestTiesToEven);
5001       return getConstantFP(apf, DL, VT);
5002     }
5003     case ISD::BITCAST:
5004       if (VT == MVT::f16 && C->getValueType(0) == MVT::i16)
5005         return getConstantFP(APFloat(APFloat::IEEEhalf(), Val), DL, VT);
5006       if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
5007         return getConstantFP(APFloat(APFloat::IEEEsingle(), Val), DL, VT);
5008       if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
5009         return getConstantFP(APFloat(APFloat::IEEEdouble(), Val), DL, VT);
5010       if (VT == MVT::f128 && C->getValueType(0) == MVT::i128)
5011         return getConstantFP(APFloat(APFloat::IEEEquad(), Val), DL, VT);
5012       break;
5013     case ISD::ABS:
5014       return getConstant(Val.abs(), DL, VT, C->isTargetOpcode(),
5015                          C->isOpaque());
5016     case ISD::BITREVERSE:
5017       return getConstant(Val.reverseBits(), DL, VT, C->isTargetOpcode(),
5018                          C->isOpaque());
5019     case ISD::BSWAP:
5020       return getConstant(Val.byteSwap(), DL, VT, C->isTargetOpcode(),
5021                          C->isOpaque());
5022     case ISD::CTPOP:
5023       return getConstant(Val.countPopulation(), DL, VT, C->isTargetOpcode(),
5024                          C->isOpaque());
5025     case ISD::CTLZ:
5026     case ISD::CTLZ_ZERO_UNDEF:
5027       return getConstant(Val.countLeadingZeros(), DL, VT, C->isTargetOpcode(),
5028                          C->isOpaque());
5029     case ISD::CTTZ:
5030     case ISD::CTTZ_ZERO_UNDEF:
5031       return getConstant(Val.countTrailingZeros(), DL, VT, C->isTargetOpcode(),
5032                          C->isOpaque());
5033     case ISD::FP16_TO_FP:
5034     case ISD::BF16_TO_FP: {
5035       bool Ignored;
5036       APFloat FPV(Opcode == ISD::FP16_TO_FP ? APFloat::IEEEhalf()
5037                                             : APFloat::BFloat(),
5038                   (Val.getBitWidth() == 16) ? Val : Val.trunc(16));
5039 
5040       // This can return overflow, underflow, or inexact; we don't care.
5041       // FIXME need to be more flexible about rounding mode.
5042       (void)FPV.convert(EVTToAPFloatSemantics(VT),
5043                         APFloat::rmNearestTiesToEven, &Ignored);
5044       return getConstantFP(FPV, DL, VT);
5045     }
5046     case ISD::STEP_VECTOR: {
5047       if (SDValue V = FoldSTEP_VECTOR(DL, VT, Operand, *this))
5048         return V;
5049       break;
5050     }
5051     }
5052   }
5053 
5054   // Constant fold unary operations with a floating point constant operand.
5055   if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand)) {
5056     APFloat V = C->getValueAPF();    // make copy
5057     switch (Opcode) {
5058     case ISD::FNEG:
5059       V.changeSign();
5060       return getConstantFP(V, DL, VT);
5061     case ISD::FABS:
5062       V.clearSign();
5063       return getConstantFP(V, DL, VT);
5064     case ISD::FCEIL: {
5065       APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardPositive);
5066       if (fs == APFloat::opOK || fs == APFloat::opInexact)
5067         return getConstantFP(V, DL, VT);
5068       break;
5069     }
5070     case ISD::FTRUNC: {
5071       APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardZero);
5072       if (fs == APFloat::opOK || fs == APFloat::opInexact)
5073         return getConstantFP(V, DL, VT);
5074       break;
5075     }
5076     case ISD::FFLOOR: {
5077       APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardNegative);
5078       if (fs == APFloat::opOK || fs == APFloat::opInexact)
5079         return getConstantFP(V, DL, VT);
5080       break;
5081     }
5082     case ISD::FP_EXTEND: {
5083       bool ignored;
5084       // This can return overflow, underflow, or inexact; we don't care.
5085       // FIXME need to be more flexible about rounding mode.
5086       (void)V.convert(EVTToAPFloatSemantics(VT),
5087                       APFloat::rmNearestTiesToEven, &ignored);
5088       return getConstantFP(V, DL, VT);
5089     }
5090     case ISD::FP_TO_SINT:
5091     case ISD::FP_TO_UINT: {
5092       bool ignored;
5093       APSInt IntVal(VT.getSizeInBits(), Opcode == ISD::FP_TO_UINT);
5094       // FIXME need to be more flexible about rounding mode.
5095       APFloat::opStatus s =
5096           V.convertToInteger(IntVal, APFloat::rmTowardZero, &ignored);
5097       if (s == APFloat::opInvalidOp) // inexact is OK, in fact usual
5098         break;
5099       return getConstant(IntVal, DL, VT);
5100     }
5101     case ISD::BITCAST:
5102       if (VT == MVT::i16 && C->getValueType(0) == MVT::f16)
5103         return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
5104       if (VT == MVT::i16 && C->getValueType(0) == MVT::bf16)
5105         return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
5106       if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
5107         return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), DL, VT);
5108       if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
5109         return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT);
5110       break;
5111     case ISD::FP_TO_FP16:
5112     case ISD::FP_TO_BF16: {
5113       bool Ignored;
5114       // This can return overflow, underflow, or inexact; we don't care.
5115       // FIXME need to be more flexible about rounding mode.
5116       (void)V.convert(Opcode == ISD::FP_TO_FP16 ? APFloat::IEEEhalf()
5117                                                 : APFloat::BFloat(),
5118                       APFloat::rmNearestTiesToEven, &Ignored);
5119       return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT);
5120     }
5121     }
5122   }
5123 
5124   // Constant fold unary operations with a vector integer or float operand.
5125   switch (Opcode) {
5126   default:
5127     // FIXME: Entirely reasonable to perform folding of other unary
5128     // operations here as the need arises.
5129     break;
5130   case ISD::FNEG:
5131   case ISD::FABS:
5132   case ISD::FCEIL:
5133   case ISD::FTRUNC:
5134   case ISD::FFLOOR:
5135   case ISD::FP_EXTEND:
5136   case ISD::FP_TO_SINT:
5137   case ISD::FP_TO_UINT:
5138   case ISD::TRUNCATE:
5139   case ISD::ANY_EXTEND:
5140   case ISD::ZERO_EXTEND:
5141   case ISD::SIGN_EXTEND:
5142   case ISD::UINT_TO_FP:
5143   case ISD::SINT_TO_FP:
5144   case ISD::ABS:
5145   case ISD::BITREVERSE:
5146   case ISD::BSWAP:
5147   case ISD::CTLZ:
5148   case ISD::CTLZ_ZERO_UNDEF:
5149   case ISD::CTTZ:
5150   case ISD::CTTZ_ZERO_UNDEF:
5151   case ISD::CTPOP: {
5152     SDValue Ops = {Operand};
5153     if (SDValue Fold = FoldConstantArithmetic(Opcode, DL, VT, Ops))
5154       return Fold;
5155   }
5156   }
5157 
5158   unsigned OpOpcode = Operand.getNode()->getOpcode();
5159   switch (Opcode) {
5160   case ISD::STEP_VECTOR:
5161     assert(VT.isScalableVector() &&
5162            "STEP_VECTOR can only be used with scalable types");
5163     assert(OpOpcode == ISD::TargetConstant &&
5164            VT.getVectorElementType() == Operand.getValueType() &&
5165            "Unexpected step operand");
5166     break;
5167   case ISD::FREEZE:
5168     assert(VT == Operand.getValueType() && "Unexpected VT!");
5169     if (isGuaranteedNotToBeUndefOrPoison(Operand))
5170       return Operand;
5171     break;
5172   case ISD::TokenFactor:
5173   case ISD::MERGE_VALUES:
5174   case ISD::CONCAT_VECTORS:
5175     return Operand;         // Factor, merge or concat of one node?  No need.
5176   case ISD::BUILD_VECTOR: {
5177     // Attempt to simplify BUILD_VECTOR.
5178     SDValue Ops[] = {Operand};
5179     if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
5180       return V;
5181     break;
5182   }
5183   case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
5184   case ISD::FP_EXTEND:
5185     assert(VT.isFloatingPoint() &&
5186            Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
5187     if (Operand.getValueType() == VT) return Operand;  // noop conversion.
5188     assert((!VT.isVector() ||
5189             VT.getVectorElementCount() ==
5190             Operand.getValueType().getVectorElementCount()) &&
5191            "Vector element count mismatch!");
5192     assert(Operand.getValueType().bitsLT(VT) &&
5193            "Invalid fpext node, dst < src!");
5194     if (Operand.isUndef())
5195       return getUNDEF(VT);
5196     break;
5197   case ISD::FP_TO_SINT:
5198   case ISD::FP_TO_UINT:
5199     if (Operand.isUndef())
5200       return getUNDEF(VT);
5201     break;
5202   case ISD::SINT_TO_FP:
5203   case ISD::UINT_TO_FP:
5204     // [us]itofp(undef) = 0, because the result value is bounded.
5205     if (Operand.isUndef())
5206       return getConstantFP(0.0, DL, VT);
5207     break;
5208   case ISD::SIGN_EXTEND:
5209     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
5210            "Invalid SIGN_EXTEND!");
5211     assert(VT.isVector() == Operand.getValueType().isVector() &&
5212            "SIGN_EXTEND result type type should be vector iff the operand "
5213            "type is vector!");
5214     if (Operand.getValueType() == VT) return Operand;   // noop extension
5215     assert((!VT.isVector() ||
5216             VT.getVectorElementCount() ==
5217                 Operand.getValueType().getVectorElementCount()) &&
5218            "Vector element count mismatch!");
5219     assert(Operand.getValueType().bitsLT(VT) &&
5220            "Invalid sext node, dst < src!");
5221     if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
5222       return getNode(OpOpcode, DL, VT, Operand.getOperand(0));
5223     if (OpOpcode == ISD::UNDEF)
5224       // sext(undef) = 0, because the top bits will all be the same.
5225       return getConstant(0, DL, VT);
5226     break;
5227   case ISD::ZERO_EXTEND:
5228     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
5229            "Invalid ZERO_EXTEND!");
5230     assert(VT.isVector() == Operand.getValueType().isVector() &&
5231            "ZERO_EXTEND result type type should be vector iff the operand "
5232            "type is vector!");
5233     if (Operand.getValueType() == VT) return Operand;   // noop extension
5234     assert((!VT.isVector() ||
5235             VT.getVectorElementCount() ==
5236                 Operand.getValueType().getVectorElementCount()) &&
5237            "Vector element count mismatch!");
5238     assert(Operand.getValueType().bitsLT(VT) &&
5239            "Invalid zext node, dst < src!");
5240     if (OpOpcode == ISD::ZERO_EXTEND)   // (zext (zext x)) -> (zext x)
5241       return getNode(ISD::ZERO_EXTEND, DL, VT, Operand.getOperand(0));
5242     if (OpOpcode == ISD::UNDEF)
5243       // zext(undef) = 0, because the top bits will be zero.
5244       return getConstant(0, DL, VT);
5245     break;
5246   case ISD::ANY_EXTEND:
5247     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
5248            "Invalid ANY_EXTEND!");
5249     assert(VT.isVector() == Operand.getValueType().isVector() &&
5250            "ANY_EXTEND result type type should be vector iff the operand "
5251            "type is vector!");
5252     if (Operand.getValueType() == VT) return Operand;   // noop extension
5253     assert((!VT.isVector() ||
5254             VT.getVectorElementCount() ==
5255                 Operand.getValueType().getVectorElementCount()) &&
5256            "Vector element count mismatch!");
5257     assert(Operand.getValueType().bitsLT(VT) &&
5258            "Invalid anyext node, dst < src!");
5259 
5260     if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
5261         OpOpcode == ISD::ANY_EXTEND)
5262       // (ext (zext x)) -> (zext x)  and  (ext (sext x)) -> (sext x)
5263       return getNode(OpOpcode, DL, VT, Operand.getOperand(0));
5264     if (OpOpcode == ISD::UNDEF)
5265       return getUNDEF(VT);
5266 
5267     // (ext (trunc x)) -> x
5268     if (OpOpcode == ISD::TRUNCATE) {
5269       SDValue OpOp = Operand.getOperand(0);
5270       if (OpOp.getValueType() == VT) {
5271         transferDbgValues(Operand, OpOp);
5272         return OpOp;
5273       }
5274     }
5275     break;
5276   case ISD::TRUNCATE:
5277     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
5278            "Invalid TRUNCATE!");
5279     assert(VT.isVector() == Operand.getValueType().isVector() &&
5280            "TRUNCATE result type type should be vector iff the operand "
5281            "type is vector!");
5282     if (Operand.getValueType() == VT) return Operand;   // noop truncate
5283     assert((!VT.isVector() ||
5284             VT.getVectorElementCount() ==
5285                 Operand.getValueType().getVectorElementCount()) &&
5286            "Vector element count mismatch!");
5287     assert(Operand.getValueType().bitsGT(VT) &&
5288            "Invalid truncate node, src < dst!");
5289     if (OpOpcode == ISD::TRUNCATE)
5290       return getNode(ISD::TRUNCATE, DL, VT, Operand.getOperand(0));
5291     if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
5292         OpOpcode == ISD::ANY_EXTEND) {
5293       // If the source is smaller than the dest, we still need an extend.
5294       if (Operand.getOperand(0).getValueType().getScalarType()
5295             .bitsLT(VT.getScalarType()))
5296         return getNode(OpOpcode, DL, VT, Operand.getOperand(0));
5297       if (Operand.getOperand(0).getValueType().bitsGT(VT))
5298         return getNode(ISD::TRUNCATE, DL, VT, Operand.getOperand(0));
5299       return Operand.getOperand(0);
5300     }
5301     if (OpOpcode == ISD::UNDEF)
5302       return getUNDEF(VT);
5303     if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
5304       return getVScale(DL, VT, Operand.getConstantOperandAPInt(0));
5305     break;
5306   case ISD::ANY_EXTEND_VECTOR_INREG:
5307   case ISD::ZERO_EXTEND_VECTOR_INREG:
5308   case ISD::SIGN_EXTEND_VECTOR_INREG:
5309     assert(VT.isVector() && "This DAG node is restricted to vector types.");
5310     assert(Operand.getValueType().bitsLE(VT) &&
5311            "The input must be the same size or smaller than the result.");
5312     assert(VT.getVectorMinNumElements() <
5313                Operand.getValueType().getVectorMinNumElements() &&
5314            "The destination vector type must have fewer lanes than the input.");
5315     break;
5316   case ISD::ABS:
5317     assert(VT.isInteger() && VT == Operand.getValueType() &&
5318            "Invalid ABS!");
5319     if (OpOpcode == ISD::UNDEF)
5320       return getConstant(0, DL, VT);
5321     break;
5322   case ISD::BSWAP:
5323     assert(VT.isInteger() && VT == Operand.getValueType() &&
5324            "Invalid BSWAP!");
5325     assert((VT.getScalarSizeInBits() % 16 == 0) &&
5326            "BSWAP types must be a multiple of 16 bits!");
5327     if (OpOpcode == ISD::UNDEF)
5328       return getUNDEF(VT);
5329     // bswap(bswap(X)) -> X.
5330     if (OpOpcode == ISD::BSWAP)
5331       return Operand.getOperand(0);
5332     break;
5333   case ISD::BITREVERSE:
5334     assert(VT.isInteger() && VT == Operand.getValueType() &&
5335            "Invalid BITREVERSE!");
5336     if (OpOpcode == ISD::UNDEF)
5337       return getUNDEF(VT);
5338     break;
5339   case ISD::BITCAST:
5340     assert(VT.getSizeInBits() == Operand.getValueSizeInBits() &&
5341            "Cannot BITCAST between types of different sizes!");
5342     if (VT == Operand.getValueType()) return Operand;  // noop conversion.
5343     if (OpOpcode == ISD::BITCAST)  // bitconv(bitconv(x)) -> bitconv(x)
5344       return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0));
5345     if (OpOpcode == ISD::UNDEF)
5346       return getUNDEF(VT);
5347     break;
5348   case ISD::SCALAR_TO_VECTOR:
5349     assert(VT.isVector() && !Operand.getValueType().isVector() &&
5350            (VT.getVectorElementType() == Operand.getValueType() ||
5351             (VT.getVectorElementType().isInteger() &&
5352              Operand.getValueType().isInteger() &&
5353              VT.getVectorElementType().bitsLE(Operand.getValueType()))) &&
5354            "Illegal SCALAR_TO_VECTOR node!");
5355     if (OpOpcode == ISD::UNDEF)
5356       return getUNDEF(VT);
5357     // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
5358     if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
5359         isa<ConstantSDNode>(Operand.getOperand(1)) &&
5360         Operand.getConstantOperandVal(1) == 0 &&
5361         Operand.getOperand(0).getValueType() == VT)
5362       return Operand.getOperand(0);
5363     break;
5364   case ISD::FNEG:
5365     // Negation of an unknown bag of bits is still completely undefined.
5366     if (OpOpcode == ISD::UNDEF)
5367       return getUNDEF(VT);
5368 
5369     if (OpOpcode == ISD::FNEG)  // --X -> X
5370       return Operand.getOperand(0);
5371     break;
5372   case ISD::FABS:
5373     if (OpOpcode == ISD::FNEG)  // abs(-X) -> abs(X)
5374       return getNode(ISD::FABS, DL, VT, Operand.getOperand(0));
5375     break;
5376   case ISD::VSCALE:
5377     assert(VT == Operand.getValueType() && "Unexpected VT!");
5378     break;
5379   case ISD::CTPOP:
5380     if (Operand.getValueType().getScalarType() == MVT::i1)
5381       return Operand;
5382     break;
5383   case ISD::CTLZ:
5384   case ISD::CTTZ:
5385     if (Operand.getValueType().getScalarType() == MVT::i1)
5386       return getNOT(DL, Operand, Operand.getValueType());
5387     break;
5388   case ISD::VECREDUCE_ADD:
5389     if (Operand.getValueType().getScalarType() == MVT::i1)
5390       return getNode(ISD::VECREDUCE_XOR, DL, VT, Operand);
5391     break;
5392   case ISD::VECREDUCE_SMIN:
5393   case ISD::VECREDUCE_UMAX:
5394     if (Operand.getValueType().getScalarType() == MVT::i1)
5395       return getNode(ISD::VECREDUCE_OR, DL, VT, Operand);
5396     break;
5397   case ISD::VECREDUCE_SMAX:
5398   case ISD::VECREDUCE_UMIN:
5399     if (Operand.getValueType().getScalarType() == MVT::i1)
5400       return getNode(ISD::VECREDUCE_AND, DL, VT, Operand);
5401     break;
5402   }
5403 
5404   SDNode *N;
5405   SDVTList VTs = getVTList(VT);
5406   SDValue Ops[] = {Operand};
5407   if (VT != MVT::Glue) { // Don't CSE flag producing nodes
5408     FoldingSetNodeID ID;
5409     AddNodeIDNode(ID, Opcode, VTs, Ops);
5410     void *IP = nullptr;
5411     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
5412       E->intersectFlagsWith(Flags);
5413       return SDValue(E, 0);
5414     }
5415 
5416     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
5417     N->setFlags(Flags);
5418     createOperands(N, Ops);
5419     CSEMap.InsertNode(N, IP);
5420   } else {
5421     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
5422     createOperands(N, Ops);
5423   }
5424 
5425   InsertNode(N);
5426   SDValue V = SDValue(N, 0);
5427   NewSDValueDbgMsg(V, "Creating new node: ", this);
5428   return V;
5429 }
5430 
5431 static llvm::Optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
5432                                        const APInt &C2) {
5433   switch (Opcode) {
5434   case ISD::ADD:  return C1 + C2;
5435   case ISD::SUB:  return C1 - C2;
5436   case ISD::MUL:  return C1 * C2;
5437   case ISD::AND:  return C1 & C2;
5438   case ISD::OR:   return C1 | C2;
5439   case ISD::XOR:  return C1 ^ C2;
5440   case ISD::SHL:  return C1 << C2;
5441   case ISD::SRL:  return C1.lshr(C2);
5442   case ISD::SRA:  return C1.ashr(C2);
5443   case ISD::ROTL: return C1.rotl(C2);
5444   case ISD::ROTR: return C1.rotr(C2);
5445   case ISD::SMIN: return C1.sle(C2) ? C1 : C2;
5446   case ISD::SMAX: return C1.sge(C2) ? C1 : C2;
5447   case ISD::UMIN: return C1.ule(C2) ? C1 : C2;
5448   case ISD::UMAX: return C1.uge(C2) ? C1 : C2;
5449   case ISD::SADDSAT: return C1.sadd_sat(C2);
5450   case ISD::UADDSAT: return C1.uadd_sat(C2);
5451   case ISD::SSUBSAT: return C1.ssub_sat(C2);
5452   case ISD::USUBSAT: return C1.usub_sat(C2);
5453   case ISD::SSHLSAT: return C1.sshl_sat(C2);
5454   case ISD::USHLSAT: return C1.ushl_sat(C2);
5455   case ISD::UDIV:
5456     if (!C2.getBoolValue())
5457       break;
5458     return C1.udiv(C2);
5459   case ISD::UREM:
5460     if (!C2.getBoolValue())
5461       break;
5462     return C1.urem(C2);
5463   case ISD::SDIV:
5464     if (!C2.getBoolValue())
5465       break;
5466     return C1.sdiv(C2);
5467   case ISD::SREM:
5468     if (!C2.getBoolValue())
5469       break;
5470     return C1.srem(C2);
5471   case ISD::MULHS: {
5472     unsigned FullWidth = C1.getBitWidth() * 2;
5473     APInt C1Ext = C1.sext(FullWidth);
5474     APInt C2Ext = C2.sext(FullWidth);
5475     return (C1Ext * C2Ext).extractBits(C1.getBitWidth(), C1.getBitWidth());
5476   }
5477   case ISD::MULHU: {
5478     unsigned FullWidth = C1.getBitWidth() * 2;
5479     APInt C1Ext = C1.zext(FullWidth);
5480     APInt C2Ext = C2.zext(FullWidth);
5481     return (C1Ext * C2Ext).extractBits(C1.getBitWidth(), C1.getBitWidth());
5482   }
5483   case ISD::AVGFLOORS: {
5484     unsigned FullWidth = C1.getBitWidth() + 1;
5485     APInt C1Ext = C1.sext(FullWidth);
5486     APInt C2Ext = C2.sext(FullWidth);
5487     return (C1Ext + C2Ext).extractBits(C1.getBitWidth(), 1);
5488   }
5489   case ISD::AVGFLOORU: {
5490     unsigned FullWidth = C1.getBitWidth() + 1;
5491     APInt C1Ext = C1.zext(FullWidth);
5492     APInt C2Ext = C2.zext(FullWidth);
5493     return (C1Ext + C2Ext).extractBits(C1.getBitWidth(), 1);
5494   }
5495   case ISD::AVGCEILS: {
5496     unsigned FullWidth = C1.getBitWidth() + 1;
5497     APInt C1Ext = C1.sext(FullWidth);
5498     APInt C2Ext = C2.sext(FullWidth);
5499     return (C1Ext + C2Ext + 1).extractBits(C1.getBitWidth(), 1);
5500   }
5501   case ISD::AVGCEILU: {
5502     unsigned FullWidth = C1.getBitWidth() + 1;
5503     APInt C1Ext = C1.zext(FullWidth);
5504     APInt C2Ext = C2.zext(FullWidth);
5505     return (C1Ext + C2Ext + 1).extractBits(C1.getBitWidth(), 1);
5506   }
5507   }
5508   return llvm::None;
5509 }
5510 
5511 SDValue SelectionDAG::FoldSymbolOffset(unsigned Opcode, EVT VT,
5512                                        const GlobalAddressSDNode *GA,
5513                                        const SDNode *N2) {
5514   if (GA->getOpcode() != ISD::GlobalAddress)
5515     return SDValue();
5516   if (!TLI->isOffsetFoldingLegal(GA))
5517     return SDValue();
5518   auto *C2 = dyn_cast<ConstantSDNode>(N2);
5519   if (!C2)
5520     return SDValue();
5521   int64_t Offset = C2->getSExtValue();
5522   switch (Opcode) {
5523   case ISD::ADD: break;
5524   case ISD::SUB: Offset = -uint64_t(Offset); break;
5525   default: return SDValue();
5526   }
5527   return getGlobalAddress(GA->getGlobal(), SDLoc(C2), VT,
5528                           GA->getOffset() + uint64_t(Offset));
5529 }
5530 
5531 bool SelectionDAG::isUndef(unsigned Opcode, ArrayRef<SDValue> Ops) {
5532   switch (Opcode) {
5533   case ISD::SDIV:
5534   case ISD::UDIV:
5535   case ISD::SREM:
5536   case ISD::UREM: {
5537     // If a divisor is zero/undef or any element of a divisor vector is
5538     // zero/undef, the whole op is undef.
5539     assert(Ops.size() == 2 && "Div/rem should have 2 operands");
5540     SDValue Divisor = Ops[1];
5541     if (Divisor.isUndef() || isNullConstant(Divisor))
5542       return true;
5543 
5544     return ISD::isBuildVectorOfConstantSDNodes(Divisor.getNode()) &&
5545            llvm::any_of(Divisor->op_values(),
5546                         [](SDValue V) { return V.isUndef() ||
5547                                         isNullConstant(V); });
5548     // TODO: Handle signed overflow.
5549   }
5550   // TODO: Handle oversized shifts.
5551   default:
5552     return false;
5553   }
5554 }
5555 
5556 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
5557                                              EVT VT, ArrayRef<SDValue> Ops) {
5558   // If the opcode is a target-specific ISD node, there's nothing we can
5559   // do here and the operand rules may not line up with the below, so
5560   // bail early.
5561   // We can't create a scalar CONCAT_VECTORS so skip it. It will break
5562   // for concats involving SPLAT_VECTOR. Concats of BUILD_VECTORS are handled by
5563   // foldCONCAT_VECTORS in getNode before this is called.
5564   if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS)
5565     return SDValue();
5566 
5567   unsigned NumOps = Ops.size();
5568   if (NumOps == 0)
5569     return SDValue();
5570 
5571   if (isUndef(Opcode, Ops))
5572     return getUNDEF(VT);
5573 
5574   // Handle binops special cases.
5575   if (NumOps == 2) {
5576     if (SDValue CFP = foldConstantFPMath(Opcode, DL, VT, Ops[0], Ops[1]))
5577       return CFP;
5578 
5579     if (auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
5580       if (auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
5581         if (C1->isOpaque() || C2->isOpaque())
5582           return SDValue();
5583 
5584         Optional<APInt> FoldAttempt =
5585             FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
5586         if (!FoldAttempt)
5587           return SDValue();
5588 
5589         SDValue Folded = getConstant(*FoldAttempt, DL, VT);
5590         assert((!Folded || !VT.isVector()) &&
5591                "Can't fold vectors ops with scalar operands");
5592         return Folded;
5593       }
5594     }
5595 
5596     // fold (add Sym, c) -> Sym+c
5597     if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Ops[0]))
5598       return FoldSymbolOffset(Opcode, VT, GA, Ops[1].getNode());
5599     if (TLI->isCommutativeBinOp(Opcode))
5600       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Ops[1]))
5601         return FoldSymbolOffset(Opcode, VT, GA, Ops[0].getNode());
5602   }
5603 
5604   // This is for vector folding only from here on.
5605   if (!VT.isVector())
5606     return SDValue();
5607 
5608   ElementCount NumElts = VT.getVectorElementCount();
5609 
5610   // See if we can fold through bitcasted integer ops.
5611   // TODO: Can we handle undef elements?
5612   if (NumOps == 2 && VT.isFixedLengthVector() && VT.isInteger() &&
5613       Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
5614       Ops[0].getOpcode() == ISD::BITCAST &&
5615       Ops[1].getOpcode() == ISD::BITCAST) {
5616     SDValue N1 = peekThroughBitcasts(Ops[0]);
5617     SDValue N2 = peekThroughBitcasts(Ops[1]);
5618     auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
5619     auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
5620     EVT BVVT = N1.getValueType();
5621     if (BV1 && BV2 && BVVT.isInteger() && BVVT == N2.getValueType()) {
5622       bool IsLE = getDataLayout().isLittleEndian();
5623       unsigned EltBits = VT.getScalarSizeInBits();
5624       SmallVector<APInt> RawBits1, RawBits2;
5625       BitVector UndefElts1, UndefElts2;
5626       if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
5627           BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2) &&
5628           UndefElts1.none() && UndefElts2.none()) {
5629         SmallVector<APInt> RawBits;
5630         for (unsigned I = 0, E = NumElts.getFixedValue(); I != E; ++I) {
5631           Optional<APInt> Fold = FoldValue(Opcode, RawBits1[I], RawBits2[I]);
5632           if (!Fold)
5633             break;
5634           RawBits.push_back(*Fold);
5635         }
5636         if (RawBits.size() == NumElts.getFixedValue()) {
5637           // We have constant folded, but we need to cast this again back to
5638           // the original (possibly legalized) type.
5639           SmallVector<APInt> DstBits;
5640           BitVector DstUndefs;
5641           BuildVectorSDNode::recastRawBits(IsLE, BVVT.getScalarSizeInBits(),
5642                                            DstBits, RawBits, DstUndefs,
5643                                            BitVector(RawBits.size(), false));
5644           EVT BVEltVT = BV1->getOperand(0).getValueType();
5645           unsigned BVEltBits = BVEltVT.getSizeInBits();
5646           SmallVector<SDValue> Ops(DstBits.size(), getUNDEF(BVEltVT));
5647           for (unsigned I = 0, E = DstBits.size(); I != E; ++I) {
5648             if (DstUndefs[I])
5649               continue;
5650             Ops[I] = getConstant(DstBits[I].sext(BVEltBits), DL, BVEltVT);
5651           }
5652           return getBitcast(VT, getBuildVector(BVVT, DL, Ops));
5653         }
5654       }
5655     }
5656   }
5657 
5658   // Fold (mul step_vector(C0), C1) to (step_vector(C0 * C1)).
5659   //      (shl step_vector(C0), C1) -> (step_vector(C0 << C1))
5660   if ((Opcode == ISD::MUL || Opcode == ISD::SHL) &&
5661       Ops[0].getOpcode() == ISD::STEP_VECTOR) {
5662     APInt RHSVal;
5663     if (ISD::isConstantSplatVector(Ops[1].getNode(), RHSVal)) {
5664       APInt NewStep = Opcode == ISD::MUL
5665                           ? Ops[0].getConstantOperandAPInt(0) * RHSVal
5666                           : Ops[0].getConstantOperandAPInt(0) << RHSVal;
5667       return getStepVector(DL, VT, NewStep);
5668     }
5669   }
5670 
5671   auto IsScalarOrSameVectorSize = [NumElts](const SDValue &Op) {
5672     return !Op.getValueType().isVector() ||
5673            Op.getValueType().getVectorElementCount() == NumElts;
5674   };
5675 
5676   auto IsBuildVectorSplatVectorOrUndef = [](const SDValue &Op) {
5677     return Op.isUndef() || Op.getOpcode() == ISD::CONDCODE ||
5678            Op.getOpcode() == ISD::BUILD_VECTOR ||
5679            Op.getOpcode() == ISD::SPLAT_VECTOR;
5680   };
5681 
5682   // All operands must be vector types with the same number of elements as
5683   // the result type and must be either UNDEF or a build/splat vector
5684   // or UNDEF scalars.
5685   if (!llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
5686       !llvm::all_of(Ops, IsScalarOrSameVectorSize))
5687     return SDValue();
5688 
5689   // If we are comparing vectors, then the result needs to be a i1 boolean that
5690   // is then extended back to the legal result type depending on how booleans
5691   // are represented.
5692   EVT SVT = (Opcode == ISD::SETCC ? MVT::i1 : VT.getScalarType());
5693   ISD::NodeType ExtendCode =
5694       (Opcode == ISD::SETCC && SVT != VT.getScalarType())
5695           ? TargetLowering::getExtendForContent(TLI->getBooleanContents(VT))
5696           : ISD::SIGN_EXTEND;
5697 
5698   // Find legal integer scalar type for constant promotion and
5699   // ensure that its scalar size is at least as large as source.
5700   EVT LegalSVT = VT.getScalarType();
5701   if (NewNodesMustHaveLegalTypes && LegalSVT.isInteger()) {
5702     LegalSVT = TLI->getTypeToTransformTo(*getContext(), LegalSVT);
5703     if (LegalSVT.bitsLT(VT.getScalarType()))
5704       return SDValue();
5705   }
5706 
5707   // For scalable vector types we know we're dealing with SPLAT_VECTORs. We
5708   // only have one operand to check. For fixed-length vector types we may have
5709   // a combination of BUILD_VECTOR and SPLAT_VECTOR.
5710   unsigned NumVectorElts = NumElts.isScalable() ? 1 : NumElts.getFixedValue();
5711 
5712   // Constant fold each scalar lane separately.
5713   SmallVector<SDValue, 4> ScalarResults;
5714   for (unsigned I = 0; I != NumVectorElts; I++) {
5715     SmallVector<SDValue, 4> ScalarOps;
5716     for (SDValue Op : Ops) {
5717       EVT InSVT = Op.getValueType().getScalarType();
5718       if (Op.getOpcode() != ISD::BUILD_VECTOR &&
5719           Op.getOpcode() != ISD::SPLAT_VECTOR) {
5720         if (Op.isUndef())
5721           ScalarOps.push_back(getUNDEF(InSVT));
5722         else
5723           ScalarOps.push_back(Op);
5724         continue;
5725       }
5726 
5727       SDValue ScalarOp =
5728           Op.getOperand(Op.getOpcode() == ISD::SPLAT_VECTOR ? 0 : I);
5729       EVT ScalarVT = ScalarOp.getValueType();
5730 
5731       // Build vector (integer) scalar operands may need implicit
5732       // truncation - do this before constant folding.
5733       if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) {
5734         // Don't create illegally-typed nodes unless they're constants or undef
5735         // - if we fail to constant fold we can't guarantee the (dead) nodes
5736         // we're creating will be cleaned up before being visited for
5737         // legalization.
5738         if (NewNodesMustHaveLegalTypes && !ScalarOp.isUndef() &&
5739             !isa<ConstantSDNode>(ScalarOp) &&
5740             TLI->getTypeAction(*getContext(), InSVT) !=
5741                 TargetLowering::TypeLegal)
5742           return SDValue();
5743         ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp);
5744       }
5745 
5746       ScalarOps.push_back(ScalarOp);
5747     }
5748 
5749     // Constant fold the scalar operands.
5750     SDValue ScalarResult = getNode(Opcode, DL, SVT, ScalarOps);
5751 
5752     // Legalize the (integer) scalar constant if necessary.
5753     if (LegalSVT != SVT)
5754       ScalarResult = getNode(ExtendCode, DL, LegalSVT, ScalarResult);
5755 
5756     // Scalar folding only succeeded if the result is a constant or UNDEF.
5757     if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant &&
5758         ScalarResult.getOpcode() != ISD::ConstantFP)
5759       return SDValue();
5760     ScalarResults.push_back(ScalarResult);
5761   }
5762 
5763   SDValue V = NumElts.isScalable() ? getSplatVector(VT, DL, ScalarResults[0])
5764                                    : getBuildVector(VT, DL, ScalarResults);
5765   NewSDValueDbgMsg(V, "New node fold constant vector: ", this);
5766   return V;
5767 }
5768 
5769 SDValue SelectionDAG::foldConstantFPMath(unsigned Opcode, const SDLoc &DL,
5770                                          EVT VT, SDValue N1, SDValue N2) {
5771   // TODO: We don't do any constant folding for strict FP opcodes here, but we
5772   //       should. That will require dealing with a potentially non-default
5773   //       rounding mode, checking the "opStatus" return value from the APFloat
5774   //       math calculations, and possibly other variations.
5775   ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, /*AllowUndefs*/ false);
5776   ConstantFPSDNode *N2CFP = isConstOrConstSplatFP(N2, /*AllowUndefs*/ false);
5777   if (N1CFP && N2CFP) {
5778     APFloat C1 = N1CFP->getValueAPF(); // make copy
5779     const APFloat &C2 = N2CFP->getValueAPF();
5780     switch (Opcode) {
5781     case ISD::FADD:
5782       C1.add(C2, APFloat::rmNearestTiesToEven);
5783       return getConstantFP(C1, DL, VT);
5784     case ISD::FSUB:
5785       C1.subtract(C2, APFloat::rmNearestTiesToEven);
5786       return getConstantFP(C1, DL, VT);
5787     case ISD::FMUL:
5788       C1.multiply(C2, APFloat::rmNearestTiesToEven);
5789       return getConstantFP(C1, DL, VT);
5790     case ISD::FDIV:
5791       C1.divide(C2, APFloat::rmNearestTiesToEven);
5792       return getConstantFP(C1, DL, VT);
5793     case ISD::FREM:
5794       C1.mod(C2);
5795       return getConstantFP(C1, DL, VT);
5796     case ISD::FCOPYSIGN:
5797       C1.copySign(C2);
5798       return getConstantFP(C1, DL, VT);
5799     case ISD::FMINNUM:
5800       return getConstantFP(minnum(C1, C2), DL, VT);
5801     case ISD::FMAXNUM:
5802       return getConstantFP(maxnum(C1, C2), DL, VT);
5803     case ISD::FMINIMUM:
5804       return getConstantFP(minimum(C1, C2), DL, VT);
5805     case ISD::FMAXIMUM:
5806       return getConstantFP(maximum(C1, C2), DL, VT);
5807     default: break;
5808     }
5809   }
5810   if (N1CFP && Opcode == ISD::FP_ROUND) {
5811     APFloat C1 = N1CFP->getValueAPF();    // make copy
5812     bool Unused;
5813     // This can return overflow, underflow, or inexact; we don't care.
5814     // FIXME need to be more flexible about rounding mode.
5815     (void) C1.convert(EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
5816                       &Unused);
5817     return getConstantFP(C1, DL, VT);
5818   }
5819 
5820   switch (Opcode) {
5821   case ISD::FSUB:
5822     // -0.0 - undef --> undef (consistent with "fneg undef")
5823     if (ConstantFPSDNode *N1C = isConstOrConstSplatFP(N1, /*AllowUndefs*/ true))
5824       if (N1C && N1C->getValueAPF().isNegZero() && N2.isUndef())
5825         return getUNDEF(VT);
5826     LLVM_FALLTHROUGH;
5827 
5828   case ISD::FADD:
5829   case ISD::FMUL:
5830   case ISD::FDIV:
5831   case ISD::FREM:
5832     // If both operands are undef, the result is undef. If 1 operand is undef,
5833     // the result is NaN. This should match the behavior of the IR optimizer.
5834     if (N1.isUndef() && N2.isUndef())
5835       return getUNDEF(VT);
5836     if (N1.isUndef() || N2.isUndef())
5837       return getConstantFP(APFloat::getNaN(EVTToAPFloatSemantics(VT)), DL, VT);
5838   }
5839   return SDValue();
5840 }
5841 
5842 SDValue SelectionDAG::getAssertAlign(const SDLoc &DL, SDValue Val, Align A) {
5843   assert(Val.getValueType().isInteger() && "Invalid AssertAlign!");
5844 
5845   // There's no need to assert on a byte-aligned pointer. All pointers are at
5846   // least byte aligned.
5847   if (A == Align(1))
5848     return Val;
5849 
5850   FoldingSetNodeID ID;
5851   AddNodeIDNode(ID, ISD::AssertAlign, getVTList(Val.getValueType()), {Val});
5852   ID.AddInteger(A.value());
5853 
5854   void *IP = nullptr;
5855   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
5856     return SDValue(E, 0);
5857 
5858   auto *N = newSDNode<AssertAlignSDNode>(DL.getIROrder(), DL.getDebugLoc(),
5859                                          Val.getValueType(), A);
5860   createOperands(N, {Val});
5861 
5862   CSEMap.InsertNode(N, IP);
5863   InsertNode(N);
5864 
5865   SDValue V(N, 0);
5866   NewSDValueDbgMsg(V, "Creating new node: ", this);
5867   return V;
5868 }
5869 
5870 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
5871                               SDValue N1, SDValue N2) {
5872   SDNodeFlags Flags;
5873   if (Inserter)
5874     Flags = Inserter->getFlags();
5875   return getNode(Opcode, DL, VT, N1, N2, Flags);
5876 }
5877 
5878 void SelectionDAG::canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1,
5879                                                 SDValue &N2) const {
5880   if (!TLI->isCommutativeBinOp(Opcode))
5881     return;
5882 
5883   // Canonicalize:
5884   //   binop(const, nonconst) -> binop(nonconst, const)
5885   bool IsN1C = isConstantIntBuildVectorOrConstantInt(N1);
5886   bool IsN2C = isConstantIntBuildVectorOrConstantInt(N2);
5887   bool IsN1CFP = isConstantFPBuildVectorOrConstantFP(N1);
5888   bool IsN2CFP = isConstantFPBuildVectorOrConstantFP(N2);
5889   if ((IsN1C && !IsN2C) || (IsN1CFP && !IsN2CFP))
5890     std::swap(N1, N2);
5891 
5892   // Canonicalize:
5893   //  binop(splat(x), step_vector) -> binop(step_vector, splat(x))
5894   else if (N1.getOpcode() == ISD::SPLAT_VECTOR &&
5895            N2.getOpcode() == ISD::STEP_VECTOR)
5896     std::swap(N1, N2);
5897 }
5898 
5899 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
5900                               SDValue N1, SDValue N2, const SDNodeFlags Flags) {
5901   assert(N1.getOpcode() != ISD::DELETED_NODE &&
5902          N2.getOpcode() != ISD::DELETED_NODE &&
5903          "Operand is DELETED_NODE!");
5904 
5905   canonicalizeCommutativeBinop(Opcode, N1, N2);
5906 
5907   auto *N1C = dyn_cast<ConstantSDNode>(N1);
5908   auto *N2C = dyn_cast<ConstantSDNode>(N2);
5909 
5910   // Don't allow undefs in vector splats - we might be returning N2 when folding
5911   // to zero etc.
5912   ConstantSDNode *N2CV =
5913       isConstOrConstSplat(N2, /*AllowUndefs*/ false, /*AllowTruncation*/ true);
5914 
5915   switch (Opcode) {
5916   default: break;
5917   case ISD::TokenFactor:
5918     assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
5919            N2.getValueType() == MVT::Other && "Invalid token factor!");
5920     // Fold trivial token factors.
5921     if (N1.getOpcode() == ISD::EntryToken) return N2;
5922     if (N2.getOpcode() == ISD::EntryToken) return N1;
5923     if (N1 == N2) return N1;
5924     break;
5925   case ISD::BUILD_VECTOR: {
5926     // Attempt to simplify BUILD_VECTOR.
5927     SDValue Ops[] = {N1, N2};
5928     if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
5929       return V;
5930     break;
5931   }
5932   case ISD::CONCAT_VECTORS: {
5933     SDValue Ops[] = {N1, N2};
5934     if (SDValue V = foldCONCAT_VECTORS(DL, VT, Ops, *this))
5935       return V;
5936     break;
5937   }
5938   case ISD::AND:
5939     assert(VT.isInteger() && "This operator does not apply to FP types!");
5940     assert(N1.getValueType() == N2.getValueType() &&
5941            N1.getValueType() == VT && "Binary operator types must match!");
5942     // (X & 0) -> 0.  This commonly occurs when legalizing i64 values, so it's
5943     // worth handling here.
5944     if (N2CV && N2CV->isZero())
5945       return N2;
5946     if (N2CV && N2CV->isAllOnes()) // X & -1 -> X
5947       return N1;
5948     break;
5949   case ISD::OR:
5950   case ISD::XOR:
5951   case ISD::ADD:
5952   case ISD::SUB:
5953     assert(VT.isInteger() && "This operator does not apply to FP types!");
5954     assert(N1.getValueType() == N2.getValueType() &&
5955            N1.getValueType() == VT && "Binary operator types must match!");
5956     // (X ^|+- 0) -> X.  This commonly occurs when legalizing i64 values, so
5957     // it's worth handling here.
5958     if (N2CV && N2CV->isZero())
5959       return N1;
5960     if ((Opcode == ISD::ADD || Opcode == ISD::SUB) && VT.isVector() &&
5961         VT.getVectorElementType() == MVT::i1)
5962       return getNode(ISD::XOR, DL, VT, N1, N2);
5963     break;
5964   case ISD::MUL:
5965     assert(VT.isInteger() && "This operator does not apply to FP types!");
5966     assert(N1.getValueType() == N2.getValueType() &&
5967            N1.getValueType() == VT && "Binary operator types must match!");
5968     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
5969       return getNode(ISD::AND, DL, VT, N1, N2);
5970     if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) {
5971       const APInt &MulImm = N1->getConstantOperandAPInt(0);
5972       const APInt &N2CImm = N2C->getAPIntValue();
5973       return getVScale(DL, VT, MulImm * N2CImm);
5974     }
5975     break;
5976   case ISD::UDIV:
5977   case ISD::UREM:
5978   case ISD::MULHU:
5979   case ISD::MULHS:
5980   case ISD::SDIV:
5981   case ISD::SREM:
5982   case ISD::SADDSAT:
5983   case ISD::SSUBSAT:
5984   case ISD::UADDSAT:
5985   case ISD::USUBSAT:
5986     assert(VT.isInteger() && "This operator does not apply to FP types!");
5987     assert(N1.getValueType() == N2.getValueType() &&
5988            N1.getValueType() == VT && "Binary operator types must match!");
5989     if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
5990       // fold (add_sat x, y) -> (or x, y) for bool types.
5991       if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT)
5992         return getNode(ISD::OR, DL, VT, N1, N2);
5993       // fold (sub_sat x, y) -> (and x, ~y) for bool types.
5994       if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT)
5995         return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT));
5996     }
5997     break;
5998   case ISD::SMIN:
5999   case ISD::UMAX:
6000     assert(VT.isInteger() && "This operator does not apply to FP types!");
6001     assert(N1.getValueType() == N2.getValueType() &&
6002            N1.getValueType() == VT && "Binary operator types must match!");
6003     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
6004       return getNode(ISD::OR, DL, VT, N1, N2);
6005     break;
6006   case ISD::SMAX:
6007   case ISD::UMIN:
6008     assert(VT.isInteger() && "This operator does not apply to FP types!");
6009     assert(N1.getValueType() == N2.getValueType() &&
6010            N1.getValueType() == VT && "Binary operator types must match!");
6011     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
6012       return getNode(ISD::AND, DL, VT, N1, N2);
6013     break;
6014   case ISD::FADD:
6015   case ISD::FSUB:
6016   case ISD::FMUL:
6017   case ISD::FDIV:
6018   case ISD::FREM:
6019     assert(VT.isFloatingPoint() && "This operator only applies to FP types!");
6020     assert(N1.getValueType() == N2.getValueType() &&
6021            N1.getValueType() == VT && "Binary operator types must match!");
6022     if (SDValue V = simplifyFPBinop(Opcode, N1, N2, Flags))
6023       return V;
6024     break;
6025   case ISD::FCOPYSIGN:   // N1 and result must match.  N1/N2 need not match.
6026     assert(N1.getValueType() == VT &&
6027            N1.getValueType().isFloatingPoint() &&
6028            N2.getValueType().isFloatingPoint() &&
6029            "Invalid FCOPYSIGN!");
6030     break;
6031   case ISD::SHL:
6032     if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) {
6033       const APInt &MulImm = N1->getConstantOperandAPInt(0);
6034       const APInt &ShiftImm = N2C->getAPIntValue();
6035       return getVScale(DL, VT, MulImm << ShiftImm);
6036     }
6037     LLVM_FALLTHROUGH;
6038   case ISD::SRA:
6039   case ISD::SRL:
6040     if (SDValue V = simplifyShift(N1, N2))
6041       return V;
6042     LLVM_FALLTHROUGH;
6043   case ISD::ROTL:
6044   case ISD::ROTR:
6045     assert(VT == N1.getValueType() &&
6046            "Shift operators return type must be the same as their first arg");
6047     assert(VT.isInteger() && N2.getValueType().isInteger() &&
6048            "Shifts only work on integers");
6049     assert((!VT.isVector() || VT == N2.getValueType()) &&
6050            "Vector shift amounts must be in the same as their first arg");
6051     // Verify that the shift amount VT is big enough to hold valid shift
6052     // amounts.  This catches things like trying to shift an i1024 value by an
6053     // i8, which is easy to fall into in generic code that uses
6054     // TLI.getShiftAmount().
6055     assert(N2.getValueType().getScalarSizeInBits() >=
6056                Log2_32_Ceil(VT.getScalarSizeInBits()) &&
6057            "Invalid use of small shift amount with oversized value!");
6058 
6059     // Always fold shifts of i1 values so the code generator doesn't need to
6060     // handle them.  Since we know the size of the shift has to be less than the
6061     // size of the value, the shift/rotate count is guaranteed to be zero.
6062     if (VT == MVT::i1)
6063       return N1;
6064     if (N2CV && N2CV->isZero())
6065       return N1;
6066     break;
6067   case ISD::FP_ROUND:
6068     assert(VT.isFloatingPoint() &&
6069            N1.getValueType().isFloatingPoint() &&
6070            VT.bitsLE(N1.getValueType()) &&
6071            N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
6072            "Invalid FP_ROUND!");
6073     if (N1.getValueType() == VT) return N1;  // noop conversion.
6074     break;
6075   case ISD::AssertSext:
6076   case ISD::AssertZext: {
6077     EVT EVT = cast<VTSDNode>(N2)->getVT();
6078     assert(VT == N1.getValueType() && "Not an inreg extend!");
6079     assert(VT.isInteger() && EVT.isInteger() &&
6080            "Cannot *_EXTEND_INREG FP types");
6081     assert(!EVT.isVector() &&
6082            "AssertSExt/AssertZExt type should be the vector element type "
6083            "rather than the vector type!");
6084     assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!");
6085     if (VT.getScalarType() == EVT) return N1; // noop assertion.
6086     break;
6087   }
6088   case ISD::SIGN_EXTEND_INREG: {
6089     EVT EVT = cast<VTSDNode>(N2)->getVT();
6090     assert(VT == N1.getValueType() && "Not an inreg extend!");
6091     assert(VT.isInteger() && EVT.isInteger() &&
6092            "Cannot *_EXTEND_INREG FP types");
6093     assert(EVT.isVector() == VT.isVector() &&
6094            "SIGN_EXTEND_INREG type should be vector iff the operand "
6095            "type is vector!");
6096     assert((!EVT.isVector() ||
6097             EVT.getVectorElementCount() == VT.getVectorElementCount()) &&
6098            "Vector element counts must match in SIGN_EXTEND_INREG");
6099     assert(EVT.bitsLE(VT) && "Not extending!");
6100     if (EVT == VT) return N1;  // Not actually extending
6101 
6102     auto SignExtendInReg = [&](APInt Val, llvm::EVT ConstantVT) {
6103       unsigned FromBits = EVT.getScalarSizeInBits();
6104       Val <<= Val.getBitWidth() - FromBits;
6105       Val.ashrInPlace(Val.getBitWidth() - FromBits);
6106       return getConstant(Val, DL, ConstantVT);
6107     };
6108 
6109     if (N1C) {
6110       const APInt &Val = N1C->getAPIntValue();
6111       return SignExtendInReg(Val, VT);
6112     }
6113 
6114     if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
6115       SmallVector<SDValue, 8> Ops;
6116       llvm::EVT OpVT = N1.getOperand(0).getValueType();
6117       for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6118         SDValue Op = N1.getOperand(i);
6119         if (Op.isUndef()) {
6120           Ops.push_back(getUNDEF(OpVT));
6121           continue;
6122         }
6123         ConstantSDNode *C = cast<ConstantSDNode>(Op);
6124         APInt Val = C->getAPIntValue();
6125         Ops.push_back(SignExtendInReg(Val, OpVT));
6126       }
6127       return getBuildVector(VT, DL, Ops);
6128     }
6129     break;
6130   }
6131   case ISD::FP_TO_SINT_SAT:
6132   case ISD::FP_TO_UINT_SAT: {
6133     assert(VT.isInteger() && cast<VTSDNode>(N2)->getVT().isInteger() &&
6134            N1.getValueType().isFloatingPoint() && "Invalid FP_TO_*INT_SAT");
6135     assert(N1.getValueType().isVector() == VT.isVector() &&
6136            "FP_TO_*INT_SAT type should be vector iff the operand type is "
6137            "vector!");
6138     assert((!VT.isVector() || VT.getVectorElementCount() ==
6139                                   N1.getValueType().getVectorElementCount()) &&
6140            "Vector element counts must match in FP_TO_*INT_SAT");
6141     assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
6142            "Type to saturate to must be a scalar.");
6143     assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) &&
6144            "Not extending!");
6145     break;
6146   }
6147   case ISD::EXTRACT_VECTOR_ELT:
6148     assert(VT.getSizeInBits() >= N1.getValueType().getScalarSizeInBits() &&
6149            "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
6150              element type of the vector.");
6151 
6152     // Extract from an undefined value or using an undefined index is undefined.
6153     if (N1.isUndef() || N2.isUndef())
6154       return getUNDEF(VT);
6155 
6156     // EXTRACT_VECTOR_ELT of out-of-bounds element is an UNDEF for fixed length
6157     // vectors. For scalable vectors we will provide appropriate support for
6158     // dealing with arbitrary indices.
6159     if (N2C && N1.getValueType().isFixedLengthVector() &&
6160         N2C->getAPIntValue().uge(N1.getValueType().getVectorNumElements()))
6161       return getUNDEF(VT);
6162 
6163     // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
6164     // expanding copies of large vectors from registers. This only works for
6165     // fixed length vectors, since we need to know the exact number of
6166     // elements.
6167     if (N2C && N1.getOperand(0).getValueType().isFixedLengthVector() &&
6168         N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) {
6169       unsigned Factor =
6170         N1.getOperand(0).getValueType().getVectorNumElements();
6171       return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
6172                      N1.getOperand(N2C->getZExtValue() / Factor),
6173                      getVectorIdxConstant(N2C->getZExtValue() % Factor, DL));
6174     }
6175 
6176     // EXTRACT_VECTOR_ELT of BUILD_VECTOR or SPLAT_VECTOR is often formed while
6177     // lowering is expanding large vector constants.
6178     if (N2C && (N1.getOpcode() == ISD::BUILD_VECTOR ||
6179                 N1.getOpcode() == ISD::SPLAT_VECTOR)) {
6180       assert((N1.getOpcode() != ISD::BUILD_VECTOR ||
6181               N1.getValueType().isFixedLengthVector()) &&
6182              "BUILD_VECTOR used for scalable vectors");
6183       unsigned Index =
6184           N1.getOpcode() == ISD::BUILD_VECTOR ? N2C->getZExtValue() : 0;
6185       SDValue Elt = N1.getOperand(Index);
6186 
6187       if (VT != Elt.getValueType())
6188         // If the vector element type is not legal, the BUILD_VECTOR operands
6189         // are promoted and implicitly truncated, and the result implicitly
6190         // extended. Make that explicit here.
6191         Elt = getAnyExtOrTrunc(Elt, DL, VT);
6192 
6193       return Elt;
6194     }
6195 
6196     // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
6197     // operations are lowered to scalars.
6198     if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
6199       // If the indices are the same, return the inserted element else
6200       // if the indices are known different, extract the element from
6201       // the original vector.
6202       SDValue N1Op2 = N1.getOperand(2);
6203       ConstantSDNode *N1Op2C = dyn_cast<ConstantSDNode>(N1Op2);
6204 
6205       if (N1Op2C && N2C) {
6206         if (N1Op2C->getZExtValue() == N2C->getZExtValue()) {
6207           if (VT == N1.getOperand(1).getValueType())
6208             return N1.getOperand(1);
6209           if (VT.isFloatingPoint()) {
6210             assert(VT.getSizeInBits() > N1.getOperand(1).getValueType().getSizeInBits());
6211             return getFPExtendOrRound(N1.getOperand(1), DL, VT);
6212           }
6213           return getSExtOrTrunc(N1.getOperand(1), DL, VT);
6214         }
6215         return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
6216       }
6217     }
6218 
6219     // EXTRACT_VECTOR_ELT of v1iX EXTRACT_SUBVECTOR could be formed
6220     // when vector types are scalarized and v1iX is legal.
6221     // vextract (v1iX extract_subvector(vNiX, Idx)) -> vextract(vNiX,Idx).
6222     // Here we are completely ignoring the extract element index (N2),
6223     // which is fine for fixed width vectors, since any index other than 0
6224     // is undefined anyway. However, this cannot be ignored for scalable
6225     // vectors - in theory we could support this, but we don't want to do this
6226     // without a profitability check.
6227     if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
6228         N1.getValueType().isFixedLengthVector() &&
6229         N1.getValueType().getVectorNumElements() == 1) {
6230       return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0),
6231                      N1.getOperand(1));
6232     }
6233     break;
6234   case ISD::EXTRACT_ELEMENT:
6235     assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
6236     assert(!N1.getValueType().isVector() && !VT.isVector() &&
6237            (N1.getValueType().isInteger() == VT.isInteger()) &&
6238            N1.getValueType() != VT &&
6239            "Wrong types for EXTRACT_ELEMENT!");
6240 
6241     // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
6242     // 64-bit integers into 32-bit parts.  Instead of building the extract of
6243     // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
6244     if (N1.getOpcode() == ISD::BUILD_PAIR)
6245       return N1.getOperand(N2C->getZExtValue());
6246 
6247     // EXTRACT_ELEMENT of a constant int is also very common.
6248     if (N1C) {
6249       unsigned ElementSize = VT.getSizeInBits();
6250       unsigned Shift = ElementSize * N2C->getZExtValue();
6251       const APInt &Val = N1C->getAPIntValue();
6252       return getConstant(Val.extractBits(ElementSize, Shift), DL, VT);
6253     }
6254     break;
6255   case ISD::EXTRACT_SUBVECTOR: {
6256     EVT N1VT = N1.getValueType();
6257     assert(VT.isVector() && N1VT.isVector() &&
6258            "Extract subvector VTs must be vectors!");
6259     assert(VT.getVectorElementType() == N1VT.getVectorElementType() &&
6260            "Extract subvector VTs must have the same element type!");
6261     assert((VT.isFixedLengthVector() || N1VT.isScalableVector()) &&
6262            "Cannot extract a scalable vector from a fixed length vector!");
6263     assert((VT.isScalableVector() != N1VT.isScalableVector() ||
6264             VT.getVectorMinNumElements() <= N1VT.getVectorMinNumElements()) &&
6265            "Extract subvector must be from larger vector to smaller vector!");
6266     assert(N2C && "Extract subvector index must be a constant");
6267     assert((VT.isScalableVector() != N1VT.isScalableVector() ||
6268             (VT.getVectorMinNumElements() + N2C->getZExtValue()) <=
6269                 N1VT.getVectorMinNumElements()) &&
6270            "Extract subvector overflow!");
6271     assert(N2C->getAPIntValue().getBitWidth() ==
6272                TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
6273            "Constant index for EXTRACT_SUBVECTOR has an invalid size");
6274 
6275     // Trivial extraction.
6276     if (VT == N1VT)
6277       return N1;
6278 
6279     // EXTRACT_SUBVECTOR of an UNDEF is an UNDEF.
6280     if (N1.isUndef())
6281       return getUNDEF(VT);
6282 
6283     // EXTRACT_SUBVECTOR of CONCAT_VECTOR can be simplified if the pieces of
6284     // the concat have the same type as the extract.
6285     if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 &&
6286         VT == N1.getOperand(0).getValueType()) {
6287       unsigned Factor = VT.getVectorMinNumElements();
6288       return N1.getOperand(N2C->getZExtValue() / Factor);
6289     }
6290 
6291     // EXTRACT_SUBVECTOR of INSERT_SUBVECTOR is often created
6292     // during shuffle legalization.
6293     if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) &&
6294         VT == N1.getOperand(1).getValueType())
6295       return N1.getOperand(1);
6296     break;
6297   }
6298   }
6299 
6300   // Perform trivial constant folding.
6301   if (SDValue SV = FoldConstantArithmetic(Opcode, DL, VT, {N1, N2}))
6302     return SV;
6303 
6304   // Canonicalize an UNDEF to the RHS, even over a constant.
6305   if (N1.isUndef()) {
6306     if (TLI->isCommutativeBinOp(Opcode)) {
6307       std::swap(N1, N2);
6308     } else {
6309       switch (Opcode) {
6310       case ISD::SUB:
6311         return getUNDEF(VT);     // fold op(undef, arg2) -> undef
6312       case ISD::SIGN_EXTEND_INREG:
6313       case ISD::UDIV:
6314       case ISD::SDIV:
6315       case ISD::UREM:
6316       case ISD::SREM:
6317       case ISD::SSUBSAT:
6318       case ISD::USUBSAT:
6319         return getConstant(0, DL, VT);    // fold op(undef, arg2) -> 0
6320       }
6321     }
6322   }
6323 
6324   // Fold a bunch of operators when the RHS is undef.
6325   if (N2.isUndef()) {
6326     switch (Opcode) {
6327     case ISD::XOR:
6328       if (N1.isUndef())
6329         // Handle undef ^ undef -> 0 special case. This is a common
6330         // idiom (misuse).
6331         return getConstant(0, DL, VT);
6332       LLVM_FALLTHROUGH;
6333     case ISD::ADD:
6334     case ISD::SUB:
6335     case ISD::UDIV:
6336     case ISD::SDIV:
6337     case ISD::UREM:
6338     case ISD::SREM:
6339       return getUNDEF(VT);       // fold op(arg1, undef) -> undef
6340     case ISD::MUL:
6341     case ISD::AND:
6342     case ISD::SSUBSAT:
6343     case ISD::USUBSAT:
6344       return getConstant(0, DL, VT);  // fold op(arg1, undef) -> 0
6345     case ISD::OR:
6346     case ISD::SADDSAT:
6347     case ISD::UADDSAT:
6348       return getAllOnesConstant(DL, VT);
6349     }
6350   }
6351 
6352   // Memoize this node if possible.
6353   SDNode *N;
6354   SDVTList VTs = getVTList(VT);
6355   SDValue Ops[] = {N1, N2};
6356   if (VT != MVT::Glue) {
6357     FoldingSetNodeID ID;
6358     AddNodeIDNode(ID, Opcode, VTs, Ops);
6359     void *IP = nullptr;
6360     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
6361       E->intersectFlagsWith(Flags);
6362       return SDValue(E, 0);
6363     }
6364 
6365     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
6366     N->setFlags(Flags);
6367     createOperands(N, Ops);
6368     CSEMap.InsertNode(N, IP);
6369   } else {
6370     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
6371     createOperands(N, Ops);
6372   }
6373 
6374   InsertNode(N);
6375   SDValue V = SDValue(N, 0);
6376   NewSDValueDbgMsg(V, "Creating new node: ", this);
6377   return V;
6378 }
6379 
6380 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
6381                               SDValue N1, SDValue N2, SDValue N3) {
6382   SDNodeFlags Flags;
6383   if (Inserter)
6384     Flags = Inserter->getFlags();
6385   return getNode(Opcode, DL, VT, N1, N2, N3, Flags);
6386 }
6387 
6388 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
6389                               SDValue N1, SDValue N2, SDValue N3,
6390                               const SDNodeFlags Flags) {
6391   assert(N1.getOpcode() != ISD::DELETED_NODE &&
6392          N2.getOpcode() != ISD::DELETED_NODE &&
6393          N3.getOpcode() != ISD::DELETED_NODE &&
6394          "Operand is DELETED_NODE!");
6395   // Perform various simplifications.
6396   switch (Opcode) {
6397   case ISD::FMA: {
6398     assert(VT.isFloatingPoint() && "This operator only applies to FP types!");
6399     assert(N1.getValueType() == VT && N2.getValueType() == VT &&
6400            N3.getValueType() == VT && "FMA types must match!");
6401     ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6402     ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
6403     ConstantFPSDNode *N3CFP = dyn_cast<ConstantFPSDNode>(N3);
6404     if (N1CFP && N2CFP && N3CFP) {
6405       APFloat  V1 = N1CFP->getValueAPF();
6406       const APFloat &V2 = N2CFP->getValueAPF();
6407       const APFloat &V3 = N3CFP->getValueAPF();
6408       V1.fusedMultiplyAdd(V2, V3, APFloat::rmNearestTiesToEven);
6409       return getConstantFP(V1, DL, VT);
6410     }
6411     break;
6412   }
6413   case ISD::BUILD_VECTOR: {
6414     // Attempt to simplify BUILD_VECTOR.
6415     SDValue Ops[] = {N1, N2, N3};
6416     if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
6417       return V;
6418     break;
6419   }
6420   case ISD::CONCAT_VECTORS: {
6421     SDValue Ops[] = {N1, N2, N3};
6422     if (SDValue V = foldCONCAT_VECTORS(DL, VT, Ops, *this))
6423       return V;
6424     break;
6425   }
6426   case ISD::SETCC: {
6427     assert(VT.isInteger() && "SETCC result type must be an integer!");
6428     assert(N1.getValueType() == N2.getValueType() &&
6429            "SETCC operands must have the same type!");
6430     assert(VT.isVector() == N1.getValueType().isVector() &&
6431            "SETCC type should be vector iff the operand type is vector!");
6432     assert((!VT.isVector() || VT.getVectorElementCount() ==
6433                                   N1.getValueType().getVectorElementCount()) &&
6434            "SETCC vector element counts must match!");
6435     // Use FoldSetCC to simplify SETCC's.
6436     if (SDValue V = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL))
6437       return V;
6438     // Vector constant folding.
6439     SDValue Ops[] = {N1, N2, N3};
6440     if (SDValue V = FoldConstantArithmetic(Opcode, DL, VT, Ops)) {
6441       NewSDValueDbgMsg(V, "New node vector constant folding: ", this);
6442       return V;
6443     }
6444     break;
6445   }
6446   case ISD::SELECT:
6447   case ISD::VSELECT:
6448     if (SDValue V = simplifySelect(N1, N2, N3))
6449       return V;
6450     break;
6451   case ISD::VECTOR_SHUFFLE:
6452     llvm_unreachable("should use getVectorShuffle constructor!");
6453   case ISD::VECTOR_SPLICE: {
6454     if (cast<ConstantSDNode>(N3)->isNullValue())
6455       return N1;
6456     break;
6457   }
6458   case ISD::INSERT_VECTOR_ELT: {
6459     ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3);
6460     // INSERT_VECTOR_ELT into out-of-bounds element is an UNDEF, except
6461     // for scalable vectors where we will generate appropriate code to
6462     // deal with out-of-bounds cases correctly.
6463     if (N3C && N1.getValueType().isFixedLengthVector() &&
6464         N3C->getZExtValue() >= N1.getValueType().getVectorNumElements())
6465       return getUNDEF(VT);
6466 
6467     // Undefined index can be assumed out-of-bounds, so that's UNDEF too.
6468     if (N3.isUndef())
6469       return getUNDEF(VT);
6470 
6471     // If the inserted element is an UNDEF, just use the input vector.
6472     if (N2.isUndef())
6473       return N1;
6474 
6475     break;
6476   }
6477   case ISD::INSERT_SUBVECTOR: {
6478     // Inserting undef into undef is still undef.
6479     if (N1.isUndef() && N2.isUndef())
6480       return getUNDEF(VT);
6481 
6482     EVT N2VT = N2.getValueType();
6483     assert(VT == N1.getValueType() &&
6484            "Dest and insert subvector source types must match!");
6485     assert(VT.isVector() && N2VT.isVector() &&
6486            "Insert subvector VTs must be vectors!");
6487     assert((VT.isScalableVector() || N2VT.isFixedLengthVector()) &&
6488            "Cannot insert a scalable vector into a fixed length vector!");
6489     assert((VT.isScalableVector() != N2VT.isScalableVector() ||
6490             VT.getVectorMinNumElements() >= N2VT.getVectorMinNumElements()) &&
6491            "Insert subvector must be from smaller vector to larger vector!");
6492     assert(isa<ConstantSDNode>(N3) &&
6493            "Insert subvector index must be constant");
6494     assert((VT.isScalableVector() != N2VT.isScalableVector() ||
6495             (N2VT.getVectorMinNumElements() +
6496              cast<ConstantSDNode>(N3)->getZExtValue()) <=
6497                 VT.getVectorMinNumElements()) &&
6498            "Insert subvector overflow!");
6499     assert(cast<ConstantSDNode>(N3)->getAPIntValue().getBitWidth() ==
6500                TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
6501            "Constant index for INSERT_SUBVECTOR has an invalid size");
6502 
6503     // Trivial insertion.
6504     if (VT == N2VT)
6505       return N2;
6506 
6507     // If this is an insert of an extracted vector into an undef vector, we
6508     // can just use the input to the extract.
6509     if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
6510         N2.getOperand(1) == N3 && N2.getOperand(0).getValueType() == VT)
6511       return N2.getOperand(0);
6512     break;
6513   }
6514   case ISD::BITCAST:
6515     // Fold bit_convert nodes from a type to themselves.
6516     if (N1.getValueType() == VT)
6517       return N1;
6518     break;
6519   }
6520 
6521   // Memoize node if it doesn't produce a flag.
6522   SDNode *N;
6523   SDVTList VTs = getVTList(VT);
6524   SDValue Ops[] = {N1, N2, N3};
6525   if (VT != MVT::Glue) {
6526     FoldingSetNodeID ID;
6527     AddNodeIDNode(ID, Opcode, VTs, Ops);
6528     void *IP = nullptr;
6529     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
6530       E->intersectFlagsWith(Flags);
6531       return SDValue(E, 0);
6532     }
6533 
6534     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
6535     N->setFlags(Flags);
6536     createOperands(N, Ops);
6537     CSEMap.InsertNode(N, IP);
6538   } else {
6539     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
6540     createOperands(N, Ops);
6541   }
6542 
6543   InsertNode(N);
6544   SDValue V = SDValue(N, 0);
6545   NewSDValueDbgMsg(V, "Creating new node: ", this);
6546   return V;
6547 }
6548 
6549 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
6550                               SDValue N1, SDValue N2, SDValue N3, SDValue N4) {
6551   SDValue Ops[] = { N1, N2, N3, N4 };
6552   return getNode(Opcode, DL, VT, Ops);
6553 }
6554 
6555 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
6556                               SDValue N1, SDValue N2, SDValue N3, SDValue N4,
6557                               SDValue N5) {
6558   SDValue Ops[] = { N1, N2, N3, N4, N5 };
6559   return getNode(Opcode, DL, VT, Ops);
6560 }
6561 
6562 /// getStackArgumentTokenFactor - Compute a TokenFactor to force all
6563 /// the incoming stack arguments to be loaded from the stack.
6564 SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) {
6565   SmallVector<SDValue, 8> ArgChains;
6566 
6567   // Include the original chain at the beginning of the list. When this is
6568   // used by target LowerCall hooks, this helps legalize find the
6569   // CALLSEQ_BEGIN node.
6570   ArgChains.push_back(Chain);
6571 
6572   // Add a chain value for each stack argument.
6573   for (SDNode *U : getEntryNode().getNode()->uses())
6574     if (LoadSDNode *L = dyn_cast<LoadSDNode>(U))
6575       if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
6576         if (FI->getIndex() < 0)
6577           ArgChains.push_back(SDValue(L, 1));
6578 
6579   // Build a tokenfactor for all the chains.
6580   return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
6581 }
6582 
6583 /// getMemsetValue - Vectorized representation of the memset value
6584 /// operand.
6585 static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
6586                               const SDLoc &dl) {
6587   assert(!Value.isUndef());
6588 
6589   unsigned NumBits = VT.getScalarSizeInBits();
6590   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
6591     assert(C->getAPIntValue().getBitWidth() == 8);
6592     APInt Val = APInt::getSplat(NumBits, C->getAPIntValue());
6593     if (VT.isInteger()) {
6594       bool IsOpaque = VT.getSizeInBits() > 64 ||
6595           !DAG.getTargetLoweringInfo().isLegalStoreImmediate(C->getSExtValue());
6596       return DAG.getConstant(Val, dl, VT, false, IsOpaque);
6597     }
6598     return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), dl,
6599                              VT);
6600   }
6601 
6602   assert(Value.getValueType() == MVT::i8 && "memset with non-byte fill value?");
6603   EVT IntVT = VT.getScalarType();
6604   if (!IntVT.isInteger())
6605     IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits());
6606 
6607   Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value);
6608   if (NumBits > 8) {
6609     // Use a multiplication with 0x010101... to extend the input to the
6610     // required length.
6611     APInt Magic = APInt::getSplat(NumBits, APInt(8, 0x01));
6612     Value = DAG.getNode(ISD::MUL, dl, IntVT, Value,
6613                         DAG.getConstant(Magic, dl, IntVT));
6614   }
6615 
6616   if (VT != Value.getValueType() && !VT.isInteger())
6617     Value = DAG.getBitcast(VT.getScalarType(), Value);
6618   if (VT != Value.getValueType())
6619     Value = DAG.getSplatBuildVector(VT, dl, Value);
6620 
6621   return Value;
6622 }
6623 
6624 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
6625 /// used when a memcpy is turned into a memset when the source is a constant
6626 /// string ptr.
6627 static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG,
6628                                   const TargetLowering &TLI,
6629                                   const ConstantDataArraySlice &Slice) {
6630   // Handle vector with all elements zero.
6631   if (Slice.Array == nullptr) {
6632     if (VT.isInteger())
6633       return DAG.getConstant(0, dl, VT);
6634     if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
6635       return DAG.getConstantFP(0.0, dl, VT);
6636     if (VT.isVector()) {
6637       unsigned NumElts = VT.getVectorNumElements();
6638       MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
6639       return DAG.getNode(ISD::BITCAST, dl, VT,
6640                          DAG.getConstant(0, dl,
6641                                          EVT::getVectorVT(*DAG.getContext(),
6642                                                           EltVT, NumElts)));
6643     }
6644     llvm_unreachable("Expected type!");
6645   }
6646 
6647   assert(!VT.isVector() && "Can't handle vector type here!");
6648   unsigned NumVTBits = VT.getSizeInBits();
6649   unsigned NumVTBytes = NumVTBits / 8;
6650   unsigned NumBytes = std::min(NumVTBytes, unsigned(Slice.Length));
6651 
6652   APInt Val(NumVTBits, 0);
6653   if (DAG.getDataLayout().isLittleEndian()) {
6654     for (unsigned i = 0; i != NumBytes; ++i)
6655       Val |= (uint64_t)(unsigned char)Slice[i] << i*8;
6656   } else {
6657     for (unsigned i = 0; i != NumBytes; ++i)
6658       Val |= (uint64_t)(unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
6659   }
6660 
6661   // If the "cost" of materializing the integer immediate is less than the cost
6662   // of a load, then it is cost effective to turn the load into the immediate.
6663   Type *Ty = VT.getTypeForEVT(*DAG.getContext());
6664   if (TLI.shouldConvertConstantLoadToIntImm(Val, Ty))
6665     return DAG.getConstant(Val, dl, VT);
6666   return SDValue();
6667 }
6668 
6669 SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, TypeSize Offset,
6670                                            const SDLoc &DL,
6671                                            const SDNodeFlags Flags) {
6672   EVT VT = Base.getValueType();
6673   SDValue Index;
6674 
6675   if (Offset.isScalable())
6676     Index = getVScale(DL, Base.getValueType(),
6677                       APInt(Base.getValueSizeInBits().getFixedSize(),
6678                             Offset.getKnownMinSize()));
6679   else
6680     Index = getConstant(Offset.getFixedSize(), DL, VT);
6681 
6682   return getMemBasePlusOffset(Base, Index, DL, Flags);
6683 }
6684 
6685 SDValue SelectionDAG::getMemBasePlusOffset(SDValue Ptr, SDValue Offset,
6686                                            const SDLoc &DL,
6687                                            const SDNodeFlags Flags) {
6688   assert(Offset.getValueType().isInteger());
6689   EVT BasePtrVT = Ptr.getValueType();
6690   return getNode(ISD::ADD, DL, BasePtrVT, Ptr, Offset, Flags);
6691 }
6692 
6693 /// Returns true if memcpy source is constant data.
6694 static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice) {
6695   uint64_t SrcDelta = 0;
6696   GlobalAddressSDNode *G = nullptr;
6697   if (Src.getOpcode() == ISD::GlobalAddress)
6698     G = cast<GlobalAddressSDNode>(Src);
6699   else if (Src.getOpcode() == ISD::ADD &&
6700            Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
6701            Src.getOperand(1).getOpcode() == ISD::Constant) {
6702     G = cast<GlobalAddressSDNode>(Src.getOperand(0));
6703     SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
6704   }
6705   if (!G)
6706     return false;
6707 
6708   return getConstantDataArrayInfo(G->getGlobal(), Slice, 8,
6709                                   SrcDelta + G->getOffset());
6710 }
6711 
6712 static bool shouldLowerMemFuncForSize(const MachineFunction &MF,
6713                                       SelectionDAG &DAG) {
6714   // On Darwin, -Os means optimize for size without hurting performance, so
6715   // only really optimize for size when -Oz (MinSize) is used.
6716   if (MF.getTarget().getTargetTriple().isOSDarwin())
6717     return MF.getFunction().hasMinSize();
6718   return DAG.shouldOptForSize();
6719 }
6720 
6721 static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
6722                           SmallVector<SDValue, 32> &OutChains, unsigned From,
6723                           unsigned To, SmallVector<SDValue, 16> &OutLoadChains,
6724                           SmallVector<SDValue, 16> &OutStoreChains) {
6725   assert(OutLoadChains.size() && "Missing loads in memcpy inlining");
6726   assert(OutStoreChains.size() && "Missing stores in memcpy inlining");
6727   SmallVector<SDValue, 16> GluedLoadChains;
6728   for (unsigned i = From; i < To; ++i) {
6729     OutChains.push_back(OutLoadChains[i]);
6730     GluedLoadChains.push_back(OutLoadChains[i]);
6731   }
6732 
6733   // Chain for all loads.
6734   SDValue LoadToken = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6735                                   GluedLoadChains);
6736 
6737   for (unsigned i = From; i < To; ++i) {
6738     StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
6739     SDValue NewStore = DAG.getTruncStore(LoadToken, dl, ST->getValue(),
6740                                   ST->getBasePtr(), ST->getMemoryVT(),
6741                                   ST->getMemOperand());
6742     OutChains.push_back(NewStore);
6743   }
6744 }
6745 
6746 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
6747                                        SDValue Chain, SDValue Dst, SDValue Src,
6748                                        uint64_t Size, Align Alignment,
6749                                        bool isVol, bool AlwaysInline,
6750                                        MachinePointerInfo DstPtrInfo,
6751                                        MachinePointerInfo SrcPtrInfo,
6752                                        const AAMDNodes &AAInfo, AAResults *AA) {
6753   // Turn a memcpy of undef to nop.
6754   // FIXME: We need to honor volatile even is Src is undef.
6755   if (Src.isUndef())
6756     return Chain;
6757 
6758   // Expand memcpy to a series of load and store ops if the size operand falls
6759   // below a certain threshold.
6760   // TODO: In the AlwaysInline case, if the size is big then generate a loop
6761   // rather than maybe a humongous number of loads and stores.
6762   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6763   const DataLayout &DL = DAG.getDataLayout();
6764   LLVMContext &C = *DAG.getContext();
6765   std::vector<EVT> MemOps;
6766   bool DstAlignCanChange = false;
6767   MachineFunction &MF = DAG.getMachineFunction();
6768   MachineFrameInfo &MFI = MF.getFrameInfo();
6769   bool OptSize = shouldLowerMemFuncForSize(MF, DAG);
6770   FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
6771   if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
6772     DstAlignCanChange = true;
6773   MaybeAlign SrcAlign = DAG.InferPtrAlign(Src);
6774   if (!SrcAlign || Alignment > *SrcAlign)
6775     SrcAlign = Alignment;
6776   assert(SrcAlign && "SrcAlign must be set");
6777   ConstantDataArraySlice Slice;
6778   // If marked as volatile, perform a copy even when marked as constant.
6779   bool CopyFromConstant = !isVol && isMemSrcFromConstant(Src, Slice);
6780   bool isZeroConstant = CopyFromConstant && Slice.Array == nullptr;
6781   unsigned Limit = AlwaysInline ? ~0U : TLI.getMaxStoresPerMemcpy(OptSize);
6782   const MemOp Op = isZeroConstant
6783                        ? MemOp::Set(Size, DstAlignCanChange, Alignment,
6784                                     /*IsZeroMemset*/ true, isVol)
6785                        : MemOp::Copy(Size, DstAlignCanChange, Alignment,
6786                                      *SrcAlign, isVol, CopyFromConstant);
6787   if (!TLI.findOptimalMemOpLowering(
6788           MemOps, Limit, Op, DstPtrInfo.getAddrSpace(),
6789           SrcPtrInfo.getAddrSpace(), MF.getFunction().getAttributes()))
6790     return SDValue();
6791 
6792   if (DstAlignCanChange) {
6793     Type *Ty = MemOps[0].getTypeForEVT(C);
6794     Align NewAlign = DL.getABITypeAlign(Ty);
6795 
6796     // Don't promote to an alignment that would require dynamic stack
6797     // realignment.
6798     const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
6799     if (!TRI->hasStackRealignment(MF))
6800       while (NewAlign > Alignment && DL.exceedsNaturalStackAlignment(NewAlign))
6801         NewAlign = NewAlign.previous();
6802 
6803     if (NewAlign > Alignment) {
6804       // Give the stack frame object a larger alignment if needed.
6805       if (MFI.getObjectAlign(FI->getIndex()) < NewAlign)
6806         MFI.setObjectAlignment(FI->getIndex(), NewAlign);
6807       Alignment = NewAlign;
6808     }
6809   }
6810 
6811   // Prepare AAInfo for loads/stores after lowering this memcpy.
6812   AAMDNodes NewAAInfo = AAInfo;
6813   NewAAInfo.TBAA = NewAAInfo.TBAAStruct = nullptr;
6814 
6815   const Value *SrcVal = SrcPtrInfo.V.dyn_cast<const Value *>();
6816   bool isConstant =
6817       AA && SrcVal &&
6818       AA->pointsToConstantMemory(MemoryLocation(SrcVal, Size, AAInfo));
6819 
6820   MachineMemOperand::Flags MMOFlags =
6821       isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
6822   SmallVector<SDValue, 16> OutLoadChains;
6823   SmallVector<SDValue, 16> OutStoreChains;
6824   SmallVector<SDValue, 32> OutChains;
6825   unsigned NumMemOps = MemOps.size();
6826   uint64_t SrcOff = 0, DstOff = 0;
6827   for (unsigned i = 0; i != NumMemOps; ++i) {
6828     EVT VT = MemOps[i];
6829     unsigned VTSize = VT.getSizeInBits() / 8;
6830     SDValue Value, Store;
6831 
6832     if (VTSize > Size) {
6833       // Issuing an unaligned load / store pair  that overlaps with the previous
6834       // pair. Adjust the offset accordingly.
6835       assert(i == NumMemOps-1 && i != 0);
6836       SrcOff -= VTSize - Size;
6837       DstOff -= VTSize - Size;
6838     }
6839 
6840     if (CopyFromConstant &&
6841         (isZeroConstant || (VT.isInteger() && !VT.isVector()))) {
6842       // It's unlikely a store of a vector immediate can be done in a single
6843       // instruction. It would require a load from a constantpool first.
6844       // We only handle zero vectors here.
6845       // FIXME: Handle other cases where store of vector immediate is done in
6846       // a single instruction.
6847       ConstantDataArraySlice SubSlice;
6848       if (SrcOff < Slice.Length) {
6849         SubSlice = Slice;
6850         SubSlice.move(SrcOff);
6851       } else {
6852         // This is an out-of-bounds access and hence UB. Pretend we read zero.
6853         SubSlice.Array = nullptr;
6854         SubSlice.Offset = 0;
6855         SubSlice.Length = VTSize;
6856       }
6857       Value = getMemsetStringVal(VT, dl, DAG, TLI, SubSlice);
6858       if (Value.getNode()) {
6859         Store = DAG.getStore(
6860             Chain, dl, Value,
6861             DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
6862             DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
6863         OutChains.push_back(Store);
6864       }
6865     }
6866 
6867     if (!Store.getNode()) {
6868       // The type might not be legal for the target.  This should only happen
6869       // if the type is smaller than a legal type, as on PPC, so the right
6870       // thing to do is generate a LoadExt/StoreTrunc pair.  These simplify
6871       // to Load/Store if NVT==VT.
6872       // FIXME does the case above also need this?
6873       EVT NVT = TLI.getTypeToTransformTo(C, VT);
6874       assert(NVT.bitsGE(VT));
6875 
6876       bool isDereferenceable =
6877         SrcPtrInfo.getWithOffset(SrcOff).isDereferenceable(VTSize, C, DL);
6878       MachineMemOperand::Flags SrcMMOFlags = MMOFlags;
6879       if (isDereferenceable)
6880         SrcMMOFlags |= MachineMemOperand::MODereferenceable;
6881       if (isConstant)
6882         SrcMMOFlags |= MachineMemOperand::MOInvariant;
6883 
6884       Value = DAG.getExtLoad(
6885           ISD::EXTLOAD, dl, NVT, Chain,
6886           DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
6887           SrcPtrInfo.getWithOffset(SrcOff), VT,
6888           commonAlignment(*SrcAlign, SrcOff), SrcMMOFlags, NewAAInfo);
6889       OutLoadChains.push_back(Value.getValue(1));
6890 
6891       Store = DAG.getTruncStore(
6892           Chain, dl, Value,
6893           DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
6894           DstPtrInfo.getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
6895       OutStoreChains.push_back(Store);
6896     }
6897     SrcOff += VTSize;
6898     DstOff += VTSize;
6899     Size -= VTSize;
6900   }
6901 
6902   unsigned GluedLdStLimit = MaxLdStGlue == 0 ?
6903                                 TLI.getMaxGluedStoresPerMemcpy() : MaxLdStGlue;
6904   unsigned NumLdStInMemcpy = OutStoreChains.size();
6905 
6906   if (NumLdStInMemcpy) {
6907     // It may be that memcpy might be converted to memset if it's memcpy
6908     // of constants. In such a case, we won't have loads and stores, but
6909     // just stores. In the absence of loads, there is nothing to gang up.
6910     if ((GluedLdStLimit <= 1) || !EnableMemCpyDAGOpt) {
6911       // If target does not care, just leave as it.
6912       for (unsigned i = 0; i < NumLdStInMemcpy; ++i) {
6913         OutChains.push_back(OutLoadChains[i]);
6914         OutChains.push_back(OutStoreChains[i]);
6915       }
6916     } else {
6917       // Ld/St less than/equal limit set by target.
6918       if (NumLdStInMemcpy <= GluedLdStLimit) {
6919           chainLoadsAndStoresForMemcpy(DAG, dl, OutChains, 0,
6920                                         NumLdStInMemcpy, OutLoadChains,
6921                                         OutStoreChains);
6922       } else {
6923         unsigned NumberLdChain =  NumLdStInMemcpy / GluedLdStLimit;
6924         unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
6925         unsigned GlueIter = 0;
6926 
6927         for (unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
6928           unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
6929           unsigned IndexTo   = NumLdStInMemcpy - GlueIter;
6930 
6931           chainLoadsAndStoresForMemcpy(DAG, dl, OutChains, IndexFrom, IndexTo,
6932                                        OutLoadChains, OutStoreChains);
6933           GlueIter += GluedLdStLimit;
6934         }
6935 
6936         // Residual ld/st.
6937         if (RemainingLdStInMemcpy) {
6938           chainLoadsAndStoresForMemcpy(DAG, dl, OutChains, 0,
6939                                         RemainingLdStInMemcpy, OutLoadChains,
6940                                         OutStoreChains);
6941         }
6942       }
6943     }
6944   }
6945   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
6946 }
6947 
6948 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
6949                                         SDValue Chain, SDValue Dst, SDValue Src,
6950                                         uint64_t Size, Align Alignment,
6951                                         bool isVol, bool AlwaysInline,
6952                                         MachinePointerInfo DstPtrInfo,
6953                                         MachinePointerInfo SrcPtrInfo,
6954                                         const AAMDNodes &AAInfo) {
6955   // Turn a memmove of undef to nop.
6956   // FIXME: We need to honor volatile even is Src is undef.
6957   if (Src.isUndef())
6958     return Chain;
6959 
6960   // Expand memmove to a series of load and store ops if the size operand falls
6961   // below a certain threshold.
6962   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6963   const DataLayout &DL = DAG.getDataLayout();
6964   LLVMContext &C = *DAG.getContext();
6965   std::vector<EVT> MemOps;
6966   bool DstAlignCanChange = false;
6967   MachineFunction &MF = DAG.getMachineFunction();
6968   MachineFrameInfo &MFI = MF.getFrameInfo();
6969   bool OptSize = shouldLowerMemFuncForSize(MF, DAG);
6970   FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
6971   if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
6972     DstAlignCanChange = true;
6973   MaybeAlign SrcAlign = DAG.InferPtrAlign(Src);
6974   if (!SrcAlign || Alignment > *SrcAlign)
6975     SrcAlign = Alignment;
6976   assert(SrcAlign && "SrcAlign must be set");
6977   unsigned Limit = AlwaysInline ? ~0U : TLI.getMaxStoresPerMemmove(OptSize);
6978   if (!TLI.findOptimalMemOpLowering(
6979           MemOps, Limit,
6980           MemOp::Copy(Size, DstAlignCanChange, Alignment, *SrcAlign,
6981                       /*IsVolatile*/ true),
6982           DstPtrInfo.getAddrSpace(), SrcPtrInfo.getAddrSpace(),
6983           MF.getFunction().getAttributes()))
6984     return SDValue();
6985 
6986   if (DstAlignCanChange) {
6987     Type *Ty = MemOps[0].getTypeForEVT(C);
6988     Align NewAlign = DL.getABITypeAlign(Ty);
6989     if (NewAlign > Alignment) {
6990       // Give the stack frame object a larger alignment if needed.
6991       if (MFI.getObjectAlign(FI->getIndex()) < NewAlign)
6992         MFI.setObjectAlignment(FI->getIndex(), NewAlign);
6993       Alignment = NewAlign;
6994     }
6995   }
6996 
6997   // Prepare AAInfo for loads/stores after lowering this memmove.
6998   AAMDNodes NewAAInfo = AAInfo;
6999   NewAAInfo.TBAA = NewAAInfo.TBAAStruct = nullptr;
7000 
7001   MachineMemOperand::Flags MMOFlags =
7002       isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
7003   uint64_t SrcOff = 0, DstOff = 0;
7004   SmallVector<SDValue, 8> LoadValues;
7005   SmallVector<SDValue, 8> LoadChains;
7006   SmallVector<SDValue, 8> OutChains;
7007   unsigned NumMemOps = MemOps.size();
7008   for (unsigned i = 0; i < NumMemOps; i++) {
7009     EVT VT = MemOps[i];
7010     unsigned VTSize = VT.getSizeInBits() / 8;
7011     SDValue Value;
7012 
7013     bool isDereferenceable =
7014       SrcPtrInfo.getWithOffset(SrcOff).isDereferenceable(VTSize, C, DL);
7015     MachineMemOperand::Flags SrcMMOFlags = MMOFlags;
7016     if (isDereferenceable)
7017       SrcMMOFlags |= MachineMemOperand::MODereferenceable;
7018 
7019     Value = DAG.getLoad(
7020         VT, dl, Chain,
7021         DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
7022         SrcPtrInfo.getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
7023     LoadValues.push_back(Value);
7024     LoadChains.push_back(Value.getValue(1));
7025     SrcOff += VTSize;
7026   }
7027   Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7028   OutChains.clear();
7029   for (unsigned i = 0; i < NumMemOps; i++) {
7030     EVT VT = MemOps[i];
7031     unsigned VTSize = VT.getSizeInBits() / 8;
7032     SDValue Store;
7033 
7034     Store = DAG.getStore(
7035         Chain, dl, LoadValues[i],
7036         DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
7037         DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7038     OutChains.push_back(Store);
7039     DstOff += VTSize;
7040   }
7041 
7042   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
7043 }
7044 
7045 /// Lower the call to 'memset' intrinsic function into a series of store
7046 /// operations.
7047 ///
7048 /// \param DAG Selection DAG where lowered code is placed.
7049 /// \param dl Link to corresponding IR location.
7050 /// \param Chain Control flow dependency.
7051 /// \param Dst Pointer to destination memory location.
7052 /// \param Src Value of byte to write into the memory.
7053 /// \param Size Number of bytes to write.
7054 /// \param Alignment Alignment of the destination in bytes.
7055 /// \param isVol True if destination is volatile.
7056 /// \param AlwaysInline Makes sure no function call is generated.
7057 /// \param DstPtrInfo IR information on the memory pointer.
7058 /// \returns New head in the control flow, if lowering was successful, empty
7059 /// SDValue otherwise.
7060 ///
7061 /// The function tries to replace 'llvm.memset' intrinsic with several store
7062 /// operations and value calculation code. This is usually profitable for small
7063 /// memory size or when the semantic requires inlining.
7064 static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
7065                                SDValue Chain, SDValue Dst, SDValue Src,
7066                                uint64_t Size, Align Alignment, bool isVol,
7067                                bool AlwaysInline, MachinePointerInfo DstPtrInfo,
7068                                const AAMDNodes &AAInfo) {
7069   // Turn a memset of undef to nop.
7070   // FIXME: We need to honor volatile even is Src is undef.
7071   if (Src.isUndef())
7072     return Chain;
7073 
7074   // Expand memset to a series of load/store ops if the size operand
7075   // falls below a certain threshold.
7076   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7077   std::vector<EVT> MemOps;
7078   bool DstAlignCanChange = false;
7079   MachineFunction &MF = DAG.getMachineFunction();
7080   MachineFrameInfo &MFI = MF.getFrameInfo();
7081   bool OptSize = shouldLowerMemFuncForSize(MF, DAG);
7082   FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
7083   if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
7084     DstAlignCanChange = true;
7085   bool IsZeroVal =
7086       isa<ConstantSDNode>(Src) && cast<ConstantSDNode>(Src)->isZero();
7087   unsigned Limit = AlwaysInline ? ~0 : TLI.getMaxStoresPerMemset(OptSize);
7088 
7089   if (!TLI.findOptimalMemOpLowering(
7090           MemOps, Limit,
7091           MemOp::Set(Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
7092           DstPtrInfo.getAddrSpace(), ~0u, MF.getFunction().getAttributes()))
7093     return SDValue();
7094 
7095   if (DstAlignCanChange) {
7096     Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext());
7097     Align NewAlign = DAG.getDataLayout().getABITypeAlign(Ty);
7098     if (NewAlign > Alignment) {
7099       // Give the stack frame object a larger alignment if needed.
7100       if (MFI.getObjectAlign(FI->getIndex()) < NewAlign)
7101         MFI.setObjectAlignment(FI->getIndex(), NewAlign);
7102       Alignment = NewAlign;
7103     }
7104   }
7105 
7106   SmallVector<SDValue, 8> OutChains;
7107   uint64_t DstOff = 0;
7108   unsigned NumMemOps = MemOps.size();
7109 
7110   // Find the largest store and generate the bit pattern for it.
7111   EVT LargestVT = MemOps[0];
7112   for (unsigned i = 1; i < NumMemOps; i++)
7113     if (MemOps[i].bitsGT(LargestVT))
7114       LargestVT = MemOps[i];
7115   SDValue MemSetValue = getMemsetValue(Src, LargestVT, DAG, dl);
7116 
7117   // Prepare AAInfo for loads/stores after lowering this memset.
7118   AAMDNodes NewAAInfo = AAInfo;
7119   NewAAInfo.TBAA = NewAAInfo.TBAAStruct = nullptr;
7120 
7121   for (unsigned i = 0; i < NumMemOps; i++) {
7122     EVT VT = MemOps[i];
7123     unsigned VTSize = VT.getSizeInBits() / 8;
7124     if (VTSize > Size) {
7125       // Issuing an unaligned load / store pair  that overlaps with the previous
7126       // pair. Adjust the offset accordingly.
7127       assert(i == NumMemOps-1 && i != 0);
7128       DstOff -= VTSize - Size;
7129     }
7130 
7131     // If this store is smaller than the largest store see whether we can get
7132     // the smaller value for free with a truncate.
7133     SDValue Value = MemSetValue;
7134     if (VT.bitsLT(LargestVT)) {
7135       if (!LargestVT.isVector() && !VT.isVector() &&
7136           TLI.isTruncateFree(LargestVT, VT))
7137         Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue);
7138       else
7139         Value = getMemsetValue(Src, VT, DAG, dl);
7140     }
7141     assert(Value.getValueType() == VT && "Value with wrong type.");
7142     SDValue Store = DAG.getStore(
7143         Chain, dl, Value,
7144         DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
7145         DstPtrInfo.getWithOffset(DstOff), Alignment,
7146         isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone,
7147         NewAAInfo);
7148     OutChains.push_back(Store);
7149     DstOff += VT.getSizeInBits() / 8;
7150     Size -= VTSize;
7151   }
7152 
7153   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
7154 }
7155 
7156 static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI,
7157                                             unsigned AS) {
7158   // Lowering memcpy / memset / memmove intrinsics to calls is only valid if all
7159   // pointer operands can be losslessly bitcasted to pointers of address space 0
7160   if (AS != 0 && !TLI->getTargetMachine().isNoopAddrSpaceCast(AS, 0)) {
7161     report_fatal_error("cannot lower memory intrinsic in address space " +
7162                        Twine(AS));
7163   }
7164 }
7165 
7166 SDValue SelectionDAG::getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst,
7167                                 SDValue Src, SDValue Size, Align Alignment,
7168                                 bool isVol, bool AlwaysInline, bool isTailCall,
7169                                 MachinePointerInfo DstPtrInfo,
7170                                 MachinePointerInfo SrcPtrInfo,
7171                                 const AAMDNodes &AAInfo, AAResults *AA) {
7172   // Check to see if we should lower the memcpy to loads and stores first.
7173   // For cases within the target-specified limits, this is the best choice.
7174   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
7175   if (ConstantSize) {
7176     // Memcpy with size zero? Just return the original chain.
7177     if (ConstantSize->isZero())
7178       return Chain;
7179 
7180     SDValue Result = getMemcpyLoadsAndStores(
7181         *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
7182         isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
7183     if (Result.getNode())
7184       return Result;
7185   }
7186 
7187   // Then check to see if we should lower the memcpy with target-specific
7188   // code. If the target chooses to do this, this is the next best.
7189   if (TSI) {
7190     SDValue Result = TSI->EmitTargetCodeForMemcpy(
7191         *this, dl, Chain, Dst, Src, Size, Alignment, isVol, AlwaysInline,
7192         DstPtrInfo, SrcPtrInfo);
7193     if (Result.getNode())
7194       return Result;
7195   }
7196 
7197   // If we really need inline code and the target declined to provide it,
7198   // use a (potentially long) sequence of loads and stores.
7199   if (AlwaysInline) {
7200     assert(ConstantSize && "AlwaysInline requires a constant size!");
7201     return getMemcpyLoadsAndStores(
7202         *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
7203         isVol, true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
7204   }
7205 
7206   checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
7207   checkAddrSpaceIsValidForLibcall(TLI, SrcPtrInfo.getAddrSpace());
7208 
7209   // FIXME: If the memcpy is volatile (isVol), lowering it to a plain libc
7210   // memcpy is not guaranteed to be safe. libc memcpys aren't required to
7211   // respect volatile, so they may do things like read or write memory
7212   // beyond the given memory regions. But fixing this isn't easy, and most
7213   // people don't care.
7214 
7215   // Emit a library call.
7216   TargetLowering::ArgListTy Args;
7217   TargetLowering::ArgListEntry Entry;
7218   Entry.Ty = Type::getInt8PtrTy(*getContext());
7219   Entry.Node = Dst; Args.push_back(Entry);
7220   Entry.Node = Src; Args.push_back(Entry);
7221 
7222   Entry.Ty = getDataLayout().getIntPtrType(*getContext());
7223   Entry.Node = Size; Args.push_back(Entry);
7224   // FIXME: pass in SDLoc
7225   TargetLowering::CallLoweringInfo CLI(*this);
7226   CLI.setDebugLoc(dl)
7227       .setChain(Chain)
7228       .setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMCPY),
7229                     Dst.getValueType().getTypeForEVT(*getContext()),
7230                     getExternalSymbol(TLI->getLibcallName(RTLIB::MEMCPY),
7231                                       TLI->getPointerTy(getDataLayout())),
7232                     std::move(Args))
7233       .setDiscardResult()
7234       .setTailCall(isTailCall);
7235 
7236   std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
7237   return CallResult.second;
7238 }
7239 
7240 SDValue SelectionDAG::getAtomicMemcpy(SDValue Chain, const SDLoc &dl,
7241                                       SDValue Dst, SDValue Src, SDValue Size,
7242                                       Type *SizeTy, unsigned ElemSz,
7243                                       bool isTailCall,
7244                                       MachinePointerInfo DstPtrInfo,
7245                                       MachinePointerInfo SrcPtrInfo) {
7246   // Emit a library call.
7247   TargetLowering::ArgListTy Args;
7248   TargetLowering::ArgListEntry Entry;
7249   Entry.Ty = getDataLayout().getIntPtrType(*getContext());
7250   Entry.Node = Dst;
7251   Args.push_back(Entry);
7252 
7253   Entry.Node = Src;
7254   Args.push_back(Entry);
7255 
7256   Entry.Ty = SizeTy;
7257   Entry.Node = Size;
7258   Args.push_back(Entry);
7259 
7260   RTLIB::Libcall LibraryCall =
7261       RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(ElemSz);
7262   if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
7263     report_fatal_error("Unsupported element size");
7264 
7265   TargetLowering::CallLoweringInfo CLI(*this);
7266   CLI.setDebugLoc(dl)
7267       .setChain(Chain)
7268       .setLibCallee(TLI->getLibcallCallingConv(LibraryCall),
7269                     Type::getVoidTy(*getContext()),
7270                     getExternalSymbol(TLI->getLibcallName(LibraryCall),
7271                                       TLI->getPointerTy(getDataLayout())),
7272                     std::move(Args))
7273       .setDiscardResult()
7274       .setTailCall(isTailCall);
7275 
7276   std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
7277   return CallResult.second;
7278 }
7279 
7280 SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
7281                                  SDValue Src, SDValue Size, Align Alignment,
7282                                  bool isVol, bool isTailCall,
7283                                  MachinePointerInfo DstPtrInfo,
7284                                  MachinePointerInfo SrcPtrInfo,
7285                                  const AAMDNodes &AAInfo, AAResults *AA) {
7286   // Check to see if we should lower the memmove to loads and stores first.
7287   // For cases within the target-specified limits, this is the best choice.
7288   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
7289   if (ConstantSize) {
7290     // Memmove with size zero? Just return the original chain.
7291     if (ConstantSize->isZero())
7292       return Chain;
7293 
7294     SDValue Result = getMemmoveLoadsAndStores(
7295         *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
7296         isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo);
7297     if (Result.getNode())
7298       return Result;
7299   }
7300 
7301   // Then check to see if we should lower the memmove with target-specific
7302   // code. If the target chooses to do this, this is the next best.
7303   if (TSI) {
7304     SDValue Result =
7305         TSI->EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size,
7306                                       Alignment, isVol, DstPtrInfo, SrcPtrInfo);
7307     if (Result.getNode())
7308       return Result;
7309   }
7310 
7311   checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
7312   checkAddrSpaceIsValidForLibcall(TLI, SrcPtrInfo.getAddrSpace());
7313 
7314   // FIXME: If the memmove is volatile, lowering it to plain libc memmove may
7315   // not be safe.  See memcpy above for more details.
7316 
7317   // Emit a library call.
7318   TargetLowering::ArgListTy Args;
7319   TargetLowering::ArgListEntry Entry;
7320   Entry.Ty = Type::getInt8PtrTy(*getContext());
7321   Entry.Node = Dst; Args.push_back(Entry);
7322   Entry.Node = Src; Args.push_back(Entry);
7323 
7324   Entry.Ty = getDataLayout().getIntPtrType(*getContext());
7325   Entry.Node = Size; Args.push_back(Entry);
7326   // FIXME:  pass in SDLoc
7327   TargetLowering::CallLoweringInfo CLI(*this);
7328   CLI.setDebugLoc(dl)
7329       .setChain(Chain)
7330       .setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMMOVE),
7331                     Dst.getValueType().getTypeForEVT(*getContext()),
7332                     getExternalSymbol(TLI->getLibcallName(RTLIB::MEMMOVE),
7333                                       TLI->getPointerTy(getDataLayout())),
7334                     std::move(Args))
7335       .setDiscardResult()
7336       .setTailCall(isTailCall);
7337 
7338   std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
7339   return CallResult.second;
7340 }
7341 
7342 SDValue SelectionDAG::getAtomicMemmove(SDValue Chain, const SDLoc &dl,
7343                                        SDValue Dst, SDValue Src, SDValue Size,
7344                                        Type *SizeTy, unsigned ElemSz,
7345                                        bool isTailCall,
7346                                        MachinePointerInfo DstPtrInfo,
7347                                        MachinePointerInfo SrcPtrInfo) {
7348   // Emit a library call.
7349   TargetLowering::ArgListTy Args;
7350   TargetLowering::ArgListEntry Entry;
7351   Entry.Ty = getDataLayout().getIntPtrType(*getContext());
7352   Entry.Node = Dst;
7353   Args.push_back(Entry);
7354 
7355   Entry.Node = Src;
7356   Args.push_back(Entry);
7357 
7358   Entry.Ty = SizeTy;
7359   Entry.Node = Size;
7360   Args.push_back(Entry);
7361 
7362   RTLIB::Libcall LibraryCall =
7363       RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(ElemSz);
7364   if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
7365     report_fatal_error("Unsupported element size");
7366 
7367   TargetLowering::CallLoweringInfo CLI(*this);
7368   CLI.setDebugLoc(dl)
7369       .setChain(Chain)
7370       .setLibCallee(TLI->getLibcallCallingConv(LibraryCall),
7371                     Type::getVoidTy(*getContext()),
7372                     getExternalSymbol(TLI->getLibcallName(LibraryCall),
7373                                       TLI->getPointerTy(getDataLayout())),
7374                     std::move(Args))
7375       .setDiscardResult()
7376       .setTailCall(isTailCall);
7377 
7378   std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
7379   return CallResult.second;
7380 }
7381 
7382 SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
7383                                 SDValue Src, SDValue Size, Align Alignment,
7384                                 bool isVol, bool AlwaysInline, bool isTailCall,
7385                                 MachinePointerInfo DstPtrInfo,
7386                                 const AAMDNodes &AAInfo) {
7387   // Check to see if we should lower the memset to stores first.
7388   // For cases within the target-specified limits, this is the best choice.
7389   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
7390   if (ConstantSize) {
7391     // Memset with size zero? Just return the original chain.
7392     if (ConstantSize->isZero())
7393       return Chain;
7394 
7395     SDValue Result = getMemsetStores(*this, dl, Chain, Dst, Src,
7396                                      ConstantSize->getZExtValue(), Alignment,
7397                                      isVol, false, DstPtrInfo, AAInfo);
7398 
7399     if (Result.getNode())
7400       return Result;
7401   }
7402 
7403   // Then check to see if we should lower the memset with target-specific
7404   // code. If the target chooses to do this, this is the next best.
7405   if (TSI) {
7406     SDValue Result = TSI->EmitTargetCodeForMemset(
7407         *this, dl, Chain, Dst, Src, Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
7408     if (Result.getNode())
7409       return Result;
7410   }
7411 
7412   // If we really need inline code and the target declined to provide it,
7413   // use a (potentially long) sequence of loads and stores.
7414   if (AlwaysInline) {
7415     assert(ConstantSize && "AlwaysInline requires a constant size!");
7416     SDValue Result = getMemsetStores(*this, dl, Chain, Dst, Src,
7417                                      ConstantSize->getZExtValue(), Alignment,
7418                                      isVol, true, DstPtrInfo, AAInfo);
7419     assert(Result &&
7420            "getMemsetStores must return a valid sequence when AlwaysInline");
7421     return Result;
7422   }
7423 
7424   checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
7425 
7426   // Emit a library call.
7427   auto &Ctx = *getContext();
7428   const auto& DL = getDataLayout();
7429 
7430   TargetLowering::CallLoweringInfo CLI(*this);
7431   // FIXME: pass in SDLoc
7432   CLI.setDebugLoc(dl).setChain(Chain);
7433 
7434   ConstantSDNode *ConstantSrc = dyn_cast<ConstantSDNode>(Src);
7435   const bool SrcIsZero = ConstantSrc && ConstantSrc->isZero();
7436   const char *BzeroName = getTargetLoweringInfo().getLibcallName(RTLIB::BZERO);
7437 
7438   // Helper function to create an Entry from Node and Type.
7439   const auto CreateEntry = [](SDValue Node, Type *Ty) {
7440     TargetLowering::ArgListEntry Entry;
7441     Entry.Node = Node;
7442     Entry.Ty = Ty;
7443     return Entry;
7444   };
7445 
7446   // If zeroing out and bzero is present, use it.
7447   if (SrcIsZero && BzeroName) {
7448     TargetLowering::ArgListTy Args;
7449     Args.push_back(CreateEntry(Dst, Type::getInt8PtrTy(Ctx)));
7450     Args.push_back(CreateEntry(Size, DL.getIntPtrType(Ctx)));
7451     CLI.setLibCallee(
7452         TLI->getLibcallCallingConv(RTLIB::BZERO), Type::getVoidTy(Ctx),
7453         getExternalSymbol(BzeroName, TLI->getPointerTy(DL)), std::move(Args));
7454   } else {
7455     TargetLowering::ArgListTy Args;
7456     Args.push_back(CreateEntry(Dst, Type::getInt8PtrTy(Ctx)));
7457     Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
7458     Args.push_back(CreateEntry(Size, DL.getIntPtrType(Ctx)));
7459     CLI.setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMSET),
7460                      Dst.getValueType().getTypeForEVT(Ctx),
7461                      getExternalSymbol(TLI->getLibcallName(RTLIB::MEMSET),
7462                                        TLI->getPointerTy(DL)),
7463                      std::move(Args));
7464   }
7465 
7466   CLI.setDiscardResult().setTailCall(isTailCall);
7467 
7468   std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
7469   return CallResult.second;
7470 }
7471 
7472 SDValue SelectionDAG::getAtomicMemset(SDValue Chain, const SDLoc &dl,
7473                                       SDValue Dst, SDValue Value, SDValue Size,
7474                                       Type *SizeTy, unsigned ElemSz,
7475                                       bool isTailCall,
7476                                       MachinePointerInfo DstPtrInfo) {
7477   // Emit a library call.
7478   TargetLowering::ArgListTy Args;
7479   TargetLowering::ArgListEntry Entry;
7480   Entry.Ty = getDataLayout().getIntPtrType(*getContext());
7481   Entry.Node = Dst;
7482   Args.push_back(Entry);
7483 
7484   Entry.Ty = Type::getInt8Ty(*getContext());
7485   Entry.Node = Value;
7486   Args.push_back(Entry);
7487 
7488   Entry.Ty = SizeTy;
7489   Entry.Node = Size;
7490   Args.push_back(Entry);
7491 
7492   RTLIB::Libcall LibraryCall =
7493       RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(ElemSz);
7494   if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
7495     report_fatal_error("Unsupported element size");
7496 
7497   TargetLowering::CallLoweringInfo CLI(*this);
7498   CLI.setDebugLoc(dl)
7499       .setChain(Chain)
7500       .setLibCallee(TLI->getLibcallCallingConv(LibraryCall),
7501                     Type::getVoidTy(*getContext()),
7502                     getExternalSymbol(TLI->getLibcallName(LibraryCall),
7503                                       TLI->getPointerTy(getDataLayout())),
7504                     std::move(Args))
7505       .setDiscardResult()
7506       .setTailCall(isTailCall);
7507 
7508   std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
7509   return CallResult.second;
7510 }
7511 
7512 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7513                                 SDVTList VTList, ArrayRef<SDValue> Ops,
7514                                 MachineMemOperand *MMO) {
7515   FoldingSetNodeID ID;
7516   ID.AddInteger(MemVT.getRawBits());
7517   AddNodeIDNode(ID, Opcode, VTList, Ops);
7518   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
7519   ID.AddInteger(MMO->getFlags());
7520   void* IP = nullptr;
7521   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
7522     cast<AtomicSDNode>(E)->refineAlignment(MMO);
7523     return SDValue(E, 0);
7524   }
7525 
7526   auto *N = newSDNode<AtomicSDNode>(Opcode, dl.getIROrder(), dl.getDebugLoc(),
7527                                     VTList, MemVT, MMO);
7528   createOperands(N, Ops);
7529 
7530   CSEMap.InsertNode(N, IP);
7531   InsertNode(N);
7532   return SDValue(N, 0);
7533 }
7534 
7535 SDValue SelectionDAG::getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl,
7536                                        EVT MemVT, SDVTList VTs, SDValue Chain,
7537                                        SDValue Ptr, SDValue Cmp, SDValue Swp,
7538                                        MachineMemOperand *MMO) {
7539   assert(Opcode == ISD::ATOMIC_CMP_SWAP ||
7540          Opcode == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
7541   assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
7542 
7543   SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
7544   return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7545 }
7546 
7547 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7548                                 SDValue Chain, SDValue Ptr, SDValue Val,
7549                                 MachineMemOperand *MMO) {
7550   assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
7551           Opcode == ISD::ATOMIC_LOAD_SUB ||
7552           Opcode == ISD::ATOMIC_LOAD_AND ||
7553           Opcode == ISD::ATOMIC_LOAD_CLR ||
7554           Opcode == ISD::ATOMIC_LOAD_OR ||
7555           Opcode == ISD::ATOMIC_LOAD_XOR ||
7556           Opcode == ISD::ATOMIC_LOAD_NAND ||
7557           Opcode == ISD::ATOMIC_LOAD_MIN ||
7558           Opcode == ISD::ATOMIC_LOAD_MAX ||
7559           Opcode == ISD::ATOMIC_LOAD_UMIN ||
7560           Opcode == ISD::ATOMIC_LOAD_UMAX ||
7561           Opcode == ISD::ATOMIC_LOAD_FADD ||
7562           Opcode == ISD::ATOMIC_LOAD_FSUB ||
7563           Opcode == ISD::ATOMIC_LOAD_FMAX ||
7564           Opcode == ISD::ATOMIC_LOAD_FMIN ||
7565           Opcode == ISD::ATOMIC_SWAP ||
7566           Opcode == ISD::ATOMIC_STORE) &&
7567          "Invalid Atomic Op");
7568 
7569   EVT VT = Val.getValueType();
7570 
7571   SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
7572                                                getVTList(VT, MVT::Other);
7573   SDValue Ops[] = {Chain, Ptr, Val};
7574   return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7575 }
7576 
7577 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
7578                                 EVT VT, SDValue Chain, SDValue Ptr,
7579                                 MachineMemOperand *MMO) {
7580   assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
7581 
7582   SDVTList VTs = getVTList(VT, MVT::Other);
7583   SDValue Ops[] = {Chain, Ptr};
7584   return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
7585 }
7586 
7587 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
7588 SDValue SelectionDAG::getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl) {
7589   if (Ops.size() == 1)
7590     return Ops[0];
7591 
7592   SmallVector<EVT, 4> VTs;
7593   VTs.reserve(Ops.size());
7594   for (const SDValue &Op : Ops)
7595     VTs.push_back(Op.getValueType());
7596   return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops);
7597 }
7598 
7599 SDValue SelectionDAG::getMemIntrinsicNode(
7600     unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
7601     EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
7602     MachineMemOperand::Flags Flags, uint64_t Size, const AAMDNodes &AAInfo) {
7603   if (!Size && MemVT.isScalableVector())
7604     Size = MemoryLocation::UnknownSize;
7605   else if (!Size)
7606     Size = MemVT.getStoreSize();
7607 
7608   MachineFunction &MF = getMachineFunction();
7609   MachineMemOperand *MMO =
7610       MF.getMachineMemOperand(PtrInfo, Flags, Size, Alignment, AAInfo);
7611 
7612   return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, MMO);
7613 }
7614 
7615 SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
7616                                           SDVTList VTList,
7617                                           ArrayRef<SDValue> Ops, EVT MemVT,
7618                                           MachineMemOperand *MMO) {
7619   assert((Opcode == ISD::INTRINSIC_VOID ||
7620           Opcode == ISD::INTRINSIC_W_CHAIN ||
7621           Opcode == ISD::PREFETCH ||
7622           ((int)Opcode <= std::numeric_limits<int>::max() &&
7623            (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
7624          "Opcode is not a memory-accessing opcode!");
7625 
7626   // Memoize the node unless it returns a flag.
7627   MemIntrinsicSDNode *N;
7628   if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
7629     FoldingSetNodeID ID;
7630     AddNodeIDNode(ID, Opcode, VTList, Ops);
7631     ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
7632         Opcode, dl.getIROrder(), VTList, MemVT, MMO));
7633     ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
7634     ID.AddInteger(MMO->getFlags());
7635     void *IP = nullptr;
7636     if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
7637       cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
7638       return SDValue(E, 0);
7639     }
7640 
7641     N = newSDNode<MemIntrinsicSDNode>(Opcode, dl.getIROrder(), dl.getDebugLoc(),
7642                                       VTList, MemVT, MMO);
7643     createOperands(N, Ops);
7644 
7645   CSEMap.InsertNode(N, IP);
7646   } else {
7647     N = newSDNode<MemIntrinsicSDNode>(Opcode, dl.getIROrder(), dl.getDebugLoc(),
7648                                       VTList, MemVT, MMO);
7649     createOperands(N, Ops);
7650   }
7651   InsertNode(N);
7652   SDValue V(N, 0);
7653   NewSDValueDbgMsg(V, "Creating new node: ", this);
7654   return V;
7655 }
7656 
7657 SDValue SelectionDAG::getLifetimeNode(bool IsStart, const SDLoc &dl,
7658                                       SDValue Chain, int FrameIndex,
7659                                       int64_t Size, int64_t Offset) {
7660   const unsigned Opcode = IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END;
7661   const auto VTs = getVTList(MVT::Other);
7662   SDValue Ops[2] = {
7663       Chain,
7664       getFrameIndex(FrameIndex,
7665                     getTargetLoweringInfo().getFrameIndexTy(getDataLayout()),
7666                     true)};
7667 
7668   FoldingSetNodeID ID;
7669   AddNodeIDNode(ID, Opcode, VTs, Ops);
7670   ID.AddInteger(FrameIndex);
7671   ID.AddInteger(Size);
7672   ID.AddInteger(Offset);
7673   void *IP = nullptr;
7674   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
7675     return SDValue(E, 0);
7676 
7677   LifetimeSDNode *N = newSDNode<LifetimeSDNode>(
7678       Opcode, dl.getIROrder(), dl.getDebugLoc(), VTs, Size, Offset);
7679   createOperands(N, Ops);
7680   CSEMap.InsertNode(N, IP);
7681   InsertNode(N);
7682   SDValue V(N, 0);
7683   NewSDValueDbgMsg(V, "Creating new node: ", this);
7684   return V;
7685 }
7686 
7687 SDValue SelectionDAG::getPseudoProbeNode(const SDLoc &Dl, SDValue Chain,
7688                                          uint64_t Guid, uint64_t Index,
7689                                          uint32_t Attr) {
7690   const unsigned Opcode = ISD::PSEUDO_PROBE;
7691   const auto VTs = getVTList(MVT::Other);
7692   SDValue Ops[] = {Chain};
7693   FoldingSetNodeID ID;
7694   AddNodeIDNode(ID, Opcode, VTs, Ops);
7695   ID.AddInteger(Guid);
7696   ID.AddInteger(Index);
7697   void *IP = nullptr;
7698   if (SDNode *E = FindNodeOrInsertPos(ID, Dl, IP))
7699     return SDValue(E, 0);
7700 
7701   auto *N = newSDNode<PseudoProbeSDNode>(
7702       Opcode, Dl.getIROrder(), Dl.getDebugLoc(), VTs, Guid, Index, Attr);
7703   createOperands(N, Ops);
7704   CSEMap.InsertNode(N, IP);
7705   InsertNode(N);
7706   SDValue V(N, 0);
7707   NewSDValueDbgMsg(V, "Creating new node: ", this);
7708   return V;
7709 }
7710 
7711 /// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
7712 /// MachinePointerInfo record from it.  This is particularly useful because the
7713 /// code generator has many cases where it doesn't bother passing in a
7714 /// MachinePointerInfo to getLoad or getStore when it has "FI+Cst".
7715 static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info,
7716                                            SelectionDAG &DAG, SDValue Ptr,
7717                                            int64_t Offset = 0) {
7718   // If this is FI+Offset, we can model it.
7719   if (const FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr))
7720     return MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
7721                                              FI->getIndex(), Offset);
7722 
7723   // If this is (FI+Offset1)+Offset2, we can model it.
7724   if (Ptr.getOpcode() != ISD::ADD ||
7725       !isa<ConstantSDNode>(Ptr.getOperand(1)) ||
7726       !isa<FrameIndexSDNode>(Ptr.getOperand(0)))
7727     return Info;
7728 
7729   int FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
7730   return MachinePointerInfo::getFixedStack(
7731       DAG.getMachineFunction(), FI,
7732       Offset + cast<ConstantSDNode>(Ptr.getOperand(1))->getSExtValue());
7733 }
7734 
7735 /// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
7736 /// MachinePointerInfo record from it.  This is particularly useful because the
7737 /// code generator has many cases where it doesn't bother passing in a
7738 /// MachinePointerInfo to getLoad or getStore when it has "FI+Cst".
7739 static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info,
7740                                            SelectionDAG &DAG, SDValue Ptr,
7741                                            SDValue OffsetOp) {
7742   // If the 'Offset' value isn't a constant, we can't handle this.
7743   if (ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
7744     return InferPointerInfo(Info, DAG, Ptr, OffsetNode->getSExtValue());
7745   if (OffsetOp.isUndef())
7746     return InferPointerInfo(Info, DAG, Ptr);
7747   return Info;
7748 }
7749 
7750 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
7751                               EVT VT, const SDLoc &dl, SDValue Chain,
7752                               SDValue Ptr, SDValue Offset,
7753                               MachinePointerInfo PtrInfo, EVT MemVT,
7754                               Align Alignment,
7755                               MachineMemOperand::Flags MMOFlags,
7756                               const AAMDNodes &AAInfo, const MDNode *Ranges) {
7757   assert(Chain.getValueType() == MVT::Other &&
7758         "Invalid chain type");
7759 
7760   MMOFlags |= MachineMemOperand::MOLoad;
7761   assert((MMOFlags & MachineMemOperand::MOStore) == 0);
7762   // If we don't have a PtrInfo, infer the trivial frame index case to simplify
7763   // clients.
7764   if (PtrInfo.V.isNull())
7765     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
7766 
7767   uint64_t Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
7768   MachineFunction &MF = getMachineFunction();
7769   MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
7770                                                    Alignment, AAInfo, Ranges);
7771   return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
7772 }
7773 
7774 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
7775                               EVT VT, const SDLoc &dl, SDValue Chain,
7776                               SDValue Ptr, SDValue Offset, EVT MemVT,
7777                               MachineMemOperand *MMO) {
7778   if (VT == MemVT) {
7779     ExtType = ISD::NON_EXTLOAD;
7780   } else if (ExtType == ISD::NON_EXTLOAD) {
7781     assert(VT == MemVT && "Non-extending load from different memory type!");
7782   } else {
7783     // Extending load.
7784     assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) &&
7785            "Should only be an extending load, not truncating!");
7786     assert(VT.isInteger() == MemVT.isInteger() &&
7787            "Cannot convert from FP to Int or Int -> FP!");
7788     assert(VT.isVector() == MemVT.isVector() &&
7789            "Cannot use an ext load to convert to or from a vector!");
7790     assert((!VT.isVector() ||
7791             VT.getVectorElementCount() == MemVT.getVectorElementCount()) &&
7792            "Cannot use an ext load to change the number of vector elements!");
7793   }
7794 
7795   bool Indexed = AM != ISD::UNINDEXED;
7796   assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
7797 
7798   SDVTList VTs = Indexed ?
7799     getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
7800   SDValue Ops[] = { Chain, Ptr, Offset };
7801   FoldingSetNodeID ID;
7802   AddNodeIDNode(ID, ISD::LOAD, VTs, Ops);
7803   ID.AddInteger(MemVT.getRawBits());
7804   ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
7805       dl.getIROrder(), VTs, AM, ExtType, MemVT, MMO));
7806   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
7807   ID.AddInteger(MMO->getFlags());
7808   void *IP = nullptr;
7809   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
7810     cast<LoadSDNode>(E)->refineAlignment(MMO);
7811     return SDValue(E, 0);
7812   }
7813   auto *N = newSDNode<LoadSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
7814                                   ExtType, MemVT, MMO);
7815   createOperands(N, Ops);
7816 
7817   CSEMap.InsertNode(N, IP);
7818   InsertNode(N);
7819   SDValue V(N, 0);
7820   NewSDValueDbgMsg(V, "Creating new node: ", this);
7821   return V;
7822 }
7823 
7824 SDValue SelectionDAG::getLoad(EVT VT, const SDLoc &dl, SDValue Chain,
7825                               SDValue Ptr, MachinePointerInfo PtrInfo,
7826                               MaybeAlign Alignment,
7827                               MachineMemOperand::Flags MMOFlags,
7828                               const AAMDNodes &AAInfo, const MDNode *Ranges) {
7829   SDValue Undef = getUNDEF(Ptr.getValueType());
7830   return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
7831                  PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
7832 }
7833 
7834 SDValue SelectionDAG::getLoad(EVT VT, const SDLoc &dl, SDValue Chain,
7835                               SDValue Ptr, MachineMemOperand *MMO) {
7836   SDValue Undef = getUNDEF(Ptr.getValueType());
7837   return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
7838                  VT, MMO);
7839 }
7840 
7841 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl,
7842                                  EVT VT, SDValue Chain, SDValue Ptr,
7843                                  MachinePointerInfo PtrInfo, EVT MemVT,
7844                                  MaybeAlign Alignment,
7845                                  MachineMemOperand::Flags MMOFlags,
7846                                  const AAMDNodes &AAInfo) {
7847   SDValue Undef = getUNDEF(Ptr.getValueType());
7848   return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo,
7849                  MemVT, Alignment, MMOFlags, AAInfo);
7850 }
7851 
7852 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl,
7853                                  EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT,
7854                                  MachineMemOperand *MMO) {
7855   SDValue Undef = getUNDEF(Ptr.getValueType());
7856   return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
7857                  MemVT, MMO);
7858 }
7859 
7860 SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, const SDLoc &dl,
7861                                      SDValue Base, SDValue Offset,
7862                                      ISD::MemIndexedMode AM) {
7863   LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
7864   assert(LD->getOffset().isUndef() && "Load is already a indexed load!");
7865   // Don't propagate the invariant or dereferenceable flags.
7866   auto MMOFlags =
7867       LD->getMemOperand()->getFlags() &
7868       ~(MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
7869   return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
7870                  LD->getChain(), Base, Offset, LD->getPointerInfo(),
7871                  LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
7872 }
7873 
7874 SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
7875                                SDValue Ptr, MachinePointerInfo PtrInfo,
7876                                Align Alignment,
7877                                MachineMemOperand::Flags MMOFlags,
7878                                const AAMDNodes &AAInfo) {
7879   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
7880 
7881   MMOFlags |= MachineMemOperand::MOStore;
7882   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
7883 
7884   if (PtrInfo.V.isNull())
7885     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
7886 
7887   MachineFunction &MF = getMachineFunction();
7888   uint64_t Size =
7889       MemoryLocation::getSizeOrUnknown(Val.getValueType().getStoreSize());
7890   MachineMemOperand *MMO =
7891       MF.getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
7892   return getStore(Chain, dl, Val, Ptr, MMO);
7893 }
7894 
7895 SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
7896                                SDValue Ptr, MachineMemOperand *MMO) {
7897   assert(Chain.getValueType() == MVT::Other &&
7898         "Invalid chain type");
7899   EVT VT = Val.getValueType();
7900   SDVTList VTs = getVTList(MVT::Other);
7901   SDValue Undef = getUNDEF(Ptr.getValueType());
7902   SDValue Ops[] = { Chain, Val, Ptr, Undef };
7903   FoldingSetNodeID ID;
7904   AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
7905   ID.AddInteger(VT.getRawBits());
7906   ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
7907       dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO));
7908   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
7909   ID.AddInteger(MMO->getFlags());
7910   void *IP = nullptr;
7911   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
7912     cast<StoreSDNode>(E)->refineAlignment(MMO);
7913     return SDValue(E, 0);
7914   }
7915   auto *N = newSDNode<StoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
7916                                    ISD::UNINDEXED, false, VT, MMO);
7917   createOperands(N, Ops);
7918 
7919   CSEMap.InsertNode(N, IP);
7920   InsertNode(N);
7921   SDValue V(N, 0);
7922   NewSDValueDbgMsg(V, "Creating new node: ", this);
7923   return V;
7924 }
7925 
7926 SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
7927                                     SDValue Ptr, MachinePointerInfo PtrInfo,
7928                                     EVT SVT, Align Alignment,
7929                                     MachineMemOperand::Flags MMOFlags,
7930                                     const AAMDNodes &AAInfo) {
7931   assert(Chain.getValueType() == MVT::Other &&
7932         "Invalid chain type");
7933 
7934   MMOFlags |= MachineMemOperand::MOStore;
7935   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
7936 
7937   if (PtrInfo.V.isNull())
7938     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
7939 
7940   MachineFunction &MF = getMachineFunction();
7941   MachineMemOperand *MMO = MF.getMachineMemOperand(
7942       PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
7943       Alignment, AAInfo);
7944   return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
7945 }
7946 
7947 SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
7948                                     SDValue Ptr, EVT SVT,
7949                                     MachineMemOperand *MMO) {
7950   EVT VT = Val.getValueType();
7951 
7952   assert(Chain.getValueType() == MVT::Other &&
7953         "Invalid chain type");
7954   if (VT == SVT)
7955     return getStore(Chain, dl, Val, Ptr, MMO);
7956 
7957   assert(SVT.getScalarType().bitsLT(VT.getScalarType()) &&
7958          "Should only be a truncating store, not extending!");
7959   assert(VT.isInteger() == SVT.isInteger() &&
7960          "Can't do FP-INT conversion!");
7961   assert(VT.isVector() == SVT.isVector() &&
7962          "Cannot use trunc store to convert to or from a vector!");
7963   assert((!VT.isVector() ||
7964           VT.getVectorElementCount() == SVT.getVectorElementCount()) &&
7965          "Cannot use trunc store to change the number of vector elements!");
7966 
7967   SDVTList VTs = getVTList(MVT::Other);
7968   SDValue Undef = getUNDEF(Ptr.getValueType());
7969   SDValue Ops[] = { Chain, Val, Ptr, Undef };
7970   FoldingSetNodeID ID;
7971   AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
7972   ID.AddInteger(SVT.getRawBits());
7973   ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
7974       dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO));
7975   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
7976   ID.AddInteger(MMO->getFlags());
7977   void *IP = nullptr;
7978   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
7979     cast<StoreSDNode>(E)->refineAlignment(MMO);
7980     return SDValue(E, 0);
7981   }
7982   auto *N = newSDNode<StoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
7983                                    ISD::UNINDEXED, true, SVT, MMO);
7984   createOperands(N, Ops);
7985 
7986   CSEMap.InsertNode(N, IP);
7987   InsertNode(N);
7988   SDValue V(N, 0);
7989   NewSDValueDbgMsg(V, "Creating new node: ", this);
7990   return V;
7991 }
7992 
7993 SDValue SelectionDAG::getIndexedStore(SDValue OrigStore, const SDLoc &dl,
7994                                       SDValue Base, SDValue Offset,
7995                                       ISD::MemIndexedMode AM) {
7996   StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
7997   assert(ST->getOffset().isUndef() && "Store is already a indexed store!");
7998   SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
7999   SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
8000   FoldingSetNodeID ID;
8001   AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
8002   ID.AddInteger(ST->getMemoryVT().getRawBits());
8003   ID.AddInteger(ST->getRawSubclassData());
8004   ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8005   ID.AddInteger(ST->getMemOperand()->getFlags());
8006   void *IP = nullptr;
8007   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
8008     return SDValue(E, 0);
8009 
8010   auto *N = newSDNode<StoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
8011                                    ST->isTruncatingStore(), ST->getMemoryVT(),
8012                                    ST->getMemOperand());
8013   createOperands(N, Ops);
8014 
8015   CSEMap.InsertNode(N, IP);
8016   InsertNode(N);
8017   SDValue V(N, 0);
8018   NewSDValueDbgMsg(V, "Creating new node: ", this);
8019   return V;
8020 }
8021 
8022 SDValue SelectionDAG::getLoadVP(
8023     ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
8024     SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL,
8025     MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment,
8026     MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo,
8027     const MDNode *Ranges, bool IsExpanding) {
8028   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8029 
8030   MMOFlags |= MachineMemOperand::MOLoad;
8031   assert((MMOFlags & MachineMemOperand::MOStore) == 0);
8032   // If we don't have a PtrInfo, infer the trivial frame index case to simplify
8033   // clients.
8034   if (PtrInfo.V.isNull())
8035     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
8036 
8037   uint64_t Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
8038   MachineFunction &MF = getMachineFunction();
8039   MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
8040                                                    Alignment, AAInfo, Ranges);
8041   return getLoadVP(AM, ExtType, VT, dl, Chain, Ptr, Offset, Mask, EVL, MemVT,
8042                    MMO, IsExpanding);
8043 }
8044 
8045 SDValue SelectionDAG::getLoadVP(ISD::MemIndexedMode AM,
8046                                 ISD::LoadExtType ExtType, EVT VT,
8047                                 const SDLoc &dl, SDValue Chain, SDValue Ptr,
8048                                 SDValue Offset, SDValue Mask, SDValue EVL,
8049                                 EVT MemVT, MachineMemOperand *MMO,
8050                                 bool IsExpanding) {
8051   bool Indexed = AM != ISD::UNINDEXED;
8052   assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
8053 
8054   SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other)
8055                          : getVTList(VT, MVT::Other);
8056   SDValue Ops[] = {Chain, Ptr, Offset, Mask, EVL};
8057   FoldingSetNodeID ID;
8058   AddNodeIDNode(ID, ISD::VP_LOAD, VTs, Ops);
8059   ID.AddInteger(VT.getRawBits());
8060   ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
8061       dl.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
8062   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8063   ID.AddInteger(MMO->getFlags());
8064   void *IP = nullptr;
8065   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8066     cast<VPLoadSDNode>(E)->refineAlignment(MMO);
8067     return SDValue(E, 0);
8068   }
8069   auto *N = newSDNode<VPLoadSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
8070                                     ExtType, IsExpanding, MemVT, MMO);
8071   createOperands(N, Ops);
8072 
8073   CSEMap.InsertNode(N, IP);
8074   InsertNode(N);
8075   SDValue V(N, 0);
8076   NewSDValueDbgMsg(V, "Creating new node: ", this);
8077   return V;
8078 }
8079 
8080 SDValue SelectionDAG::getLoadVP(EVT VT, const SDLoc &dl, SDValue Chain,
8081                                 SDValue Ptr, SDValue Mask, SDValue EVL,
8082                                 MachinePointerInfo PtrInfo,
8083                                 MaybeAlign Alignment,
8084                                 MachineMemOperand::Flags MMOFlags,
8085                                 const AAMDNodes &AAInfo, const MDNode *Ranges,
8086                                 bool IsExpanding) {
8087   SDValue Undef = getUNDEF(Ptr.getValueType());
8088   return getLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
8089                    Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
8090                    IsExpanding);
8091 }
8092 
8093 SDValue SelectionDAG::getLoadVP(EVT VT, const SDLoc &dl, SDValue Chain,
8094                                 SDValue Ptr, SDValue Mask, SDValue EVL,
8095                                 MachineMemOperand *MMO, bool IsExpanding) {
8096   SDValue Undef = getUNDEF(Ptr.getValueType());
8097   return getLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
8098                    Mask, EVL, VT, MMO, IsExpanding);
8099 }
8100 
8101 SDValue SelectionDAG::getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl,
8102                                    EVT VT, SDValue Chain, SDValue Ptr,
8103                                    SDValue Mask, SDValue EVL,
8104                                    MachinePointerInfo PtrInfo, EVT MemVT,
8105                                    MaybeAlign Alignment,
8106                                    MachineMemOperand::Flags MMOFlags,
8107                                    const AAMDNodes &AAInfo, bool IsExpanding) {
8108   SDValue Undef = getUNDEF(Ptr.getValueType());
8109   return getLoadVP(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, Mask,
8110                    EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo, nullptr,
8111                    IsExpanding);
8112 }
8113 
8114 SDValue SelectionDAG::getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl,
8115                                    EVT VT, SDValue Chain, SDValue Ptr,
8116                                    SDValue Mask, SDValue EVL, EVT MemVT,
8117                                    MachineMemOperand *MMO, bool IsExpanding) {
8118   SDValue Undef = getUNDEF(Ptr.getValueType());
8119   return getLoadVP(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, Mask,
8120                    EVL, MemVT, MMO, IsExpanding);
8121 }
8122 
8123 SDValue SelectionDAG::getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl,
8124                                        SDValue Base, SDValue Offset,
8125                                        ISD::MemIndexedMode AM) {
8126   auto *LD = cast<VPLoadSDNode>(OrigLoad);
8127   assert(LD->getOffset().isUndef() && "Load is already a indexed load!");
8128   // Don't propagate the invariant or dereferenceable flags.
8129   auto MMOFlags =
8130       LD->getMemOperand()->getFlags() &
8131       ~(MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
8132   return getLoadVP(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
8133                    LD->getChain(), Base, Offset, LD->getMask(),
8134                    LD->getVectorLength(), LD->getPointerInfo(),
8135                    LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
8136                    nullptr, LD->isExpandingLoad());
8137 }
8138 
8139 SDValue SelectionDAG::getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val,
8140                                  SDValue Ptr, SDValue Offset, SDValue Mask,
8141                                  SDValue EVL, EVT MemVT, MachineMemOperand *MMO,
8142                                  ISD::MemIndexedMode AM, bool IsTruncating,
8143                                  bool IsCompressing) {
8144   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8145   bool Indexed = AM != ISD::UNINDEXED;
8146   assert((Indexed || Offset.isUndef()) && "Unindexed vp_store with an offset!");
8147   SDVTList VTs = Indexed ? getVTList(Ptr.getValueType(), MVT::Other)
8148                          : getVTList(MVT::Other);
8149   SDValue Ops[] = {Chain, Val, Ptr, Offset, Mask, EVL};
8150   FoldingSetNodeID ID;
8151   AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops);
8152   ID.AddInteger(MemVT.getRawBits());
8153   ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
8154       dl.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
8155   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8156   ID.AddInteger(MMO->getFlags());
8157   void *IP = nullptr;
8158   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8159     cast<VPStoreSDNode>(E)->refineAlignment(MMO);
8160     return SDValue(E, 0);
8161   }
8162   auto *N = newSDNode<VPStoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
8163                                      IsTruncating, IsCompressing, MemVT, MMO);
8164   createOperands(N, Ops);
8165 
8166   CSEMap.InsertNode(N, IP);
8167   InsertNode(N);
8168   SDValue V(N, 0);
8169   NewSDValueDbgMsg(V, "Creating new node: ", this);
8170   return V;
8171 }
8172 
8173 SDValue SelectionDAG::getTruncStoreVP(SDValue Chain, const SDLoc &dl,
8174                                       SDValue Val, SDValue Ptr, SDValue Mask,
8175                                       SDValue EVL, MachinePointerInfo PtrInfo,
8176                                       EVT SVT, Align Alignment,
8177                                       MachineMemOperand::Flags MMOFlags,
8178                                       const AAMDNodes &AAInfo,
8179                                       bool IsCompressing) {
8180   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8181 
8182   MMOFlags |= MachineMemOperand::MOStore;
8183   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
8184 
8185   if (PtrInfo.V.isNull())
8186     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
8187 
8188   MachineFunction &MF = getMachineFunction();
8189   MachineMemOperand *MMO = MF.getMachineMemOperand(
8190       PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
8191       Alignment, AAInfo);
8192   return getTruncStoreVP(Chain, dl, Val, Ptr, Mask, EVL, SVT, MMO,
8193                          IsCompressing);
8194 }
8195 
8196 SDValue SelectionDAG::getTruncStoreVP(SDValue Chain, const SDLoc &dl,
8197                                       SDValue Val, SDValue Ptr, SDValue Mask,
8198                                       SDValue EVL, EVT SVT,
8199                                       MachineMemOperand *MMO,
8200                                       bool IsCompressing) {
8201   EVT VT = Val.getValueType();
8202 
8203   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8204   if (VT == SVT)
8205     return getStoreVP(Chain, dl, Val, Ptr, getUNDEF(Ptr.getValueType()), Mask,
8206                       EVL, VT, MMO, ISD::UNINDEXED,
8207                       /*IsTruncating*/ false, IsCompressing);
8208 
8209   assert(SVT.getScalarType().bitsLT(VT.getScalarType()) &&
8210          "Should only be a truncating store, not extending!");
8211   assert(VT.isInteger() == SVT.isInteger() && "Can't do FP-INT conversion!");
8212   assert(VT.isVector() == SVT.isVector() &&
8213          "Cannot use trunc store to convert to or from a vector!");
8214   assert((!VT.isVector() ||
8215           VT.getVectorElementCount() == SVT.getVectorElementCount()) &&
8216          "Cannot use trunc store to change the number of vector elements!");
8217 
8218   SDVTList VTs = getVTList(MVT::Other);
8219   SDValue Undef = getUNDEF(Ptr.getValueType());
8220   SDValue Ops[] = {Chain, Val, Ptr, Undef, Mask, EVL};
8221   FoldingSetNodeID ID;
8222   AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops);
8223   ID.AddInteger(SVT.getRawBits());
8224   ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
8225       dl.getIROrder(), VTs, ISD::UNINDEXED, true, IsCompressing, SVT, MMO));
8226   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8227   ID.AddInteger(MMO->getFlags());
8228   void *IP = nullptr;
8229   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8230     cast<VPStoreSDNode>(E)->refineAlignment(MMO);
8231     return SDValue(E, 0);
8232   }
8233   auto *N =
8234       newSDNode<VPStoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
8235                                ISD::UNINDEXED, true, IsCompressing, SVT, MMO);
8236   createOperands(N, Ops);
8237 
8238   CSEMap.InsertNode(N, IP);
8239   InsertNode(N);
8240   SDValue V(N, 0);
8241   NewSDValueDbgMsg(V, "Creating new node: ", this);
8242   return V;
8243 }
8244 
8245 SDValue SelectionDAG::getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl,
8246                                         SDValue Base, SDValue Offset,
8247                                         ISD::MemIndexedMode AM) {
8248   auto *ST = cast<VPStoreSDNode>(OrigStore);
8249   assert(ST->getOffset().isUndef() && "Store is already an indexed store!");
8250   SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
8251   SDValue Ops[] = {ST->getChain(), ST->getValue(), Base,
8252                    Offset,         ST->getMask(),  ST->getVectorLength()};
8253   FoldingSetNodeID ID;
8254   AddNodeIDNode(ID, ISD::VP_STORE, VTs, Ops);
8255   ID.AddInteger(ST->getMemoryVT().getRawBits());
8256   ID.AddInteger(ST->getRawSubclassData());
8257   ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8258   ID.AddInteger(ST->getMemOperand()->getFlags());
8259   void *IP = nullptr;
8260   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
8261     return SDValue(E, 0);
8262 
8263   auto *N = newSDNode<VPStoreSDNode>(
8264       dl.getIROrder(), dl.getDebugLoc(), VTs, AM, ST->isTruncatingStore(),
8265       ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
8266   createOperands(N, Ops);
8267 
8268   CSEMap.InsertNode(N, IP);
8269   InsertNode(N);
8270   SDValue V(N, 0);
8271   NewSDValueDbgMsg(V, "Creating new node: ", this);
8272   return V;
8273 }
8274 
8275 SDValue SelectionDAG::getStridedLoadVP(
8276     ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL,
8277     SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask,
8278     SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment,
8279     MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo,
8280     const MDNode *Ranges, bool IsExpanding) {
8281   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8282 
8283   MMOFlags |= MachineMemOperand::MOLoad;
8284   assert((MMOFlags & MachineMemOperand::MOStore) == 0);
8285   // If we don't have a PtrInfo, infer the trivial frame index case to simplify
8286   // clients.
8287   if (PtrInfo.V.isNull())
8288     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
8289 
8290   uint64_t Size = MemoryLocation::UnknownSize;
8291   MachineFunction &MF = getMachineFunction();
8292   MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
8293                                                    Alignment, AAInfo, Ranges);
8294   return getStridedLoadVP(AM, ExtType, VT, DL, Chain, Ptr, Offset, Stride, Mask,
8295                           EVL, MemVT, MMO, IsExpanding);
8296 }
8297 
8298 SDValue SelectionDAG::getStridedLoadVP(
8299     ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL,
8300     SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask,
8301     SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding) {
8302   bool Indexed = AM != ISD::UNINDEXED;
8303   assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
8304 
8305   SDValue Ops[] = {Chain, Ptr, Offset, Stride, Mask, EVL};
8306   SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other)
8307                          : getVTList(VT, MVT::Other);
8308   FoldingSetNodeID ID;
8309   AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_LOAD, VTs, Ops);
8310   ID.AddInteger(VT.getRawBits());
8311   ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
8312       DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
8313   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8314 
8315   void *IP = nullptr;
8316   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
8317     cast<VPStridedLoadSDNode>(E)->refineAlignment(MMO);
8318     return SDValue(E, 0);
8319   }
8320 
8321   auto *N =
8322       newSDNode<VPStridedLoadSDNode>(DL.getIROrder(), DL.getDebugLoc(), VTs, AM,
8323                                      ExtType, IsExpanding, MemVT, MMO);
8324   createOperands(N, Ops);
8325   CSEMap.InsertNode(N, IP);
8326   InsertNode(N);
8327   SDValue V(N, 0);
8328   NewSDValueDbgMsg(V, "Creating new node: ", this);
8329   return V;
8330 }
8331 
8332 SDValue SelectionDAG::getStridedLoadVP(
8333     EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride,
8334     SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment,
8335     MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo,
8336     const MDNode *Ranges, bool IsExpanding) {
8337   SDValue Undef = getUNDEF(Ptr.getValueType());
8338   return getStridedLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, DL, Chain, Ptr,
8339                           Undef, Stride, Mask, EVL, PtrInfo, VT, Alignment,
8340                           MMOFlags, AAInfo, Ranges, IsExpanding);
8341 }
8342 
8343 SDValue SelectionDAG::getStridedLoadVP(EVT VT, const SDLoc &DL, SDValue Chain,
8344                                        SDValue Ptr, SDValue Stride,
8345                                        SDValue Mask, SDValue EVL,
8346                                        MachineMemOperand *MMO,
8347                                        bool IsExpanding) {
8348   SDValue Undef = getUNDEF(Ptr.getValueType());
8349   return getStridedLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, DL, Chain, Ptr,
8350                           Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
8351 }
8352 
8353 SDValue SelectionDAG::getExtStridedLoadVP(
8354     ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain,
8355     SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL,
8356     MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment,
8357     MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo,
8358     bool IsExpanding) {
8359   SDValue Undef = getUNDEF(Ptr.getValueType());
8360   return getStridedLoadVP(ISD::UNINDEXED, ExtType, VT, DL, Chain, Ptr, Undef,
8361                           Stride, Mask, EVL, PtrInfo, MemVT, Alignment,
8362                           MMOFlags, AAInfo, nullptr, IsExpanding);
8363 }
8364 
8365 SDValue SelectionDAG::getExtStridedLoadVP(
8366     ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain,
8367     SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT,
8368     MachineMemOperand *MMO, bool IsExpanding) {
8369   SDValue Undef = getUNDEF(Ptr.getValueType());
8370   return getStridedLoadVP(ISD::UNINDEXED, ExtType, VT, DL, Chain, Ptr, Undef,
8371                           Stride, Mask, EVL, MemVT, MMO, IsExpanding);
8372 }
8373 
8374 SDValue SelectionDAG::getIndexedStridedLoadVP(SDValue OrigLoad, const SDLoc &DL,
8375                                               SDValue Base, SDValue Offset,
8376                                               ISD::MemIndexedMode AM) {
8377   auto *SLD = cast<VPStridedLoadSDNode>(OrigLoad);
8378   assert(SLD->getOffset().isUndef() &&
8379          "Strided load is already a indexed load!");
8380   // Don't propagate the invariant or dereferenceable flags.
8381   auto MMOFlags =
8382       SLD->getMemOperand()->getFlags() &
8383       ~(MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
8384   return getStridedLoadVP(
8385       AM, SLD->getExtensionType(), OrigLoad.getValueType(), DL, SLD->getChain(),
8386       Base, Offset, SLD->getStride(), SLD->getMask(), SLD->getVectorLength(),
8387       SLD->getPointerInfo(), SLD->getMemoryVT(), SLD->getAlign(), MMOFlags,
8388       SLD->getAAInfo(), nullptr, SLD->isExpandingLoad());
8389 }
8390 
8391 SDValue SelectionDAG::getStridedStoreVP(SDValue Chain, const SDLoc &DL,
8392                                         SDValue Val, SDValue Ptr,
8393                                         SDValue Offset, SDValue Stride,
8394                                         SDValue Mask, SDValue EVL, EVT MemVT,
8395                                         MachineMemOperand *MMO,
8396                                         ISD::MemIndexedMode AM,
8397                                         bool IsTruncating, bool IsCompressing) {
8398   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8399   bool Indexed = AM != ISD::UNINDEXED;
8400   assert((Indexed || Offset.isUndef()) && "Unindexed vp_store with an offset!");
8401   SDVTList VTs = Indexed ? getVTList(Ptr.getValueType(), MVT::Other)
8402                          : getVTList(MVT::Other);
8403   SDValue Ops[] = {Chain, Val, Ptr, Offset, Stride, Mask, EVL};
8404   FoldingSetNodeID ID;
8405   AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops);
8406   ID.AddInteger(MemVT.getRawBits());
8407   ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
8408       DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
8409   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8410   void *IP = nullptr;
8411   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
8412     cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
8413     return SDValue(E, 0);
8414   }
8415   auto *N = newSDNode<VPStridedStoreSDNode>(DL.getIROrder(), DL.getDebugLoc(),
8416                                             VTs, AM, IsTruncating,
8417                                             IsCompressing, MemVT, MMO);
8418   createOperands(N, Ops);
8419 
8420   CSEMap.InsertNode(N, IP);
8421   InsertNode(N);
8422   SDValue V(N, 0);
8423   NewSDValueDbgMsg(V, "Creating new node: ", this);
8424   return V;
8425 }
8426 
8427 SDValue SelectionDAG::getTruncStridedStoreVP(
8428     SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride,
8429     SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT,
8430     Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo,
8431     bool IsCompressing) {
8432   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8433 
8434   MMOFlags |= MachineMemOperand::MOStore;
8435   assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
8436 
8437   if (PtrInfo.V.isNull())
8438     PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
8439 
8440   MachineFunction &MF = getMachineFunction();
8441   MachineMemOperand *MMO = MF.getMachineMemOperand(
8442       PtrInfo, MMOFlags, MemoryLocation::UnknownSize, Alignment, AAInfo);
8443   return getTruncStridedStoreVP(Chain, DL, Val, Ptr, Stride, Mask, EVL, SVT,
8444                                 MMO, IsCompressing);
8445 }
8446 
8447 SDValue SelectionDAG::getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL,
8448                                              SDValue Val, SDValue Ptr,
8449                                              SDValue Stride, SDValue Mask,
8450                                              SDValue EVL, EVT SVT,
8451                                              MachineMemOperand *MMO,
8452                                              bool IsCompressing) {
8453   EVT VT = Val.getValueType();
8454 
8455   assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
8456   if (VT == SVT)
8457     return getStridedStoreVP(Chain, DL, Val, Ptr, getUNDEF(Ptr.getValueType()),
8458                              Stride, Mask, EVL, VT, MMO, ISD::UNINDEXED,
8459                              /*IsTruncating*/ false, IsCompressing);
8460 
8461   assert(SVT.getScalarType().bitsLT(VT.getScalarType()) &&
8462          "Should only be a truncating store, not extending!");
8463   assert(VT.isInteger() == SVT.isInteger() && "Can't do FP-INT conversion!");
8464   assert(VT.isVector() == SVT.isVector() &&
8465          "Cannot use trunc store to convert to or from a vector!");
8466   assert((!VT.isVector() ||
8467           VT.getVectorElementCount() == SVT.getVectorElementCount()) &&
8468          "Cannot use trunc store to change the number of vector elements!");
8469 
8470   SDVTList VTs = getVTList(MVT::Other);
8471   SDValue Undef = getUNDEF(Ptr.getValueType());
8472   SDValue Ops[] = {Chain, Val, Ptr, Undef, Stride, Mask, EVL};
8473   FoldingSetNodeID ID;
8474   AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops);
8475   ID.AddInteger(SVT.getRawBits());
8476   ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
8477       DL.getIROrder(), VTs, ISD::UNINDEXED, true, IsCompressing, SVT, MMO));
8478   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8479   void *IP = nullptr;
8480   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
8481     cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
8482     return SDValue(E, 0);
8483   }
8484   auto *N = newSDNode<VPStridedStoreSDNode>(DL.getIROrder(), DL.getDebugLoc(),
8485                                             VTs, ISD::UNINDEXED, true,
8486                                             IsCompressing, SVT, MMO);
8487   createOperands(N, Ops);
8488 
8489   CSEMap.InsertNode(N, IP);
8490   InsertNode(N);
8491   SDValue V(N, 0);
8492   NewSDValueDbgMsg(V, "Creating new node: ", this);
8493   return V;
8494 }
8495 
8496 SDValue SelectionDAG::getIndexedStridedStoreVP(SDValue OrigStore,
8497                                                const SDLoc &DL, SDValue Base,
8498                                                SDValue Offset,
8499                                                ISD::MemIndexedMode AM) {
8500   auto *SST = cast<VPStridedStoreSDNode>(OrigStore);
8501   assert(SST->getOffset().isUndef() &&
8502          "Strided store is already an indexed store!");
8503   SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
8504   SDValue Ops[] = {
8505       SST->getChain(), SST->getValue(),       Base, Offset, SST->getStride(),
8506       SST->getMask(),  SST->getVectorLength()};
8507   FoldingSetNodeID ID;
8508   AddNodeIDNode(ID, ISD::EXPERIMENTAL_VP_STRIDED_STORE, VTs, Ops);
8509   ID.AddInteger(SST->getMemoryVT().getRawBits());
8510   ID.AddInteger(SST->getRawSubclassData());
8511   ID.AddInteger(SST->getPointerInfo().getAddrSpace());
8512   void *IP = nullptr;
8513   if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
8514     return SDValue(E, 0);
8515 
8516   auto *N = newSDNode<VPStridedStoreSDNode>(
8517       DL.getIROrder(), DL.getDebugLoc(), VTs, AM, SST->isTruncatingStore(),
8518       SST->isCompressingStore(), SST->getMemoryVT(), SST->getMemOperand());
8519   createOperands(N, Ops);
8520 
8521   CSEMap.InsertNode(N, IP);
8522   InsertNode(N);
8523   SDValue V(N, 0);
8524   NewSDValueDbgMsg(V, "Creating new node: ", this);
8525   return V;
8526 }
8527 
8528 SDValue SelectionDAG::getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl,
8529                                   ArrayRef<SDValue> Ops, MachineMemOperand *MMO,
8530                                   ISD::MemIndexType IndexType) {
8531   assert(Ops.size() == 6 && "Incompatible number of operands");
8532 
8533   FoldingSetNodeID ID;
8534   AddNodeIDNode(ID, ISD::VP_GATHER, VTs, Ops);
8535   ID.AddInteger(VT.getRawBits());
8536   ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
8537       dl.getIROrder(), VTs, VT, MMO, IndexType));
8538   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8539   ID.AddInteger(MMO->getFlags());
8540   void *IP = nullptr;
8541   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8542     cast<VPGatherSDNode>(E)->refineAlignment(MMO);
8543     return SDValue(E, 0);
8544   }
8545 
8546   auto *N = newSDNode<VPGatherSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
8547                                       VT, MMO, IndexType);
8548   createOperands(N, Ops);
8549 
8550   assert(N->getMask().getValueType().getVectorElementCount() ==
8551              N->getValueType(0).getVectorElementCount() &&
8552          "Vector width mismatch between mask and data");
8553   assert(N->getIndex().getValueType().getVectorElementCount().isScalable() ==
8554              N->getValueType(0).getVectorElementCount().isScalable() &&
8555          "Scalable flags of index and data do not match");
8556   assert(ElementCount::isKnownGE(
8557              N->getIndex().getValueType().getVectorElementCount(),
8558              N->getValueType(0).getVectorElementCount()) &&
8559          "Vector width mismatch between index and data");
8560   assert(isa<ConstantSDNode>(N->getScale()) &&
8561          cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
8562          "Scale should be a constant power of 2");
8563 
8564   CSEMap.InsertNode(N, IP);
8565   InsertNode(N);
8566   SDValue V(N, 0);
8567   NewSDValueDbgMsg(V, "Creating new node: ", this);
8568   return V;
8569 }
8570 
8571 SDValue SelectionDAG::getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl,
8572                                    ArrayRef<SDValue> Ops,
8573                                    MachineMemOperand *MMO,
8574                                    ISD::MemIndexType IndexType) {
8575   assert(Ops.size() == 7 && "Incompatible number of operands");
8576 
8577   FoldingSetNodeID ID;
8578   AddNodeIDNode(ID, ISD::VP_SCATTER, VTs, Ops);
8579   ID.AddInteger(VT.getRawBits());
8580   ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
8581       dl.getIROrder(), VTs, VT, MMO, IndexType));
8582   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8583   ID.AddInteger(MMO->getFlags());
8584   void *IP = nullptr;
8585   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8586     cast<VPScatterSDNode>(E)->refineAlignment(MMO);
8587     return SDValue(E, 0);
8588   }
8589   auto *N = newSDNode<VPScatterSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
8590                                        VT, MMO, IndexType);
8591   createOperands(N, Ops);
8592 
8593   assert(N->getMask().getValueType().getVectorElementCount() ==
8594              N->getValue().getValueType().getVectorElementCount() &&
8595          "Vector width mismatch between mask and data");
8596   assert(
8597       N->getIndex().getValueType().getVectorElementCount().isScalable() ==
8598           N->getValue().getValueType().getVectorElementCount().isScalable() &&
8599       "Scalable flags of index and data do not match");
8600   assert(ElementCount::isKnownGE(
8601              N->getIndex().getValueType().getVectorElementCount(),
8602              N->getValue().getValueType().getVectorElementCount()) &&
8603          "Vector width mismatch between index and data");
8604   assert(isa<ConstantSDNode>(N->getScale()) &&
8605          cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
8606          "Scale should be a constant power of 2");
8607 
8608   CSEMap.InsertNode(N, IP);
8609   InsertNode(N);
8610   SDValue V(N, 0);
8611   NewSDValueDbgMsg(V, "Creating new node: ", this);
8612   return V;
8613 }
8614 
8615 SDValue SelectionDAG::getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain,
8616                                     SDValue Base, SDValue Offset, SDValue Mask,
8617                                     SDValue PassThru, EVT MemVT,
8618                                     MachineMemOperand *MMO,
8619                                     ISD::MemIndexedMode AM,
8620                                     ISD::LoadExtType ExtTy, bool isExpanding) {
8621   bool Indexed = AM != ISD::UNINDEXED;
8622   assert((Indexed || Offset.isUndef()) &&
8623          "Unindexed masked load with an offset!");
8624   SDVTList VTs = Indexed ? getVTList(VT, Base.getValueType(), MVT::Other)
8625                          : getVTList(VT, MVT::Other);
8626   SDValue Ops[] = {Chain, Base, Offset, Mask, PassThru};
8627   FoldingSetNodeID ID;
8628   AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops);
8629   ID.AddInteger(MemVT.getRawBits());
8630   ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
8631       dl.getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
8632   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8633   ID.AddInteger(MMO->getFlags());
8634   void *IP = nullptr;
8635   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8636     cast<MaskedLoadSDNode>(E)->refineAlignment(MMO);
8637     return SDValue(E, 0);
8638   }
8639   auto *N = newSDNode<MaskedLoadSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
8640                                         AM, ExtTy, isExpanding, MemVT, MMO);
8641   createOperands(N, Ops);
8642 
8643   CSEMap.InsertNode(N, IP);
8644   InsertNode(N);
8645   SDValue V(N, 0);
8646   NewSDValueDbgMsg(V, "Creating new node: ", this);
8647   return V;
8648 }
8649 
8650 SDValue SelectionDAG::getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl,
8651                                            SDValue Base, SDValue Offset,
8652                                            ISD::MemIndexedMode AM) {
8653   MaskedLoadSDNode *LD = cast<MaskedLoadSDNode>(OrigLoad);
8654   assert(LD->getOffset().isUndef() && "Masked load is already a indexed load!");
8655   return getMaskedLoad(OrigLoad.getValueType(), dl, LD->getChain(), Base,
8656                        Offset, LD->getMask(), LD->getPassThru(),
8657                        LD->getMemoryVT(), LD->getMemOperand(), AM,
8658                        LD->getExtensionType(), LD->isExpandingLoad());
8659 }
8660 
8661 SDValue SelectionDAG::getMaskedStore(SDValue Chain, const SDLoc &dl,
8662                                      SDValue Val, SDValue Base, SDValue Offset,
8663                                      SDValue Mask, EVT MemVT,
8664                                      MachineMemOperand *MMO,
8665                                      ISD::MemIndexedMode AM, bool IsTruncating,
8666                                      bool IsCompressing) {
8667   assert(Chain.getValueType() == MVT::Other &&
8668         "Invalid chain type");
8669   bool Indexed = AM != ISD::UNINDEXED;
8670   assert((Indexed || Offset.isUndef()) &&
8671          "Unindexed masked store with an offset!");
8672   SDVTList VTs = Indexed ? getVTList(Base.getValueType(), MVT::Other)
8673                          : getVTList(MVT::Other);
8674   SDValue Ops[] = {Chain, Val, Base, Offset, Mask};
8675   FoldingSetNodeID ID;
8676   AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops);
8677   ID.AddInteger(MemVT.getRawBits());
8678   ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
8679       dl.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
8680   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8681   ID.AddInteger(MMO->getFlags());
8682   void *IP = nullptr;
8683   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8684     cast<MaskedStoreSDNode>(E)->refineAlignment(MMO);
8685     return SDValue(E, 0);
8686   }
8687   auto *N =
8688       newSDNode<MaskedStoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
8689                                    IsTruncating, IsCompressing, MemVT, MMO);
8690   createOperands(N, Ops);
8691 
8692   CSEMap.InsertNode(N, IP);
8693   InsertNode(N);
8694   SDValue V(N, 0);
8695   NewSDValueDbgMsg(V, "Creating new node: ", this);
8696   return V;
8697 }
8698 
8699 SDValue SelectionDAG::getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl,
8700                                             SDValue Base, SDValue Offset,
8701                                             ISD::MemIndexedMode AM) {
8702   MaskedStoreSDNode *ST = cast<MaskedStoreSDNode>(OrigStore);
8703   assert(ST->getOffset().isUndef() &&
8704          "Masked store is already a indexed store!");
8705   return getMaskedStore(ST->getChain(), dl, ST->getValue(), Base, Offset,
8706                         ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
8707                         AM, ST->isTruncatingStore(), ST->isCompressingStore());
8708 }
8709 
8710 SDValue SelectionDAG::getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl,
8711                                       ArrayRef<SDValue> Ops,
8712                                       MachineMemOperand *MMO,
8713                                       ISD::MemIndexType IndexType,
8714                                       ISD::LoadExtType ExtTy) {
8715   assert(Ops.size() == 6 && "Incompatible number of operands");
8716 
8717   FoldingSetNodeID ID;
8718   AddNodeIDNode(ID, ISD::MGATHER, VTs, Ops);
8719   ID.AddInteger(MemVT.getRawBits());
8720   ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
8721       dl.getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
8722   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8723   ID.AddInteger(MMO->getFlags());
8724   void *IP = nullptr;
8725   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8726     cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
8727     return SDValue(E, 0);
8728   }
8729 
8730   auto *N = newSDNode<MaskedGatherSDNode>(dl.getIROrder(), dl.getDebugLoc(),
8731                                           VTs, MemVT, MMO, IndexType, ExtTy);
8732   createOperands(N, Ops);
8733 
8734   assert(N->getPassThru().getValueType() == N->getValueType(0) &&
8735          "Incompatible type of the PassThru value in MaskedGatherSDNode");
8736   assert(N->getMask().getValueType().getVectorElementCount() ==
8737              N->getValueType(0).getVectorElementCount() &&
8738          "Vector width mismatch between mask and data");
8739   assert(N->getIndex().getValueType().getVectorElementCount().isScalable() ==
8740              N->getValueType(0).getVectorElementCount().isScalable() &&
8741          "Scalable flags of index and data do not match");
8742   assert(ElementCount::isKnownGE(
8743              N->getIndex().getValueType().getVectorElementCount(),
8744              N->getValueType(0).getVectorElementCount()) &&
8745          "Vector width mismatch between index and data");
8746   assert(isa<ConstantSDNode>(N->getScale()) &&
8747          cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
8748          "Scale should be a constant power of 2");
8749 
8750   CSEMap.InsertNode(N, IP);
8751   InsertNode(N);
8752   SDValue V(N, 0);
8753   NewSDValueDbgMsg(V, "Creating new node: ", this);
8754   return V;
8755 }
8756 
8757 SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl,
8758                                        ArrayRef<SDValue> Ops,
8759                                        MachineMemOperand *MMO,
8760                                        ISD::MemIndexType IndexType,
8761                                        bool IsTrunc) {
8762   assert(Ops.size() == 6 && "Incompatible number of operands");
8763 
8764   FoldingSetNodeID ID;
8765   AddNodeIDNode(ID, ISD::MSCATTER, VTs, Ops);
8766   ID.AddInteger(MemVT.getRawBits());
8767   ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
8768       dl.getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
8769   ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
8770   ID.AddInteger(MMO->getFlags());
8771   void *IP = nullptr;
8772   if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
8773     cast<MaskedScatterSDNode>(E)->refineAlignment(MMO);
8774     return SDValue(E, 0);
8775   }
8776 
8777   auto *N = newSDNode<MaskedScatterSDNode>(dl.getIROrder(), dl.getDebugLoc(),
8778                                            VTs, MemVT, MMO, IndexType, IsTrunc);
8779   createOperands(N, Ops);
8780 
8781   assert(N->getMask().getValueType().getVectorElementCount() ==
8782              N->getValue().getValueType().getVectorElementCount() &&
8783          "Vector width mismatch between mask and data");
8784   assert(
8785       N->getIndex().getValueType().getVectorElementCount().isScalable() ==
8786           N->getValue().getValueType().getVectorElementCount().isScalable() &&
8787       "Scalable flags of index and data do not match");
8788   assert(ElementCount::isKnownGE(
8789              N->getIndex().getValueType().getVectorElementCount(),
8790              N->getValue().getValueType().getVectorElementCount()) &&
8791          "Vector width mismatch between index and data");
8792   assert(isa<ConstantSDNode>(N->getScale()) &&
8793          cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
8794          "Scale should be a constant power of 2");
8795 
8796   CSEMap.InsertNode(N, IP);
8797   InsertNode(N);
8798   SDValue V(N, 0);
8799   NewSDValueDbgMsg(V, "Creating new node: ", this);
8800   return V;
8801 }
8802 
8803 SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
8804   // select undef, T, F --> T (if T is a constant), otherwise F
8805   // select, ?, undef, F --> F
8806   // select, ?, T, undef --> T
8807   if (Cond.isUndef())
8808     return isConstantValueOfAnyType(T) ? T : F;
8809   if (T.isUndef())
8810     return F;
8811   if (F.isUndef())
8812     return T;
8813 
8814   // select true, T, F --> T
8815   // select false, T, F --> F
8816   if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
8817     return CondC->isZero() ? F : T;
8818 
8819   // TODO: This should simplify VSELECT with constant condition using something
8820   // like this (but check boolean contents to be complete?):
8821   //  if (ISD::isBuildVectorAllOnes(Cond.getNode()))
8822   //    return T;
8823   //  if (ISD::isBuildVectorAllZeros(Cond.getNode()))
8824   //    return F;
8825 
8826   // select ?, T, T --> T
8827   if (T == F)
8828     return T;
8829 
8830   return SDValue();
8831 }
8832 
8833 SDValue SelectionDAG::simplifyShift(SDValue X, SDValue Y) {
8834   // shift undef, Y --> 0 (can always assume that the undef value is 0)
8835   if (X.isUndef())
8836     return getConstant(0, SDLoc(X.getNode()), X.getValueType());
8837   // shift X, undef --> undef (because it may shift by the bitwidth)
8838   if (Y.isUndef())
8839     return getUNDEF(X.getValueType());
8840 
8841   // shift 0, Y --> 0
8842   // shift X, 0 --> X
8843   if (isNullOrNullSplat(X) || isNullOrNullSplat(Y))
8844     return X;
8845 
8846   // shift X, C >= bitwidth(X) --> undef
8847   // All vector elements must be too big (or undef) to avoid partial undefs.
8848   auto isShiftTooBig = [X](ConstantSDNode *Val) {
8849     return !Val || Val->getAPIntValue().uge(X.getScalarValueSizeInBits());
8850   };
8851   if (ISD::matchUnaryPredicate(Y, isShiftTooBig, true))
8852     return getUNDEF(X.getValueType());
8853 
8854   return SDValue();
8855 }
8856 
8857 SDValue SelectionDAG::simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
8858                                       SDNodeFlags Flags) {
8859   // If this operation has 'nnan' or 'ninf' and at least 1 disallowed operand
8860   // (an undef operand can be chosen to be Nan/Inf), then the result of this
8861   // operation is poison. That result can be relaxed to undef.
8862   ConstantFPSDNode *XC = isConstOrConstSplatFP(X, /* AllowUndefs */ true);
8863   ConstantFPSDNode *YC = isConstOrConstSplatFP(Y, /* AllowUndefs */ true);
8864   bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
8865                 (YC && YC->getValueAPF().isNaN());
8866   bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
8867                 (YC && YC->getValueAPF().isInfinity());
8868 
8869   if (Flags.hasNoNaNs() && (HasNan || X.isUndef() || Y.isUndef()))
8870     return getUNDEF(X.getValueType());
8871 
8872   if (Flags.hasNoInfs() && (HasInf || X.isUndef() || Y.isUndef()))
8873     return getUNDEF(X.getValueType());
8874 
8875   if (!YC)
8876     return SDValue();
8877 
8878   // X + -0.0 --> X
8879   if (Opcode == ISD::FADD)
8880     if (YC->getValueAPF().isNegZero())
8881       return X;
8882 
8883   // X - +0.0 --> X
8884   if (Opcode == ISD::FSUB)
8885     if (YC->getValueAPF().isPosZero())
8886       return X;
8887 
8888   // X * 1.0 --> X
8889   // X / 1.0 --> X
8890   if (Opcode == ISD::FMUL || Opcode == ISD::FDIV)
8891     if (YC->getValueAPF().isExactlyValue(1.0))
8892       return X;
8893 
8894   // X * 0.0 --> 0.0
8895   if (Opcode == ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
8896     if (YC->getValueAPF().isZero())
8897       return getConstantFP(0.0, SDLoc(Y), Y.getValueType());
8898 
8899   return SDValue();
8900 }
8901 
8902 SDValue SelectionDAG::getVAArg(EVT VT, const SDLoc &dl, SDValue Chain,
8903                                SDValue Ptr, SDValue SV, unsigned Align) {
8904   SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32) };
8905   return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops);
8906 }
8907 
8908 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
8909                               ArrayRef<SDUse> Ops) {
8910   switch (Ops.size()) {
8911   case 0: return getNode(Opcode, DL, VT);
8912   case 1: return getNode(Opcode, DL, VT, static_cast<const SDValue>(Ops[0]));
8913   case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
8914   case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
8915   default: break;
8916   }
8917 
8918   // Copy from an SDUse array into an SDValue array for use with
8919   // the regular getNode logic.
8920   SmallVector<SDValue, 8> NewOps(Ops.begin(), Ops.end());
8921   return getNode(Opcode, DL, VT, NewOps);
8922 }
8923 
8924 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
8925                               ArrayRef<SDValue> Ops) {
8926   SDNodeFlags Flags;
8927   if (Inserter)
8928     Flags = Inserter->getFlags();
8929   return getNode(Opcode, DL, VT, Ops, Flags);
8930 }
8931 
8932 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
8933                               ArrayRef<SDValue> Ops, const SDNodeFlags Flags) {
8934   unsigned NumOps = Ops.size();
8935   switch (NumOps) {
8936   case 0: return getNode(Opcode, DL, VT);
8937   case 1: return getNode(Opcode, DL, VT, Ops[0], Flags);
8938   case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Flags);
8939   case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2], Flags);
8940   default: break;
8941   }
8942 
8943 #ifndef NDEBUG
8944   for (const auto &Op : Ops)
8945     assert(Op.getOpcode() != ISD::DELETED_NODE &&
8946            "Operand is DELETED_NODE!");
8947 #endif
8948 
8949   switch (Opcode) {
8950   default: break;
8951   case ISD::BUILD_VECTOR:
8952     // Attempt to simplify BUILD_VECTOR.
8953     if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
8954       return V;
8955     break;
8956   case ISD::CONCAT_VECTORS:
8957     if (SDValue V = foldCONCAT_VECTORS(DL, VT, Ops, *this))
8958       return V;
8959     break;
8960   case ISD::SELECT_CC:
8961     assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
8962     assert(Ops[0].getValueType() == Ops[1].getValueType() &&
8963            "LHS and RHS of condition must have same type!");
8964     assert(Ops[2].getValueType() == Ops[3].getValueType() &&
8965            "True and False arms of SelectCC must have same type!");
8966     assert(Ops[2].getValueType() == VT &&
8967            "select_cc node must be of same type as true and false value!");
8968     assert((!Ops[0].getValueType().isVector() ||
8969             Ops[0].getValueType().getVectorElementCount() ==
8970                 VT.getVectorElementCount()) &&
8971            "Expected select_cc with vector result to have the same sized "
8972            "comparison type!");
8973     break;
8974   case ISD::BR_CC:
8975     assert(NumOps == 5 && "BR_CC takes 5 operands!");
8976     assert(Ops[2].getValueType() == Ops[3].getValueType() &&
8977            "LHS/RHS of comparison should match types!");
8978     break;
8979   case ISD::VP_ADD:
8980   case ISD::VP_SUB:
8981     // If it is VP_ADD/VP_SUB mask operation then turn it to VP_XOR
8982     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
8983       Opcode = ISD::VP_XOR;
8984     break;
8985   case ISD::VP_MUL:
8986     // If it is VP_MUL mask operation then turn it to VP_AND
8987     if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
8988       Opcode = ISD::VP_AND;
8989     break;
8990   case ISD::VP_REDUCE_MUL:
8991     // If it is VP_REDUCE_MUL mask operation then turn it to VP_REDUCE_AND
8992     if (VT == MVT::i1)
8993       Opcode = ISD::VP_REDUCE_AND;
8994     break;
8995   case ISD::VP_REDUCE_ADD:
8996     // If it is VP_REDUCE_ADD mask operation then turn it to VP_REDUCE_XOR
8997     if (VT == MVT::i1)
8998       Opcode = ISD::VP_REDUCE_XOR;
8999     break;
9000   case ISD::VP_REDUCE_SMAX:
9001   case ISD::VP_REDUCE_UMIN:
9002     // If it is VP_REDUCE_SMAX/VP_REDUCE_UMIN mask operation then turn it to
9003     // VP_REDUCE_AND.
9004     if (VT == MVT::i1)
9005       Opcode = ISD::VP_REDUCE_AND;
9006     break;
9007   case ISD::VP_REDUCE_SMIN:
9008   case ISD::VP_REDUCE_UMAX:
9009     // If it is VP_REDUCE_SMIN/VP_REDUCE_UMAX mask operation then turn it to
9010     // VP_REDUCE_OR.
9011     if (VT == MVT::i1)
9012       Opcode = ISD::VP_REDUCE_OR;
9013     break;
9014   }
9015 
9016   // Memoize nodes.
9017   SDNode *N;
9018   SDVTList VTs = getVTList(VT);
9019 
9020   if (VT != MVT::Glue) {
9021     FoldingSetNodeID ID;
9022     AddNodeIDNode(ID, Opcode, VTs, Ops);
9023     void *IP = nullptr;
9024 
9025     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
9026       return SDValue(E, 0);
9027 
9028     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
9029     createOperands(N, Ops);
9030 
9031     CSEMap.InsertNode(N, IP);
9032   } else {
9033     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
9034     createOperands(N, Ops);
9035   }
9036 
9037   N->setFlags(Flags);
9038   InsertNode(N);
9039   SDValue V(N, 0);
9040   NewSDValueDbgMsg(V, "Creating new node: ", this);
9041   return V;
9042 }
9043 
9044 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
9045                               ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) {
9046   return getNode(Opcode, DL, getVTList(ResultTys), Ops);
9047 }
9048 
9049 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9050                               ArrayRef<SDValue> Ops) {
9051   SDNodeFlags Flags;
9052   if (Inserter)
9053     Flags = Inserter->getFlags();
9054   return getNode(Opcode, DL, VTList, Ops, Flags);
9055 }
9056 
9057 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9058                               ArrayRef<SDValue> Ops, const SDNodeFlags Flags) {
9059   if (VTList.NumVTs == 1)
9060     return getNode(Opcode, DL, VTList.VTs[0], Ops, Flags);
9061 
9062 #ifndef NDEBUG
9063   for (const auto &Op : Ops)
9064     assert(Op.getOpcode() != ISD::DELETED_NODE &&
9065            "Operand is DELETED_NODE!");
9066 #endif
9067 
9068   switch (Opcode) {
9069   case ISD::SADDO:
9070   case ISD::UADDO:
9071   case ISD::SSUBO:
9072   case ISD::USUBO: {
9073     assert(VTList.NumVTs == 2 && Ops.size() == 2 &&
9074            "Invalid add/sub overflow op!");
9075     assert(VTList.VTs[0].isInteger() && VTList.VTs[1].isInteger() &&
9076            Ops[0].getValueType() == Ops[1].getValueType() &&
9077            Ops[0].getValueType() == VTList.VTs[0] &&
9078            "Binary operator types must match!");
9079     SDValue N1 = Ops[0], N2 = Ops[1];
9080     canonicalizeCommutativeBinop(Opcode, N1, N2);
9081 
9082     // (X +- 0) -> X with zero-overflow.
9083     ConstantSDNode *N2CV = isConstOrConstSplat(N2, /*AllowUndefs*/ false,
9084                                                /*AllowTruncation*/ true);
9085     if (N2CV && N2CV->isZero()) {
9086       SDValue ZeroOverFlow = getConstant(0, DL, VTList.VTs[1]);
9087       return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags);
9088     }
9089     break;
9090   }
9091   case ISD::SMUL_LOHI:
9092   case ISD::UMUL_LOHI: {
9093     assert(VTList.NumVTs == 2 && Ops.size() == 2 && "Invalid mul lo/hi op!");
9094     assert(VTList.VTs[0].isInteger() && VTList.VTs[0] == VTList.VTs[1] &&
9095            VTList.VTs[0] == Ops[0].getValueType() &&
9096            VTList.VTs[0] == Ops[1].getValueType() &&
9097            "Binary operator types must match!");
9098     break;
9099   }
9100   case ISD::STRICT_FP_EXTEND:
9101     assert(VTList.NumVTs == 2 && Ops.size() == 2 &&
9102            "Invalid STRICT_FP_EXTEND!");
9103     assert(VTList.VTs[0].isFloatingPoint() &&
9104            Ops[1].getValueType().isFloatingPoint() && "Invalid FP cast!");
9105     assert(VTList.VTs[0].isVector() == Ops[1].getValueType().isVector() &&
9106            "STRICT_FP_EXTEND result type should be vector iff the operand "
9107            "type is vector!");
9108     assert((!VTList.VTs[0].isVector() ||
9109             VTList.VTs[0].getVectorNumElements() ==
9110             Ops[1].getValueType().getVectorNumElements()) &&
9111            "Vector element count mismatch!");
9112     assert(Ops[1].getValueType().bitsLT(VTList.VTs[0]) &&
9113            "Invalid fpext node, dst <= src!");
9114     break;
9115   case ISD::STRICT_FP_ROUND:
9116     assert(VTList.NumVTs == 2 && Ops.size() == 3 && "Invalid STRICT_FP_ROUND!");
9117     assert(VTList.VTs[0].isVector() == Ops[1].getValueType().isVector() &&
9118            "STRICT_FP_ROUND result type should be vector iff the operand "
9119            "type is vector!");
9120     assert((!VTList.VTs[0].isVector() ||
9121             VTList.VTs[0].getVectorNumElements() ==
9122             Ops[1].getValueType().getVectorNumElements()) &&
9123            "Vector element count mismatch!");
9124     assert(VTList.VTs[0].isFloatingPoint() &&
9125            Ops[1].getValueType().isFloatingPoint() &&
9126            VTList.VTs[0].bitsLT(Ops[1].getValueType()) &&
9127            isa<ConstantSDNode>(Ops[2]) &&
9128            (cast<ConstantSDNode>(Ops[2])->getZExtValue() == 0 ||
9129             cast<ConstantSDNode>(Ops[2])->getZExtValue() == 1) &&
9130            "Invalid STRICT_FP_ROUND!");
9131     break;
9132 #if 0
9133   // FIXME: figure out how to safely handle things like
9134   // int foo(int x) { return 1 << (x & 255); }
9135   // int bar() { return foo(256); }
9136   case ISD::SRA_PARTS:
9137   case ISD::SRL_PARTS:
9138   case ISD::SHL_PARTS:
9139     if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
9140         cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
9141       return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
9142     else if (N3.getOpcode() == ISD::AND)
9143       if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
9144         // If the and is only masking out bits that cannot effect the shift,
9145         // eliminate the and.
9146         unsigned NumBits = VT.getScalarSizeInBits()*2;
9147         if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
9148           return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
9149       }
9150     break;
9151 #endif
9152   }
9153 
9154   // Memoize the node unless it returns a flag.
9155   SDNode *N;
9156   if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
9157     FoldingSetNodeID ID;
9158     AddNodeIDNode(ID, Opcode, VTList, Ops);
9159     void *IP = nullptr;
9160     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
9161       return SDValue(E, 0);
9162 
9163     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTList);
9164     createOperands(N, Ops);
9165     CSEMap.InsertNode(N, IP);
9166   } else {
9167     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTList);
9168     createOperands(N, Ops);
9169   }
9170 
9171   N->setFlags(Flags);
9172   InsertNode(N);
9173   SDValue V(N, 0);
9174   NewSDValueDbgMsg(V, "Creating new node: ", this);
9175   return V;
9176 }
9177 
9178 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
9179                               SDVTList VTList) {
9180   return getNode(Opcode, DL, VTList, None);
9181 }
9182 
9183 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9184                               SDValue N1) {
9185   SDValue Ops[] = { N1 };
9186   return getNode(Opcode, DL, VTList, Ops);
9187 }
9188 
9189 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9190                               SDValue N1, SDValue N2) {
9191   SDValue Ops[] = { N1, N2 };
9192   return getNode(Opcode, DL, VTList, Ops);
9193 }
9194 
9195 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9196                               SDValue N1, SDValue N2, SDValue N3) {
9197   SDValue Ops[] = { N1, N2, N3 };
9198   return getNode(Opcode, DL, VTList, Ops);
9199 }
9200 
9201 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9202                               SDValue N1, SDValue N2, SDValue N3, SDValue N4) {
9203   SDValue Ops[] = { N1, N2, N3, N4 };
9204   return getNode(Opcode, DL, VTList, Ops);
9205 }
9206 
9207 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
9208                               SDValue N1, SDValue N2, SDValue N3, SDValue N4,
9209                               SDValue N5) {
9210   SDValue Ops[] = { N1, N2, N3, N4, N5 };
9211   return getNode(Opcode, DL, VTList, Ops);
9212 }
9213 
9214 SDVTList SelectionDAG::getVTList(EVT VT) {
9215   return makeVTList(SDNode::getValueTypeList(VT), 1);
9216 }
9217 
9218 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) {
9219   FoldingSetNodeID ID;
9220   ID.AddInteger(2U);
9221   ID.AddInteger(VT1.getRawBits());
9222   ID.AddInteger(VT2.getRawBits());
9223 
9224   void *IP = nullptr;
9225   SDVTListNode *Result = VTListMap.FindNodeOrInsertPos(ID, IP);
9226   if (!Result) {
9227     EVT *Array = Allocator.Allocate<EVT>(2);
9228     Array[0] = VT1;
9229     Array[1] = VT2;
9230     Result = new (Allocator) SDVTListNode(ID.Intern(Allocator), Array, 2);
9231     VTListMap.InsertNode(Result, IP);
9232   }
9233   return Result->getSDVTList();
9234 }
9235 
9236 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) {
9237   FoldingSetNodeID ID;
9238   ID.AddInteger(3U);
9239   ID.AddInteger(VT1.getRawBits());
9240   ID.AddInteger(VT2.getRawBits());
9241   ID.AddInteger(VT3.getRawBits());
9242 
9243   void *IP = nullptr;
9244   SDVTListNode *Result = VTListMap.FindNodeOrInsertPos(ID, IP);
9245   if (!Result) {
9246     EVT *Array = Allocator.Allocate<EVT>(3);
9247     Array[0] = VT1;
9248     Array[1] = VT2;
9249     Array[2] = VT3;
9250     Result = new (Allocator) SDVTListNode(ID.Intern(Allocator), Array, 3);
9251     VTListMap.InsertNode(Result, IP);
9252   }
9253   return Result->getSDVTList();
9254 }
9255 
9256 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) {
9257   FoldingSetNodeID ID;
9258   ID.AddInteger(4U);
9259   ID.AddInteger(VT1.getRawBits());
9260   ID.AddInteger(VT2.getRawBits());
9261   ID.AddInteger(VT3.getRawBits());
9262   ID.AddInteger(VT4.getRawBits());
9263 
9264   void *IP = nullptr;
9265   SDVTListNode *Result = VTListMap.FindNodeOrInsertPos(ID, IP);
9266   if (!Result) {
9267     EVT *Array = Allocator.Allocate<EVT>(4);
9268     Array[0] = VT1;
9269     Array[1] = VT2;
9270     Array[2] = VT3;
9271     Array[3] = VT4;
9272     Result = new (Allocator) SDVTListNode(ID.Intern(Allocator), Array, 4);
9273     VTListMap.InsertNode(Result, IP);
9274   }
9275   return Result->getSDVTList();
9276 }
9277 
9278 SDVTList SelectionDAG::getVTList(ArrayRef<EVT> VTs) {
9279   unsigned NumVTs = VTs.size();
9280   FoldingSetNodeID ID;
9281   ID.AddInteger(NumVTs);
9282   for (unsigned index = 0; index < NumVTs; index++) {
9283     ID.AddInteger(VTs[index].getRawBits());
9284   }
9285 
9286   void *IP = nullptr;
9287   SDVTListNode *Result = VTListMap.FindNodeOrInsertPos(ID, IP);
9288   if (!Result) {
9289     EVT *Array = Allocator.Allocate<EVT>(NumVTs);
9290     llvm::copy(VTs, Array);
9291     Result = new (Allocator) SDVTListNode(ID.Intern(Allocator), Array, NumVTs);
9292     VTListMap.InsertNode(Result, IP);
9293   }
9294   return Result->getSDVTList();
9295 }
9296 
9297 
9298 /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
9299 /// specified operands.  If the resultant node already exists in the DAG,
9300 /// this does not modify the specified node, instead it returns the node that
9301 /// already exists.  If the resultant node does not exist in the DAG, the
9302 /// input node is returned.  As a degenerate case, if you specify the same
9303 /// input operands as the node already has, the input node is returned.
9304 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op) {
9305   assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
9306 
9307   // Check to see if there is no change.
9308   if (Op == N->getOperand(0)) return N;
9309 
9310   // See if the modified node already exists.
9311   void *InsertPos = nullptr;
9312   if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
9313     return Existing;
9314 
9315   // Nope it doesn't.  Remove the node from its current place in the maps.
9316   if (InsertPos)
9317     if (!RemoveNodeFromCSEMaps(N))
9318       InsertPos = nullptr;
9319 
9320   // Now we update the operands.
9321   N->OperandList[0].set(Op);
9322 
9323   updateDivergence(N);
9324   // If this gets put into a CSE map, add it.
9325   if (InsertPos) CSEMap.InsertNode(N, InsertPos);
9326   return N;
9327 }
9328 
9329 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) {
9330   assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
9331 
9332   // Check to see if there is no change.
9333   if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
9334     return N;   // No operands changed, just return the input node.
9335 
9336   // See if the modified node already exists.
9337   void *InsertPos = nullptr;
9338   if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
9339     return Existing;
9340 
9341   // Nope it doesn't.  Remove the node from its current place in the maps.
9342   if (InsertPos)
9343     if (!RemoveNodeFromCSEMaps(N))
9344       InsertPos = nullptr;
9345 
9346   // Now we update the operands.
9347   if (N->OperandList[0] != Op1)
9348     N->OperandList[0].set(Op1);
9349   if (N->OperandList[1] != Op2)
9350     N->OperandList[1].set(Op2);
9351 
9352   updateDivergence(N);
9353   // If this gets put into a CSE map, add it.
9354   if (InsertPos) CSEMap.InsertNode(N, InsertPos);
9355   return N;
9356 }
9357 
9358 SDNode *SelectionDAG::
9359 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) {
9360   SDValue Ops[] = { Op1, Op2, Op3 };
9361   return UpdateNodeOperands(N, Ops);
9362 }
9363 
9364 SDNode *SelectionDAG::
9365 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
9366                    SDValue Op3, SDValue Op4) {
9367   SDValue Ops[] = { Op1, Op2, Op3, Op4 };
9368   return UpdateNodeOperands(N, Ops);
9369 }
9370 
9371 SDNode *SelectionDAG::
9372 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
9373                    SDValue Op3, SDValue Op4, SDValue Op5) {
9374   SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
9375   return UpdateNodeOperands(N, Ops);
9376 }
9377 
9378 SDNode *SelectionDAG::
9379 UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops) {
9380   unsigned NumOps = Ops.size();
9381   assert(N->getNumOperands() == NumOps &&
9382          "Update with wrong number of operands");
9383 
9384   // If no operands changed just return the input node.
9385   if (std::equal(Ops.begin(), Ops.end(), N->op_begin()))
9386     return N;
9387 
9388   // See if the modified node already exists.
9389   void *InsertPos = nullptr;
9390   if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, InsertPos))
9391     return Existing;
9392 
9393   // Nope it doesn't.  Remove the node from its current place in the maps.
9394   if (InsertPos)
9395     if (!RemoveNodeFromCSEMaps(N))
9396       InsertPos = nullptr;
9397 
9398   // Now we update the operands.
9399   for (unsigned i = 0; i != NumOps; ++i)
9400     if (N->OperandList[i] != Ops[i])
9401       N->OperandList[i].set(Ops[i]);
9402 
9403   updateDivergence(N);
9404   // If this gets put into a CSE map, add it.
9405   if (InsertPos) CSEMap.InsertNode(N, InsertPos);
9406   return N;
9407 }
9408 
9409 /// DropOperands - Release the operands and set this node to have
9410 /// zero operands.
9411 void SDNode::DropOperands() {
9412   // Unlike the code in MorphNodeTo that does this, we don't need to
9413   // watch for dead nodes here.
9414   for (op_iterator I = op_begin(), E = op_end(); I != E; ) {
9415     SDUse &Use = *I++;
9416     Use.set(SDValue());
9417   }
9418 }
9419 
9420 void SelectionDAG::setNodeMemRefs(MachineSDNode *N,
9421                                   ArrayRef<MachineMemOperand *> NewMemRefs) {
9422   if (NewMemRefs.empty()) {
9423     N->clearMemRefs();
9424     return;
9425   }
9426 
9427   // Check if we can avoid allocating by storing a single reference directly.
9428   if (NewMemRefs.size() == 1) {
9429     N->MemRefs = NewMemRefs[0];
9430     N->NumMemRefs = 1;
9431     return;
9432   }
9433 
9434   MachineMemOperand **MemRefsBuffer =
9435       Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.size());
9436   llvm::copy(NewMemRefs, MemRefsBuffer);
9437   N->MemRefs = MemRefsBuffer;
9438   N->NumMemRefs = static_cast<int>(NewMemRefs.size());
9439 }
9440 
9441 /// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
9442 /// machine opcode.
9443 ///
9444 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9445                                    EVT VT) {
9446   SDVTList VTs = getVTList(VT);
9447   return SelectNodeTo(N, MachineOpc, VTs, None);
9448 }
9449 
9450 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9451                                    EVT VT, SDValue Op1) {
9452   SDVTList VTs = getVTList(VT);
9453   SDValue Ops[] = { Op1 };
9454   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9455 }
9456 
9457 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9458                                    EVT VT, SDValue Op1,
9459                                    SDValue Op2) {
9460   SDVTList VTs = getVTList(VT);
9461   SDValue Ops[] = { Op1, Op2 };
9462   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9463 }
9464 
9465 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9466                                    EVT VT, SDValue Op1,
9467                                    SDValue Op2, SDValue Op3) {
9468   SDVTList VTs = getVTList(VT);
9469   SDValue Ops[] = { Op1, Op2, Op3 };
9470   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9471 }
9472 
9473 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9474                                    EVT VT, ArrayRef<SDValue> Ops) {
9475   SDVTList VTs = getVTList(VT);
9476   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9477 }
9478 
9479 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9480                                    EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) {
9481   SDVTList VTs = getVTList(VT1, VT2);
9482   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9483 }
9484 
9485 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9486                                    EVT VT1, EVT VT2) {
9487   SDVTList VTs = getVTList(VT1, VT2);
9488   return SelectNodeTo(N, MachineOpc, VTs, None);
9489 }
9490 
9491 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9492                                    EVT VT1, EVT VT2, EVT VT3,
9493                                    ArrayRef<SDValue> Ops) {
9494   SDVTList VTs = getVTList(VT1, VT2, VT3);
9495   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9496 }
9497 
9498 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9499                                    EVT VT1, EVT VT2,
9500                                    SDValue Op1, SDValue Op2) {
9501   SDVTList VTs = getVTList(VT1, VT2);
9502   SDValue Ops[] = { Op1, Op2 };
9503   return SelectNodeTo(N, MachineOpc, VTs, Ops);
9504 }
9505 
9506 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
9507                                    SDVTList VTs,ArrayRef<SDValue> Ops) {
9508   SDNode *New = MorphNodeTo(N, ~MachineOpc, VTs, Ops);
9509   // Reset the NodeID to -1.
9510   New->setNodeId(-1);
9511   if (New != N) {
9512     ReplaceAllUsesWith(N, New);
9513     RemoveDeadNode(N);
9514   }
9515   return New;
9516 }
9517 
9518 /// UpdateSDLocOnMergeSDNode - If the opt level is -O0 then it throws away
9519 /// the line number information on the merged node since it is not possible to
9520 /// preserve the information that operation is associated with multiple lines.
9521 /// This will make the debugger working better at -O0, were there is a higher
9522 /// probability having other instructions associated with that line.
9523 ///
9524 /// For IROrder, we keep the smaller of the two
9525 SDNode *SelectionDAG::UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &OLoc) {
9526   DebugLoc NLoc = N->getDebugLoc();
9527   if (NLoc && OptLevel == CodeGenOpt::None && OLoc.getDebugLoc() != NLoc) {
9528     N->setDebugLoc(DebugLoc());
9529   }
9530   unsigned Order = std::min(N->getIROrder(), OLoc.getIROrder());
9531   N->setIROrder(Order);
9532   return N;
9533 }
9534 
9535 /// MorphNodeTo - This *mutates* the specified node to have the specified
9536 /// return type, opcode, and operands.
9537 ///
9538 /// Note that MorphNodeTo returns the resultant node.  If there is already a
9539 /// node of the specified opcode and operands, it returns that node instead of
9540 /// the current one.  Note that the SDLoc need not be the same.
9541 ///
9542 /// Using MorphNodeTo is faster than creating a new node and swapping it in
9543 /// with ReplaceAllUsesWith both because it often avoids allocating a new
9544 /// node, and because it doesn't require CSE recalculation for any of
9545 /// the node's users.
9546 ///
9547 /// However, note that MorphNodeTo recursively deletes dead nodes from the DAG.
9548 /// As a consequence it isn't appropriate to use from within the DAG combiner or
9549 /// the legalizer which maintain worklists that would need to be updated when
9550 /// deleting things.
9551 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
9552                                   SDVTList VTs, ArrayRef<SDValue> Ops) {
9553   // If an identical node already exists, use it.
9554   void *IP = nullptr;
9555   if (VTs.VTs[VTs.NumVTs-1] != MVT::Glue) {
9556     FoldingSetNodeID ID;
9557     AddNodeIDNode(ID, Opc, VTs, Ops);
9558     if (SDNode *ON = FindNodeOrInsertPos(ID, SDLoc(N), IP))
9559       return UpdateSDLocOnMergeSDNode(ON, SDLoc(N));
9560   }
9561 
9562   if (!RemoveNodeFromCSEMaps(N))
9563     IP = nullptr;
9564 
9565   // Start the morphing.
9566   N->NodeType = Opc;
9567   N->ValueList = VTs.VTs;
9568   N->NumValues = VTs.NumVTs;
9569 
9570   // Clear the operands list, updating used nodes to remove this from their
9571   // use list.  Keep track of any operands that become dead as a result.
9572   SmallPtrSet<SDNode*, 16> DeadNodeSet;
9573   for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
9574     SDUse &Use = *I++;
9575     SDNode *Used = Use.getNode();
9576     Use.set(SDValue());
9577     if (Used->use_empty())
9578       DeadNodeSet.insert(Used);
9579   }
9580 
9581   // For MachineNode, initialize the memory references information.
9582   if (MachineSDNode *MN = dyn_cast<MachineSDNode>(N))
9583     MN->clearMemRefs();
9584 
9585   // Swap for an appropriately sized array from the recycler.
9586   removeOperands(N);
9587   createOperands(N, Ops);
9588 
9589   // Delete any nodes that are still dead after adding the uses for the
9590   // new operands.
9591   if (!DeadNodeSet.empty()) {
9592     SmallVector<SDNode *, 16> DeadNodes;
9593     for (SDNode *N : DeadNodeSet)
9594       if (N->use_empty())
9595         DeadNodes.push_back(N);
9596     RemoveDeadNodes(DeadNodes);
9597   }
9598 
9599   if (IP)
9600     CSEMap.InsertNode(N, IP);   // Memoize the new node.
9601   return N;
9602 }
9603 
9604 SDNode* SelectionDAG::mutateStrictFPToFP(SDNode *Node) {
9605   unsigned OrigOpc = Node->getOpcode();
9606   unsigned NewOpc;
9607   switch (OrigOpc) {
9608   default:
9609     llvm_unreachable("mutateStrictFPToFP called with unexpected opcode!");
9610 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
9611   case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
9612 #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
9613   case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
9614 #include "llvm/IR/ConstrainedOps.def"
9615   }
9616 
9617   assert(Node->getNumValues() == 2 && "Unexpected number of results!");
9618 
9619   // We're taking this node out of the chain, so we need to re-link things.
9620   SDValue InputChain = Node->getOperand(0);
9621   SDValue OutputChain = SDValue(Node, 1);
9622   ReplaceAllUsesOfValueWith(OutputChain, InputChain);
9623 
9624   SmallVector<SDValue, 3> Ops;
9625   for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
9626     Ops.push_back(Node->getOperand(i));
9627 
9628   SDVTList VTs = getVTList(Node->getValueType(0));
9629   SDNode *Res = MorphNodeTo(Node, NewOpc, VTs, Ops);
9630 
9631   // MorphNodeTo can operate in two ways: if an existing node with the
9632   // specified operands exists, it can just return it.  Otherwise, it
9633   // updates the node in place to have the requested operands.
9634   if (Res == Node) {
9635     // If we updated the node in place, reset the node ID.  To the isel,
9636     // this should be just like a newly allocated machine node.
9637     Res->setNodeId(-1);
9638   } else {
9639     ReplaceAllUsesWith(Node, Res);
9640     RemoveDeadNode(Node);
9641   }
9642 
9643   return Res;
9644 }
9645 
9646 /// getMachineNode - These are used for target selectors to create a new node
9647 /// with specified return type(s), MachineInstr opcode, and operands.
9648 ///
9649 /// Note that getMachineNode returns the resultant node.  If there is already a
9650 /// node of the specified opcode and operands, it returns that node instead of
9651 /// the current one.
9652 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9653                                             EVT VT) {
9654   SDVTList VTs = getVTList(VT);
9655   return getMachineNode(Opcode, dl, VTs, None);
9656 }
9657 
9658 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9659                                             EVT VT, SDValue Op1) {
9660   SDVTList VTs = getVTList(VT);
9661   SDValue Ops[] = { Op1 };
9662   return getMachineNode(Opcode, dl, VTs, Ops);
9663 }
9664 
9665 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9666                                             EVT VT, SDValue Op1, SDValue Op2) {
9667   SDVTList VTs = getVTList(VT);
9668   SDValue Ops[] = { Op1, Op2 };
9669   return getMachineNode(Opcode, dl, VTs, Ops);
9670 }
9671 
9672 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9673                                             EVT VT, SDValue Op1, SDValue Op2,
9674                                             SDValue Op3) {
9675   SDVTList VTs = getVTList(VT);
9676   SDValue Ops[] = { Op1, Op2, Op3 };
9677   return getMachineNode(Opcode, dl, VTs, Ops);
9678 }
9679 
9680 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9681                                             EVT VT, ArrayRef<SDValue> Ops) {
9682   SDVTList VTs = getVTList(VT);
9683   return getMachineNode(Opcode, dl, VTs, Ops);
9684 }
9685 
9686 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9687                                             EVT VT1, EVT VT2, SDValue Op1,
9688                                             SDValue Op2) {
9689   SDVTList VTs = getVTList(VT1, VT2);
9690   SDValue Ops[] = { Op1, Op2 };
9691   return getMachineNode(Opcode, dl, VTs, Ops);
9692 }
9693 
9694 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9695                                             EVT VT1, EVT VT2, SDValue Op1,
9696                                             SDValue Op2, SDValue Op3) {
9697   SDVTList VTs = getVTList(VT1, VT2);
9698   SDValue Ops[] = { Op1, Op2, Op3 };
9699   return getMachineNode(Opcode, dl, VTs, Ops);
9700 }
9701 
9702 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9703                                             EVT VT1, EVT VT2,
9704                                             ArrayRef<SDValue> Ops) {
9705   SDVTList VTs = getVTList(VT1, VT2);
9706   return getMachineNode(Opcode, dl, VTs, Ops);
9707 }
9708 
9709 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9710                                             EVT VT1, EVT VT2, EVT VT3,
9711                                             SDValue Op1, SDValue Op2) {
9712   SDVTList VTs = getVTList(VT1, VT2, VT3);
9713   SDValue Ops[] = { Op1, Op2 };
9714   return getMachineNode(Opcode, dl, VTs, Ops);
9715 }
9716 
9717 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9718                                             EVT VT1, EVT VT2, EVT VT3,
9719                                             SDValue Op1, SDValue Op2,
9720                                             SDValue Op3) {
9721   SDVTList VTs = getVTList(VT1, VT2, VT3);
9722   SDValue Ops[] = { Op1, Op2, Op3 };
9723   return getMachineNode(Opcode, dl, VTs, Ops);
9724 }
9725 
9726 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9727                                             EVT VT1, EVT VT2, EVT VT3,
9728                                             ArrayRef<SDValue> Ops) {
9729   SDVTList VTs = getVTList(VT1, VT2, VT3);
9730   return getMachineNode(Opcode, dl, VTs, Ops);
9731 }
9732 
9733 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
9734                                             ArrayRef<EVT> ResultTys,
9735                                             ArrayRef<SDValue> Ops) {
9736   SDVTList VTs = getVTList(ResultTys);
9737   return getMachineNode(Opcode, dl, VTs, Ops);
9738 }
9739 
9740 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &DL,
9741                                             SDVTList VTs,
9742                                             ArrayRef<SDValue> Ops) {
9743   bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Glue;
9744   MachineSDNode *N;
9745   void *IP = nullptr;
9746 
9747   if (DoCSE) {
9748     FoldingSetNodeID ID;
9749     AddNodeIDNode(ID, ~Opcode, VTs, Ops);
9750     IP = nullptr;
9751     if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
9752       return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(E, DL));
9753     }
9754   }
9755 
9756   // Allocate a new MachineSDNode.
9757   N = newSDNode<MachineSDNode>(~Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
9758   createOperands(N, Ops);
9759 
9760   if (DoCSE)
9761     CSEMap.InsertNode(N, IP);
9762 
9763   InsertNode(N);
9764   NewSDValueDbgMsg(SDValue(N, 0), "Creating new machine node: ", this);
9765   return N;
9766 }
9767 
9768 /// getTargetExtractSubreg - A convenience function for creating
9769 /// TargetOpcode::EXTRACT_SUBREG nodes.
9770 SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
9771                                              SDValue Operand) {
9772   SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
9773   SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
9774                                   VT, Operand, SRIdxVal);
9775   return SDValue(Subreg, 0);
9776 }
9777 
9778 /// getTargetInsertSubreg - A convenience function for creating
9779 /// TargetOpcode::INSERT_SUBREG nodes.
9780 SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
9781                                             SDValue Operand, SDValue Subreg) {
9782   SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
9783   SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
9784                                   VT, Operand, Subreg, SRIdxVal);
9785   return SDValue(Result, 0);
9786 }
9787 
9788 /// getNodeIfExists - Get the specified node if it's already available, or
9789 /// else return NULL.
9790 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
9791                                       ArrayRef<SDValue> Ops) {
9792   SDNodeFlags Flags;
9793   if (Inserter)
9794     Flags = Inserter->getFlags();
9795   return getNodeIfExists(Opcode, VTList, Ops, Flags);
9796 }
9797 
9798 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
9799                                       ArrayRef<SDValue> Ops,
9800                                       const SDNodeFlags Flags) {
9801   if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
9802     FoldingSetNodeID ID;
9803     AddNodeIDNode(ID, Opcode, VTList, Ops);
9804     void *IP = nullptr;
9805     if (SDNode *E = FindNodeOrInsertPos(ID, SDLoc(), IP)) {
9806       E->intersectFlagsWith(Flags);
9807       return E;
9808     }
9809   }
9810   return nullptr;
9811 }
9812 
9813 /// doesNodeExist - Check if a node exists without modifying its flags.
9814 bool SelectionDAG::doesNodeExist(unsigned Opcode, SDVTList VTList,
9815                                  ArrayRef<SDValue> Ops) {
9816   if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
9817     FoldingSetNodeID ID;
9818     AddNodeIDNode(ID, Opcode, VTList, Ops);
9819     void *IP = nullptr;
9820     if (FindNodeOrInsertPos(ID, SDLoc(), IP))
9821       return true;
9822   }
9823   return false;
9824 }
9825 
9826 /// getDbgValue - Creates a SDDbgValue node.
9827 ///
9828 /// SDNode
9829 SDDbgValue *SelectionDAG::getDbgValue(DIVariable *Var, DIExpression *Expr,
9830                                       SDNode *N, unsigned R, bool IsIndirect,
9831                                       const DebugLoc &DL, unsigned O) {
9832   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9833          "Expected inlined-at fields to agree");
9834   return new (DbgInfo->getAlloc())
9835       SDDbgValue(DbgInfo->getAlloc(), Var, Expr, SDDbgOperand::fromNode(N, R),
9836                  {}, IsIndirect, DL, O,
9837                  /*IsVariadic=*/false);
9838 }
9839 
9840 /// Constant
9841 SDDbgValue *SelectionDAG::getConstantDbgValue(DIVariable *Var,
9842                                               DIExpression *Expr,
9843                                               const Value *C,
9844                                               const DebugLoc &DL, unsigned O) {
9845   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9846          "Expected inlined-at fields to agree");
9847   return new (DbgInfo->getAlloc())
9848       SDDbgValue(DbgInfo->getAlloc(), Var, Expr, SDDbgOperand::fromConst(C), {},
9849                  /*IsIndirect=*/false, DL, O,
9850                  /*IsVariadic=*/false);
9851 }
9852 
9853 /// FrameIndex
9854 SDDbgValue *SelectionDAG::getFrameIndexDbgValue(DIVariable *Var,
9855                                                 DIExpression *Expr, unsigned FI,
9856                                                 bool IsIndirect,
9857                                                 const DebugLoc &DL,
9858                                                 unsigned O) {
9859   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9860          "Expected inlined-at fields to agree");
9861   return getFrameIndexDbgValue(Var, Expr, FI, {}, IsIndirect, DL, O);
9862 }
9863 
9864 /// FrameIndex with dependencies
9865 SDDbgValue *SelectionDAG::getFrameIndexDbgValue(DIVariable *Var,
9866                                                 DIExpression *Expr, unsigned FI,
9867                                                 ArrayRef<SDNode *> Dependencies,
9868                                                 bool IsIndirect,
9869                                                 const DebugLoc &DL,
9870                                                 unsigned O) {
9871   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9872          "Expected inlined-at fields to agree");
9873   return new (DbgInfo->getAlloc())
9874       SDDbgValue(DbgInfo->getAlloc(), Var, Expr, SDDbgOperand::fromFrameIdx(FI),
9875                  Dependencies, IsIndirect, DL, O,
9876                  /*IsVariadic=*/false);
9877 }
9878 
9879 /// VReg
9880 SDDbgValue *SelectionDAG::getVRegDbgValue(DIVariable *Var, DIExpression *Expr,
9881                                           unsigned VReg, bool IsIndirect,
9882                                           const DebugLoc &DL, unsigned O) {
9883   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9884          "Expected inlined-at fields to agree");
9885   return new (DbgInfo->getAlloc())
9886       SDDbgValue(DbgInfo->getAlloc(), Var, Expr, SDDbgOperand::fromVReg(VReg),
9887                  {}, IsIndirect, DL, O,
9888                  /*IsVariadic=*/false);
9889 }
9890 
9891 SDDbgValue *SelectionDAG::getDbgValueList(DIVariable *Var, DIExpression *Expr,
9892                                           ArrayRef<SDDbgOperand> Locs,
9893                                           ArrayRef<SDNode *> Dependencies,
9894                                           bool IsIndirect, const DebugLoc &DL,
9895                                           unsigned O, bool IsVariadic) {
9896   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
9897          "Expected inlined-at fields to agree");
9898   return new (DbgInfo->getAlloc())
9899       SDDbgValue(DbgInfo->getAlloc(), Var, Expr, Locs, Dependencies, IsIndirect,
9900                  DL, O, IsVariadic);
9901 }
9902 
9903 void SelectionDAG::transferDbgValues(SDValue From, SDValue To,
9904                                      unsigned OffsetInBits, unsigned SizeInBits,
9905                                      bool InvalidateDbg) {
9906   SDNode *FromNode = From.getNode();
9907   SDNode *ToNode = To.getNode();
9908   assert(FromNode && ToNode && "Can't modify dbg values");
9909 
9910   // PR35338
9911   // TODO: assert(From != To && "Redundant dbg value transfer");
9912   // TODO: assert(FromNode != ToNode && "Intranode dbg value transfer");
9913   if (From == To || FromNode == ToNode)
9914     return;
9915 
9916   if (!FromNode->getHasDebugValue())
9917     return;
9918 
9919   SDDbgOperand FromLocOp =
9920       SDDbgOperand::fromNode(From.getNode(), From.getResNo());
9921   SDDbgOperand ToLocOp = SDDbgOperand::fromNode(To.getNode(), To.getResNo());
9922 
9923   SmallVector<SDDbgValue *, 2> ClonedDVs;
9924   for (SDDbgValue *Dbg : GetDbgValues(FromNode)) {
9925     if (Dbg->isInvalidated())
9926       continue;
9927 
9928     // TODO: assert(!Dbg->isInvalidated() && "Transfer of invalid dbg value");
9929 
9930     // Create a new location ops vector that is equal to the old vector, but
9931     // with each instance of FromLocOp replaced with ToLocOp.
9932     bool Changed = false;
9933     auto NewLocOps = Dbg->copyLocationOps();
9934     std::replace_if(
9935         NewLocOps.begin(), NewLocOps.end(),
9936         [&Changed, FromLocOp](const SDDbgOperand &Op) {
9937           bool Match = Op == FromLocOp;
9938           Changed |= Match;
9939           return Match;
9940         },
9941         ToLocOp);
9942     // Ignore this SDDbgValue if we didn't find a matching location.
9943     if (!Changed)
9944       continue;
9945 
9946     DIVariable *Var = Dbg->getVariable();
9947     auto *Expr = Dbg->getExpression();
9948     // If a fragment is requested, update the expression.
9949     if (SizeInBits) {
9950       // When splitting a larger (e.g., sign-extended) value whose
9951       // lower bits are described with an SDDbgValue, do not attempt
9952       // to transfer the SDDbgValue to the upper bits.
9953       if (auto FI = Expr->getFragmentInfo())
9954         if (OffsetInBits + SizeInBits > FI->SizeInBits)
9955           continue;
9956       auto Fragment = DIExpression::createFragmentExpression(Expr, OffsetInBits,
9957                                                              SizeInBits);
9958       if (!Fragment)
9959         continue;
9960       Expr = *Fragment;
9961     }
9962 
9963     auto AdditionalDependencies = Dbg->getAdditionalDependencies();
9964     // Clone the SDDbgValue and move it to To.
9965     SDDbgValue *Clone = getDbgValueList(
9966         Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
9967         Dbg->getDebugLoc(), std::max(ToNode->getIROrder(), Dbg->getOrder()),
9968         Dbg->isVariadic());
9969     ClonedDVs.push_back(Clone);
9970 
9971     if (InvalidateDbg) {
9972       // Invalidate value and indicate the SDDbgValue should not be emitted.
9973       Dbg->setIsInvalidated();
9974       Dbg->setIsEmitted();
9975     }
9976   }
9977 
9978   for (SDDbgValue *Dbg : ClonedDVs) {
9979     assert(is_contained(Dbg->getSDNodes(), ToNode) &&
9980            "Transferred DbgValues should depend on the new SDNode");
9981     AddDbgValue(Dbg, false);
9982   }
9983 }
9984 
9985 void SelectionDAG::salvageDebugInfo(SDNode &N) {
9986   if (!N.getHasDebugValue())
9987     return;
9988 
9989   SmallVector<SDDbgValue *, 2> ClonedDVs;
9990   for (auto *DV : GetDbgValues(&N)) {
9991     if (DV->isInvalidated())
9992       continue;
9993     switch (N.getOpcode()) {
9994     default:
9995       break;
9996     case ISD::ADD:
9997       SDValue N0 = N.getOperand(0);
9998       SDValue N1 = N.getOperand(1);
9999       if (!isConstantIntBuildVectorOrConstantInt(N0) &&
10000           isConstantIntBuildVectorOrConstantInt(N1)) {
10001         uint64_t Offset = N.getConstantOperandVal(1);
10002 
10003         // Rewrite an ADD constant node into a DIExpression. Since we are
10004         // performing arithmetic to compute the variable's *value* in the
10005         // DIExpression, we need to mark the expression with a
10006         // DW_OP_stack_value.
10007         auto *DIExpr = DV->getExpression();
10008         auto NewLocOps = DV->copyLocationOps();
10009         bool Changed = false;
10010         for (size_t i = 0; i < NewLocOps.size(); ++i) {
10011           // We're not given a ResNo to compare against because the whole
10012           // node is going away. We know that any ISD::ADD only has one
10013           // result, so we can assume any node match is using the result.
10014           if (NewLocOps[i].getKind() != SDDbgOperand::SDNODE ||
10015               NewLocOps[i].getSDNode() != &N)
10016             continue;
10017           NewLocOps[i] = SDDbgOperand::fromNode(N0.getNode(), N0.getResNo());
10018           SmallVector<uint64_t, 3> ExprOps;
10019           DIExpression::appendOffset(ExprOps, Offset);
10020           DIExpr = DIExpression::appendOpsToArg(DIExpr, ExprOps, i, true);
10021           Changed = true;
10022         }
10023         (void)Changed;
10024         assert(Changed && "Salvage target doesn't use N");
10025 
10026         auto AdditionalDependencies = DV->getAdditionalDependencies();
10027         SDDbgValue *Clone = getDbgValueList(DV->getVariable(), DIExpr,
10028                                             NewLocOps, AdditionalDependencies,
10029                                             DV->isIndirect(), DV->getDebugLoc(),
10030                                             DV->getOrder(), DV->isVariadic());
10031         ClonedDVs.push_back(Clone);
10032         DV->setIsInvalidated();
10033         DV->setIsEmitted();
10034         LLVM_DEBUG(dbgs() << "SALVAGE: Rewriting";
10035                    N0.getNode()->dumprFull(this);
10036                    dbgs() << " into " << *DIExpr << '\n');
10037       }
10038     }
10039   }
10040 
10041   for (SDDbgValue *Dbg : ClonedDVs) {
10042     assert(!Dbg->getSDNodes().empty() &&
10043            "Salvaged DbgValue should depend on a new SDNode");
10044     AddDbgValue(Dbg, false);
10045   }
10046 }
10047 
10048 /// Creates a SDDbgLabel node.
10049 SDDbgLabel *SelectionDAG::getDbgLabel(DILabel *Label,
10050                                       const DebugLoc &DL, unsigned O) {
10051   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
10052          "Expected inlined-at fields to agree");
10053   return new (DbgInfo->getAlloc()) SDDbgLabel(Label, DL, O);
10054 }
10055 
10056 namespace {
10057 
10058 /// RAUWUpdateListener - Helper for ReplaceAllUsesWith - When the node
10059 /// pointed to by a use iterator is deleted, increment the use iterator
10060 /// so that it doesn't dangle.
10061 ///
10062 class RAUWUpdateListener : public SelectionDAG::DAGUpdateListener {
10063   SDNode::use_iterator &UI;
10064   SDNode::use_iterator &UE;
10065 
10066   void NodeDeleted(SDNode *N, SDNode *E) override {
10067     // Increment the iterator as needed.
10068     while (UI != UE && N == *UI)
10069       ++UI;
10070   }
10071 
10072 public:
10073   RAUWUpdateListener(SelectionDAG &d,
10074                      SDNode::use_iterator &ui,
10075                      SDNode::use_iterator &ue)
10076     : SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
10077 };
10078 
10079 } // end anonymous namespace
10080 
10081 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
10082 /// This can cause recursive merging of nodes in the DAG.
10083 ///
10084 /// This version assumes From has a single result value.
10085 ///
10086 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To) {
10087   SDNode *From = FromN.getNode();
10088   assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
10089          "Cannot replace with this method!");
10090   assert(From != To.getNode() && "Cannot replace uses of with self");
10091 
10092   // Preserve Debug Values
10093   transferDbgValues(FromN, To);
10094 
10095   // Iterate over all the existing uses of From. New uses will be added
10096   // to the beginning of the use list, which we avoid visiting.
10097   // This specifically avoids visiting uses of From that arise while the
10098   // replacement is happening, because any such uses would be the result
10099   // of CSE: If an existing node looks like From after one of its operands
10100   // is replaced by To, we don't want to replace of all its users with To
10101   // too. See PR3018 for more info.
10102   SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
10103   RAUWUpdateListener Listener(*this, UI, UE);
10104   while (UI != UE) {
10105     SDNode *User = *UI;
10106 
10107     // This node is about to morph, remove its old self from the CSE maps.
10108     RemoveNodeFromCSEMaps(User);
10109 
10110     // A user can appear in a use list multiple times, and when this
10111     // happens the uses are usually next to each other in the list.
10112     // To help reduce the number of CSE recomputations, process all
10113     // the uses of this user that we can find this way.
10114     do {
10115       SDUse &Use = UI.getUse();
10116       ++UI;
10117       Use.set(To);
10118       if (To->isDivergent() != From->isDivergent())
10119         updateDivergence(User);
10120     } while (UI != UE && *UI == User);
10121     // Now that we have modified User, add it back to the CSE maps.  If it
10122     // already exists there, recursively merge the results together.
10123     AddModifiedNodeToCSEMaps(User);
10124   }
10125 
10126   // If we just RAUW'd the root, take note.
10127   if (FromN == getRoot())
10128     setRoot(To);
10129 }
10130 
10131 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
10132 /// This can cause recursive merging of nodes in the DAG.
10133 ///
10134 /// This version assumes that for each value of From, there is a
10135 /// corresponding value in To in the same position with the same type.
10136 ///
10137 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) {
10138 #ifndef NDEBUG
10139   for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
10140     assert((!From->hasAnyUseOfValue(i) ||
10141             From->getValueType(i) == To->getValueType(i)) &&
10142            "Cannot use this version of ReplaceAllUsesWith!");
10143 #endif
10144 
10145   // Handle the trivial case.
10146   if (From == To)
10147     return;
10148 
10149   // Preserve Debug Info. Only do this if there's a use.
10150   for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
10151     if (From->hasAnyUseOfValue(i)) {
10152       assert((i < To->getNumValues()) && "Invalid To location");
10153       transferDbgValues(SDValue(From, i), SDValue(To, i));
10154     }
10155 
10156   // Iterate over just the existing users of From. See the comments in
10157   // the ReplaceAllUsesWith above.
10158   SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
10159   RAUWUpdateListener Listener(*this, UI, UE);
10160   while (UI != UE) {
10161     SDNode *User = *UI;
10162 
10163     // This node is about to morph, remove its old self from the CSE maps.
10164     RemoveNodeFromCSEMaps(User);
10165 
10166     // A user can appear in a use list multiple times, and when this
10167     // happens the uses are usually next to each other in the list.
10168     // To help reduce the number of CSE recomputations, process all
10169     // the uses of this user that we can find this way.
10170     do {
10171       SDUse &Use = UI.getUse();
10172       ++UI;
10173       Use.setNode(To);
10174       if (To->isDivergent() != From->isDivergent())
10175         updateDivergence(User);
10176     } while (UI != UE && *UI == User);
10177 
10178     // Now that we have modified User, add it back to the CSE maps.  If it
10179     // already exists there, recursively merge the results together.
10180     AddModifiedNodeToCSEMaps(User);
10181   }
10182 
10183   // If we just RAUW'd the root, take note.
10184   if (From == getRoot().getNode())
10185     setRoot(SDValue(To, getRoot().getResNo()));
10186 }
10187 
10188 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
10189 /// This can cause recursive merging of nodes in the DAG.
10190 ///
10191 /// This version can replace From with any result values.  To must match the
10192 /// number and types of values returned by From.
10193 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, const SDValue *To) {
10194   if (From->getNumValues() == 1)  // Handle the simple case efficiently.
10195     return ReplaceAllUsesWith(SDValue(From, 0), To[0]);
10196 
10197   // Preserve Debug Info.
10198   for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
10199     transferDbgValues(SDValue(From, i), To[i]);
10200 
10201   // Iterate over just the existing users of From. See the comments in
10202   // the ReplaceAllUsesWith above.
10203   SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
10204   RAUWUpdateListener Listener(*this, UI, UE);
10205   while (UI != UE) {
10206     SDNode *User = *UI;
10207 
10208     // This node is about to morph, remove its old self from the CSE maps.
10209     RemoveNodeFromCSEMaps(User);
10210 
10211     // A user can appear in a use list multiple times, and when this happens the
10212     // uses are usually next to each other in the list.  To help reduce the
10213     // number of CSE and divergence recomputations, process all the uses of this
10214     // user that we can find this way.
10215     bool To_IsDivergent = false;
10216     do {
10217       SDUse &Use = UI.getUse();
10218       const SDValue &ToOp = To[Use.getResNo()];
10219       ++UI;
10220       Use.set(ToOp);
10221       To_IsDivergent |= ToOp->isDivergent();
10222     } while (UI != UE && *UI == User);
10223 
10224     if (To_IsDivergent != From->isDivergent())
10225       updateDivergence(User);
10226 
10227     // Now that we have modified User, add it back to the CSE maps.  If it
10228     // already exists there, recursively merge the results together.
10229     AddModifiedNodeToCSEMaps(User);
10230   }
10231 
10232   // If we just RAUW'd the root, take note.
10233   if (From == getRoot().getNode())
10234     setRoot(SDValue(To[getRoot().getResNo()]));
10235 }
10236 
10237 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
10238 /// uses of other values produced by From.getNode() alone.  The Deleted
10239 /// vector is handled the same way as for ReplaceAllUsesWith.
10240 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To){
10241   // Handle the really simple, really trivial case efficiently.
10242   if (From == To) return;
10243 
10244   // Handle the simple, trivial, case efficiently.
10245   if (From.getNode()->getNumValues() == 1) {
10246     ReplaceAllUsesWith(From, To);
10247     return;
10248   }
10249 
10250   // Preserve Debug Info.
10251   transferDbgValues(From, To);
10252 
10253   // Iterate over just the existing users of From. See the comments in
10254   // the ReplaceAllUsesWith above.
10255   SDNode::use_iterator UI = From.getNode()->use_begin(),
10256                        UE = From.getNode()->use_end();
10257   RAUWUpdateListener Listener(*this, UI, UE);
10258   while (UI != UE) {
10259     SDNode *User = *UI;
10260     bool UserRemovedFromCSEMaps = false;
10261 
10262     // A user can appear in a use list multiple times, and when this
10263     // happens the uses are usually next to each other in the list.
10264     // To help reduce the number of CSE recomputations, process all
10265     // the uses of this user that we can find this way.
10266     do {
10267       SDUse &Use = UI.getUse();
10268 
10269       // Skip uses of different values from the same node.
10270       if (Use.getResNo() != From.getResNo()) {
10271         ++UI;
10272         continue;
10273       }
10274 
10275       // If this node hasn't been modified yet, it's still in the CSE maps,
10276       // so remove its old self from the CSE maps.
10277       if (!UserRemovedFromCSEMaps) {
10278         RemoveNodeFromCSEMaps(User);
10279         UserRemovedFromCSEMaps = true;
10280       }
10281 
10282       ++UI;
10283       Use.set(To);
10284       if (To->isDivergent() != From->isDivergent())
10285         updateDivergence(User);
10286     } while (UI != UE && *UI == User);
10287     // We are iterating over all uses of the From node, so if a use
10288     // doesn't use the specific value, no changes are made.
10289     if (!UserRemovedFromCSEMaps)
10290       continue;
10291 
10292     // Now that we have modified User, add it back to the CSE maps.  If it
10293     // already exists there, recursively merge the results together.
10294     AddModifiedNodeToCSEMaps(User);
10295   }
10296 
10297   // If we just RAUW'd the root, take note.
10298   if (From == getRoot())
10299     setRoot(To);
10300 }
10301 
10302 namespace {
10303 
10304 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith
10305 /// to record information about a use.
10306 struct UseMemo {
10307   SDNode *User;
10308   unsigned Index;
10309   SDUse *Use;
10310 };
10311 
10312 /// operator< - Sort Memos by User.
10313 bool operator<(const UseMemo &L, const UseMemo &R) {
10314   return (intptr_t)L.User < (intptr_t)R.User;
10315 }
10316 
10317 /// RAUOVWUpdateListener - Helper for ReplaceAllUsesOfValuesWith - When the node
10318 /// pointed to by a UseMemo is deleted, set the User to nullptr to indicate that
10319 /// the node already has been taken care of recursively.
10320 class RAUOVWUpdateListener : public SelectionDAG::DAGUpdateListener {
10321   SmallVector<UseMemo, 4> &Uses;
10322 
10323   void NodeDeleted(SDNode *N, SDNode *E) override {
10324     for (UseMemo &Memo : Uses)
10325       if (Memo.User == N)
10326         Memo.User = nullptr;
10327   }
10328 
10329 public:
10330   RAUOVWUpdateListener(SelectionDAG &d, SmallVector<UseMemo, 4> &uses)
10331       : SelectionDAG::DAGUpdateListener(d), Uses(uses) {}
10332 };
10333 
10334 } // end anonymous namespace
10335 
10336 bool SelectionDAG::calculateDivergence(SDNode *N) {
10337   if (TLI->isSDNodeAlwaysUniform(N)) {
10338     assert(!TLI->isSDNodeSourceOfDivergence(N, FLI, DA) &&
10339            "Conflicting divergence information!");
10340     return false;
10341   }
10342   if (TLI->isSDNodeSourceOfDivergence(N, FLI, DA))
10343     return true;
10344   for (const auto &Op : N->ops()) {
10345     if (Op.Val.getValueType() != MVT::Other && Op.getNode()->isDivergent())
10346       return true;
10347   }
10348   return false;
10349 }
10350 
10351 void SelectionDAG::updateDivergence(SDNode *N) {
10352   SmallVector<SDNode *, 16> Worklist(1, N);
10353   do {
10354     N = Worklist.pop_back_val();
10355     bool IsDivergent = calculateDivergence(N);
10356     if (N->SDNodeBits.IsDivergent != IsDivergent) {
10357       N->SDNodeBits.IsDivergent = IsDivergent;
10358       llvm::append_range(Worklist, N->uses());
10359     }
10360   } while (!Worklist.empty());
10361 }
10362 
10363 void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
10364   DenseMap<SDNode *, unsigned> Degree;
10365   Order.reserve(AllNodes.size());
10366   for (auto &N : allnodes()) {
10367     unsigned NOps = N.getNumOperands();
10368     Degree[&N] = NOps;
10369     if (0 == NOps)
10370       Order.push_back(&N);
10371   }
10372   for (size_t I = 0; I != Order.size(); ++I) {
10373     SDNode *N = Order[I];
10374     for (auto *U : N->uses()) {
10375       unsigned &UnsortedOps = Degree[U];
10376       if (0 == --UnsortedOps)
10377         Order.push_back(U);
10378     }
10379   }
10380 }
10381 
10382 #ifndef NDEBUG
10383 void SelectionDAG::VerifyDAGDivergence() {
10384   std::vector<SDNode *> TopoOrder;
10385   CreateTopologicalOrder(TopoOrder);
10386   for (auto *N : TopoOrder) {
10387     assert(calculateDivergence(N) == N->isDivergent() &&
10388            "Divergence bit inconsistency detected");
10389   }
10390 }
10391 #endif
10392 
10393 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
10394 /// uses of other values produced by From.getNode() alone.  The same value
10395 /// may appear in both the From and To list.  The Deleted vector is
10396 /// handled the same way as for ReplaceAllUsesWith.
10397 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
10398                                               const SDValue *To,
10399                                               unsigned Num){
10400   // Handle the simple, trivial case efficiently.
10401   if (Num == 1)
10402     return ReplaceAllUsesOfValueWith(*From, *To);
10403 
10404   transferDbgValues(*From, *To);
10405 
10406   // Read up all the uses and make records of them. This helps
10407   // processing new uses that are introduced during the
10408   // replacement process.
10409   SmallVector<UseMemo, 4> Uses;
10410   for (unsigned i = 0; i != Num; ++i) {
10411     unsigned FromResNo = From[i].getResNo();
10412     SDNode *FromNode = From[i].getNode();
10413     for (SDNode::use_iterator UI = FromNode->use_begin(),
10414          E = FromNode->use_end(); UI != E; ++UI) {
10415       SDUse &Use = UI.getUse();
10416       if (Use.getResNo() == FromResNo) {
10417         UseMemo Memo = { *UI, i, &Use };
10418         Uses.push_back(Memo);
10419       }
10420     }
10421   }
10422 
10423   // Sort the uses, so that all the uses from a given User are together.
10424   llvm::sort(Uses);
10425   RAUOVWUpdateListener Listener(*this, Uses);
10426 
10427   for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
10428        UseIndex != UseIndexEnd; ) {
10429     // We know that this user uses some value of From.  If it is the right
10430     // value, update it.
10431     SDNode *User = Uses[UseIndex].User;
10432     // If the node has been deleted by recursive CSE updates when updating
10433     // another node, then just skip this entry.
10434     if (User == nullptr) {
10435       ++UseIndex;
10436       continue;
10437     }
10438 
10439     // This node is about to morph, remove its old self from the CSE maps.
10440     RemoveNodeFromCSEMaps(User);
10441 
10442     // The Uses array is sorted, so all the uses for a given User
10443     // are next to each other in the list.
10444     // To help reduce the number of CSE recomputations, process all
10445     // the uses of this user that we can find this way.
10446     do {
10447       unsigned i = Uses[UseIndex].Index;
10448       SDUse &Use = *Uses[UseIndex].Use;
10449       ++UseIndex;
10450 
10451       Use.set(To[i]);
10452     } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User);
10453 
10454     // Now that we have modified User, add it back to the CSE maps.  If it
10455     // already exists there, recursively merge the results together.
10456     AddModifiedNodeToCSEMaps(User);
10457   }
10458 }
10459 
10460 /// AssignTopologicalOrder - Assign a unique node id for each node in the DAG
10461 /// based on their topological order. It returns the maximum id and a vector
10462 /// of the SDNodes* in assigned order by reference.
10463 unsigned SelectionDAG::AssignTopologicalOrder() {
10464   unsigned DAGSize = 0;
10465 
10466   // SortedPos tracks the progress of the algorithm. Nodes before it are
10467   // sorted, nodes after it are unsorted. When the algorithm completes
10468   // it is at the end of the list.
10469   allnodes_iterator SortedPos = allnodes_begin();
10470 
10471   // Visit all the nodes. Move nodes with no operands to the front of
10472   // the list immediately. Annotate nodes that do have operands with their
10473   // operand count. Before we do this, the Node Id fields of the nodes
10474   // may contain arbitrary values. After, the Node Id fields for nodes
10475   // before SortedPos will contain the topological sort index, and the
10476   // Node Id fields for nodes At SortedPos and after will contain the
10477   // count of outstanding operands.
10478   for (SDNode &N : llvm::make_early_inc_range(allnodes())) {
10479     checkForCycles(&N, this);
10480     unsigned Degree = N.getNumOperands();
10481     if (Degree == 0) {
10482       // A node with no uses, add it to the result array immediately.
10483       N.setNodeId(DAGSize++);
10484       allnodes_iterator Q(&N);
10485       if (Q != SortedPos)
10486         SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
10487       assert(SortedPos != AllNodes.end() && "Overran node list");
10488       ++SortedPos;
10489     } else {
10490       // Temporarily use the Node Id as scratch space for the degree count.
10491       N.setNodeId(Degree);
10492     }
10493   }
10494 
10495   // Visit all the nodes. As we iterate, move nodes into sorted order,
10496   // such that by the time the end is reached all nodes will be sorted.
10497   for (SDNode &Node : allnodes()) {
10498     SDNode *N = &Node;
10499     checkForCycles(N, this);
10500     // N is in sorted position, so all its uses have one less operand
10501     // that needs to be sorted.
10502     for (SDNode *P : N->uses()) {
10503       unsigned Degree = P->getNodeId();
10504       assert(Degree != 0 && "Invalid node degree");
10505       --Degree;
10506       if (Degree == 0) {
10507         // All of P's operands are sorted, so P may sorted now.
10508         P->setNodeId(DAGSize++);
10509         if (P->getIterator() != SortedPos)
10510           SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P));
10511         assert(SortedPos != AllNodes.end() && "Overran node list");
10512         ++SortedPos;
10513       } else {
10514         // Update P's outstanding operand count.
10515         P->setNodeId(Degree);
10516       }
10517     }
10518     if (Node.getIterator() == SortedPos) {
10519 #ifndef NDEBUG
10520       allnodes_iterator I(N);
10521       SDNode *S = &*++I;
10522       dbgs() << "Overran sorted position:\n";
10523       S->dumprFull(this); dbgs() << "\n";
10524       dbgs() << "Checking if this is due to cycles\n";
10525       checkForCycles(this, true);
10526 #endif
10527       llvm_unreachable(nullptr);
10528     }
10529   }
10530 
10531   assert(SortedPos == AllNodes.end() &&
10532          "Topological sort incomplete!");
10533   assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
10534          "First node in topological sort is not the entry token!");
10535   assert(AllNodes.front().getNodeId() == 0 &&
10536          "First node in topological sort has non-zero id!");
10537   assert(AllNodes.front().getNumOperands() == 0 &&
10538          "First node in topological sort has operands!");
10539   assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
10540          "Last node in topologic sort has unexpected id!");
10541   assert(AllNodes.back().use_empty() &&
10542          "Last node in topologic sort has users!");
10543   assert(DAGSize == allnodes_size() && "Node count mismatch!");
10544   return DAGSize;
10545 }
10546 
10547 /// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
10548 /// value is produced by SD.
10549 void SelectionDAG::AddDbgValue(SDDbgValue *DB, bool isParameter) {
10550   for (SDNode *SD : DB->getSDNodes()) {
10551     if (!SD)
10552       continue;
10553     assert(DbgInfo->getSDDbgValues(SD).empty() || SD->getHasDebugValue());
10554     SD->setHasDebugValue(true);
10555   }
10556   DbgInfo->add(DB, isParameter);
10557 }
10558 
10559 void SelectionDAG::AddDbgLabel(SDDbgLabel *DB) { DbgInfo->add(DB); }
10560 
10561 SDValue SelectionDAG::makeEquivalentMemoryOrdering(SDValue OldChain,
10562                                                    SDValue NewMemOpChain) {
10563   assert(isa<MemSDNode>(NewMemOpChain) && "Expected a memop node");
10564   assert(NewMemOpChain.getValueType() == MVT::Other && "Expected a token VT");
10565   // The new memory operation must have the same position as the old load in
10566   // terms of memory dependency. Create a TokenFactor for the old load and new
10567   // memory operation and update uses of the old load's output chain to use that
10568   // TokenFactor.
10569   if (OldChain == NewMemOpChain || OldChain.use_empty())
10570     return NewMemOpChain;
10571 
10572   SDValue TokenFactor = getNode(ISD::TokenFactor, SDLoc(OldChain), MVT::Other,
10573                                 OldChain, NewMemOpChain);
10574   ReplaceAllUsesOfValueWith(OldChain, TokenFactor);
10575   UpdateNodeOperands(TokenFactor.getNode(), OldChain, NewMemOpChain);
10576   return TokenFactor;
10577 }
10578 
10579 SDValue SelectionDAG::makeEquivalentMemoryOrdering(LoadSDNode *OldLoad,
10580                                                    SDValue NewMemOp) {
10581   assert(isa<MemSDNode>(NewMemOp.getNode()) && "Expected a memop node");
10582   SDValue OldChain = SDValue(OldLoad, 1);
10583   SDValue NewMemOpChain = NewMemOp.getValue(1);
10584   return makeEquivalentMemoryOrdering(OldChain, NewMemOpChain);
10585 }
10586 
10587 SDValue SelectionDAG::getSymbolFunctionGlobalAddress(SDValue Op,
10588                                                      Function **OutFunction) {
10589   assert(isa<ExternalSymbolSDNode>(Op) && "Node should be an ExternalSymbol");
10590 
10591   auto *Symbol = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10592   auto *Module = MF->getFunction().getParent();
10593   auto *Function = Module->getFunction(Symbol);
10594 
10595   if (OutFunction != nullptr)
10596       *OutFunction = Function;
10597 
10598   if (Function != nullptr) {
10599     auto PtrTy = TLI->getPointerTy(getDataLayout(), Function->getAddressSpace());
10600     return getGlobalAddress(Function, SDLoc(Op), PtrTy);
10601   }
10602 
10603   std::string ErrorStr;
10604   raw_string_ostream ErrorFormatter(ErrorStr);
10605   ErrorFormatter << "Undefined external symbol ";
10606   ErrorFormatter << '"' << Symbol << '"';
10607   report_fatal_error(Twine(ErrorFormatter.str()));
10608 }
10609 
10610 //===----------------------------------------------------------------------===//
10611 //                              SDNode Class
10612 //===----------------------------------------------------------------------===//
10613 
10614 bool llvm::isNullConstant(SDValue V) {
10615   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
10616   return Const != nullptr && Const->isZero();
10617 }
10618 
10619 bool llvm::isNullFPConstant(SDValue V) {
10620   ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(V);
10621   return Const != nullptr && Const->isZero() && !Const->isNegative();
10622 }
10623 
10624 bool llvm::isAllOnesConstant(SDValue V) {
10625   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
10626   return Const != nullptr && Const->isAllOnes();
10627 }
10628 
10629 bool llvm::isOneConstant(SDValue V) {
10630   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
10631   return Const != nullptr && Const->isOne();
10632 }
10633 
10634 bool llvm::isMinSignedConstant(SDValue V) {
10635   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
10636   return Const != nullptr && Const->isMinSignedValue();
10637 }
10638 
10639 SDValue llvm::peekThroughBitcasts(SDValue V) {
10640   while (V.getOpcode() == ISD::BITCAST)
10641     V = V.getOperand(0);
10642   return V;
10643 }
10644 
10645 SDValue llvm::peekThroughOneUseBitcasts(SDValue V) {
10646   while (V.getOpcode() == ISD::BITCAST && V.getOperand(0).hasOneUse())
10647     V = V.getOperand(0);
10648   return V;
10649 }
10650 
10651 SDValue llvm::peekThroughExtractSubvectors(SDValue V) {
10652   while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR)
10653     V = V.getOperand(0);
10654   return V;
10655 }
10656 
10657 bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
10658   if (V.getOpcode() != ISD::XOR)
10659     return false;
10660   V = peekThroughBitcasts(V.getOperand(1));
10661   unsigned NumBits = V.getScalarValueSizeInBits();
10662   ConstantSDNode *C =
10663       isConstOrConstSplat(V, AllowUndefs, /*AllowTruncation*/ true);
10664   return C && (C->getAPIntValue().countTrailingOnes() >= NumBits);
10665 }
10666 
10667 ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, bool AllowUndefs,
10668                                           bool AllowTruncation) {
10669   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
10670     return CN;
10671 
10672   // SplatVectors can truncate their operands. Ignore that case here unless
10673   // AllowTruncation is set.
10674   if (N->getOpcode() == ISD::SPLAT_VECTOR) {
10675     EVT VecEltVT = N->getValueType(0).getVectorElementType();
10676     if (auto *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10677       EVT CVT = CN->getValueType(0);
10678       assert(CVT.bitsGE(VecEltVT) && "Illegal splat_vector element extension");
10679       if (AllowTruncation || CVT == VecEltVT)
10680         return CN;
10681     }
10682   }
10683 
10684   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
10685     BitVector UndefElements;
10686     ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
10687 
10688     // BuildVectors can truncate their operands. Ignore that case here unless
10689     // AllowTruncation is set.
10690     if (CN && (UndefElements.none() || AllowUndefs)) {
10691       EVT CVT = CN->getValueType(0);
10692       EVT NSVT = N.getValueType().getScalarType();
10693       assert(CVT.bitsGE(NSVT) && "Illegal build vector element extension");
10694       if (AllowTruncation || (CVT == NSVT))
10695         return CN;
10696     }
10697   }
10698 
10699   return nullptr;
10700 }
10701 
10702 ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
10703                                           bool AllowUndefs,
10704                                           bool AllowTruncation) {
10705   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
10706     return CN;
10707 
10708   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
10709     BitVector UndefElements;
10710     ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
10711 
10712     // BuildVectors can truncate their operands. Ignore that case here unless
10713     // AllowTruncation is set.
10714     if (CN && (UndefElements.none() || AllowUndefs)) {
10715       EVT CVT = CN->getValueType(0);
10716       EVT NSVT = N.getValueType().getScalarType();
10717       assert(CVT.bitsGE(NSVT) && "Illegal build vector element extension");
10718       if (AllowTruncation || (CVT == NSVT))
10719         return CN;
10720     }
10721   }
10722 
10723   return nullptr;
10724 }
10725 
10726 ConstantFPSDNode *llvm::isConstOrConstSplatFP(SDValue N, bool AllowUndefs) {
10727   if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
10728     return CN;
10729 
10730   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
10731     BitVector UndefElements;
10732     ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
10733     if (CN && (UndefElements.none() || AllowUndefs))
10734       return CN;
10735   }
10736 
10737   if (N.getOpcode() == ISD::SPLAT_VECTOR)
10738     if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
10739       return CN;
10740 
10741   return nullptr;
10742 }
10743 
10744 ConstantFPSDNode *llvm::isConstOrConstSplatFP(SDValue N,
10745                                               const APInt &DemandedElts,
10746                                               bool AllowUndefs) {
10747   if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
10748     return CN;
10749 
10750   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
10751     BitVector UndefElements;
10752     ConstantFPSDNode *CN =
10753         BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
10754     if (CN && (UndefElements.none() || AllowUndefs))
10755       return CN;
10756   }
10757 
10758   return nullptr;
10759 }
10760 
10761 bool llvm::isNullOrNullSplat(SDValue N, bool AllowUndefs) {
10762   // TODO: may want to use peekThroughBitcast() here.
10763   ConstantSDNode *C =
10764       isConstOrConstSplat(N, AllowUndefs, /*AllowTruncation=*/true);
10765   return C && C->isZero();
10766 }
10767 
10768 bool llvm::isOneOrOneSplat(SDValue N, bool AllowUndefs) {
10769   ConstantSDNode *C =
10770       isConstOrConstSplat(N, AllowUndefs, /*AllowTruncation*/ true);
10771   return C && C->isOne();
10772 }
10773 
10774 bool llvm::isAllOnesOrAllOnesSplat(SDValue N, bool AllowUndefs) {
10775   N = peekThroughBitcasts(N);
10776   unsigned BitWidth = N.getScalarValueSizeInBits();
10777   ConstantSDNode *C = isConstOrConstSplat(N, AllowUndefs);
10778   return C && C->isAllOnes() && C->getValueSizeInBits(0) == BitWidth;
10779 }
10780 
10781 HandleSDNode::~HandleSDNode() {
10782   DropOperands();
10783 }
10784 
10785 GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, unsigned Order,
10786                                          const DebugLoc &DL,
10787                                          const GlobalValue *GA, EVT VT,
10788                                          int64_t o, unsigned TF)
10789     : SDNode(Opc, Order, DL, getSDVTList(VT)), Offset(o), TargetFlags(TF) {
10790   TheGlobal = GA;
10791 }
10792 
10793 AddrSpaceCastSDNode::AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl,
10794                                          EVT VT, unsigned SrcAS,
10795                                          unsigned DestAS)
10796     : SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)),
10797       SrcAddrSpace(SrcAS), DestAddrSpace(DestAS) {}
10798 
10799 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
10800                      SDVTList VTs, EVT memvt, MachineMemOperand *mmo)
10801     : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
10802   MemSDNodeBits.IsVolatile = MMO->isVolatile();
10803   MemSDNodeBits.IsNonTemporal = MMO->isNonTemporal();
10804   MemSDNodeBits.IsDereferenceable = MMO->isDereferenceable();
10805   MemSDNodeBits.IsInvariant = MMO->isInvariant();
10806 
10807   // We check here that the size of the memory operand fits within the size of
10808   // the MMO. This is because the MMO might indicate only a possible address
10809   // range instead of specifying the affected memory addresses precisely.
10810   // TODO: Make MachineMemOperands aware of scalable vectors.
10811   assert(memvt.getStoreSize().getKnownMinSize() <= MMO->getSize() &&
10812          "Size mismatch!");
10813 }
10814 
10815 /// Profile - Gather unique data for the node.
10816 ///
10817 void SDNode::Profile(FoldingSetNodeID &ID) const {
10818   AddNodeIDNode(ID, this);
10819 }
10820 
10821 namespace {
10822 
10823   struct EVTArray {
10824     std::vector<EVT> VTs;
10825 
10826     EVTArray() {
10827       VTs.reserve(MVT::VALUETYPE_SIZE);
10828       for (unsigned i = 0; i < MVT::VALUETYPE_SIZE; ++i)
10829         VTs.push_back(MVT((MVT::SimpleValueType)i));
10830     }
10831   };
10832 
10833 } // end anonymous namespace
10834 
10835 /// getValueTypeList - Return a pointer to the specified value type.
10836 ///
10837 const EVT *SDNode::getValueTypeList(EVT VT) {
10838   static std::set<EVT, EVT::compareRawBits> EVTs;
10839   static EVTArray SimpleVTArray;
10840   static sys::SmartMutex<true> VTMutex;
10841 
10842   if (VT.isExtended()) {
10843     sys::SmartScopedLock<true> Lock(VTMutex);
10844     return &(*EVTs.insert(VT).first);
10845   }
10846   assert(VT.getSimpleVT() < MVT::VALUETYPE_SIZE && "Value type out of range!");
10847   return &SimpleVTArray.VTs[VT.getSimpleVT().SimpleTy];
10848 }
10849 
10850 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
10851 /// indicated value.  This method ignores uses of other values defined by this
10852 /// operation.
10853 bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
10854   assert(Value < getNumValues() && "Bad value!");
10855 
10856   // TODO: Only iterate over uses of a given value of the node
10857   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
10858     if (UI.getUse().getResNo() == Value) {
10859       if (NUses == 0)
10860         return false;
10861       --NUses;
10862     }
10863   }
10864 
10865   // Found exactly the right number of uses?
10866   return NUses == 0;
10867 }
10868 
10869 /// hasAnyUseOfValue - Return true if there are any use of the indicated
10870 /// value. This method ignores uses of other values defined by this operation.
10871 bool SDNode::hasAnyUseOfValue(unsigned Value) const {
10872   assert(Value < getNumValues() && "Bad value!");
10873 
10874   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
10875     if (UI.getUse().getResNo() == Value)
10876       return true;
10877 
10878   return false;
10879 }
10880 
10881 /// isOnlyUserOf - Return true if this node is the only use of N.
10882 bool SDNode::isOnlyUserOf(const SDNode *N) const {
10883   bool Seen = false;
10884   for (const SDNode *User : N->uses()) {
10885     if (User == this)
10886       Seen = true;
10887     else
10888       return false;
10889   }
10890 
10891   return Seen;
10892 }
10893 
10894 /// Return true if the only users of N are contained in Nodes.
10895 bool SDNode::areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N) {
10896   bool Seen = false;
10897   for (const SDNode *User : N->uses()) {
10898     if (llvm::is_contained(Nodes, User))
10899       Seen = true;
10900     else
10901       return false;
10902   }
10903 
10904   return Seen;
10905 }
10906 
10907 /// isOperand - Return true if this node is an operand of N.
10908 bool SDValue::isOperandOf(const SDNode *N) const {
10909   return is_contained(N->op_values(), *this);
10910 }
10911 
10912 bool SDNode::isOperandOf(const SDNode *N) const {
10913   return any_of(N->op_values(),
10914                 [this](SDValue Op) { return this == Op.getNode(); });
10915 }
10916 
10917 /// reachesChainWithoutSideEffects - Return true if this operand (which must
10918 /// be a chain) reaches the specified operand without crossing any
10919 /// side-effecting instructions on any chain path.  In practice, this looks
10920 /// through token factors and non-volatile loads.  In order to remain efficient,
10921 /// this only looks a couple of nodes in, it does not do an exhaustive search.
10922 ///
10923 /// Note that we only need to examine chains when we're searching for
10924 /// side-effects; SelectionDAG requires that all side-effects are represented
10925 /// by chains, even if another operand would force a specific ordering. This
10926 /// constraint is necessary to allow transformations like splitting loads.
10927 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
10928                                              unsigned Depth) const {
10929   if (*this == Dest) return true;
10930 
10931   // Don't search too deeply, we just want to be able to see through
10932   // TokenFactor's etc.
10933   if (Depth == 0) return false;
10934 
10935   // If this is a token factor, all inputs to the TF happen in parallel.
10936   if (getOpcode() == ISD::TokenFactor) {
10937     // First, try a shallow search.
10938     if (is_contained((*this)->ops(), Dest)) {
10939       // We found the chain we want as an operand of this TokenFactor.
10940       // Essentially, we reach the chain without side-effects if we could
10941       // serialize the TokenFactor into a simple chain of operations with
10942       // Dest as the last operation. This is automatically true if the
10943       // chain has one use: there are no other ordering constraints.
10944       // If the chain has more than one use, we give up: some other
10945       // use of Dest might force a side-effect between Dest and the current
10946       // node.
10947       if (Dest.hasOneUse())
10948         return true;
10949     }
10950     // Next, try a deep search: check whether every operand of the TokenFactor
10951     // reaches Dest.
10952     return llvm::all_of((*this)->ops(), [=](SDValue Op) {
10953       return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
10954     });
10955   }
10956 
10957   // Loads don't have side effects, look through them.
10958   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
10959     if (Ld->isUnordered())
10960       return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
10961   }
10962   return false;
10963 }
10964 
10965 bool SDNode::hasPredecessor(const SDNode *N) const {
10966   SmallPtrSet<const SDNode *, 32> Visited;
10967   SmallVector<const SDNode *, 16> Worklist;
10968   Worklist.push_back(this);
10969   return hasPredecessorHelper(N, Visited, Worklist);
10970 }
10971 
10972 void SDNode::intersectFlagsWith(const SDNodeFlags Flags) {
10973   this->Flags.intersectWith(Flags);
10974 }
10975 
10976 SDValue
10977 SelectionDAG::matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp,
10978                                   ArrayRef<ISD::NodeType> CandidateBinOps,
10979                                   bool AllowPartials) {
10980   // The pattern must end in an extract from index 0.
10981   if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10982       !isNullConstant(Extract->getOperand(1)))
10983     return SDValue();
10984 
10985   // Match against one of the candidate binary ops.
10986   SDValue Op = Extract->getOperand(0);
10987   if (llvm::none_of(CandidateBinOps, [Op](ISD::NodeType BinOp) {
10988         return Op.getOpcode() == unsigned(BinOp);
10989       }))
10990     return SDValue();
10991 
10992   // Floating-point reductions may require relaxed constraints on the final step
10993   // of the reduction because they may reorder intermediate operations.
10994   unsigned CandidateBinOp = Op.getOpcode();
10995   if (Op.getValueType().isFloatingPoint()) {
10996     SDNodeFlags Flags = Op->getFlags();
10997     switch (CandidateBinOp) {
10998     case ISD::FADD:
10999       if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
11000         return SDValue();
11001       break;
11002     default:
11003       llvm_unreachable("Unhandled FP opcode for binop reduction");
11004     }
11005   }
11006 
11007   // Matching failed - attempt to see if we did enough stages that a partial
11008   // reduction from a subvector is possible.
11009   auto PartialReduction = [&](SDValue Op, unsigned NumSubElts) {
11010     if (!AllowPartials || !Op)
11011       return SDValue();
11012     EVT OpVT = Op.getValueType();
11013     EVT OpSVT = OpVT.getScalarType();
11014     EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts);
11015     if (!TLI->isExtractSubvectorCheap(SubVT, OpVT, 0))
11016       return SDValue();
11017     BinOp = (ISD::NodeType)CandidateBinOp;
11018     return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op,
11019                    getVectorIdxConstant(0, SDLoc(Op)));
11020   };
11021 
11022   // At each stage, we're looking for something that looks like:
11023   // %s = shufflevector <8 x i32> %op, <8 x i32> undef,
11024   //                    <8 x i32> <i32 2, i32 3, i32 undef, i32 undef,
11025   //                               i32 undef, i32 undef, i32 undef, i32 undef>
11026   // %a = binop <8 x i32> %op, %s
11027   // Where the mask changes according to the stage. E.g. for a 3-stage pyramid,
11028   // we expect something like:
11029   // <4,5,6,7,u,u,u,u>
11030   // <2,3,u,u,u,u,u,u>
11031   // <1,u,u,u,u,u,u,u>
11032   // While a partial reduction match would be:
11033   // <2,3,u,u,u,u,u,u>
11034   // <1,u,u,u,u,u,u,u>
11035   unsigned Stages = Log2_32(Op.getValueType().getVectorNumElements());
11036   SDValue PrevOp;
11037   for (unsigned i = 0; i < Stages; ++i) {
11038     unsigned MaskEnd = (1 << i);
11039 
11040     if (Op.getOpcode() != CandidateBinOp)
11041       return PartialReduction(PrevOp, MaskEnd);
11042 
11043     SDValue Op0 = Op.getOperand(0);
11044     SDValue Op1 = Op.getOperand(1);
11045 
11046     ShuffleVectorSDNode *Shuffle = dyn_cast<ShuffleVectorSDNode>(Op0);
11047     if (Shuffle) {
11048       Op = Op1;
11049     } else {
11050       Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
11051       Op = Op0;
11052     }
11053 
11054     // The first operand of the shuffle should be the same as the other operand
11055     // of the binop.
11056     if (!Shuffle || Shuffle->getOperand(0) != Op)
11057       return PartialReduction(PrevOp, MaskEnd);
11058 
11059     // Verify the shuffle has the expected (at this stage of the pyramid) mask.
11060     for (int Index = 0; Index < (int)MaskEnd; ++Index)
11061       if (Shuffle->getMaskElt(Index) != (int)(MaskEnd + Index))
11062         return PartialReduction(PrevOp, MaskEnd);
11063 
11064     PrevOp = Op;
11065   }
11066 
11067   // Handle subvector reductions, which tend to appear after the shuffle
11068   // reduction stages.
11069   while (Op.getOpcode() == CandidateBinOp) {
11070     unsigned NumElts = Op.getValueType().getVectorNumElements();
11071     SDValue Op0 = Op.getOperand(0);
11072     SDValue Op1 = Op.getOperand(1);
11073     if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
11074         Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
11075         Op0.getOperand(0) != Op1.getOperand(0))
11076       break;
11077     SDValue Src = Op0.getOperand(0);
11078     unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
11079     if (NumSrcElts != (2 * NumElts))
11080       break;
11081     if (!(Op0.getConstantOperandAPInt(1) == 0 &&
11082           Op1.getConstantOperandAPInt(1) == NumElts) &&
11083         !(Op1.getConstantOperandAPInt(1) == 0 &&
11084           Op0.getConstantOperandAPInt(1) == NumElts))
11085       break;
11086     Op = Src;
11087   }
11088 
11089   BinOp = (ISD::NodeType)CandidateBinOp;
11090   return Op;
11091 }
11092 
11093 SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
11094   assert(N->getNumValues() == 1 &&
11095          "Can't unroll a vector with multiple results!");
11096 
11097   EVT VT = N->getValueType(0);
11098   unsigned NE = VT.getVectorNumElements();
11099   EVT EltVT = VT.getVectorElementType();
11100   SDLoc dl(N);
11101 
11102   SmallVector<SDValue, 8> Scalars;
11103   SmallVector<SDValue, 4> Operands(N->getNumOperands());
11104 
11105   // If ResNE is 0, fully unroll the vector op.
11106   if (ResNE == 0)
11107     ResNE = NE;
11108   else if (NE > ResNE)
11109     NE = ResNE;
11110 
11111   unsigned i;
11112   for (i= 0; i != NE; ++i) {
11113     for (unsigned j = 0, e = N->getNumOperands(); j != e; ++j) {
11114       SDValue Operand = N->getOperand(j);
11115       EVT OperandVT = Operand.getValueType();
11116       if (OperandVT.isVector()) {
11117         // A vector operand; extract a single element.
11118         EVT OperandEltVT = OperandVT.getVectorElementType();
11119         Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT,
11120                               Operand, getVectorIdxConstant(i, dl));
11121       } else {
11122         // A scalar operand; just use it as is.
11123         Operands[j] = Operand;
11124       }
11125     }
11126 
11127     switch (N->getOpcode()) {
11128     default: {
11129       Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands,
11130                                 N->getFlags()));
11131       break;
11132     }
11133     case ISD::VSELECT:
11134       Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands));
11135       break;
11136     case ISD::SHL:
11137     case ISD::SRA:
11138     case ISD::SRL:
11139     case ISD::ROTL:
11140     case ISD::ROTR:
11141       Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
11142                                getShiftAmountOperand(Operands[0].getValueType(),
11143                                                      Operands[1])));
11144       break;
11145     case ISD::SIGN_EXTEND_INREG: {
11146       EVT ExtVT = cast<VTSDNode>(Operands[1])->getVT().getVectorElementType();
11147       Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
11148                                 Operands[0],
11149                                 getValueType(ExtVT)));
11150     }
11151     }
11152   }
11153 
11154   for (; i < ResNE; ++i)
11155     Scalars.push_back(getUNDEF(EltVT));
11156 
11157   EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE);
11158   return getBuildVector(VecVT, dl, Scalars);
11159 }
11160 
11161 std::pair<SDValue, SDValue> SelectionDAG::UnrollVectorOverflowOp(
11162     SDNode *N, unsigned ResNE) {
11163   unsigned Opcode = N->getOpcode();
11164   assert((Opcode == ISD::UADDO || Opcode == ISD::SADDO ||
11165           Opcode == ISD::USUBO || Opcode == ISD::SSUBO ||
11166           Opcode == ISD::UMULO || Opcode == ISD::SMULO) &&
11167          "Expected an overflow opcode");
11168 
11169   EVT ResVT = N->getValueType(0);
11170   EVT OvVT = N->getValueType(1);
11171   EVT ResEltVT = ResVT.getVectorElementType();
11172   EVT OvEltVT = OvVT.getVectorElementType();
11173   SDLoc dl(N);
11174 
11175   // If ResNE is 0, fully unroll the vector op.
11176   unsigned NE = ResVT.getVectorNumElements();
11177   if (ResNE == 0)
11178     ResNE = NE;
11179   else if (NE > ResNE)
11180     NE = ResNE;
11181 
11182   SmallVector<SDValue, 8> LHSScalars;
11183   SmallVector<SDValue, 8> RHSScalars;
11184   ExtractVectorElements(N->getOperand(0), LHSScalars, 0, NE);
11185   ExtractVectorElements(N->getOperand(1), RHSScalars, 0, NE);
11186 
11187   EVT SVT = TLI->getSetCCResultType(getDataLayout(), *getContext(), ResEltVT);
11188   SDVTList VTs = getVTList(ResEltVT, SVT);
11189   SmallVector<SDValue, 8> ResScalars;
11190   SmallVector<SDValue, 8> OvScalars;
11191   for (unsigned i = 0; i < NE; ++i) {
11192     SDValue Res = getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
11193     SDValue Ov =
11194         getSelect(dl, OvEltVT, Res.getValue(1),
11195                   getBoolConstant(true, dl, OvEltVT, ResVT),
11196                   getConstant(0, dl, OvEltVT));
11197 
11198     ResScalars.push_back(Res);
11199     OvScalars.push_back(Ov);
11200   }
11201 
11202   ResScalars.append(ResNE - NE, getUNDEF(ResEltVT));
11203   OvScalars.append(ResNE - NE, getUNDEF(OvEltVT));
11204 
11205   EVT NewResVT = EVT::getVectorVT(*getContext(), ResEltVT, ResNE);
11206   EVT NewOvVT = EVT::getVectorVT(*getContext(), OvEltVT, ResNE);
11207   return std::make_pair(getBuildVector(NewResVT, dl, ResScalars),
11208                         getBuildVector(NewOvVT, dl, OvScalars));
11209 }
11210 
11211 bool SelectionDAG::areNonVolatileConsecutiveLoads(LoadSDNode *LD,
11212                                                   LoadSDNode *Base,
11213                                                   unsigned Bytes,
11214                                                   int Dist) const {
11215   if (LD->isVolatile() || Base->isVolatile())
11216     return false;
11217   // TODO: probably too restrictive for atomics, revisit
11218   if (!LD->isSimple())
11219     return false;
11220   if (LD->isIndexed() || Base->isIndexed())
11221     return false;
11222   if (LD->getChain() != Base->getChain())
11223     return false;
11224   EVT VT = LD->getValueType(0);
11225   if (VT.getSizeInBits() / 8 != Bytes)
11226     return false;
11227 
11228   auto BaseLocDecomp = BaseIndexOffset::match(Base, *this);
11229   auto LocDecomp = BaseIndexOffset::match(LD, *this);
11230 
11231   int64_t Offset = 0;
11232   if (BaseLocDecomp.equalBaseIndex(LocDecomp, *this, Offset))
11233     return (Dist * Bytes == Offset);
11234   return false;
11235 }
11236 
11237 /// InferPtrAlignment - Infer alignment of a load / store address. Return None
11238 /// if it cannot be inferred.
11239 MaybeAlign SelectionDAG::InferPtrAlign(SDValue Ptr) const {
11240   // If this is a GlobalAddress + cst, return the alignment.
11241   const GlobalValue *GV = nullptr;
11242   int64_t GVOffset = 0;
11243   if (TLI->isGAPlusOffset(Ptr.getNode(), GV, GVOffset)) {
11244     unsigned PtrWidth = getDataLayout().getPointerTypeSizeInBits(GV->getType());
11245     KnownBits Known(PtrWidth);
11246     llvm::computeKnownBits(GV, Known, getDataLayout());
11247     unsigned AlignBits = Known.countMinTrailingZeros();
11248     if (AlignBits)
11249       return commonAlignment(Align(1ull << std::min(31U, AlignBits)), GVOffset);
11250   }
11251 
11252   // If this is a direct reference to a stack slot, use information about the
11253   // stack slot's alignment.
11254   int FrameIdx = INT_MIN;
11255   int64_t FrameOffset = 0;
11256   if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
11257     FrameIdx = FI->getIndex();
11258   } else if (isBaseWithConstantOffset(Ptr) &&
11259              isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
11260     // Handle FI+Cst
11261     FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
11262     FrameOffset = Ptr.getConstantOperandVal(1);
11263   }
11264 
11265   if (FrameIdx != INT_MIN) {
11266     const MachineFrameInfo &MFI = getMachineFunction().getFrameInfo();
11267     return commonAlignment(MFI.getObjectAlign(FrameIdx), FrameOffset);
11268   }
11269 
11270   return None;
11271 }
11272 
11273 /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
11274 /// which is split (or expanded) into two not necessarily identical pieces.
11275 std::pair<EVT, EVT> SelectionDAG::GetSplitDestVTs(const EVT &VT) const {
11276   // Currently all types are split in half.
11277   EVT LoVT, HiVT;
11278   if (!VT.isVector())
11279     LoVT = HiVT = TLI->getTypeToTransformTo(*getContext(), VT);
11280   else
11281     LoVT = HiVT = VT.getHalfNumVectorElementsVT(*getContext());
11282 
11283   return std::make_pair(LoVT, HiVT);
11284 }
11285 
11286 /// GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a
11287 /// type, dependent on an enveloping VT that has been split into two identical
11288 /// pieces. Sets the HiIsEmpty flag when hi type has zero storage size.
11289 std::pair<EVT, EVT>
11290 SelectionDAG::GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT,
11291                                        bool *HiIsEmpty) const {
11292   EVT EltTp = VT.getVectorElementType();
11293   // Examples:
11294   //   custom VL=8  with enveloping VL=8/8 yields 8/0 (hi empty)
11295   //   custom VL=9  with enveloping VL=8/8 yields 8/1
11296   //   custom VL=10 with enveloping VL=8/8 yields 8/2
11297   //   etc.
11298   ElementCount VTNumElts = VT.getVectorElementCount();
11299   ElementCount EnvNumElts = EnvVT.getVectorElementCount();
11300   assert(VTNumElts.isScalable() == EnvNumElts.isScalable() &&
11301          "Mixing fixed width and scalable vectors when enveloping a type");
11302   EVT LoVT, HiVT;
11303   if (VTNumElts.getKnownMinValue() > EnvNumElts.getKnownMinValue()) {
11304     LoVT = EVT::getVectorVT(*getContext(), EltTp, EnvNumElts);
11305     HiVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts - EnvNumElts);
11306     *HiIsEmpty = false;
11307   } else {
11308     // Flag that hi type has zero storage size, but return split envelop type
11309     // (this would be easier if vector types with zero elements were allowed).
11310     LoVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts);
11311     HiVT = EVT::getVectorVT(*getContext(), EltTp, EnvNumElts);
11312     *HiIsEmpty = true;
11313   }
11314   return std::make_pair(LoVT, HiVT);
11315 }
11316 
11317 /// SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the
11318 /// low/high part.
11319 std::pair<SDValue, SDValue>
11320 SelectionDAG::SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT,
11321                           const EVT &HiVT) {
11322   assert(LoVT.isScalableVector() == HiVT.isScalableVector() &&
11323          LoVT.isScalableVector() == N.getValueType().isScalableVector() &&
11324          "Splitting vector with an invalid mixture of fixed and scalable "
11325          "vector types");
11326   assert(LoVT.getVectorMinNumElements() + HiVT.getVectorMinNumElements() <=
11327              N.getValueType().getVectorMinNumElements() &&
11328          "More vector elements requested than available!");
11329   SDValue Lo, Hi;
11330   Lo =
11331       getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, getVectorIdxConstant(0, DL));
11332   // For scalable vectors it is safe to use LoVT.getVectorMinNumElements()
11333   // (rather than having to use ElementCount), because EXTRACT_SUBVECTOR scales
11334   // IDX with the runtime scaling factor of the result vector type. For
11335   // fixed-width result vectors, that runtime scaling factor is 1.
11336   Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N,
11337                getVectorIdxConstant(LoVT.getVectorMinNumElements(), DL));
11338   return std::make_pair(Lo, Hi);
11339 }
11340 
11341 std::pair<SDValue, SDValue> SelectionDAG::SplitEVL(SDValue N, EVT VecVT,
11342                                                    const SDLoc &DL) {
11343   // Split the vector length parameter.
11344   // %evl -> umin(%evl, %halfnumelts) and usubsat(%evl - %halfnumelts).
11345   EVT VT = N.getValueType();
11346   assert(VecVT.getVectorElementCount().isKnownEven() &&
11347          "Expecting the mask to be an evenly-sized vector");
11348   unsigned HalfMinNumElts = VecVT.getVectorMinNumElements() / 2;
11349   SDValue HalfNumElts =
11350       VecVT.isFixedLengthVector()
11351           ? getConstant(HalfMinNumElts, DL, VT)
11352           : getVScale(DL, VT, APInt(VT.getScalarSizeInBits(), HalfMinNumElts));
11353   SDValue Lo = getNode(ISD::UMIN, DL, VT, N, HalfNumElts);
11354   SDValue Hi = getNode(ISD::USUBSAT, DL, VT, N, HalfNumElts);
11355   return std::make_pair(Lo, Hi);
11356 }
11357 
11358 /// Widen the vector up to the next power of two using INSERT_SUBVECTOR.
11359 SDValue SelectionDAG::WidenVector(const SDValue &N, const SDLoc &DL) {
11360   EVT VT = N.getValueType();
11361   EVT WideVT = EVT::getVectorVT(*getContext(), VT.getVectorElementType(),
11362                                 NextPowerOf2(VT.getVectorNumElements()));
11363   return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N,
11364                  getVectorIdxConstant(0, DL));
11365 }
11366 
11367 void SelectionDAG::ExtractVectorElements(SDValue Op,
11368                                          SmallVectorImpl<SDValue> &Args,
11369                                          unsigned Start, unsigned Count,
11370                                          EVT EltVT) {
11371   EVT VT = Op.getValueType();
11372   if (Count == 0)
11373     Count = VT.getVectorNumElements();
11374   if (EltVT == EVT())
11375     EltVT = VT.getVectorElementType();
11376   SDLoc SL(Op);
11377   for (unsigned i = Start, e = Start + Count; i != e; ++i) {
11378     Args.push_back(getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Op,
11379                            getVectorIdxConstant(i, SL)));
11380   }
11381 }
11382 
11383 // getAddressSpace - Return the address space this GlobalAddress belongs to.
11384 unsigned GlobalAddressSDNode::getAddressSpace() const {
11385   return getGlobal()->getType()->getAddressSpace();
11386 }
11387 
11388 Type *ConstantPoolSDNode::getType() const {
11389   if (isMachineConstantPoolEntry())
11390     return Val.MachineCPVal->getType();
11391   return Val.ConstVal->getType();
11392 }
11393 
11394 bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
11395                                         unsigned &SplatBitSize,
11396                                         bool &HasAnyUndefs,
11397                                         unsigned MinSplatBits,
11398                                         bool IsBigEndian) const {
11399   EVT VT = getValueType(0);
11400   assert(VT.isVector() && "Expected a vector type");
11401   unsigned VecWidth = VT.getSizeInBits();
11402   if (MinSplatBits > VecWidth)
11403     return false;
11404 
11405   // FIXME: The widths are based on this node's type, but build vectors can
11406   // truncate their operands.
11407   SplatValue = APInt(VecWidth, 0);
11408   SplatUndef = APInt(VecWidth, 0);
11409 
11410   // Get the bits. Bits with undefined values (when the corresponding element
11411   // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
11412   // in SplatValue. If any of the values are not constant, give up and return
11413   // false.
11414   unsigned int NumOps = getNumOperands();
11415   assert(NumOps > 0 && "isConstantSplat has 0-size build vector");
11416   unsigned EltWidth = VT.getScalarSizeInBits();
11417 
11418   for (unsigned j = 0; j < NumOps; ++j) {
11419     unsigned i = IsBigEndian ? NumOps - 1 - j : j;
11420     SDValue OpVal = getOperand(i);
11421     unsigned BitPos = j * EltWidth;
11422 
11423     if (OpVal.isUndef())
11424       SplatUndef.setBits(BitPos, BitPos + EltWidth);
11425     else if (auto *CN = dyn_cast<ConstantSDNode>(OpVal))
11426       SplatValue.insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
11427     else if (auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
11428       SplatValue.insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
11429     else
11430       return false;
11431   }
11432 
11433   // The build_vector is all constants or undefs. Find the smallest element
11434   // size that splats the vector.
11435   HasAnyUndefs = (SplatUndef != 0);
11436 
11437   // FIXME: This does not work for vectors with elements less than 8 bits.
11438   while (VecWidth > 8) {
11439     unsigned HalfSize = VecWidth / 2;
11440     APInt HighValue = SplatValue.extractBits(HalfSize, HalfSize);
11441     APInt LowValue = SplatValue.extractBits(HalfSize, 0);
11442     APInt HighUndef = SplatUndef.extractBits(HalfSize, HalfSize);
11443     APInt LowUndef = SplatUndef.extractBits(HalfSize, 0);
11444 
11445     // If the two halves do not match (ignoring undef bits), stop here.
11446     if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
11447         MinSplatBits > HalfSize)
11448       break;
11449 
11450     SplatValue = HighValue | LowValue;
11451     SplatUndef = HighUndef & LowUndef;
11452 
11453     VecWidth = HalfSize;
11454   }
11455 
11456   SplatBitSize = VecWidth;
11457   return true;
11458 }
11459 
11460 SDValue BuildVectorSDNode::getSplatValue(const APInt &DemandedElts,
11461                                          BitVector *UndefElements) const {
11462   unsigned NumOps = getNumOperands();
11463   if (UndefElements) {
11464     UndefElements->clear();
11465     UndefElements->resize(NumOps);
11466   }
11467   assert(NumOps == DemandedElts.getBitWidth() && "Unexpected vector size");
11468   if (!DemandedElts)
11469     return SDValue();
11470   SDValue Splatted;
11471   for (unsigned i = 0; i != NumOps; ++i) {
11472     if (!DemandedElts[i])
11473       continue;
11474     SDValue Op = getOperand(i);
11475     if (Op.isUndef()) {
11476       if (UndefElements)
11477         (*UndefElements)[i] = true;
11478     } else if (!Splatted) {
11479       Splatted = Op;
11480     } else if (Splatted != Op) {
11481       return SDValue();
11482     }
11483   }
11484 
11485   if (!Splatted) {
11486     unsigned FirstDemandedIdx = DemandedElts.countTrailingZeros();
11487     assert(getOperand(FirstDemandedIdx).isUndef() &&
11488            "Can only have a splat without a constant for all undefs.");
11489     return getOperand(FirstDemandedIdx);
11490   }
11491 
11492   return Splatted;
11493 }
11494 
11495 SDValue BuildVectorSDNode::getSplatValue(BitVector *UndefElements) const {
11496   APInt DemandedElts = APInt::getAllOnes(getNumOperands());
11497   return getSplatValue(DemandedElts, UndefElements);
11498 }
11499 
11500 bool BuildVectorSDNode::getRepeatedSequence(const APInt &DemandedElts,
11501                                             SmallVectorImpl<SDValue> &Sequence,
11502                                             BitVector *UndefElements) const {
11503   unsigned NumOps = getNumOperands();
11504   Sequence.clear();
11505   if (UndefElements) {
11506     UndefElements->clear();
11507     UndefElements->resize(NumOps);
11508   }
11509   assert(NumOps == DemandedElts.getBitWidth() && "Unexpected vector size");
11510   if (!DemandedElts || NumOps < 2 || !isPowerOf2_32(NumOps))
11511     return false;
11512 
11513   // Set the undefs even if we don't find a sequence (like getSplatValue).
11514   if (UndefElements)
11515     for (unsigned I = 0; I != NumOps; ++I)
11516       if (DemandedElts[I] && getOperand(I).isUndef())
11517         (*UndefElements)[I] = true;
11518 
11519   // Iteratively widen the sequence length looking for repetitions.
11520   for (unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
11521     Sequence.append(SeqLen, SDValue());
11522     for (unsigned I = 0; I != NumOps; ++I) {
11523       if (!DemandedElts[I])
11524         continue;
11525       SDValue &SeqOp = Sequence[I % SeqLen];
11526       SDValue Op = getOperand(I);
11527       if (Op.isUndef()) {
11528         if (!SeqOp)
11529           SeqOp = Op;
11530         continue;
11531       }
11532       if (SeqOp && !SeqOp.isUndef() && SeqOp != Op) {
11533         Sequence.clear();
11534         break;
11535       }
11536       SeqOp = Op;
11537     }
11538     if (!Sequence.empty())
11539       return true;
11540   }
11541 
11542   assert(Sequence.empty() && "Failed to empty non-repeating sequence pattern");
11543   return false;
11544 }
11545 
11546 bool BuildVectorSDNode::getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
11547                                             BitVector *UndefElements) const {
11548   APInt DemandedElts = APInt::getAllOnes(getNumOperands());
11549   return getRepeatedSequence(DemandedElts, Sequence, UndefElements);
11550 }
11551 
11552 ConstantSDNode *
11553 BuildVectorSDNode::getConstantSplatNode(const APInt &DemandedElts,
11554                                         BitVector *UndefElements) const {
11555   return dyn_cast_or_null<ConstantSDNode>(
11556       getSplatValue(DemandedElts, UndefElements));
11557 }
11558 
11559 ConstantSDNode *
11560 BuildVectorSDNode::getConstantSplatNode(BitVector *UndefElements) const {
11561   return dyn_cast_or_null<ConstantSDNode>(getSplatValue(UndefElements));
11562 }
11563 
11564 ConstantFPSDNode *
11565 BuildVectorSDNode::getConstantFPSplatNode(const APInt &DemandedElts,
11566                                           BitVector *UndefElements) const {
11567   return dyn_cast_or_null<ConstantFPSDNode>(
11568       getSplatValue(DemandedElts, UndefElements));
11569 }
11570 
11571 ConstantFPSDNode *
11572 BuildVectorSDNode::getConstantFPSplatNode(BitVector *UndefElements) const {
11573   return dyn_cast_or_null<ConstantFPSDNode>(getSplatValue(UndefElements));
11574 }
11575 
11576 int32_t
11577 BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
11578                                                    uint32_t BitWidth) const {
11579   if (ConstantFPSDNode *CN =
11580           dyn_cast_or_null<ConstantFPSDNode>(getSplatValue(UndefElements))) {
11581     bool IsExact;
11582     APSInt IntVal(BitWidth);
11583     const APFloat &APF = CN->getValueAPF();
11584     if (APF.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact) !=
11585             APFloat::opOK ||
11586         !IsExact)
11587       return -1;
11588 
11589     return IntVal.exactLogBase2();
11590   }
11591   return -1;
11592 }
11593 
11594 bool BuildVectorSDNode::getConstantRawBits(
11595     bool IsLittleEndian, unsigned DstEltSizeInBits,
11596     SmallVectorImpl<APInt> &RawBitElements, BitVector &UndefElements) const {
11597   // Early-out if this contains anything but Undef/Constant/ConstantFP.
11598   if (!isConstant())
11599     return false;
11600 
11601   unsigned NumSrcOps = getNumOperands();
11602   unsigned SrcEltSizeInBits = getValueType(0).getScalarSizeInBits();
11603   assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
11604          "Invalid bitcast scale");
11605 
11606   // Extract raw src bits.
11607   SmallVector<APInt> SrcBitElements(NumSrcOps,
11608                                     APInt::getNullValue(SrcEltSizeInBits));
11609   BitVector SrcUndeElements(NumSrcOps, false);
11610 
11611   for (unsigned I = 0; I != NumSrcOps; ++I) {
11612     SDValue Op = getOperand(I);
11613     if (Op.isUndef()) {
11614       SrcUndeElements.set(I);
11615       continue;
11616     }
11617     auto *CInt = dyn_cast<ConstantSDNode>(Op);
11618     auto *CFP = dyn_cast<ConstantFPSDNode>(Op);
11619     assert((CInt || CFP) && "Unknown constant");
11620     SrcBitElements[I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
11621                              : CFP->getValueAPF().bitcastToAPInt();
11622   }
11623 
11624   // Recast to dst width.
11625   recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
11626                 SrcBitElements, UndefElements, SrcUndeElements);
11627   return true;
11628 }
11629 
11630 void BuildVectorSDNode::recastRawBits(bool IsLittleEndian,
11631                                       unsigned DstEltSizeInBits,
11632                                       SmallVectorImpl<APInt> &DstBitElements,
11633                                       ArrayRef<APInt> SrcBitElements,
11634                                       BitVector &DstUndefElements,
11635                                       const BitVector &SrcUndefElements) {
11636   unsigned NumSrcOps = SrcBitElements.size();
11637   unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
11638   assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
11639          "Invalid bitcast scale");
11640   assert(NumSrcOps == SrcUndefElements.size() &&
11641          "Vector size mismatch");
11642 
11643   unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
11644   DstUndefElements.clear();
11645   DstUndefElements.resize(NumDstOps, false);
11646   DstBitElements.assign(NumDstOps, APInt::getNullValue(DstEltSizeInBits));
11647 
11648   // Concatenate src elements constant bits together into dst element.
11649   if (SrcEltSizeInBits <= DstEltSizeInBits) {
11650     unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
11651     for (unsigned I = 0; I != NumDstOps; ++I) {
11652       DstUndefElements.set(I);
11653       APInt &DstBits = DstBitElements[I];
11654       for (unsigned J = 0; J != Scale; ++J) {
11655         unsigned Idx = (I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
11656         if (SrcUndefElements[Idx])
11657           continue;
11658         DstUndefElements.reset(I);
11659         const APInt &SrcBits = SrcBitElements[Idx];
11660         assert(SrcBits.getBitWidth() == SrcEltSizeInBits &&
11661                "Illegal constant bitwidths");
11662         DstBits.insertBits(SrcBits, J * SrcEltSizeInBits);
11663       }
11664     }
11665     return;
11666   }
11667 
11668   // Split src element constant bits into dst elements.
11669   unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
11670   for (unsigned I = 0; I != NumSrcOps; ++I) {
11671     if (SrcUndefElements[I]) {
11672       DstUndefElements.set(I * Scale, (I + 1) * Scale);
11673       continue;
11674     }
11675     const APInt &SrcBits = SrcBitElements[I];
11676     for (unsigned J = 0; J != Scale; ++J) {
11677       unsigned Idx = (I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
11678       APInt &DstBits = DstBitElements[Idx];
11679       DstBits = SrcBits.extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
11680     }
11681   }
11682 }
11683 
11684 bool BuildVectorSDNode::isConstant() const {
11685   for (const SDValue &Op : op_values()) {
11686     unsigned Opc = Op.getOpcode();
11687     if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP)
11688       return false;
11689   }
11690   return true;
11691 }
11692 
11693 Optional<std::pair<APInt, APInt>>
11694 BuildVectorSDNode::isConstantSequence() const {
11695   unsigned NumOps = getNumOperands();
11696   if (NumOps < 2)
11697     return None;
11698 
11699   if (!isa<ConstantSDNode>(getOperand(0)) ||
11700       !isa<ConstantSDNode>(getOperand(1)))
11701     return None;
11702 
11703   unsigned EltSize = getValueType(0).getScalarSizeInBits();
11704   APInt Start = getConstantOperandAPInt(0).trunc(EltSize);
11705   APInt Stride = getConstantOperandAPInt(1).trunc(EltSize) - Start;
11706 
11707   if (Stride.isZero())
11708     return None;
11709 
11710   for (unsigned i = 2; i < NumOps; ++i) {
11711     if (!isa<ConstantSDNode>(getOperand(i)))
11712       return None;
11713 
11714     APInt Val = getConstantOperandAPInt(i).trunc(EltSize);
11715     if (Val != (Start + (Stride * i)))
11716       return None;
11717   }
11718 
11719   return std::make_pair(Start, Stride);
11720 }
11721 
11722 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
11723   // Find the first non-undef value in the shuffle mask.
11724   unsigned i, e;
11725   for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
11726     /* search */;
11727 
11728   // If all elements are undefined, this shuffle can be considered a splat
11729   // (although it should eventually get simplified away completely).
11730   if (i == e)
11731     return true;
11732 
11733   // Make sure all remaining elements are either undef or the same as the first
11734   // non-undef value.
11735   for (int Idx = Mask[i]; i != e; ++i)
11736     if (Mask[i] >= 0 && Mask[i] != Idx)
11737       return false;
11738   return true;
11739 }
11740 
11741 // Returns the SDNode if it is a constant integer BuildVector
11742 // or constant integer.
11743 SDNode *SelectionDAG::isConstantIntBuildVectorOrConstantInt(SDValue N) const {
11744   if (isa<ConstantSDNode>(N))
11745     return N.getNode();
11746   if (ISD::isBuildVectorOfConstantSDNodes(N.getNode()))
11747     return N.getNode();
11748   // Treat a GlobalAddress supporting constant offset folding as a
11749   // constant integer.
11750   if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N))
11751     if (GA->getOpcode() == ISD::GlobalAddress &&
11752         TLI->isOffsetFoldingLegal(GA))
11753       return GA;
11754   if ((N.getOpcode() == ISD::SPLAT_VECTOR) &&
11755       isa<ConstantSDNode>(N.getOperand(0)))
11756     return N.getNode();
11757   return nullptr;
11758 }
11759 
11760 // Returns the SDNode if it is a constant float BuildVector
11761 // or constant float.
11762 SDNode *SelectionDAG::isConstantFPBuildVectorOrConstantFP(SDValue N) const {
11763   if (isa<ConstantFPSDNode>(N))
11764     return N.getNode();
11765 
11766   if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
11767     return N.getNode();
11768 
11769   if ((N.getOpcode() == ISD::SPLAT_VECTOR) &&
11770       isa<ConstantFPSDNode>(N.getOperand(0)))
11771     return N.getNode();
11772 
11773   return nullptr;
11774 }
11775 
11776 void SelectionDAG::createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
11777   assert(!Node->OperandList && "Node already has operands");
11778   assert(SDNode::getMaxNumOperands() >= Vals.size() &&
11779          "too many operands to fit into SDNode");
11780   SDUse *Ops = OperandRecycler.allocate(
11781       ArrayRecycler<SDUse>::Capacity::get(Vals.size()), OperandAllocator);
11782 
11783   bool IsDivergent = false;
11784   for (unsigned I = 0; I != Vals.size(); ++I) {
11785     Ops[I].setUser(Node);
11786     Ops[I].setInitial(Vals[I]);
11787     if (Ops[I].Val.getValueType() != MVT::Other) // Skip Chain. It does not carry divergence.
11788       IsDivergent |= Ops[I].getNode()->isDivergent();
11789   }
11790   Node->NumOperands = Vals.size();
11791   Node->OperandList = Ops;
11792   if (!TLI->isSDNodeAlwaysUniform(Node)) {
11793     IsDivergent |= TLI->isSDNodeSourceOfDivergence(Node, FLI, DA);
11794     Node->SDNodeBits.IsDivergent = IsDivergent;
11795   }
11796   checkForCycles(Node);
11797 }
11798 
11799 SDValue SelectionDAG::getTokenFactor(const SDLoc &DL,
11800                                      SmallVectorImpl<SDValue> &Vals) {
11801   size_t Limit = SDNode::getMaxNumOperands();
11802   while (Vals.size() > Limit) {
11803     unsigned SliceIdx = Vals.size() - Limit;
11804     auto ExtractedTFs = ArrayRef<SDValue>(Vals).slice(SliceIdx, Limit);
11805     SDValue NewTF = getNode(ISD::TokenFactor, DL, MVT::Other, ExtractedTFs);
11806     Vals.erase(Vals.begin() + SliceIdx, Vals.end());
11807     Vals.emplace_back(NewTF);
11808   }
11809   return getNode(ISD::TokenFactor, DL, MVT::Other, Vals);
11810 }
11811 
11812 SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
11813                                         EVT VT, SDNodeFlags Flags) {
11814   switch (Opcode) {
11815   default:
11816     return SDValue();
11817   case ISD::ADD:
11818   case ISD::OR:
11819   case ISD::XOR:
11820   case ISD::UMAX:
11821     return getConstant(0, DL, VT);
11822   case ISD::MUL:
11823     return getConstant(1, DL, VT);
11824   case ISD::AND:
11825   case ISD::UMIN:
11826     return getAllOnesConstant(DL, VT);
11827   case ISD::SMAX:
11828     return getConstant(APInt::getSignedMinValue(VT.getSizeInBits()), DL, VT);
11829   case ISD::SMIN:
11830     return getConstant(APInt::getSignedMaxValue(VT.getSizeInBits()), DL, VT);
11831   case ISD::FADD:
11832     return getConstantFP(-0.0, DL, VT);
11833   case ISD::FMUL:
11834     return getConstantFP(1.0, DL, VT);
11835   case ISD::FMINNUM:
11836   case ISD::FMAXNUM: {
11837     // Neutral element for fminnum is NaN, Inf or FLT_MAX, depending on FMF.
11838     const fltSemantics &Semantics = EVTToAPFloatSemantics(VT);
11839     APFloat NeutralAF = !Flags.hasNoNaNs() ? APFloat::getQNaN(Semantics) :
11840                         !Flags.hasNoInfs() ? APFloat::getInf(Semantics) :
11841                         APFloat::getLargest(Semantics);
11842     if (Opcode == ISD::FMAXNUM)
11843       NeutralAF.changeSign();
11844 
11845     return getConstantFP(NeutralAF, DL, VT);
11846   }
11847   }
11848 }
11849 
11850 #ifndef NDEBUG
11851 static void checkForCyclesHelper(const SDNode *N,
11852                                  SmallPtrSetImpl<const SDNode*> &Visited,
11853                                  SmallPtrSetImpl<const SDNode*> &Checked,
11854                                  const llvm::SelectionDAG *DAG) {
11855   // If this node has already been checked, don't check it again.
11856   if (Checked.count(N))
11857     return;
11858 
11859   // If a node has already been visited on this depth-first walk, reject it as
11860   // a cycle.
11861   if (!Visited.insert(N).second) {
11862     errs() << "Detected cycle in SelectionDAG\n";
11863     dbgs() << "Offending node:\n";
11864     N->dumprFull(DAG); dbgs() << "\n";
11865     abort();
11866   }
11867 
11868   for (const SDValue &Op : N->op_values())
11869     checkForCyclesHelper(Op.getNode(), Visited, Checked, DAG);
11870 
11871   Checked.insert(N);
11872   Visited.erase(N);
11873 }
11874 #endif
11875 
11876 void llvm::checkForCycles(const llvm::SDNode *N,
11877                           const llvm::SelectionDAG *DAG,
11878                           bool force) {
11879 #ifndef NDEBUG
11880   bool check = force;
11881 #ifdef EXPENSIVE_CHECKS
11882   check = true;
11883 #endif  // EXPENSIVE_CHECKS
11884   if (check) {
11885     assert(N && "Checking nonexistent SDNode");
11886     SmallPtrSet<const SDNode*, 32> visited;
11887     SmallPtrSet<const SDNode*, 32> checked;
11888     checkForCyclesHelper(N, visited, checked, DAG);
11889   }
11890 #endif  // !NDEBUG
11891 }
11892 
11893 void llvm::checkForCycles(const llvm::SelectionDAG *DAG, bool force) {
11894   checkForCycles(DAG->getRoot().getNode(), DAG, force);
11895 }
11896