1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This declares the Emit routines for the SelectionDAG class, which creates 10 // MachineInstrs based on the decisions of the SelectionDAG instruction 11 // selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAGNodes.h" 21 22 namespace llvm { 23 24 class MachineInstrBuilder; 25 class MCInstrDesc; 26 class SDDbgLabel; 27 class SDDbgValue; 28 class SDDbgOperand; 29 class TargetLowering; 30 class TargetMachine; 31 32 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 33 MachineFunction *MF; 34 MachineRegisterInfo *MRI; 35 const TargetInstrInfo *TII; 36 const TargetRegisterInfo *TRI; 37 const TargetLowering *TLI; 38 39 MachineBasicBlock *MBB; 40 MachineBasicBlock::iterator InsertPos; 41 42 /// Should we try to produce DBG_INSTR_REF instructions? 43 bool EmitDebugInstrRefs; 44 45 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 46 /// implicit physical register output. 47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 48 bool IsClone, bool IsCloned, 49 Register SrcReg, 50 DenseMap<SDValue, Register> &VRBaseMap); 51 52 void CreateVirtualRegisters(SDNode *Node, 53 MachineInstrBuilder &MIB, 54 const MCInstrDesc &II, 55 bool IsClone, bool IsCloned, 56 DenseMap<SDValue, Register> &VRBaseMap); 57 58 /// getVR - Return the virtual register corresponding to the specified result 59 /// of the specified node. 60 Register getVR(SDValue Op, 61 DenseMap<SDValue, Register> &VRBaseMap); 62 63 /// AddRegisterOperand - Add the specified register as an operand to the 64 /// specified machine instr. Insert register copies if the register is 65 /// not in the required register class. 66 void AddRegisterOperand(MachineInstrBuilder &MIB, 67 SDValue Op, 68 unsigned IIOpNum, 69 const MCInstrDesc *II, 70 DenseMap<SDValue, Register> &VRBaseMap, 71 bool IsDebug, bool IsClone, bool IsCloned); 72 73 /// AddOperand - Add the specified operand to the specified machine instr. II 74 /// specifies the instruction information for the node, and IIOpNum is the 75 /// operand number (in the II) that we are adding. IIOpNum and II are used for 76 /// assertions only. 77 void AddOperand(MachineInstrBuilder &MIB, 78 SDValue Op, 79 unsigned IIOpNum, 80 const MCInstrDesc *II, 81 DenseMap<SDValue, Register> &VRBaseMap, 82 bool IsDebug, bool IsClone, bool IsCloned); 83 84 /// ConstrainForSubReg - Try to constrain VReg to a register class that 85 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 86 /// Return the virtual register to use. 87 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT, 88 bool isDivergent, const DebugLoc &DL); 89 90 /// EmitSubregNode - Generate machine code for subreg nodes. 91 /// 92 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 93 bool IsClone, bool IsCloned); 94 95 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 96 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 97 /// register is constrained to be in a particular register class. 98 /// 99 void EmitCopyToRegClassNode(SDNode *Node, 100 DenseMap<SDValue, Register> &VRBaseMap); 101 102 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 103 /// 104 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 105 bool IsClone, bool IsCloned); 106 public: 107 /// CountResults - The results of target nodes have register or immediate 108 /// operands first, then an optional chain, and optional flag operands 109 /// (which do not go into the machine instrs.) 110 static unsigned CountResults(SDNode *Node); 111 112 void AddDbgValueLocationOps(MachineInstrBuilder &MIB, 113 const MCInstrDesc &DbgValDesc, 114 ArrayRef<SDDbgOperand> Locations, 115 DenseMap<SDValue, Register> &VRBaseMap); 116 117 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 118 /// 119 MachineInstr *EmitDbgValue(SDDbgValue *SD, 120 DenseMap<SDValue, Register> &VRBaseMap); 121 122 /// Emit a dbg_value as a DBG_INSTR_REF. May produce DBG_VALUE $noreg instead 123 /// if there is no variable location; alternately a half-formed DBG_INSTR_REF 124 /// that refers to a virtual register and is corrected later in isel. 125 MachineInstr *EmitDbgInstrRef(SDDbgValue *SD, 126 DenseMap<SDValue, Register> &VRBaseMap); 127 128 /// Emit a DBG_VALUE $noreg, indicating a variable has no location. 129 MachineInstr *EmitDbgNoLocation(SDDbgValue *SD); 130 131 /// Emit a DBG_VALUE from the operands to SDDbgValue. 132 MachineInstr *EmitDbgValueFromSingleOp(SDDbgValue *SD, 133 DenseMap<SDValue, Register> &VRBaseMap); 134 135 /// Generate machine instruction for a dbg_label node. 136 MachineInstr *EmitDbgLabel(SDDbgLabel *SD); 137 138 /// EmitNode - Generate machine code for a node and needed dependencies. 139 /// 140 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 141 DenseMap<SDValue, Register> &VRBaseMap) { 142 if (Node->isMachineOpcode()) 143 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 144 else 145 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 146 } 147 148 /// getBlock - Return the current basic block. 149 MachineBasicBlock *getBlock() { return MBB; } 150 151 /// getInsertPos - Return the current insertion position. 152 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 153 154 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 155 /// at the given position in the given block. 156 InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, 157 MachineBasicBlock::iterator insertpos); 158 159 private: 160 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 161 DenseMap<SDValue, Register> &VRBaseMap); 162 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 163 DenseMap<SDValue, Register> &VRBaseMap); 164 }; 165 } // namespace llvm 166 167 #endif 168