1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating functions from LLVM IR into 10 // Machine IR. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/FunctionLoweringInfo.h" 15 #include "llvm/ADT/APInt.h" 16 #include "llvm/Analysis/LegacyDivergenceAnalysis.h" 17 #include "llvm/CodeGen/Analysis.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetFrameLowering.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/TargetRegisterInfo.h" 26 #include "llvm/CodeGen/TargetSubtargetInfo.h" 27 #include "llvm/CodeGen/WasmEHFuncInfo.h" 28 #include "llvm/CodeGen/WinEHFuncInfo.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/IR/DerivedTypes.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Instructions.h" 33 #include "llvm/IR/IntrinsicInst.h" 34 #include "llvm/IR/Module.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <algorithm> 39 using namespace llvm; 40 41 #define DEBUG_TYPE "function-lowering-info" 42 43 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 44 /// PHI nodes or outside of the basic block that defines it, or used by a 45 /// switch or atomic instruction, which may expand to multiple basic blocks. 46 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { 47 if (I->use_empty()) return false; 48 if (isa<PHINode>(I)) return true; 49 const BasicBlock *BB = I->getParent(); 50 for (const User *U : I->users()) 51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U)) 52 return true; 53 54 return false; 55 } 56 57 static ISD::NodeType getPreferredExtendForValue(const Instruction *I) { 58 // For the users of the source value being used for compare instruction, if 59 // the number of signed predicate is greater than unsigned predicate, we 60 // prefer to use SIGN_EXTEND. 61 // 62 // With this optimization, we would be able to reduce some redundant sign or 63 // zero extension instruction, and eventually more machine CSE opportunities 64 // can be exposed. 65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 66 unsigned NumOfSigned = 0, NumOfUnsigned = 0; 67 for (const User *U : I->users()) { 68 if (const auto *CI = dyn_cast<CmpInst>(U)) { 69 NumOfSigned += CI->isSigned(); 70 NumOfUnsigned += CI->isUnsigned(); 71 } 72 } 73 if (NumOfSigned > NumOfUnsigned) 74 ExtendKind = ISD::SIGN_EXTEND; 75 76 return ExtendKind; 77 } 78 79 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, 80 SelectionDAG *DAG) { 81 Fn = &fn; 82 MF = &mf; 83 TLI = MF->getSubtarget().getTargetLowering(); 84 RegInfo = &MF->getRegInfo(); 85 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); 86 DA = DAG->getDivergenceAnalysis(); 87 88 // Check whether the function can return without sret-demotion. 89 SmallVector<ISD::OutputArg, 4> Outs; 90 CallingConv::ID CC = Fn->getCallingConv(); 91 92 GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI, 93 mf.getDataLayout()); 94 CanLowerReturn = 95 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext()); 96 97 // If this personality uses funclets, we need to do a bit more work. 98 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects; 99 EHPersonality Personality = classifyEHPersonality( 100 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr); 101 if (isFuncletEHPersonality(Personality)) { 102 // Calculate state numbers if we haven't already. 103 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 104 if (Personality == EHPersonality::MSVC_CXX) 105 calculateWinCXXEHStateNumbers(&fn, EHInfo); 106 else if (isAsynchronousEHPersonality(Personality)) 107 calculateSEHStateNumbers(&fn, EHInfo); 108 else if (Personality == EHPersonality::CoreCLR) 109 calculateClrEHStateNumbers(&fn, EHInfo); 110 111 // Map all BB references in the WinEH data to MBBs. 112 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 113 for (WinEHHandlerType &H : TBME.HandlerArray) { 114 if (const AllocaInst *AI = H.CatchObj.Alloca) 115 CatchObjects.insert({AI, {}}).first->second.push_back( 116 &H.CatchObj.FrameIndex); 117 else 118 H.CatchObj.FrameIndex = INT_MAX; 119 } 120 } 121 } 122 if (Personality == EHPersonality::Wasm_CXX) { 123 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); 124 calculateWasmEHInfo(&fn, EHInfo); 125 } 126 127 // Initialize the mapping of values to registers. This is only set up for 128 // instruction values that are used outside of the block that defines 129 // them. 130 const Align StackAlign = TFI->getStackAlign(); 131 for (const BasicBlock &BB : *Fn) { 132 for (const Instruction &I : BB) { 133 if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) { 134 Type *Ty = AI->getAllocatedType(); 135 Align TyPrefAlign = MF->getDataLayout().getPrefTypeAlign(Ty); 136 // The "specified" alignment is the alignment written on the alloca, 137 // or the preferred alignment of the type if none is specified. 138 // 139 // (Unspecified alignment on allocas will be going away soon.) 140 Align SpecifiedAlign = AI->getAlign(); 141 142 // If the preferred alignment of the type is higher than the specified 143 // alignment of the alloca, promote the alignment, as long as it doesn't 144 // require realigning the stack. 145 // 146 // FIXME: Do we really want to second-guess the IR in isel? 147 Align Alignment = 148 std::max(std::min(TyPrefAlign, StackAlign), SpecifiedAlign); 149 150 // Static allocas can be folded into the initial stack frame 151 // adjustment. For targets that don't realign the stack, don't 152 // do this if there is an extra alignment requirement. 153 if (AI->isStaticAlloca() && 154 (TFI->isStackRealignable() || (Alignment <= StackAlign))) { 155 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize()); 156 uint64_t TySize = 157 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinSize(); 158 159 TySize *= CUI->getZExtValue(); // Get total allocated size. 160 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 161 int FrameIndex = INT_MAX; 162 auto Iter = CatchObjects.find(AI); 163 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) { 164 FrameIndex = MF->getFrameInfo().CreateFixedObject( 165 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true); 166 MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment); 167 } else { 168 FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment, 169 false, AI); 170 } 171 172 // Scalable vectors may need a special StackID to distinguish 173 // them from other (fixed size) stack objects. 174 if (isa<ScalableVectorType>(Ty)) 175 MF->getFrameInfo().setStackID(FrameIndex, 176 TFI->getStackIDForScalableVectors()); 177 178 StaticAllocaMap[AI] = FrameIndex; 179 // Update the catch handler information. 180 if (Iter != CatchObjects.end()) { 181 for (int *CatchObjPtr : Iter->second) 182 *CatchObjPtr = FrameIndex; 183 } 184 } else { 185 // FIXME: Overaligned static allocas should be grouped into 186 // a single dynamic allocation instead of using a separate 187 // stack allocation for each one. 188 // Inform the Frame Information that we have variable-sized objects. 189 MF->getFrameInfo().CreateVariableSizedObject( 190 Alignment <= StackAlign ? Align(1) : Alignment, AI); 191 } 192 } else if (auto *Call = dyn_cast<CallBase>(&I)) { 193 // Look for inline asm that clobbers the SP register. 194 if (Call->isInlineAsm()) { 195 Register SP = TLI->getStackPointerRegisterToSaveRestore(); 196 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 197 std::vector<TargetLowering::AsmOperandInfo> Ops = 198 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, 199 *Call); 200 for (TargetLowering::AsmOperandInfo &Op : Ops) { 201 if (Op.Type == InlineAsm::isClobber) { 202 // Clobbers don't have SDValue operands, hence SDValue(). 203 TLI->ComputeConstraintToUse(Op, SDValue(), DAG); 204 std::pair<unsigned, const TargetRegisterClass *> PhysReg = 205 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode, 206 Op.ConstraintVT); 207 if (PhysReg.first == SP) 208 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 209 } 210 } 211 } 212 // Look for calls to the @llvm.va_start intrinsic. We can omit some 213 // prologue boilerplate for variadic functions that don't examine their 214 // arguments. 215 if (const auto *II = dyn_cast<IntrinsicInst>(&I)) { 216 if (II->getIntrinsicID() == Intrinsic::vastart) 217 MF->getFrameInfo().setHasVAStart(true); 218 } 219 220 // If we have a musttail call in a variadic function, we need to ensure 221 // we forward implicit register parameters. 222 if (const auto *CI = dyn_cast<CallInst>(&I)) { 223 if (CI->isMustTailCall() && Fn->isVarArg()) 224 MF->getFrameInfo().setHasMustTailInVarArgFunc(true); 225 } 226 } 227 228 // Mark values used outside their block as exported, by allocating 229 // a virtual register for them. 230 if (isUsedOutsideOfDefiningBlock(&I)) 231 if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I))) 232 InitializeRegForValue(&I); 233 234 // Decide the preferred extend type for a value. 235 PreferredExtendType[&I] = getPreferredExtendForValue(&I); 236 } 237 } 238 239 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 240 // also creates the initial PHI MachineInstrs, though none of the input 241 // operands are populated. 242 for (const BasicBlock &BB : *Fn) { 243 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks 244 // are really data, and no instructions can live here. 245 if (BB.isEHPad()) { 246 const Instruction *PadInst = BB.getFirstNonPHI(); 247 // If this is a non-landingpad EH pad, mark this function as using 248 // funclets. 249 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid 250 // setting this in such cases in order to improve frame layout. 251 if (!isa<LandingPadInst>(PadInst)) { 252 MF->setHasEHScopes(true); 253 MF->setHasEHFunclets(true); 254 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 255 } 256 if (isa<CatchSwitchInst>(PadInst)) { 257 assert(&*BB.begin() == PadInst && 258 "WinEHPrepare failed to remove PHIs from imaginary BBs"); 259 continue; 260 } 261 if (isa<FuncletPadInst>(PadInst)) 262 assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs"); 263 } 264 265 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB); 266 MBBMap[&BB] = MBB; 267 MF->push_back(MBB); 268 269 // Transfer the address-taken flag. This is necessary because there could 270 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only 271 // the first one should be marked. 272 if (BB.hasAddressTaken()) 273 MBB->setHasAddressTaken(); 274 275 // Mark landing pad blocks. 276 if (BB.isEHPad()) 277 MBB->setIsEHPad(); 278 279 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 280 // appropriate. 281 for (const PHINode &PN : BB.phis()) { 282 if (PN.use_empty()) 283 continue; 284 285 // Skip empty types 286 if (PN.getType()->isEmptyTy()) 287 continue; 288 289 DebugLoc DL = PN.getDebugLoc(); 290 unsigned PHIReg = ValueMap[&PN]; 291 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 292 293 SmallVector<EVT, 4> ValueVTs; 294 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); 295 for (EVT VT : ValueVTs) { 296 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 297 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 298 for (unsigned i = 0; i != NumRegisters; ++i) 299 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); 300 PHIReg += NumRegisters; 301 } 302 } 303 } 304 305 if (isFuncletEHPersonality(Personality)) { 306 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 307 308 // Map all BB references in the WinEH data to MBBs. 309 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 310 for (WinEHHandlerType &H : TBME.HandlerArray) { 311 if (H.Handler) 312 H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()]; 313 } 314 } 315 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap) 316 if (UME.Cleanup) 317 UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()]; 318 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) { 319 const auto *BB = UME.Handler.get<const BasicBlock *>(); 320 UME.Handler = MBBMap[BB]; 321 } 322 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) { 323 const auto *BB = CME.Handler.get<const BasicBlock *>(); 324 CME.Handler = MBBMap[BB]; 325 } 326 } 327 328 else if (Personality == EHPersonality::Wasm_CXX) { 329 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); 330 // Map all BB references in the Wasm EH data to MBBs. 331 DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest; 332 for (auto &KV : EHInfo.SrcToUnwindDest) { 333 const auto *Src = KV.first.get<const BasicBlock *>(); 334 const auto *Dest = KV.second.get<const BasicBlock *>(); 335 SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest]; 336 } 337 EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest); 338 DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs; 339 for (auto &KV : EHInfo.UnwindDestToSrcs) { 340 const auto *Dest = KV.first.get<const BasicBlock *>(); 341 UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>(); 342 for (const auto P : KV.second) 343 UnwindDestToSrcs[MBBMap[Dest]].insert( 344 MBBMap[P.get<const BasicBlock *>()]); 345 } 346 EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs); 347 } 348 } 349 350 /// clear - Clear out all the function-specific state. This returns this 351 /// FunctionLoweringInfo to an empty state, ready to be used for a 352 /// different function. 353 void FunctionLoweringInfo::clear() { 354 MBBMap.clear(); 355 ValueMap.clear(); 356 VirtReg2Value.clear(); 357 StaticAllocaMap.clear(); 358 LiveOutRegInfo.clear(); 359 VisitedBBs.clear(); 360 ArgDbgValues.clear(); 361 DescribedArgs.clear(); 362 ByValArgFrameIndexMap.clear(); 363 RegFixups.clear(); 364 RegsWithFixups.clear(); 365 StatepointStackSlots.clear(); 366 StatepointRelocationMaps.clear(); 367 PreferredExtendType.clear(); 368 } 369 370 /// CreateReg - Allocate a single virtual register for the given type. 371 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { 372 return RegInfo->createVirtualRegister( 373 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); 374 } 375 376 /// CreateRegs - Allocate the appropriate number of virtual registers of 377 /// the correctly promoted or expanded types. Assign these registers 378 /// consecutive vreg numbers and return the first assigned number. 379 /// 380 /// In the case that the given value has struct or array type, this function 381 /// will assign registers for each member or element. 382 /// 383 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { 384 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); 385 386 SmallVector<EVT, 4> ValueVTs; 387 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 388 389 Register FirstReg; 390 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 391 EVT ValueVT = ValueVTs[Value]; 392 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); 393 394 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); 395 for (unsigned i = 0; i != NumRegs; ++i) { 396 Register R = CreateReg(RegisterVT, isDivergent); 397 if (!FirstReg) FirstReg = R; 398 } 399 } 400 return FirstReg; 401 } 402 403 Register FunctionLoweringInfo::CreateRegs(const Value *V) { 404 return CreateRegs(V->getType(), DA && DA->isDivergent(V) && 405 !TLI->requiresUniformRegister(*MF, V)); 406 } 407 408 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 409 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If 410 /// the register's LiveOutInfo is for a smaller bit width, it is extended to 411 /// the larger bit width by zero extension. The bit width must be no smaller 412 /// than the LiveOutInfo's existing bit width. 413 const FunctionLoweringInfo::LiveOutInfo * 414 FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) { 415 if (!LiveOutRegInfo.inBounds(Reg)) 416 return nullptr; 417 418 LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 419 if (!LOI->IsValid) 420 return nullptr; 421 422 if (BitWidth > LOI->Known.getBitWidth()) { 423 LOI->NumSignBits = 1; 424 LOI->Known = LOI->Known.anyext(BitWidth); 425 } 426 427 return LOI; 428 } 429 430 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination 431 /// register based on the LiveOutInfo of its operands. 432 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { 433 Type *Ty = PN->getType(); 434 if (!Ty->isIntegerTy() || Ty->isVectorTy()) 435 return; 436 437 SmallVector<EVT, 1> ValueVTs; 438 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 439 assert(ValueVTs.size() == 1 && 440 "PHIs with non-vector integer types should have a single VT."); 441 EVT IntVT = ValueVTs[0]; 442 443 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) 444 return; 445 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); 446 unsigned BitWidth = IntVT.getSizeInBits(); 447 448 auto It = ValueMap.find(PN); 449 if (It == ValueMap.end()) 450 return; 451 452 Register DestReg = It->second; 453 if (DestReg == 0) 454 return 455 assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg"); 456 LiveOutRegInfo.grow(DestReg); 457 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg]; 458 459 Value *V = PN->getIncomingValue(0); 460 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 461 DestLOI.NumSignBits = 1; 462 DestLOI.Known = KnownBits(BitWidth); 463 return; 464 } 465 466 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 467 APInt Val; 468 if (TLI->signExtendConstant(CI)) 469 Val = CI->getValue().sext(BitWidth); 470 else 471 Val = CI->getValue().zext(BitWidth); 472 DestLOI.NumSignBits = Val.getNumSignBits(); 473 DestLOI.Known = KnownBits::makeConstant(Val); 474 } else { 475 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its" 476 "CopyToReg node was created."); 477 Register SrcReg = ValueMap[V]; 478 if (!Register::isVirtualRegister(SrcReg)) { 479 DestLOI.IsValid = false; 480 return; 481 } 482 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 483 if (!SrcLOI) { 484 DestLOI.IsValid = false; 485 return; 486 } 487 DestLOI = *SrcLOI; 488 } 489 490 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth && 491 DestLOI.Known.One.getBitWidth() == BitWidth && 492 "Masks should have the same bit width as the type."); 493 494 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) { 495 Value *V = PN->getIncomingValue(i); 496 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 497 DestLOI.NumSignBits = 1; 498 DestLOI.Known = KnownBits(BitWidth); 499 return; 500 } 501 502 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 503 APInt Val; 504 if (TLI->signExtendConstant(CI)) 505 Val = CI->getValue().sext(BitWidth); 506 else 507 Val = CI->getValue().zext(BitWidth); 508 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits()); 509 DestLOI.Known.Zero &= ~Val; 510 DestLOI.Known.One &= Val; 511 continue; 512 } 513 514 assert(ValueMap.count(V) && "V should have been placed in ValueMap when " 515 "its CopyToReg node was created."); 516 Register SrcReg = ValueMap[V]; 517 if (!SrcReg.isVirtual()) { 518 DestLOI.IsValid = false; 519 return; 520 } 521 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 522 if (!SrcLOI) { 523 DestLOI.IsValid = false; 524 return; 525 } 526 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits); 527 DestLOI.Known = KnownBits::commonBits(DestLOI.Known, SrcLOI->Known); 528 } 529 } 530 531 /// setArgumentFrameIndex - Record frame index for the byval 532 /// argument. This overrides previous frame index entry for this argument, 533 /// if any. 534 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A, 535 int FI) { 536 ByValArgFrameIndexMap[A] = FI; 537 } 538 539 /// getArgumentFrameIndex - Get frame index for the byval argument. 540 /// If the argument does not have any assigned frame index then 0 is 541 /// returned. 542 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) { 543 auto I = ByValArgFrameIndexMap.find(A); 544 if (I != ByValArgFrameIndexMap.end()) 545 return I->second; 546 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n"); 547 return INT_MAX; 548 } 549 550 Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg( 551 const Value *CPI, const TargetRegisterClass *RC) { 552 MachineRegisterInfo &MRI = MF->getRegInfo(); 553 auto I = CatchPadExceptionPointers.insert({CPI, 0}); 554 Register &VReg = I.first->second; 555 if (I.second) 556 VReg = MRI.createVirtualRegister(RC); 557 assert(VReg && "null vreg in exception pointer table!"); 558 return VReg; 559 } 560 561 const Value * 562 FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) { 563 if (VirtReg2Value.empty()) { 564 SmallVector<EVT, 4> ValueVTs; 565 for (auto &P : ValueMap) { 566 ValueVTs.clear(); 567 ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(), 568 P.first->getType(), ValueVTs); 569 unsigned Reg = P.second; 570 for (EVT VT : ValueVTs) { 571 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 572 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 573 VirtReg2Value[Reg++] = P.first; 574 } 575 } 576 } 577 return VirtReg2Value.lookup(Vreg); 578 } 579