1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating functions from LLVM IR into 10 // Machine IR. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/FunctionLoweringInfo.h" 15 #include "llvm/ADT/APInt.h" 16 #include "llvm/Analysis/UniformityAnalysis.h" 17 #include "llvm/CodeGen/Analysis.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetFrameLowering.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/TargetRegisterInfo.h" 26 #include "llvm/CodeGen/TargetSubtargetInfo.h" 27 #include "llvm/CodeGen/WasmEHFuncInfo.h" 28 #include "llvm/CodeGen/WinEHFuncInfo.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/IR/DerivedTypes.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Instructions.h" 33 #include "llvm/IR/IntrinsicInst.h" 34 #include "llvm/IR/Module.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <algorithm> 39 using namespace llvm; 40 41 #define DEBUG_TYPE "function-lowering-info" 42 43 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 44 /// PHI nodes or outside of the basic block that defines it, or used by a 45 /// switch or atomic instruction, which may expand to multiple basic blocks. 46 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { 47 if (I->use_empty()) return false; 48 if (isa<PHINode>(I)) return true; 49 const BasicBlock *BB = I->getParent(); 50 for (const User *U : I->users()) 51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U)) 52 return true; 53 54 return false; 55 } 56 57 static ISD::NodeType getPreferredExtendForValue(const Instruction *I) { 58 // For the users of the source value being used for compare instruction, if 59 // the number of signed predicate is greater than unsigned predicate, we 60 // prefer to use SIGN_EXTEND. 61 // 62 // With this optimization, we would be able to reduce some redundant sign or 63 // zero extension instruction, and eventually more machine CSE opportunities 64 // can be exposed. 65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 66 unsigned NumOfSigned = 0, NumOfUnsigned = 0; 67 for (const Use &U : I->uses()) { 68 if (const auto *CI = dyn_cast<CmpInst>(U.getUser())) { 69 NumOfSigned += CI->isSigned(); 70 NumOfUnsigned += CI->isUnsigned(); 71 } 72 if (const auto *CallI = dyn_cast<CallBase>(U.getUser())) { 73 if (!CallI->isArgOperand(&U)) 74 continue; 75 unsigned ArgNo = CallI->getArgOperandNo(&U); 76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt); 77 NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt); 78 } 79 } 80 if (NumOfSigned > NumOfUnsigned) 81 ExtendKind = ISD::SIGN_EXTEND; 82 83 return ExtendKind; 84 } 85 86 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, 87 SelectionDAG *DAG) { 88 Fn = &fn; 89 MF = &mf; 90 TLI = MF->getSubtarget().getTargetLowering(); 91 RegInfo = &MF->getRegInfo(); 92 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); 93 UA = DAG->getUniformityInfo(); 94 95 // Check whether the function can return without sret-demotion. 96 SmallVector<ISD::OutputArg, 4> Outs; 97 CallingConv::ID CC = Fn->getCallingConv(); 98 99 GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI, 100 mf.getDataLayout()); 101 CanLowerReturn = 102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext()); 103 104 // If this personality uses funclets, we need to do a bit more work. 105 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects; 106 EHPersonality Personality = classifyEHPersonality( 107 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr); 108 if (isFuncletEHPersonality(Personality)) { 109 // Calculate state numbers if we haven't already. 110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 111 if (Personality == EHPersonality::MSVC_CXX) 112 calculateWinCXXEHStateNumbers(&fn, EHInfo); 113 else if (isAsynchronousEHPersonality(Personality)) 114 calculateSEHStateNumbers(&fn, EHInfo); 115 else if (Personality == EHPersonality::CoreCLR) 116 calculateClrEHStateNumbers(&fn, EHInfo); 117 118 // Map all BB references in the WinEH data to MBBs. 119 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 120 for (WinEHHandlerType &H : TBME.HandlerArray) { 121 if (const AllocaInst *AI = H.CatchObj.Alloca) 122 CatchObjects.insert({AI, {}}).first->second.push_back( 123 &H.CatchObj.FrameIndex); 124 else 125 H.CatchObj.FrameIndex = INT_MAX; 126 } 127 } 128 } 129 130 // Initialize the mapping of values to registers. This is only set up for 131 // instruction values that are used outside of the block that defines 132 // them. 133 const Align StackAlign = TFI->getStackAlign(); 134 for (const BasicBlock &BB : *Fn) { 135 for (const Instruction &I : BB) { 136 if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) { 137 Type *Ty = AI->getAllocatedType(); 138 Align Alignment = AI->getAlign(); 139 140 // Static allocas can be folded into the initial stack frame 141 // adjustment. For targets that don't realign the stack, don't 142 // do this if there is an extra alignment requirement. 143 if (AI->isStaticAlloca() && 144 (TFI->isStackRealignable() || (Alignment <= StackAlign))) { 145 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize()); 146 uint64_t TySize = 147 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue(); 148 149 TySize *= CUI->getZExtValue(); // Get total allocated size. 150 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 151 int FrameIndex = INT_MAX; 152 auto Iter = CatchObjects.find(AI); 153 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) { 154 FrameIndex = MF->getFrameInfo().CreateFixedObject( 155 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true); 156 MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment); 157 } else { 158 FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment, 159 false, AI); 160 } 161 162 // Scalable vectors and structures that contain scalable vectors may 163 // need a special StackID to distinguish them from other (fixed size) 164 // stack objects. 165 if (Ty->isScalableTy()) 166 MF->getFrameInfo().setStackID(FrameIndex, 167 TFI->getStackIDForScalableVectors()); 168 169 StaticAllocaMap[AI] = FrameIndex; 170 // Update the catch handler information. 171 if (Iter != CatchObjects.end()) { 172 for (int *CatchObjPtr : Iter->second) 173 *CatchObjPtr = FrameIndex; 174 } 175 } else { 176 // FIXME: Overaligned static allocas should be grouped into 177 // a single dynamic allocation instead of using a separate 178 // stack allocation for each one. 179 // Inform the Frame Information that we have variable-sized objects. 180 MF->getFrameInfo().CreateVariableSizedObject( 181 Alignment <= StackAlign ? Align(1) : Alignment, AI); 182 } 183 } else if (auto *Call = dyn_cast<CallBase>(&I)) { 184 // Look for inline asm that clobbers the SP register. 185 if (Call->isInlineAsm()) { 186 Register SP = TLI->getStackPointerRegisterToSaveRestore(); 187 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 188 std::vector<TargetLowering::AsmOperandInfo> Ops = 189 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, 190 *Call); 191 for (TargetLowering::AsmOperandInfo &Op : Ops) { 192 if (Op.Type == InlineAsm::isClobber) { 193 // Clobbers don't have SDValue operands, hence SDValue(). 194 TLI->ComputeConstraintToUse(Op, SDValue(), DAG); 195 std::pair<unsigned, const TargetRegisterClass *> PhysReg = 196 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode, 197 Op.ConstraintVT); 198 if (PhysReg.first == SP) 199 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 200 } 201 } 202 } 203 // Look for calls to the @llvm.va_start intrinsic. We can omit some 204 // prologue boilerplate for variadic functions that don't examine their 205 // arguments. 206 if (const auto *II = dyn_cast<IntrinsicInst>(&I)) { 207 if (II->getIntrinsicID() == Intrinsic::vastart) 208 MF->getFrameInfo().setHasVAStart(true); 209 } 210 211 // If we have a musttail call in a variadic function, we need to ensure 212 // we forward implicit register parameters. 213 if (const auto *CI = dyn_cast<CallInst>(&I)) { 214 if (CI->isMustTailCall() && Fn->isVarArg()) 215 MF->getFrameInfo().setHasMustTailInVarArgFunc(true); 216 } 217 } 218 219 // Mark values used outside their block as exported, by allocating 220 // a virtual register for them. 221 if (isUsedOutsideOfDefiningBlock(&I)) 222 if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I))) 223 InitializeRegForValue(&I); 224 225 // Decide the preferred extend type for a value. 226 PreferredExtendType[&I] = getPreferredExtendForValue(&I); 227 } 228 } 229 230 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 231 // also creates the initial PHI MachineInstrs, though none of the input 232 // operands are populated. 233 for (const BasicBlock &BB : *Fn) { 234 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks 235 // are really data, and no instructions can live here. 236 if (BB.isEHPad()) { 237 const Instruction *PadInst = BB.getFirstNonPHI(); 238 // If this is a non-landingpad EH pad, mark this function as using 239 // funclets. 240 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid 241 // setting this in such cases in order to improve frame layout. 242 if (!isa<LandingPadInst>(PadInst)) { 243 MF->setHasEHScopes(true); 244 MF->setHasEHFunclets(true); 245 MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 246 } 247 if (isa<CatchSwitchInst>(PadInst)) { 248 assert(&*BB.begin() == PadInst && 249 "WinEHPrepare failed to remove PHIs from imaginary BBs"); 250 continue; 251 } 252 if (isa<FuncletPadInst>(PadInst)) 253 assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs"); 254 } 255 256 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB); 257 MBBMap[&BB] = MBB; 258 MF->push_back(MBB); 259 260 // Transfer the address-taken flag. This is necessary because there could 261 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only 262 // the first one should be marked. 263 if (BB.hasAddressTaken()) 264 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB)); 265 266 // Mark landing pad blocks. 267 if (BB.isEHPad()) 268 MBB->setIsEHPad(); 269 270 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 271 // appropriate. 272 for (const PHINode &PN : BB.phis()) { 273 if (PN.use_empty()) 274 continue; 275 276 // Skip empty types 277 if (PN.getType()->isEmptyTy()) 278 continue; 279 280 DebugLoc DL = PN.getDebugLoc(); 281 unsigned PHIReg = ValueMap[&PN]; 282 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 283 284 SmallVector<EVT, 4> ValueVTs; 285 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); 286 for (EVT VT : ValueVTs) { 287 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 288 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 289 for (unsigned i = 0; i != NumRegisters; ++i) 290 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); 291 PHIReg += NumRegisters; 292 } 293 } 294 } 295 296 if (isFuncletEHPersonality(Personality)) { 297 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 298 299 // Map all BB references in the WinEH data to MBBs. 300 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 301 for (WinEHHandlerType &H : TBME.HandlerArray) { 302 if (H.Handler) 303 H.Handler = MBBMap[cast<const BasicBlock *>(H.Handler)]; 304 } 305 } 306 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap) 307 if (UME.Cleanup) 308 UME.Cleanup = MBBMap[cast<const BasicBlock *>(UME.Cleanup)]; 309 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) { 310 const auto *BB = cast<const BasicBlock *>(UME.Handler); 311 UME.Handler = MBBMap[BB]; 312 } 313 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) { 314 const auto *BB = cast<const BasicBlock *>(CME.Handler); 315 CME.Handler = MBBMap[BB]; 316 } 317 } else if (Personality == EHPersonality::Wasm_CXX) { 318 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); 319 calculateWasmEHInfo(&fn, EHInfo); 320 321 // Map all BB references in the Wasm EH data to MBBs. 322 DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest; 323 for (auto &KV : EHInfo.SrcToUnwindDest) { 324 const auto *Src = cast<const BasicBlock *>(KV.first); 325 const auto *Dest = cast<const BasicBlock *>(KV.second); 326 SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest]; 327 } 328 EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest); 329 DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs; 330 for (auto &KV : EHInfo.UnwindDestToSrcs) { 331 const auto *Dest = cast<const BasicBlock *>(KV.first); 332 UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>(); 333 for (const auto P : KV.second) 334 UnwindDestToSrcs[MBBMap[Dest]].insert( 335 MBBMap[cast<const BasicBlock *>(P)]); 336 } 337 EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs); 338 } 339 } 340 341 /// clear - Clear out all the function-specific state. This returns this 342 /// FunctionLoweringInfo to an empty state, ready to be used for a 343 /// different function. 344 void FunctionLoweringInfo::clear() { 345 MBBMap.clear(); 346 ValueMap.clear(); 347 VirtReg2Value.clear(); 348 StaticAllocaMap.clear(); 349 LiveOutRegInfo.clear(); 350 VisitedBBs.clear(); 351 ArgDbgValues.clear(); 352 DescribedArgs.clear(); 353 ByValArgFrameIndexMap.clear(); 354 RegFixups.clear(); 355 RegsWithFixups.clear(); 356 StatepointStackSlots.clear(); 357 StatepointRelocationMaps.clear(); 358 PreferredExtendType.clear(); 359 PreprocessedDbgDeclares.clear(); 360 PreprocessedDPVDeclares.clear(); 361 } 362 363 /// CreateReg - Allocate a single virtual register for the given type. 364 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { 365 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); 366 } 367 368 /// CreateRegs - Allocate the appropriate number of virtual registers of 369 /// the correctly promoted or expanded types. Assign these registers 370 /// consecutive vreg numbers and return the first assigned number. 371 /// 372 /// In the case that the given value has struct or array type, this function 373 /// will assign registers for each member or element. 374 /// 375 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { 376 SmallVector<EVT, 4> ValueVTs; 377 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 378 379 Register FirstReg; 380 for (EVT ValueVT : ValueVTs) { 381 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); 382 383 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); 384 for (unsigned i = 0; i != NumRegs; ++i) { 385 Register R = CreateReg(RegisterVT, isDivergent); 386 if (!FirstReg) FirstReg = R; 387 } 388 } 389 return FirstReg; 390 } 391 392 Register FunctionLoweringInfo::CreateRegs(const Value *V) { 393 return CreateRegs(V->getType(), UA && UA->isDivergent(V) && 394 !TLI->requiresUniformRegister(*MF, V)); 395 } 396 397 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 398 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If 399 /// the register's LiveOutInfo is for a smaller bit width, it is extended to 400 /// the larger bit width by zero extension. The bit width must be no smaller 401 /// than the LiveOutInfo's existing bit width. 402 const FunctionLoweringInfo::LiveOutInfo * 403 FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) { 404 if (!LiveOutRegInfo.inBounds(Reg)) 405 return nullptr; 406 407 LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 408 if (!LOI->IsValid) 409 return nullptr; 410 411 if (BitWidth > LOI->Known.getBitWidth()) { 412 LOI->NumSignBits = 1; 413 LOI->Known = LOI->Known.anyext(BitWidth); 414 } 415 416 return LOI; 417 } 418 419 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination 420 /// register based on the LiveOutInfo of its operands. 421 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { 422 Type *Ty = PN->getType(); 423 if (!Ty->isIntegerTy() || Ty->isVectorTy()) 424 return; 425 426 SmallVector<EVT, 1> ValueVTs; 427 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 428 assert(ValueVTs.size() == 1 && 429 "PHIs with non-vector integer types should have a single VT."); 430 EVT IntVT = ValueVTs[0]; 431 432 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) 433 return; 434 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); 435 unsigned BitWidth = IntVT.getSizeInBits(); 436 437 auto It = ValueMap.find(PN); 438 if (It == ValueMap.end()) 439 return; 440 441 Register DestReg = It->second; 442 if (DestReg == 0) 443 return; 444 assert(DestReg.isVirtual() && "Expected a virtual reg"); 445 LiveOutRegInfo.grow(DestReg); 446 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg]; 447 448 Value *V = PN->getIncomingValue(0); 449 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 450 DestLOI.NumSignBits = 1; 451 DestLOI.Known = KnownBits(BitWidth); 452 return; 453 } 454 455 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 456 APInt Val; 457 if (TLI->signExtendConstant(CI)) 458 Val = CI->getValue().sext(BitWidth); 459 else 460 Val = CI->getValue().zext(BitWidth); 461 DestLOI.NumSignBits = Val.getNumSignBits(); 462 DestLOI.Known = KnownBits::makeConstant(Val); 463 } else { 464 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its" 465 "CopyToReg node was created."); 466 Register SrcReg = ValueMap[V]; 467 if (!SrcReg.isVirtual()) { 468 DestLOI.IsValid = false; 469 return; 470 } 471 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 472 if (!SrcLOI) { 473 DestLOI.IsValid = false; 474 return; 475 } 476 DestLOI = *SrcLOI; 477 } 478 479 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth && 480 DestLOI.Known.One.getBitWidth() == BitWidth && 481 "Masks should have the same bit width as the type."); 482 483 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) { 484 Value *V = PN->getIncomingValue(i); 485 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 486 DestLOI.NumSignBits = 1; 487 DestLOI.Known = KnownBits(BitWidth); 488 return; 489 } 490 491 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 492 APInt Val; 493 if (TLI->signExtendConstant(CI)) 494 Val = CI->getValue().sext(BitWidth); 495 else 496 Val = CI->getValue().zext(BitWidth); 497 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits()); 498 DestLOI.Known.Zero &= ~Val; 499 DestLOI.Known.One &= Val; 500 continue; 501 } 502 503 assert(ValueMap.count(V) && "V should have been placed in ValueMap when " 504 "its CopyToReg node was created."); 505 Register SrcReg = ValueMap[V]; 506 if (!SrcReg.isVirtual()) { 507 DestLOI.IsValid = false; 508 return; 509 } 510 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 511 if (!SrcLOI) { 512 DestLOI.IsValid = false; 513 return; 514 } 515 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits); 516 DestLOI.Known = DestLOI.Known.intersectWith(SrcLOI->Known); 517 } 518 } 519 520 /// setArgumentFrameIndex - Record frame index for the byval 521 /// argument. This overrides previous frame index entry for this argument, 522 /// if any. 523 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A, 524 int FI) { 525 ByValArgFrameIndexMap[A] = FI; 526 } 527 528 /// getArgumentFrameIndex - Get frame index for the byval argument. 529 /// If the argument does not have any assigned frame index then 0 is 530 /// returned. 531 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) { 532 auto I = ByValArgFrameIndexMap.find(A); 533 if (I != ByValArgFrameIndexMap.end()) 534 return I->second; 535 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n"); 536 return INT_MAX; 537 } 538 539 Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg( 540 const Value *CPI, const TargetRegisterClass *RC) { 541 MachineRegisterInfo &MRI = MF->getRegInfo(); 542 auto I = CatchPadExceptionPointers.insert({CPI, 0}); 543 Register &VReg = I.first->second; 544 if (I.second) 545 VReg = MRI.createVirtualRegister(RC); 546 assert(VReg && "null vreg in exception pointer table!"); 547 return VReg; 548 } 549 550 const Value * 551 FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) { 552 if (VirtReg2Value.empty()) { 553 SmallVector<EVT, 4> ValueVTs; 554 for (auto &P : ValueMap) { 555 ValueVTs.clear(); 556 ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(), 557 P.first->getType(), ValueVTs); 558 unsigned Reg = P.second; 559 for (EVT VT : ValueVTs) { 560 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 561 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 562 VirtReg2Value[Reg++] = P.first; 563 } 564 } 565 } 566 return VirtReg2Value.lookup(Vreg); 567 } 568