1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// This pass is required to take advantage of the interprocedural register 10 /// allocation infrastructure. 11 /// 12 /// This pass is simple MachineFunction pass which collects register usage 13 /// details by iterating through each physical registers and checking 14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details. 15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp 16 /// 17 //===----------------------------------------------------------------------===// 18 19 #include "llvm/ADT/Statistic.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/MachineOperand.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/Passes.h" 24 #include "llvm/CodeGen/RegisterUsageInfo.h" 25 #include "llvm/CodeGen/TargetFrameLowering.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "ip-regalloc" 33 34 STATISTIC(NumCSROpt, 35 "Number of functions optimized for callee saved registers"); 36 37 namespace { 38 39 class RegUsageInfoCollector : public MachineFunctionPass { 40 public: 41 RegUsageInfoCollector() : MachineFunctionPass(ID) { 42 PassRegistry &Registry = *PassRegistry::getPassRegistry(); 43 initializeRegUsageInfoCollectorPass(Registry); 44 } 45 46 StringRef getPassName() const override { 47 return "Register Usage Information Collector Pass"; 48 } 49 50 void getAnalysisUsage(AnalysisUsage &AU) const override { 51 AU.addRequired<PhysicalRegisterUsageInfo>(); 52 AU.setPreservesAll(); 53 MachineFunctionPass::getAnalysisUsage(AU); 54 } 55 56 bool runOnMachineFunction(MachineFunction &MF) override; 57 58 // Call getCalleeSaves and then also set the bits for subregs and 59 // fully saved superregs. 60 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF); 61 62 static char ID; 63 }; 64 65 } // end of anonymous namespace 66 67 char RegUsageInfoCollector::ID = 0; 68 69 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", 70 "Register Usage Information Collector", false, false) 71 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo) 72 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector", 73 "Register Usage Information Collector", false, false) 74 75 FunctionPass *llvm::createRegUsageInfoCollector() { 76 return new RegUsageInfoCollector(); 77 } 78 79 // TODO: Move to hook somwehere? 80 81 // Return true if it is useful to track the used registers for IPRA / no CSR 82 // optimizations. This is not useful for entry points, and computing the 83 // register usage information is expensive. 84 static bool isCallableFunction(const MachineFunction &MF) { 85 switch (MF.getFunction().getCallingConv()) { 86 case CallingConv::AMDGPU_VS: 87 case CallingConv::AMDGPU_GS: 88 case CallingConv::AMDGPU_PS: 89 case CallingConv::AMDGPU_CS: 90 case CallingConv::AMDGPU_HS: 91 case CallingConv::AMDGPU_ES: 92 case CallingConv::AMDGPU_LS: 93 case CallingConv::AMDGPU_KERNEL: 94 return false; 95 default: 96 return true; 97 } 98 } 99 100 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { 101 MachineRegisterInfo *MRI = &MF.getRegInfo(); 102 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 103 const LLVMTargetMachine &TM = MF.getTarget(); 104 105 LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() 106 << " -------------------- \nFunction Name : " 107 << MF.getName() << '\n'); 108 109 // Analyzing the register usage may be expensive on some targets. 110 if (!isCallableFunction(MF)) { 111 LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n"); 112 return false; 113 } 114 115 // If there are no callers, there's no point in computing more precise 116 // register usage here. 117 if (MF.getFunction().use_empty()) { 118 LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n"); 119 return false; 120 } 121 122 std::vector<uint32_t> RegMask; 123 124 // Compute the size of the bit vector to represent all the registers. 125 // The bit vector is broken into 32-bit chunks, thus takes the ceil of 126 // the number of registers divided by 32 for the size. 127 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); 128 RegMask.resize(RegMaskSize, ~((uint32_t)0)); 129 130 const Function &F = MF.getFunction(); 131 132 PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>(); 133 PRUI.setTargetMachine(TM); 134 135 LLVM_DEBUG(dbgs() << "Clobbered Registers: "); 136 137 BitVector SavedRegs; 138 computeCalleeSavedRegs(SavedRegs, MF); 139 140 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); 141 auto SetRegAsDefined = [&RegMask] (unsigned Reg) { 142 RegMask[Reg / 32] &= ~(1u << Reg % 32); 143 }; 144 145 // Some targets can clobber registers "inside" a call, typically in 146 // linker-generated code. 147 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF)) 148 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 149 SetRegAsDefined(*AI); 150 151 // Scan all the physical registers. When a register is defined in the current 152 // function set it and all the aliasing registers as defined in the regmask. 153 // FIXME: Rewrite to use regunits. 154 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 155 // Don't count registers that are saved and restored. 156 if (SavedRegs.test(PReg)) 157 continue; 158 // If a register is defined by an instruction mark it as defined together 159 // with all it's unsaved aliases. 160 if (!MRI->def_empty(PReg)) { 161 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) 162 if (!SavedRegs.test(*AI)) 163 SetRegAsDefined(*AI); 164 continue; 165 } 166 // If a register is in the UsedPhysRegsMask set then mark it as defined. 167 // All clobbered aliases will also be in the set, so we can skip setting 168 // as defined all the aliases here. 169 if (UsedPhysRegsMask.test(PReg)) 170 SetRegAsDefined(PReg); 171 } 172 173 if (TargetFrameLowering::isSafeForNoCSROpt(F) && 174 MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) { 175 ++NumCSROpt; 176 LLVM_DEBUG(dbgs() << MF.getName() 177 << " function optimized for not having CSR.\n"); 178 } 179 180 LLVM_DEBUG( 181 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 182 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) 183 dbgs() << printReg(PReg, TRI) << " "; 184 } 185 186 dbgs() << " \n----------------------------------------\n"; 187 ); 188 189 PRUI.storeUpdateRegUsageInfo(F, RegMask); 190 191 return false; 192 } 193 194 void RegUsageInfoCollector:: 195 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { 196 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering(); 197 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 198 199 // Target will return the set of registers that it saves/restores as needed. 200 SavedRegs.clear(); 201 TFI.getCalleeSaves(MF, SavedRegs); 202 if (SavedRegs.none()) 203 return; 204 205 // Insert subregs. 206 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); 207 for (unsigned i = 0; CSRegs[i]; ++i) { 208 MCPhysReg Reg = CSRegs[i]; 209 if (SavedRegs.test(Reg)) { 210 // Save subregisters 211 for (MCPhysReg SR : TRI.subregs(Reg)) 212 SavedRegs.set(SR); 213 } 214 } 215 } 216