xref: /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/CodeGen/MIRFormatter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/IRPrintingPasses.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/Target/TargetIntrinsicInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 
32 using namespace llvm;
33 
34 static cl::opt<int>
35     PrintRegMaskNumRegs("print-regmask-num-regs",
36                         cl::desc("Number of registers to limit to when "
37                                  "printing regmask operands in IR dumps. "
38                                  "unlimited = -1"),
39                         cl::init(32), cl::Hidden);
40 
41 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
42   if (const MachineInstr *MI = MO.getParent())
43     if (const MachineBasicBlock *MBB = MI->getParent())
44       if (const MachineFunction *MF = MBB->getParent())
45         return MF;
46   return nullptr;
47 }
48 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
49   return const_cast<MachineFunction *>(
50       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
51 }
52 
53 void MachineOperand::setReg(Register Reg) {
54   if (getReg() == Reg)
55     return; // No change.
56 
57   // Clear the IsRenamable bit to keep it conservatively correct.
58   IsRenamable = false;
59 
60   // Otherwise, we have to change the register.  If this operand is embedded
61   // into a machine function, we need to update the old and new register's
62   // use/def lists.
63   if (MachineFunction *MF = getMFIfAvailable(*this)) {
64     MachineRegisterInfo &MRI = MF->getRegInfo();
65     MRI.removeRegOperandFromUseList(this);
66     SmallContents.RegNo = Reg;
67     MRI.addRegOperandToUseList(this);
68     return;
69   }
70 
71   // Otherwise, just change the register, no problem.  :)
72   SmallContents.RegNo = Reg;
73 }
74 
75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
76                                   const TargetRegisterInfo &TRI) {
77   assert(Reg.isVirtual());
78   if (SubIdx && getSubReg())
79     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80   setReg(Reg);
81   if (SubIdx)
82     setSubReg(SubIdx);
83 }
84 
85 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
86   assert(Register::isPhysicalRegister(Reg));
87   if (getSubReg()) {
88     Reg = TRI.getSubReg(Reg, getSubReg());
89     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
90     // That won't happen in legal code.
91     setSubReg(0);
92     if (isDef())
93       setIsUndef(false);
94   }
95   setReg(Reg);
96 }
97 
98 /// Change a def to a use, or a use to a def.
99 void MachineOperand::setIsDef(bool Val) {
100   assert(isReg() && "Wrong MachineOperand accessor");
101   assert((!Val || !isDebug()) && "Marking a debug operation as def");
102   if (IsDef == Val)
103     return;
104   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
105   // MRI may keep uses and defs in different list positions.
106   if (MachineFunction *MF = getMFIfAvailable(*this)) {
107     MachineRegisterInfo &MRI = MF->getRegInfo();
108     MRI.removeRegOperandFromUseList(this);
109     IsDef = Val;
110     MRI.addRegOperandToUseList(this);
111     return;
112   }
113   IsDef = Val;
114 }
115 
116 bool MachineOperand::isRenamable() const {
117   assert(isReg() && "Wrong MachineOperand accessor");
118   assert(Register::isPhysicalRegister(getReg()) &&
119          "isRenamable should only be checked on physical registers");
120   if (!IsRenamable)
121     return false;
122 
123   const MachineInstr *MI = getParent();
124   if (!MI)
125     return true;
126 
127   if (isDef())
128     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
129 
130   assert(isUse() && "Reg is not def or use");
131   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
132 }
133 
134 void MachineOperand::setIsRenamable(bool Val) {
135   assert(isReg() && "Wrong MachineOperand accessor");
136   assert(Register::isPhysicalRegister(getReg()) &&
137          "setIsRenamable should only be called on physical registers");
138   IsRenamable = Val;
139 }
140 
141 // If this operand is currently a register operand, and if this is in a
142 // function, deregister the operand from the register's use/def list.
143 void MachineOperand::removeRegFromUses() {
144   if (!isReg() || !isOnRegUseList())
145     return;
146 
147   if (MachineFunction *MF = getMFIfAvailable(*this))
148     MF->getRegInfo().removeRegOperandFromUseList(this);
149 }
150 
151 /// ChangeToImmediate - Replace this operand with a new immediate operand of
152 /// the specified value.  If an operand is known to be an immediate already,
153 /// the setImm method should be used.
154 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
155   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
156 
157   removeRegFromUses();
158 
159   OpKind = MO_Immediate;
160   Contents.ImmVal = ImmVal;
161   setTargetFlags(TargetFlags);
162 }
163 
164 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
165                                          unsigned TargetFlags) {
166   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
167 
168   removeRegFromUses();
169 
170   OpKind = MO_FPImmediate;
171   Contents.CFP = FPImm;
172   setTargetFlags(TargetFlags);
173 }
174 
175 void MachineOperand::ChangeToES(const char *SymName,
176                                 unsigned TargetFlags) {
177   assert((!isReg() || !isTied()) &&
178          "Cannot change a tied operand into an external symbol");
179 
180   removeRegFromUses();
181 
182   OpKind = MO_ExternalSymbol;
183   Contents.OffsetedInfo.Val.SymbolName = SymName;
184   setOffset(0); // Offset is always 0.
185   setTargetFlags(TargetFlags);
186 }
187 
188 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
189                                 unsigned TargetFlags) {
190   assert((!isReg() || !isTied()) &&
191          "Cannot change a tied operand into a global address");
192 
193   removeRegFromUses();
194 
195   OpKind = MO_GlobalAddress;
196   Contents.OffsetedInfo.Val.GV = GV;
197   setOffset(Offset);
198   setTargetFlags(TargetFlags);
199 }
200 
201 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
202   assert((!isReg() || !isTied()) &&
203          "Cannot change a tied operand into an MCSymbol");
204 
205   removeRegFromUses();
206 
207   OpKind = MO_MCSymbol;
208   Contents.Sym = Sym;
209   setTargetFlags(TargetFlags);
210 }
211 
212 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
213   assert((!isReg() || !isTied()) &&
214          "Cannot change a tied operand into a FrameIndex");
215 
216   removeRegFromUses();
217 
218   OpKind = MO_FrameIndex;
219   setIndex(Idx);
220   setTargetFlags(TargetFlags);
221 }
222 
223 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
224                                          unsigned TargetFlags) {
225   assert((!isReg() || !isTied()) &&
226          "Cannot change a tied operand into a FrameIndex");
227 
228   removeRegFromUses();
229 
230   OpKind = MO_TargetIndex;
231   setIndex(Idx);
232   setOffset(Offset);
233   setTargetFlags(TargetFlags);
234 }
235 
236 /// ChangeToRegister - Replace this operand with a new register operand of
237 /// the specified value.  If an operand is known to be an register already,
238 /// the setReg method should be used.
239 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
240                                       bool isKill, bool isDead, bool isUndef,
241                                       bool isDebug) {
242   MachineRegisterInfo *RegInfo = nullptr;
243   if (MachineFunction *MF = getMFIfAvailable(*this))
244     RegInfo = &MF->getRegInfo();
245   // If this operand is already a register operand, remove it from the
246   // register's use/def lists.
247   bool WasReg = isReg();
248   if (RegInfo && WasReg)
249     RegInfo->removeRegOperandFromUseList(this);
250 
251   // Ensure debug instructions set debug flag on register uses.
252   const MachineInstr *MI = getParent();
253   if (!isDef && MI && MI->isDebugInstr())
254     isDebug = true;
255 
256   // Change this to a register and set the reg#.
257   assert(!(isDead && !isDef) && "Dead flag on non-def");
258   assert(!(isKill && isDef) && "Kill flag on def");
259   OpKind = MO_Register;
260   SmallContents.RegNo = Reg;
261   SubReg_TargetFlags = 0;
262   IsDef = isDef;
263   IsImp = isImp;
264   IsDeadOrKill = isKill | isDead;
265   IsRenamable = false;
266   IsUndef = isUndef;
267   IsInternalRead = false;
268   IsEarlyClobber = false;
269   IsDebug = isDebug;
270   // Ensure isOnRegUseList() returns false.
271   Contents.Reg.Prev = nullptr;
272   // Preserve the tie when the operand was already a register.
273   if (!WasReg)
274     TiedTo = 0;
275 
276   // If this operand is embedded in a function, add the operand to the
277   // register's use/def list.
278   if (RegInfo)
279     RegInfo->addRegOperandToUseList(this);
280 }
281 
282 /// isIdenticalTo - Return true if this operand is identical to the specified
283 /// operand. Note that this should stay in sync with the hash_value overload
284 /// below.
285 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
286   if (getType() != Other.getType() ||
287       getTargetFlags() != Other.getTargetFlags())
288     return false;
289 
290   switch (getType()) {
291   case MachineOperand::MO_Register:
292     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
293            getSubReg() == Other.getSubReg();
294   case MachineOperand::MO_Immediate:
295     return getImm() == Other.getImm();
296   case MachineOperand::MO_CImmediate:
297     return getCImm() == Other.getCImm();
298   case MachineOperand::MO_FPImmediate:
299     return getFPImm() == Other.getFPImm();
300   case MachineOperand::MO_MachineBasicBlock:
301     return getMBB() == Other.getMBB();
302   case MachineOperand::MO_FrameIndex:
303     return getIndex() == Other.getIndex();
304   case MachineOperand::MO_ConstantPoolIndex:
305   case MachineOperand::MO_TargetIndex:
306     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
307   case MachineOperand::MO_JumpTableIndex:
308     return getIndex() == Other.getIndex();
309   case MachineOperand::MO_GlobalAddress:
310     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
311   case MachineOperand::MO_ExternalSymbol:
312     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
313            getOffset() == Other.getOffset();
314   case MachineOperand::MO_BlockAddress:
315     return getBlockAddress() == Other.getBlockAddress() &&
316            getOffset() == Other.getOffset();
317   case MachineOperand::MO_RegisterMask:
318   case MachineOperand::MO_RegisterLiveOut: {
319     // Shallow compare of the two RegMasks
320     const uint32_t *RegMask = getRegMask();
321     const uint32_t *OtherRegMask = Other.getRegMask();
322     if (RegMask == OtherRegMask)
323       return true;
324 
325     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
326       // Calculate the size of the RegMask
327       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
328       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
329 
330       // Deep compare of the two RegMasks
331       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
332     }
333     // We don't know the size of the RegMask, so we can't deep compare the two
334     // reg masks.
335     return false;
336   }
337   case MachineOperand::MO_MCSymbol:
338     return getMCSymbol() == Other.getMCSymbol();
339   case MachineOperand::MO_CFIIndex:
340     return getCFIIndex() == Other.getCFIIndex();
341   case MachineOperand::MO_Metadata:
342     return getMetadata() == Other.getMetadata();
343   case MachineOperand::MO_IntrinsicID:
344     return getIntrinsicID() == Other.getIntrinsicID();
345   case MachineOperand::MO_Predicate:
346     return getPredicate() == Other.getPredicate();
347   case MachineOperand::MO_ShuffleMask:
348     return getShuffleMask() == Other.getShuffleMask();
349   }
350   llvm_unreachable("Invalid machine operand type");
351 }
352 
353 // Note: this must stay exactly in sync with isIdenticalTo above.
354 hash_code llvm::hash_value(const MachineOperand &MO) {
355   switch (MO.getType()) {
356   case MachineOperand::MO_Register:
357     // Register operands don't have target flags.
358     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
359   case MachineOperand::MO_Immediate:
360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
361   case MachineOperand::MO_CImmediate:
362     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
363   case MachineOperand::MO_FPImmediate:
364     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
365   case MachineOperand::MO_MachineBasicBlock:
366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
367   case MachineOperand::MO_FrameIndex:
368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
369   case MachineOperand::MO_ConstantPoolIndex:
370   case MachineOperand::MO_TargetIndex:
371     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
372                         MO.getOffset());
373   case MachineOperand::MO_JumpTableIndex:
374     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
375   case MachineOperand::MO_ExternalSymbol:
376     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
377                         StringRef(MO.getSymbolName()));
378   case MachineOperand::MO_GlobalAddress:
379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
380                         MO.getOffset());
381   case MachineOperand::MO_BlockAddress:
382     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
383                         MO.getOffset());
384   case MachineOperand::MO_RegisterMask:
385   case MachineOperand::MO_RegisterLiveOut:
386     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
387   case MachineOperand::MO_Metadata:
388     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
389   case MachineOperand::MO_MCSymbol:
390     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
391   case MachineOperand::MO_CFIIndex:
392     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
393   case MachineOperand::MO_IntrinsicID:
394     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
395   case MachineOperand::MO_Predicate:
396     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
397   case MachineOperand::MO_ShuffleMask:
398     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
399   }
400   llvm_unreachable("Invalid machine operand type");
401 }
402 
403 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
404 // it.
405 static void tryToGetTargetInfo(const MachineOperand &MO,
406                                const TargetRegisterInfo *&TRI,
407                                const TargetIntrinsicInfo *&IntrinsicInfo) {
408   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
409     TRI = MF->getSubtarget().getRegisterInfo();
410     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
411   }
412 }
413 
414 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
415   const auto *TII = MF.getSubtarget().getInstrInfo();
416   assert(TII && "expected instruction info");
417   auto Indices = TII->getSerializableTargetIndices();
418   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
419     return I.first == Index;
420   });
421   if (Found != Indices.end())
422     return Found->second;
423   return nullptr;
424 }
425 
426 const char *MachineOperand::getTargetIndexName() const {
427   const MachineFunction *MF = getMFIfAvailable(*this);
428   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
429 }
430 
431 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
432   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
433   for (const auto &I : Flags) {
434     if (I.first == TF) {
435       return I.second;
436     }
437   }
438   return nullptr;
439 }
440 
441 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
442                              const TargetRegisterInfo *TRI) {
443   if (!TRI) {
444     OS << "%dwarfreg." << DwarfReg;
445     return;
446   }
447 
448   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
449     OS << printReg(*Reg, TRI);
450   else
451     OS << "<badreg>";
452 }
453 
454 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
455                                   ModuleSlotTracker &MST) {
456   OS << "%ir-block.";
457   if (BB.hasName()) {
458     printLLVMNameWithoutPrefix(OS, BB.getName());
459     return;
460   }
461   Optional<int> Slot;
462   if (const Function *F = BB.getParent()) {
463     if (F == MST.getCurrentFunction()) {
464       Slot = MST.getLocalSlot(&BB);
465     } else if (const Module *M = F->getParent()) {
466       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
467       CustomMST.incorporateFunction(*F);
468       Slot = CustomMST.getLocalSlot(&BB);
469     }
470   }
471   if (Slot)
472     MachineOperand::printIRSlotNumber(OS, *Slot);
473   else
474     OS << "<unknown>";
475 }
476 
477 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
478                            SyncScope::ID SSID,
479                            SmallVectorImpl<StringRef> &SSNs) {
480   switch (SSID) {
481   case SyncScope::System:
482     break;
483   default:
484     if (SSNs.empty())
485       Context.getSyncScopeNames(SSNs);
486 
487     OS << "syncscope(\"";
488     printEscapedString(SSNs[SSID], OS);
489     OS << "\") ";
490     break;
491   }
492 }
493 
494 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
495                                         unsigned TMMOFlag) {
496   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
497   for (const auto &I : Flags) {
498     if (I.first == TMMOFlag) {
499       return I.second;
500     }
501   }
502   return nullptr;
503 }
504 
505 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
506                             const MachineFrameInfo *MFI) {
507   StringRef Name;
508   if (MFI) {
509     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
510     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
511       if (Alloca->hasName())
512         Name = Alloca->getName();
513     if (IsFixed)
514       FrameIndex -= MFI->getObjectIndexBegin();
515   }
516   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
517 }
518 
519 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
520                                     const TargetRegisterInfo *TRI) {
521   OS << "%subreg.";
522   if (TRI)
523     OS << TRI->getSubRegIndexName(Index);
524   else
525     OS << Index;
526 }
527 
528 void MachineOperand::printTargetFlags(raw_ostream &OS,
529                                       const MachineOperand &Op) {
530   if (!Op.getTargetFlags())
531     return;
532   const MachineFunction *MF = getMFIfAvailable(Op);
533   if (!MF)
534     return;
535 
536   const auto *TII = MF->getSubtarget().getInstrInfo();
537   assert(TII && "expected instruction info");
538   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
539   OS << "target-flags(";
540   const bool HasDirectFlags = Flags.first;
541   const bool HasBitmaskFlags = Flags.second;
542   if (!HasDirectFlags && !HasBitmaskFlags) {
543     OS << "<unknown>) ";
544     return;
545   }
546   if (HasDirectFlags) {
547     if (const auto *Name = getTargetFlagName(TII, Flags.first))
548       OS << Name;
549     else
550       OS << "<unknown target flag>";
551   }
552   if (!HasBitmaskFlags) {
553     OS << ") ";
554     return;
555   }
556   bool IsCommaNeeded = HasDirectFlags;
557   unsigned BitMask = Flags.second;
558   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
559   for (const auto &Mask : BitMasks) {
560     // Check if the flag's bitmask has the bits of the current mask set.
561     if ((BitMask & Mask.first) == Mask.first) {
562       if (IsCommaNeeded)
563         OS << ", ";
564       IsCommaNeeded = true;
565       OS << Mask.second;
566       // Clear the bits which were serialized from the flag's bitmask.
567       BitMask &= ~(Mask.first);
568     }
569   }
570   if (BitMask) {
571     // When the resulting flag's bitmask isn't zero, we know that we didn't
572     // serialize all of the bit flags.
573     if (IsCommaNeeded)
574       OS << ", ";
575     OS << "<unknown bitmask target flag>";
576   }
577   OS << ") ";
578 }
579 
580 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
581   OS << "<mcsymbol " << Sym << ">";
582 }
583 
584 void MachineOperand::printStackObjectReference(raw_ostream &OS,
585                                                unsigned FrameIndex,
586                                                bool IsFixed, StringRef Name) {
587   if (IsFixed) {
588     OS << "%fixed-stack." << FrameIndex;
589     return;
590   }
591 
592   OS << "%stack." << FrameIndex;
593   if (!Name.empty())
594     OS << '.' << Name;
595 }
596 
597 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
598   if (Offset == 0)
599     return;
600   if (Offset < 0) {
601     OS << " - " << -Offset;
602     return;
603   }
604   OS << " + " << Offset;
605 }
606 
607 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
608   if (Slot == -1)
609     OS << "<badref>";
610   else
611     OS << Slot;
612 }
613 
614 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
615                      const TargetRegisterInfo *TRI) {
616   switch (CFI.getOperation()) {
617   case MCCFIInstruction::OpSameValue:
618     OS << "same_value ";
619     if (MCSymbol *Label = CFI.getLabel())
620       MachineOperand::printSymbol(OS, *Label);
621     printCFIRegister(CFI.getRegister(), OS, TRI);
622     break;
623   case MCCFIInstruction::OpRememberState:
624     OS << "remember_state ";
625     if (MCSymbol *Label = CFI.getLabel())
626       MachineOperand::printSymbol(OS, *Label);
627     break;
628   case MCCFIInstruction::OpRestoreState:
629     OS << "restore_state ";
630     if (MCSymbol *Label = CFI.getLabel())
631       MachineOperand::printSymbol(OS, *Label);
632     break;
633   case MCCFIInstruction::OpOffset:
634     OS << "offset ";
635     if (MCSymbol *Label = CFI.getLabel())
636       MachineOperand::printSymbol(OS, *Label);
637     printCFIRegister(CFI.getRegister(), OS, TRI);
638     OS << ", " << CFI.getOffset();
639     break;
640   case MCCFIInstruction::OpDefCfaRegister:
641     OS << "def_cfa_register ";
642     if (MCSymbol *Label = CFI.getLabel())
643       MachineOperand::printSymbol(OS, *Label);
644     printCFIRegister(CFI.getRegister(), OS, TRI);
645     break;
646   case MCCFIInstruction::OpDefCfaOffset:
647     OS << "def_cfa_offset ";
648     if (MCSymbol *Label = CFI.getLabel())
649       MachineOperand::printSymbol(OS, *Label);
650     OS << CFI.getOffset();
651     break;
652   case MCCFIInstruction::OpDefCfa:
653     OS << "def_cfa ";
654     if (MCSymbol *Label = CFI.getLabel())
655       MachineOperand::printSymbol(OS, *Label);
656     printCFIRegister(CFI.getRegister(), OS, TRI);
657     OS << ", " << CFI.getOffset();
658     break;
659   case MCCFIInstruction::OpLLVMDefAspaceCfa:
660     OS << "llvm_def_aspace_cfa ";
661     if (MCSymbol *Label = CFI.getLabel())
662       MachineOperand::printSymbol(OS, *Label);
663     printCFIRegister(CFI.getRegister(), OS, TRI);
664     OS << ", " << CFI.getOffset();
665     OS << ", " << CFI.getAddressSpace();
666     break;
667   case MCCFIInstruction::OpRelOffset:
668     OS << "rel_offset ";
669     if (MCSymbol *Label = CFI.getLabel())
670       MachineOperand::printSymbol(OS, *Label);
671     printCFIRegister(CFI.getRegister(), OS, TRI);
672     OS << ", " << CFI.getOffset();
673     break;
674   case MCCFIInstruction::OpAdjustCfaOffset:
675     OS << "adjust_cfa_offset ";
676     if (MCSymbol *Label = CFI.getLabel())
677       MachineOperand::printSymbol(OS, *Label);
678     OS << CFI.getOffset();
679     break;
680   case MCCFIInstruction::OpRestore:
681     OS << "restore ";
682     if (MCSymbol *Label = CFI.getLabel())
683       MachineOperand::printSymbol(OS, *Label);
684     printCFIRegister(CFI.getRegister(), OS, TRI);
685     break;
686   case MCCFIInstruction::OpEscape: {
687     OS << "escape ";
688     if (MCSymbol *Label = CFI.getLabel())
689       MachineOperand::printSymbol(OS, *Label);
690     if (!CFI.getValues().empty()) {
691       size_t e = CFI.getValues().size() - 1;
692       for (size_t i = 0; i < e; ++i)
693         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
694       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
695     }
696     break;
697   }
698   case MCCFIInstruction::OpUndefined:
699     OS << "undefined ";
700     if (MCSymbol *Label = CFI.getLabel())
701       MachineOperand::printSymbol(OS, *Label);
702     printCFIRegister(CFI.getRegister(), OS, TRI);
703     break;
704   case MCCFIInstruction::OpRegister:
705     OS << "register ";
706     if (MCSymbol *Label = CFI.getLabel())
707       MachineOperand::printSymbol(OS, *Label);
708     printCFIRegister(CFI.getRegister(), OS, TRI);
709     OS << ", ";
710     printCFIRegister(CFI.getRegister2(), OS, TRI);
711     break;
712   case MCCFIInstruction::OpWindowSave:
713     OS << "window_save ";
714     if (MCSymbol *Label = CFI.getLabel())
715       MachineOperand::printSymbol(OS, *Label);
716     break;
717   case MCCFIInstruction::OpNegateRAState:
718     OS << "negate_ra_sign_state ";
719     if (MCSymbol *Label = CFI.getLabel())
720       MachineOperand::printSymbol(OS, *Label);
721     break;
722   default:
723     // TODO: Print the other CFI Operations.
724     OS << "<unserializable cfi directive>";
725     break;
726   }
727 }
728 
729 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
730                            const TargetIntrinsicInfo *IntrinsicInfo) const {
731   print(OS, LLT{}, TRI, IntrinsicInfo);
732 }
733 
734 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
735                            const TargetRegisterInfo *TRI,
736                            const TargetIntrinsicInfo *IntrinsicInfo) const {
737   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
738   ModuleSlotTracker DummyMST(nullptr);
739   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
740         /*IsStandalone=*/true,
741         /*ShouldPrintRegisterTies=*/true,
742         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
743 }
744 
745 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
746                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
747                            bool IsStandalone, bool ShouldPrintRegisterTies,
748                            unsigned TiedOperandIdx,
749                            const TargetRegisterInfo *TRI,
750                            const TargetIntrinsicInfo *IntrinsicInfo) const {
751   printTargetFlags(OS, *this);
752   switch (getType()) {
753   case MachineOperand::MO_Register: {
754     Register Reg = getReg();
755     if (isImplicit())
756       OS << (isDef() ? "implicit-def " : "implicit ");
757     else if (PrintDef && isDef())
758       // Print the 'def' flag only when the operand is defined after '='.
759       OS << "def ";
760     if (isInternalRead())
761       OS << "internal ";
762     if (isDead())
763       OS << "dead ";
764     if (isKill())
765       OS << "killed ";
766     if (isUndef())
767       OS << "undef ";
768     if (isEarlyClobber())
769       OS << "early-clobber ";
770     if (Register::isPhysicalRegister(getReg()) && isRenamable())
771       OS << "renamable ";
772     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
773     // simply infer it when parsing and do not need to print it.
774 
775     const MachineRegisterInfo *MRI = nullptr;
776     if (Register::isVirtualRegister(Reg)) {
777       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
778         MRI = &MF->getRegInfo();
779       }
780     }
781 
782     OS << printReg(Reg, TRI, 0, MRI);
783     // Print the sub register.
784     if (unsigned SubReg = getSubReg()) {
785       if (TRI)
786         OS << '.' << TRI->getSubRegIndexName(SubReg);
787       else
788         OS << ".subreg" << SubReg;
789     }
790     // Print the register class / bank.
791     if (Register::isVirtualRegister(Reg)) {
792       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
793         const MachineRegisterInfo &MRI = MF->getRegInfo();
794         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
795           OS << ':';
796           OS << printRegClassOrBank(Reg, MRI, TRI);
797         }
798       }
799     }
800     // Print ties.
801     if (ShouldPrintRegisterTies && isTied() && !isDef())
802       OS << "(tied-def " << TiedOperandIdx << ")";
803     // Print types.
804     if (TypeToPrint.isValid())
805       OS << '(' << TypeToPrint << ')';
806     break;
807   }
808   case MachineOperand::MO_Immediate: {
809     const MIRFormatter *Formatter = nullptr;
810     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
811       const auto *TII = MF->getSubtarget().getInstrInfo();
812       assert(TII && "expected instruction info");
813       Formatter = TII->getMIRFormatter();
814     }
815     if (Formatter)
816       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
817     else
818       OS << getImm();
819     break;
820   }
821   case MachineOperand::MO_CImmediate:
822     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
823     break;
824   case MachineOperand::MO_FPImmediate:
825     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
826     break;
827   case MachineOperand::MO_MachineBasicBlock:
828     OS << printMBBReference(*getMBB());
829     break;
830   case MachineOperand::MO_FrameIndex: {
831     int FrameIndex = getIndex();
832     bool IsFixed = false;
833     const MachineFrameInfo *MFI = nullptr;
834     if (const MachineFunction *MF = getMFIfAvailable(*this))
835       MFI = &MF->getFrameInfo();
836     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
837     break;
838   }
839   case MachineOperand::MO_ConstantPoolIndex:
840     OS << "%const." << getIndex();
841     printOperandOffset(OS, getOffset());
842     break;
843   case MachineOperand::MO_TargetIndex: {
844     OS << "target-index(";
845     const char *Name = "<unknown>";
846     if (const MachineFunction *MF = getMFIfAvailable(*this))
847       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
848         Name = TargetIndexName;
849     OS << Name << ')';
850     printOperandOffset(OS, getOffset());
851     break;
852   }
853   case MachineOperand::MO_JumpTableIndex:
854     OS << printJumpTableEntryReference(getIndex());
855     break;
856   case MachineOperand::MO_GlobalAddress:
857     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
858     printOperandOffset(OS, getOffset());
859     break;
860   case MachineOperand::MO_ExternalSymbol: {
861     StringRef Name = getSymbolName();
862     OS << '&';
863     if (Name.empty()) {
864       OS << "\"\"";
865     } else {
866       printLLVMNameWithoutPrefix(OS, Name);
867     }
868     printOperandOffset(OS, getOffset());
869     break;
870   }
871   case MachineOperand::MO_BlockAddress: {
872     OS << "blockaddress(";
873     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
874                                                      MST);
875     OS << ", ";
876     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
877     OS << ')';
878     MachineOperand::printOperandOffset(OS, getOffset());
879     break;
880   }
881   case MachineOperand::MO_RegisterMask: {
882     OS << "<regmask";
883     if (TRI) {
884       unsigned NumRegsInMask = 0;
885       unsigned NumRegsEmitted = 0;
886       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
887         unsigned MaskWord = i / 32;
888         unsigned MaskBit = i % 32;
889         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
890           if (PrintRegMaskNumRegs < 0 ||
891               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
892             OS << " " << printReg(i, TRI);
893             NumRegsEmitted++;
894           }
895           NumRegsInMask++;
896         }
897       }
898       if (NumRegsEmitted != NumRegsInMask)
899         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
900     } else {
901       OS << " ...";
902     }
903     OS << ">";
904     break;
905   }
906   case MachineOperand::MO_RegisterLiveOut: {
907     const uint32_t *RegMask = getRegLiveOut();
908     OS << "liveout(";
909     if (!TRI) {
910       OS << "<unknown>";
911     } else {
912       bool IsCommaNeeded = false;
913       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
914         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
915           if (IsCommaNeeded)
916             OS << ", ";
917           OS << printReg(Reg, TRI);
918           IsCommaNeeded = true;
919         }
920       }
921     }
922     OS << ")";
923     break;
924   }
925   case MachineOperand::MO_Metadata:
926     getMetadata()->printAsOperand(OS, MST);
927     break;
928   case MachineOperand::MO_MCSymbol:
929     printSymbol(OS, *getMCSymbol());
930     break;
931   case MachineOperand::MO_CFIIndex: {
932     if (const MachineFunction *MF = getMFIfAvailable(*this))
933       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
934     else
935       OS << "<cfi directive>";
936     break;
937   }
938   case MachineOperand::MO_IntrinsicID: {
939     Intrinsic::ID ID = getIntrinsicID();
940     if (ID < Intrinsic::num_intrinsics)
941       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
942     else if (IntrinsicInfo)
943       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
944     else
945       OS << "intrinsic(" << ID << ')';
946     break;
947   }
948   case MachineOperand::MO_Predicate: {
949     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
950     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
951        << CmpInst::getPredicateName(Pred) << ')';
952     break;
953   }
954   case MachineOperand::MO_ShuffleMask:
955     OS << "shufflemask(";
956     ArrayRef<int> Mask = getShuffleMask();
957     StringRef Separator;
958     for (int Elt : Mask) {
959       if (Elt == -1)
960         OS << Separator << "undef";
961       else
962         OS << Separator << Elt;
963       Separator = ", ";
964     }
965 
966     OS << ')';
967     break;
968   }
969 }
970 
971 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
972 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
973 #endif
974 
975 //===----------------------------------------------------------------------===//
976 // MachineMemOperand Implementation
977 //===----------------------------------------------------------------------===//
978 
979 /// getAddrSpace - Return the LLVM IR address space number that this pointer
980 /// points into.
981 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
982 
983 /// isDereferenceable - Return true if V is always dereferenceable for
984 /// Offset + Size byte.
985 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
986                                            const DataLayout &DL) const {
987   if (!V.is<const Value *>())
988     return false;
989 
990   const Value *BasePtr = V.get<const Value *>();
991   if (BasePtr == nullptr)
992     return false;
993 
994   return isDereferenceableAndAlignedPointer(
995       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
996 }
997 
998 /// getConstantPool - Return a MachinePointerInfo record that refers to the
999 /// constant pool.
1000 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1001   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1002 }
1003 
1004 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1005 /// the specified FrameIndex.
1006 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1007                                                      int FI, int64_t Offset) {
1008   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1009 }
1010 
1011 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1012   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1013 }
1014 
1015 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1016   return MachinePointerInfo(MF.getPSVManager().getGOT());
1017 }
1018 
1019 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1020                                                 int64_t Offset, uint8_t ID) {
1021   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1022 }
1023 
1024 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1025   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1026 }
1027 
1028 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1029                                      LLT type, Align a, const AAMDNodes &AAInfo,
1030                                      const MDNode *Ranges, SyncScope::ID SSID,
1031                                      AtomicOrdering Ordering,
1032                                      AtomicOrdering FailureOrdering)
1033     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1034       AAInfo(AAInfo), Ranges(Ranges) {
1035   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1036           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1037          "invalid pointer value");
1038   assert((isLoad() || isStore()) && "Not a load/store!");
1039 
1040   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1041   assert(getSyncScopeID() == SSID && "Value truncated");
1042   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1043   assert(getSuccessOrdering() == Ordering && "Value truncated");
1044   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1045   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1046 }
1047 
1048 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1049                                      uint64_t s, Align a,
1050                                      const AAMDNodes &AAInfo,
1051                                      const MDNode *Ranges, SyncScope::ID SSID,
1052                                      AtomicOrdering Ordering,
1053                                      AtomicOrdering FailureOrdering)
1054     : MachineMemOperand(ptrinfo, f,
1055                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1056                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1057 
1058 /// Profile - Gather unique data for the object.
1059 ///
1060 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1061   ID.AddInteger(getOffset());
1062   ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1063   ID.AddPointer(getOpaqueValue());
1064   ID.AddInteger(getFlags());
1065   ID.AddInteger(getBaseAlign().value());
1066 }
1067 
1068 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1069   // The Value and Offset may differ due to CSE. But the flags and size
1070   // should be the same.
1071   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1072   assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1073           MMO->getSize() == getSize()) &&
1074          "Size mismatch!");
1075 
1076   if (MMO->getBaseAlign() >= getBaseAlign()) {
1077     // Update the alignment value.
1078     BaseAlign = MMO->getBaseAlign();
1079     // Also update the base and offset, because the new alignment may
1080     // not be applicable with the old ones.
1081     PtrInfo = MMO->PtrInfo;
1082   }
1083 }
1084 
1085 /// getAlign - Return the minimum known alignment in bytes of the
1086 /// actual memory reference.
1087 Align MachineMemOperand::getAlign() const {
1088   return commonAlignment(getBaseAlign(), getOffset());
1089 }
1090 
1091 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1092                               SmallVectorImpl<StringRef> &SSNs,
1093                               const LLVMContext &Context,
1094                               const MachineFrameInfo *MFI,
1095                               const TargetInstrInfo *TII) const {
1096   OS << '(';
1097   if (isVolatile())
1098     OS << "volatile ";
1099   if (isNonTemporal())
1100     OS << "non-temporal ";
1101   if (isDereferenceable())
1102     OS << "dereferenceable ";
1103   if (isInvariant())
1104     OS << "invariant ";
1105   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1106     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1107        << "\" ";
1108   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1109     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1110        << "\" ";
1111   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1112     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1113        << "\" ";
1114 
1115   assert((isLoad() || isStore()) &&
1116          "machine memory operand must be a load or store (or both)");
1117   if (isLoad())
1118     OS << "load ";
1119   if (isStore())
1120     OS << "store ";
1121 
1122   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1123 
1124   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1125     OS << toIRString(getSuccessOrdering()) << ' ';
1126   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1127     OS << toIRString(getFailureOrdering()) << ' ';
1128 
1129   if (getMemoryType().isValid())
1130     OS << '(' << getMemoryType() << ')';
1131   else
1132     OS << "unknown-size";
1133 
1134   if (const Value *Val = getValue()) {
1135     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1136     MIRFormatter::printIRValue(OS, *Val, MST);
1137   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1138     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1139     assert(PVal && "Expected a pseudo source value");
1140     switch (PVal->kind()) {
1141     case PseudoSourceValue::Stack:
1142       OS << "stack";
1143       break;
1144     case PseudoSourceValue::GOT:
1145       OS << "got";
1146       break;
1147     case PseudoSourceValue::JumpTable:
1148       OS << "jump-table";
1149       break;
1150     case PseudoSourceValue::ConstantPool:
1151       OS << "constant-pool";
1152       break;
1153     case PseudoSourceValue::FixedStack: {
1154       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1155       bool IsFixed = true;
1156       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1157       break;
1158     }
1159     case PseudoSourceValue::GlobalValueCallEntry:
1160       OS << "call-entry ";
1161       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1162           OS, /*PrintType=*/false, MST);
1163       break;
1164     case PseudoSourceValue::ExternalSymbolCallEntry:
1165       OS << "call-entry &";
1166       printLLVMNameWithoutPrefix(
1167           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1168       break;
1169     default: {
1170       const MIRFormatter *Formatter = TII->getMIRFormatter();
1171       // FIXME: This is not necessarily the correct MIR serialization format for
1172       // a custom pseudo source value, but at least it allows
1173       // MIR printing to work on a target with custom pseudo source
1174       // values.
1175       OS << "custom \"";
1176       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1177       OS << '\"';
1178       break;
1179     }
1180     }
1181   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1182     OS << ((isLoad() && isStore()) ? " on "
1183            : isLoad()              ? " from "
1184                                    : " into ")
1185        << "unknown-address";
1186   }
1187   MachineOperand::printOperandOffset(OS, getOffset());
1188   if (getSize() > 0 && getAlign() != getSize())
1189     OS << ", align " << getAlign().value();
1190   if (getAlign() != getBaseAlign())
1191     OS << ", basealign " << getBaseAlign().value();
1192   auto AAInfo = getAAInfo();
1193   if (AAInfo.TBAA) {
1194     OS << ", !tbaa ";
1195     AAInfo.TBAA->printAsOperand(OS, MST);
1196   }
1197   if (AAInfo.Scope) {
1198     OS << ", !alias.scope ";
1199     AAInfo.Scope->printAsOperand(OS, MST);
1200   }
1201   if (AAInfo.NoAlias) {
1202     OS << ", !noalias ";
1203     AAInfo.NoAlias->printAsOperand(OS, MST);
1204   }
1205   if (getRanges()) {
1206     OS << ", !range ";
1207     getRanges()->printAsOperand(OS, MST);
1208   }
1209   // FIXME: Implement addrspace printing/parsing in MIR.
1210   // For now, print this even though parsing it is not available in MIR.
1211   if (unsigned AS = getAddrSpace())
1212     OS << ", addrspace " << AS;
1213 
1214   OS << ')';
1215 }
1216