xref: /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/CodeGen/MIRFormatter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/StableHashing.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/ModuleSlotTracker.h"
29 #include "llvm/MC/MCDwarf.h"
30 #include "llvm/Target/TargetIntrinsicInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include <optional>
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37     PrintRegMaskNumRegs("print-regmask-num-regs",
38                         cl::desc("Number of registers to limit to when "
39                                  "printing regmask operands in IR dumps. "
40                                  "unlimited = -1"),
41                         cl::init(32), cl::Hidden);
42 
43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
44   if (const MachineInstr *MI = MO.getParent())
45     if (const MachineBasicBlock *MBB = MI->getParent())
46       if (const MachineFunction *MF = MBB->getParent())
47         return MF;
48   return nullptr;
49 }
50 
51 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
52   return const_cast<MachineFunction *>(
53       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
54 }
55 
56 void MachineOperand::setReg(Register Reg) {
57   if (getReg() == Reg)
58     return; // No change.
59 
60   // Clear the IsRenamable bit to keep it conservatively correct.
61   IsRenamable = false;
62 
63   // Otherwise, we have to change the register.  If this operand is embedded
64   // into a machine function, we need to update the old and new register's
65   // use/def lists.
66   if (MachineFunction *MF = getMFIfAvailable(*this)) {
67     MachineRegisterInfo &MRI = MF->getRegInfo();
68     MRI.removeRegOperandFromUseList(this);
69     SmallContents.RegNo = Reg;
70     MRI.addRegOperandToUseList(this);
71     return;
72   }
73 
74   // Otherwise, just change the register, no problem.  :)
75   SmallContents.RegNo = Reg;
76 }
77 
78 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
79                                   const TargetRegisterInfo &TRI) {
80   assert(Reg.isVirtual());
81   if (SubIdx && getSubReg())
82     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
83   setReg(Reg);
84   if (SubIdx)
85     setSubReg(SubIdx);
86 }
87 
88 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
89   assert(Register::isPhysicalRegister(Reg));
90   if (getSubReg()) {
91     Reg = TRI.getSubReg(Reg, getSubReg());
92     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
93     // That won't happen in legal code.
94     setSubReg(0);
95     if (isDef())
96       setIsUndef(false);
97   }
98   setReg(Reg);
99 }
100 
101 /// Change a def to a use, or a use to a def.
102 void MachineOperand::setIsDef(bool Val) {
103   assert(isReg() && "Wrong MachineOperand accessor");
104   assert((!Val || !isDebug()) && "Marking a debug operation as def");
105   if (IsDef == Val)
106     return;
107   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
108   // MRI may keep uses and defs in different list positions.
109   if (MachineFunction *MF = getMFIfAvailable(*this)) {
110     MachineRegisterInfo &MRI = MF->getRegInfo();
111     MRI.removeRegOperandFromUseList(this);
112     IsDef = Val;
113     MRI.addRegOperandToUseList(this);
114     return;
115   }
116   IsDef = Val;
117 }
118 
119 bool MachineOperand::isRenamable() const {
120   assert(isReg() && "Wrong MachineOperand accessor");
121   assert(getReg().isPhysical() &&
122          "isRenamable should only be checked on physical registers");
123   if (!IsRenamable)
124     return false;
125 
126   const MachineInstr *MI = getParent();
127   if (!MI)
128     return true;
129 
130   if (isDef())
131     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
132 
133   assert(isUse() && "Reg is not def or use");
134   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
135 }
136 
137 void MachineOperand::setIsRenamable(bool Val) {
138   assert(isReg() && "Wrong MachineOperand accessor");
139   assert(getReg().isPhysical() &&
140          "setIsRenamable should only be called on physical registers");
141   IsRenamable = Val;
142 }
143 
144 // If this operand is currently a register operand, and if this is in a
145 // function, deregister the operand from the register's use/def list.
146 void MachineOperand::removeRegFromUses() {
147   if (!isReg() || !isOnRegUseList())
148     return;
149 
150   if (MachineFunction *MF = getMFIfAvailable(*this))
151     MF->getRegInfo().removeRegOperandFromUseList(this);
152 }
153 
154 /// ChangeToImmediate - Replace this operand with a new immediate operand of
155 /// the specified value.  If an operand is known to be an immediate already,
156 /// the setImm method should be used.
157 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
158   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
159 
160   removeRegFromUses();
161 
162   OpKind = MO_Immediate;
163   Contents.ImmVal = ImmVal;
164   setTargetFlags(TargetFlags);
165 }
166 
167 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
168                                          unsigned TargetFlags) {
169   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
170 
171   removeRegFromUses();
172 
173   OpKind = MO_FPImmediate;
174   Contents.CFP = FPImm;
175   setTargetFlags(TargetFlags);
176 }
177 
178 void MachineOperand::ChangeToES(const char *SymName,
179                                 unsigned TargetFlags) {
180   assert((!isReg() || !isTied()) &&
181          "Cannot change a tied operand into an external symbol");
182 
183   removeRegFromUses();
184 
185   OpKind = MO_ExternalSymbol;
186   Contents.OffsetedInfo.Val.SymbolName = SymName;
187   setOffset(0); // Offset is always 0.
188   setTargetFlags(TargetFlags);
189 }
190 
191 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
192                                 unsigned TargetFlags) {
193   assert((!isReg() || !isTied()) &&
194          "Cannot change a tied operand into a global address");
195 
196   removeRegFromUses();
197 
198   OpKind = MO_GlobalAddress;
199   Contents.OffsetedInfo.Val.GV = GV;
200   setOffset(Offset);
201   setTargetFlags(TargetFlags);
202 }
203 
204 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
205   assert((!isReg() || !isTied()) &&
206          "Cannot change a tied operand into an MCSymbol");
207 
208   removeRegFromUses();
209 
210   OpKind = MO_MCSymbol;
211   Contents.Sym = Sym;
212   setTargetFlags(TargetFlags);
213 }
214 
215 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
216   assert((!isReg() || !isTied()) &&
217          "Cannot change a tied operand into a FrameIndex");
218 
219   removeRegFromUses();
220 
221   OpKind = MO_FrameIndex;
222   setIndex(Idx);
223   setTargetFlags(TargetFlags);
224 }
225 
226 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
227                                          unsigned TargetFlags) {
228   assert((!isReg() || !isTied()) &&
229          "Cannot change a tied operand into a FrameIndex");
230 
231   removeRegFromUses();
232 
233   OpKind = MO_TargetIndex;
234   setIndex(Idx);
235   setOffset(Offset);
236   setTargetFlags(TargetFlags);
237 }
238 
239 void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
240                                          unsigned TargetFlags) {
241   assert((!isReg() || !isTied()) &&
242          "Cannot change a tied operand into a DbgInstrRef");
243 
244   removeRegFromUses();
245 
246   OpKind = MO_DbgInstrRef;
247   setInstrRefInstrIndex(InstrIdx);
248   setInstrRefOpIndex(OpIdx);
249   setTargetFlags(TargetFlags);
250 }
251 
252 /// ChangeToRegister - Replace this operand with a new register operand of
253 /// the specified value.  If an operand is known to be an register already,
254 /// the setReg method should be used.
255 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
256                                       bool isKill, bool isDead, bool isUndef,
257                                       bool isDebug) {
258   MachineRegisterInfo *RegInfo = nullptr;
259   if (MachineFunction *MF = getMFIfAvailable(*this))
260     RegInfo = &MF->getRegInfo();
261   // If this operand is already a register operand, remove it from the
262   // register's use/def lists.
263   bool WasReg = isReg();
264   if (RegInfo && WasReg)
265     RegInfo->removeRegOperandFromUseList(this);
266 
267   // Ensure debug instructions set debug flag on register uses.
268   const MachineInstr *MI = getParent();
269   if (!isDef && MI && MI->isDebugInstr())
270     isDebug = true;
271 
272   // Change this to a register and set the reg#.
273   assert(!(isDead && !isDef) && "Dead flag on non-def");
274   assert(!(isKill && isDef) && "Kill flag on def");
275   OpKind = MO_Register;
276   SmallContents.RegNo = Reg;
277   SubReg_TargetFlags = 0;
278   IsDef = isDef;
279   IsImp = isImp;
280   IsDeadOrKill = isKill | isDead;
281   IsRenamable = false;
282   IsUndef = isUndef;
283   IsInternalRead = false;
284   IsEarlyClobber = false;
285   IsDebug = isDebug;
286   // Ensure isOnRegUseList() returns false.
287   Contents.Reg.Prev = nullptr;
288   // Preserve the tie when the operand was already a register.
289   if (!WasReg)
290     TiedTo = 0;
291 
292   // If this operand is embedded in a function, add the operand to the
293   // register's use/def list.
294   if (RegInfo)
295     RegInfo->addRegOperandToUseList(this);
296 }
297 
298 /// isIdenticalTo - Return true if this operand is identical to the specified
299 /// operand. Note that this should stay in sync with the hash_value overload
300 /// below.
301 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
302   if (getType() != Other.getType() ||
303       getTargetFlags() != Other.getTargetFlags())
304     return false;
305 
306   switch (getType()) {
307   case MachineOperand::MO_Register:
308     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
309            getSubReg() == Other.getSubReg();
310   case MachineOperand::MO_Immediate:
311     return getImm() == Other.getImm();
312   case MachineOperand::MO_CImmediate:
313     return getCImm() == Other.getCImm();
314   case MachineOperand::MO_FPImmediate:
315     return getFPImm() == Other.getFPImm();
316   case MachineOperand::MO_MachineBasicBlock:
317     return getMBB() == Other.getMBB();
318   case MachineOperand::MO_FrameIndex:
319     return getIndex() == Other.getIndex();
320   case MachineOperand::MO_ConstantPoolIndex:
321   case MachineOperand::MO_TargetIndex:
322     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
323   case MachineOperand::MO_JumpTableIndex:
324     return getIndex() == Other.getIndex();
325   case MachineOperand::MO_GlobalAddress:
326     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
327   case MachineOperand::MO_ExternalSymbol:
328     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
329            getOffset() == Other.getOffset();
330   case MachineOperand::MO_BlockAddress:
331     return getBlockAddress() == Other.getBlockAddress() &&
332            getOffset() == Other.getOffset();
333   case MachineOperand::MO_RegisterMask:
334   case MachineOperand::MO_RegisterLiveOut: {
335     // Shallow compare of the two RegMasks
336     const uint32_t *RegMask = getRegMask();
337     const uint32_t *OtherRegMask = Other.getRegMask();
338     if (RegMask == OtherRegMask)
339       return true;
340 
341     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
342       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
343       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
344       // Deep compare of the two RegMasks
345       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
346     }
347     // We don't know the size of the RegMask, so we can't deep compare the two
348     // reg masks.
349     return false;
350   }
351   case MachineOperand::MO_MCSymbol:
352     return getMCSymbol() == Other.getMCSymbol();
353   case MachineOperand::MO_DbgInstrRef:
354     return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
355            getInstrRefOpIndex() == Other.getInstrRefOpIndex();
356   case MachineOperand::MO_CFIIndex:
357     return getCFIIndex() == Other.getCFIIndex();
358   case MachineOperand::MO_Metadata:
359     return getMetadata() == Other.getMetadata();
360   case MachineOperand::MO_IntrinsicID:
361     return getIntrinsicID() == Other.getIntrinsicID();
362   case MachineOperand::MO_Predicate:
363     return getPredicate() == Other.getPredicate();
364   case MachineOperand::MO_ShuffleMask:
365     return getShuffleMask() == Other.getShuffleMask();
366   }
367   llvm_unreachable("Invalid machine operand type");
368 }
369 
370 // Note: this must stay exactly in sync with isIdenticalTo above.
371 hash_code llvm::hash_value(const MachineOperand &MO) {
372   switch (MO.getType()) {
373   case MachineOperand::MO_Register:
374     // Register operands don't have target flags.
375     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
376   case MachineOperand::MO_Immediate:
377     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
378   case MachineOperand::MO_CImmediate:
379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
380   case MachineOperand::MO_FPImmediate:
381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
382   case MachineOperand::MO_MachineBasicBlock:
383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
384   case MachineOperand::MO_FrameIndex:
385     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
386   case MachineOperand::MO_ConstantPoolIndex:
387   case MachineOperand::MO_TargetIndex:
388     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
389                         MO.getOffset());
390   case MachineOperand::MO_JumpTableIndex:
391     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
392   case MachineOperand::MO_ExternalSymbol:
393     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
394                         StringRef(MO.getSymbolName()));
395   case MachineOperand::MO_GlobalAddress:
396     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
397                         MO.getOffset());
398   case MachineOperand::MO_BlockAddress:
399     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
400                         MO.getOffset());
401   case MachineOperand::MO_RegisterMask:
402   case MachineOperand::MO_RegisterLiveOut: {
403     if (const MachineFunction *MF = getMFIfAvailable(MO)) {
404       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
405       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
406       const uint32_t *RegMask = MO.getRegMask();
407       std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
408       return hash_combine(MO.getType(), MO.getTargetFlags(),
409                           stable_hash_combine_array(RegMaskHashes.data(),
410                                                     RegMaskHashes.size()));
411     }
412 
413     assert(0 && "MachineOperand not associated with any MachineFunction");
414     return hash_combine(MO.getType(), MO.getTargetFlags());
415   }
416   case MachineOperand::MO_Metadata:
417     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
418   case MachineOperand::MO_MCSymbol:
419     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
420   case MachineOperand::MO_DbgInstrRef:
421     return hash_combine(MO.getType(), MO.getTargetFlags(),
422                         MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());
423   case MachineOperand::MO_CFIIndex:
424     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
425   case MachineOperand::MO_IntrinsicID:
426     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
427   case MachineOperand::MO_Predicate:
428     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
429   case MachineOperand::MO_ShuffleMask:
430     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
431   }
432   llvm_unreachable("Invalid machine operand type");
433 }
434 
435 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
436 // it.
437 static void tryToGetTargetInfo(const MachineOperand &MO,
438                                const TargetRegisterInfo *&TRI,
439                                const TargetIntrinsicInfo *&IntrinsicInfo) {
440   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
441     TRI = MF->getSubtarget().getRegisterInfo();
442     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
443   }
444 }
445 
446 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
447   const auto *TII = MF.getSubtarget().getInstrInfo();
448   assert(TII && "expected instruction info");
449   auto Indices = TII->getSerializableTargetIndices();
450   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
451     return I.first == Index;
452   });
453   if (Found != Indices.end())
454     return Found->second;
455   return nullptr;
456 }
457 
458 const char *MachineOperand::getTargetIndexName() const {
459   const MachineFunction *MF = getMFIfAvailable(*this);
460   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
461 }
462 
463 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
464   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
465   for (const auto &I : Flags) {
466     if (I.first == TF) {
467       return I.second;
468     }
469   }
470   return nullptr;
471 }
472 
473 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
474                              const TargetRegisterInfo *TRI) {
475   if (!TRI) {
476     OS << "%dwarfreg." << DwarfReg;
477     return;
478   }
479 
480   if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
481     OS << printReg(*Reg, TRI);
482   else
483     OS << "<badreg>";
484 }
485 
486 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
487                                   ModuleSlotTracker &MST) {
488   OS << "%ir-block.";
489   if (BB.hasName()) {
490     printLLVMNameWithoutPrefix(OS, BB.getName());
491     return;
492   }
493   std::optional<int> Slot;
494   if (const Function *F = BB.getParent()) {
495     if (F == MST.getCurrentFunction()) {
496       Slot = MST.getLocalSlot(&BB);
497     } else if (const Module *M = F->getParent()) {
498       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
499       CustomMST.incorporateFunction(*F);
500       Slot = CustomMST.getLocalSlot(&BB);
501     }
502   }
503   if (Slot)
504     MachineOperand::printIRSlotNumber(OS, *Slot);
505   else
506     OS << "<unknown>";
507 }
508 
509 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
510                            SyncScope::ID SSID,
511                            SmallVectorImpl<StringRef> &SSNs) {
512   switch (SSID) {
513   case SyncScope::System:
514     break;
515   default:
516     if (SSNs.empty())
517       Context.getSyncScopeNames(SSNs);
518 
519     OS << "syncscope(\"";
520     printEscapedString(SSNs[SSID], OS);
521     OS << "\") ";
522     break;
523   }
524 }
525 
526 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
527                                         unsigned TMMOFlag) {
528   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
529   for (const auto &I : Flags) {
530     if (I.first == TMMOFlag) {
531       return I.second;
532     }
533   }
534   return nullptr;
535 }
536 
537 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
538                             const MachineFrameInfo *MFI) {
539   StringRef Name;
540   if (MFI) {
541     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
542     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
543       if (Alloca->hasName())
544         Name = Alloca->getName();
545     if (IsFixed)
546       FrameIndex -= MFI->getObjectIndexBegin();
547   }
548   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
549 }
550 
551 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
552                                     const TargetRegisterInfo *TRI) {
553   OS << "%subreg.";
554   if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
555     OS << TRI->getSubRegIndexName(Index);
556   else
557     OS << Index;
558 }
559 
560 void MachineOperand::printTargetFlags(raw_ostream &OS,
561                                       const MachineOperand &Op) {
562   if (!Op.getTargetFlags())
563     return;
564   const MachineFunction *MF = getMFIfAvailable(Op);
565   if (!MF)
566     return;
567 
568   const auto *TII = MF->getSubtarget().getInstrInfo();
569   assert(TII && "expected instruction info");
570   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
571   OS << "target-flags(";
572   const bool HasDirectFlags = Flags.first;
573   const bool HasBitmaskFlags = Flags.second;
574   if (!HasDirectFlags && !HasBitmaskFlags) {
575     OS << "<unknown>) ";
576     return;
577   }
578   if (HasDirectFlags) {
579     if (const auto *Name = getTargetFlagName(TII, Flags.first))
580       OS << Name;
581     else
582       OS << "<unknown target flag>";
583   }
584   if (!HasBitmaskFlags) {
585     OS << ") ";
586     return;
587   }
588   bool IsCommaNeeded = HasDirectFlags;
589   unsigned BitMask = Flags.second;
590   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
591   for (const auto &Mask : BitMasks) {
592     // Check if the flag's bitmask has the bits of the current mask set.
593     if ((BitMask & Mask.first) == Mask.first) {
594       if (IsCommaNeeded)
595         OS << ", ";
596       IsCommaNeeded = true;
597       OS << Mask.second;
598       // Clear the bits which were serialized from the flag's bitmask.
599       BitMask &= ~(Mask.first);
600     }
601   }
602   if (BitMask) {
603     // When the resulting flag's bitmask isn't zero, we know that we didn't
604     // serialize all of the bit flags.
605     if (IsCommaNeeded)
606       OS << ", ";
607     OS << "<unknown bitmask target flag>";
608   }
609   OS << ") ";
610 }
611 
612 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
613   OS << "<mcsymbol " << Sym << ">";
614 }
615 
616 void MachineOperand::printStackObjectReference(raw_ostream &OS,
617                                                unsigned FrameIndex,
618                                                bool IsFixed, StringRef Name) {
619   if (IsFixed) {
620     OS << "%fixed-stack." << FrameIndex;
621     return;
622   }
623 
624   OS << "%stack." << FrameIndex;
625   if (!Name.empty())
626     OS << '.' << Name;
627 }
628 
629 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
630   if (Offset == 0)
631     return;
632   if (Offset < 0) {
633     OS << " - " << -Offset;
634     return;
635   }
636   OS << " + " << Offset;
637 }
638 
639 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
640   if (Slot == -1)
641     OS << "<badref>";
642   else
643     OS << Slot;
644 }
645 
646 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
647                      const TargetRegisterInfo *TRI) {
648   switch (CFI.getOperation()) {
649   case MCCFIInstruction::OpSameValue:
650     OS << "same_value ";
651     if (MCSymbol *Label = CFI.getLabel())
652       MachineOperand::printSymbol(OS, *Label);
653     printCFIRegister(CFI.getRegister(), OS, TRI);
654     break;
655   case MCCFIInstruction::OpRememberState:
656     OS << "remember_state ";
657     if (MCSymbol *Label = CFI.getLabel())
658       MachineOperand::printSymbol(OS, *Label);
659     break;
660   case MCCFIInstruction::OpRestoreState:
661     OS << "restore_state ";
662     if (MCSymbol *Label = CFI.getLabel())
663       MachineOperand::printSymbol(OS, *Label);
664     break;
665   case MCCFIInstruction::OpOffset:
666     OS << "offset ";
667     if (MCSymbol *Label = CFI.getLabel())
668       MachineOperand::printSymbol(OS, *Label);
669     printCFIRegister(CFI.getRegister(), OS, TRI);
670     OS << ", " << CFI.getOffset();
671     break;
672   case MCCFIInstruction::OpDefCfaRegister:
673     OS << "def_cfa_register ";
674     if (MCSymbol *Label = CFI.getLabel())
675       MachineOperand::printSymbol(OS, *Label);
676     printCFIRegister(CFI.getRegister(), OS, TRI);
677     break;
678   case MCCFIInstruction::OpDefCfaOffset:
679     OS << "def_cfa_offset ";
680     if (MCSymbol *Label = CFI.getLabel())
681       MachineOperand::printSymbol(OS, *Label);
682     OS << CFI.getOffset();
683     break;
684   case MCCFIInstruction::OpDefCfa:
685     OS << "def_cfa ";
686     if (MCSymbol *Label = CFI.getLabel())
687       MachineOperand::printSymbol(OS, *Label);
688     printCFIRegister(CFI.getRegister(), OS, TRI);
689     OS << ", " << CFI.getOffset();
690     break;
691   case MCCFIInstruction::OpLLVMDefAspaceCfa:
692     OS << "llvm_def_aspace_cfa ";
693     if (MCSymbol *Label = CFI.getLabel())
694       MachineOperand::printSymbol(OS, *Label);
695     printCFIRegister(CFI.getRegister(), OS, TRI);
696     OS << ", " << CFI.getOffset();
697     OS << ", " << CFI.getAddressSpace();
698     break;
699   case MCCFIInstruction::OpRelOffset:
700     OS << "rel_offset ";
701     if (MCSymbol *Label = CFI.getLabel())
702       MachineOperand::printSymbol(OS, *Label);
703     printCFIRegister(CFI.getRegister(), OS, TRI);
704     OS << ", " << CFI.getOffset();
705     break;
706   case MCCFIInstruction::OpAdjustCfaOffset:
707     OS << "adjust_cfa_offset ";
708     if (MCSymbol *Label = CFI.getLabel())
709       MachineOperand::printSymbol(OS, *Label);
710     OS << CFI.getOffset();
711     break;
712   case MCCFIInstruction::OpRestore:
713     OS << "restore ";
714     if (MCSymbol *Label = CFI.getLabel())
715       MachineOperand::printSymbol(OS, *Label);
716     printCFIRegister(CFI.getRegister(), OS, TRI);
717     break;
718   case MCCFIInstruction::OpEscape: {
719     OS << "escape ";
720     if (MCSymbol *Label = CFI.getLabel())
721       MachineOperand::printSymbol(OS, *Label);
722     if (!CFI.getValues().empty()) {
723       size_t e = CFI.getValues().size() - 1;
724       for (size_t i = 0; i < e; ++i)
725         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
726       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
727     }
728     break;
729   }
730   case MCCFIInstruction::OpUndefined:
731     OS << "undefined ";
732     if (MCSymbol *Label = CFI.getLabel())
733       MachineOperand::printSymbol(OS, *Label);
734     printCFIRegister(CFI.getRegister(), OS, TRI);
735     break;
736   case MCCFIInstruction::OpRegister:
737     OS << "register ";
738     if (MCSymbol *Label = CFI.getLabel())
739       MachineOperand::printSymbol(OS, *Label);
740     printCFIRegister(CFI.getRegister(), OS, TRI);
741     OS << ", ";
742     printCFIRegister(CFI.getRegister2(), OS, TRI);
743     break;
744   case MCCFIInstruction::OpWindowSave:
745     OS << "window_save ";
746     if (MCSymbol *Label = CFI.getLabel())
747       MachineOperand::printSymbol(OS, *Label);
748     break;
749   case MCCFIInstruction::OpNegateRAState:
750     OS << "negate_ra_sign_state ";
751     if (MCSymbol *Label = CFI.getLabel())
752       MachineOperand::printSymbol(OS, *Label);
753     break;
754   default:
755     // TODO: Print the other CFI Operations.
756     OS << "<unserializable cfi directive>";
757     break;
758   }
759 }
760 
761 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
762                            const TargetIntrinsicInfo *IntrinsicInfo) const {
763   print(OS, LLT{}, TRI, IntrinsicInfo);
764 }
765 
766 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
767                            const TargetRegisterInfo *TRI,
768                            const TargetIntrinsicInfo *IntrinsicInfo) const {
769   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
770   ModuleSlotTracker DummyMST(nullptr);
771   print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
772         /*IsStandalone=*/true,
773         /*ShouldPrintRegisterTies=*/true,
774         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
775 }
776 
777 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
778                            LLT TypeToPrint, std::optional<unsigned> OpIdx,
779                            bool PrintDef, bool IsStandalone,
780                            bool ShouldPrintRegisterTies,
781                            unsigned TiedOperandIdx,
782                            const TargetRegisterInfo *TRI,
783                            const TargetIntrinsicInfo *IntrinsicInfo) const {
784   printTargetFlags(OS, *this);
785   switch (getType()) {
786   case MachineOperand::MO_Register: {
787     Register Reg = getReg();
788     if (isImplicit())
789       OS << (isDef() ? "implicit-def " : "implicit ");
790     else if (PrintDef && isDef())
791       // Print the 'def' flag only when the operand is defined after '='.
792       OS << "def ";
793     if (isInternalRead())
794       OS << "internal ";
795     if (isDead())
796       OS << "dead ";
797     if (isKill())
798       OS << "killed ";
799     if (isUndef())
800       OS << "undef ";
801     if (isEarlyClobber())
802       OS << "early-clobber ";
803     if (getReg().isPhysical() && isRenamable())
804       OS << "renamable ";
805     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
806     // simply infer it when parsing and do not need to print it.
807 
808     const MachineRegisterInfo *MRI = nullptr;
809     if (Reg.isVirtual()) {
810       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
811         MRI = &MF->getRegInfo();
812       }
813     }
814 
815     OS << printReg(Reg, TRI, 0, MRI);
816     // Print the sub register.
817     if (unsigned SubReg = getSubReg()) {
818       if (TRI)
819         OS << '.' << TRI->getSubRegIndexName(SubReg);
820       else
821         OS << ".subreg" << SubReg;
822     }
823     // Print the register class / bank.
824     if (Reg.isVirtual()) {
825       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
826         const MachineRegisterInfo &MRI = MF->getRegInfo();
827         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
828           OS << ':';
829           OS << printRegClassOrBank(Reg, MRI, TRI);
830         }
831       }
832     }
833     // Print ties.
834     if (ShouldPrintRegisterTies && isTied() && !isDef())
835       OS << "(tied-def " << TiedOperandIdx << ")";
836     // Print types.
837     if (TypeToPrint.isValid())
838       OS << '(' << TypeToPrint << ')';
839     break;
840   }
841   case MachineOperand::MO_Immediate: {
842     const MIRFormatter *Formatter = nullptr;
843     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
844       const auto *TII = MF->getSubtarget().getInstrInfo();
845       assert(TII && "expected instruction info");
846       Formatter = TII->getMIRFormatter();
847     }
848     if (Formatter)
849       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
850     else
851       OS << getImm();
852     break;
853   }
854   case MachineOperand::MO_CImmediate:
855     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
856     break;
857   case MachineOperand::MO_FPImmediate:
858     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
859     break;
860   case MachineOperand::MO_MachineBasicBlock:
861     OS << printMBBReference(*getMBB());
862     break;
863   case MachineOperand::MO_FrameIndex: {
864     int FrameIndex = getIndex();
865     bool IsFixed = false;
866     const MachineFrameInfo *MFI = nullptr;
867     if (const MachineFunction *MF = getMFIfAvailable(*this))
868       MFI = &MF->getFrameInfo();
869     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
870     break;
871   }
872   case MachineOperand::MO_ConstantPoolIndex:
873     OS << "%const." << getIndex();
874     printOperandOffset(OS, getOffset());
875     break;
876   case MachineOperand::MO_TargetIndex: {
877     OS << "target-index(";
878     const char *Name = "<unknown>";
879     if (const MachineFunction *MF = getMFIfAvailable(*this))
880       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
881         Name = TargetIndexName;
882     OS << Name << ')';
883     printOperandOffset(OS, getOffset());
884     break;
885   }
886   case MachineOperand::MO_JumpTableIndex:
887     OS << printJumpTableEntryReference(getIndex());
888     break;
889   case MachineOperand::MO_GlobalAddress:
890     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
891     printOperandOffset(OS, getOffset());
892     break;
893   case MachineOperand::MO_ExternalSymbol: {
894     StringRef Name = getSymbolName();
895     OS << '&';
896     if (Name.empty()) {
897       OS << "\"\"";
898     } else {
899       printLLVMNameWithoutPrefix(OS, Name);
900     }
901     printOperandOffset(OS, getOffset());
902     break;
903   }
904   case MachineOperand::MO_BlockAddress: {
905     OS << "blockaddress(";
906     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
907                                                      MST);
908     OS << ", ";
909     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
910     OS << ')';
911     MachineOperand::printOperandOffset(OS, getOffset());
912     break;
913   }
914   case MachineOperand::MO_RegisterMask: {
915     OS << "<regmask";
916     if (TRI) {
917       unsigned NumRegsInMask = 0;
918       unsigned NumRegsEmitted = 0;
919       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
920         unsigned MaskWord = i / 32;
921         unsigned MaskBit = i % 32;
922         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
923           if (PrintRegMaskNumRegs < 0 ||
924               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
925             OS << " " << printReg(i, TRI);
926             NumRegsEmitted++;
927           }
928           NumRegsInMask++;
929         }
930       }
931       if (NumRegsEmitted != NumRegsInMask)
932         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
933     } else {
934       OS << " ...";
935     }
936     OS << ">";
937     break;
938   }
939   case MachineOperand::MO_RegisterLiveOut: {
940     const uint32_t *RegMask = getRegLiveOut();
941     OS << "liveout(";
942     if (!TRI) {
943       OS << "<unknown>";
944     } else {
945       bool IsCommaNeeded = false;
946       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
947         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
948           if (IsCommaNeeded)
949             OS << ", ";
950           OS << printReg(Reg, TRI);
951           IsCommaNeeded = true;
952         }
953       }
954     }
955     OS << ")";
956     break;
957   }
958   case MachineOperand::MO_Metadata:
959     getMetadata()->printAsOperand(OS, MST);
960     break;
961   case MachineOperand::MO_MCSymbol:
962     printSymbol(OS, *getMCSymbol());
963     break;
964   case MachineOperand::MO_DbgInstrRef: {
965     OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
966        << getInstrRefOpIndex() << ')';
967     break;
968   }
969   case MachineOperand::MO_CFIIndex: {
970     if (const MachineFunction *MF = getMFIfAvailable(*this))
971       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
972     else
973       OS << "<cfi directive>";
974     break;
975   }
976   case MachineOperand::MO_IntrinsicID: {
977     Intrinsic::ID ID = getIntrinsicID();
978     if (ID < Intrinsic::num_intrinsics)
979       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
980     else if (IntrinsicInfo)
981       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
982     else
983       OS << "intrinsic(" << ID << ')';
984     break;
985   }
986   case MachineOperand::MO_Predicate: {
987     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
988     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
989        << CmpInst::getPredicateName(Pred) << ')';
990     break;
991   }
992   case MachineOperand::MO_ShuffleMask:
993     OS << "shufflemask(";
994     ArrayRef<int> Mask = getShuffleMask();
995     StringRef Separator;
996     for (int Elt : Mask) {
997       if (Elt == -1)
998         OS << Separator << "undef";
999       else
1000         OS << Separator << Elt;
1001       Separator = ", ";
1002     }
1003 
1004     OS << ')';
1005     break;
1006   }
1007 }
1008 
1009 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1010 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1011 #endif
1012 
1013 //===----------------------------------------------------------------------===//
1014 // MachineMemOperand Implementation
1015 //===----------------------------------------------------------------------===//
1016 
1017 /// getAddrSpace - Return the LLVM IR address space number that this pointer
1018 /// points into.
1019 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
1020 
1021 /// isDereferenceable - Return true if V is always dereferenceable for
1022 /// Offset + Size byte.
1023 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
1024                                            const DataLayout &DL) const {
1025   if (!V.is<const Value *>())
1026     return false;
1027 
1028   const Value *BasePtr = V.get<const Value *>();
1029   if (BasePtr == nullptr)
1030     return false;
1031 
1032   return isDereferenceableAndAlignedPointer(
1033       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1034 }
1035 
1036 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1037 /// constant pool.
1038 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1039   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1040 }
1041 
1042 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1043 /// the specified FrameIndex.
1044 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1045                                                      int FI, int64_t Offset) {
1046   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1047 }
1048 
1049 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1050   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1051 }
1052 
1053 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1054   return MachinePointerInfo(MF.getPSVManager().getGOT());
1055 }
1056 
1057 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1058                                                 int64_t Offset, uint8_t ID) {
1059   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1060 }
1061 
1062 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1063   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1064 }
1065 
1066 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1067                                      LLT type, Align a, const AAMDNodes &AAInfo,
1068                                      const MDNode *Ranges, SyncScope::ID SSID,
1069                                      AtomicOrdering Ordering,
1070                                      AtomicOrdering FailureOrdering)
1071     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1072       AAInfo(AAInfo), Ranges(Ranges) {
1073   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1074           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1075          "invalid pointer value");
1076   assert((isLoad() || isStore()) && "Not a load/store!");
1077 
1078   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1079   assert(getSyncScopeID() == SSID && "Value truncated");
1080   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1081   assert(getSuccessOrdering() == Ordering && "Value truncated");
1082   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1083   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1084 }
1085 
1086 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1087                                      uint64_t s, Align a,
1088                                      const AAMDNodes &AAInfo,
1089                                      const MDNode *Ranges, SyncScope::ID SSID,
1090                                      AtomicOrdering Ordering,
1091                                      AtomicOrdering FailureOrdering)
1092     : MachineMemOperand(ptrinfo, f,
1093                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1094                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1095 
1096 /// Profile - Gather unique data for the object.
1097 ///
1098 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1099   ID.AddInteger(getOffset());
1100   ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1101   ID.AddPointer(getOpaqueValue());
1102   ID.AddInteger(getFlags());
1103   ID.AddInteger(getBaseAlign().value());
1104 }
1105 
1106 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1107   // The Value and Offset may differ due to CSE. But the flags and size
1108   // should be the same.
1109   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1110   assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1111           MMO->getSize() == getSize()) &&
1112          "Size mismatch!");
1113 
1114   if (MMO->getBaseAlign() >= getBaseAlign()) {
1115     // Update the alignment value.
1116     BaseAlign = MMO->getBaseAlign();
1117     // Also update the base and offset, because the new alignment may
1118     // not be applicable with the old ones.
1119     PtrInfo = MMO->PtrInfo;
1120   }
1121 }
1122 
1123 /// getAlign - Return the minimum known alignment in bytes of the
1124 /// actual memory reference.
1125 Align MachineMemOperand::getAlign() const {
1126   return commonAlignment(getBaseAlign(), getOffset());
1127 }
1128 
1129 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1130                               SmallVectorImpl<StringRef> &SSNs,
1131                               const LLVMContext &Context,
1132                               const MachineFrameInfo *MFI,
1133                               const TargetInstrInfo *TII) const {
1134   OS << '(';
1135   if (isVolatile())
1136     OS << "volatile ";
1137   if (isNonTemporal())
1138     OS << "non-temporal ";
1139   if (isDereferenceable())
1140     OS << "dereferenceable ";
1141   if (isInvariant())
1142     OS << "invariant ";
1143   if (TII) {
1144     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1145       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1146          << "\" ";
1147     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1148       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1149          << "\" ";
1150     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1151       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1152          << "\" ";
1153   } else {
1154     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1155       OS << "\"MOTargetFlag1\" ";
1156     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1157       OS << "\"MOTargetFlag2\" ";
1158     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1159       OS << "\"MOTargetFlag3\" ";
1160   }
1161 
1162   assert((isLoad() || isStore()) &&
1163          "machine memory operand must be a load or store (or both)");
1164   if (isLoad())
1165     OS << "load ";
1166   if (isStore())
1167     OS << "store ";
1168 
1169   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1170 
1171   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1172     OS << toIRString(getSuccessOrdering()) << ' ';
1173   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1174     OS << toIRString(getFailureOrdering()) << ' ';
1175 
1176   if (getMemoryType().isValid())
1177     OS << '(' << getMemoryType() << ')';
1178   else
1179     OS << "unknown-size";
1180 
1181   if (const Value *Val = getValue()) {
1182     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1183     MIRFormatter::printIRValue(OS, *Val, MST);
1184   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1185     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1186     assert(PVal && "Expected a pseudo source value");
1187     switch (PVal->kind()) {
1188     case PseudoSourceValue::Stack:
1189       OS << "stack";
1190       break;
1191     case PseudoSourceValue::GOT:
1192       OS << "got";
1193       break;
1194     case PseudoSourceValue::JumpTable:
1195       OS << "jump-table";
1196       break;
1197     case PseudoSourceValue::ConstantPool:
1198       OS << "constant-pool";
1199       break;
1200     case PseudoSourceValue::FixedStack: {
1201       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1202       bool IsFixed = true;
1203       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1204       break;
1205     }
1206     case PseudoSourceValue::GlobalValueCallEntry:
1207       OS << "call-entry ";
1208       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1209           OS, /*PrintType=*/false, MST);
1210       break;
1211     case PseudoSourceValue::ExternalSymbolCallEntry:
1212       OS << "call-entry &";
1213       printLLVMNameWithoutPrefix(
1214           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1215       break;
1216     default: {
1217       const MIRFormatter *Formatter = TII->getMIRFormatter();
1218       // FIXME: This is not necessarily the correct MIR serialization format for
1219       // a custom pseudo source value, but at least it allows
1220       // MIR printing to work on a target with custom pseudo source
1221       // values.
1222       OS << "custom \"";
1223       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1224       OS << '\"';
1225       break;
1226     }
1227     }
1228   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1229     OS << ((isLoad() && isStore()) ? " on "
1230            : isLoad()              ? " from "
1231                                    : " into ")
1232        << "unknown-address";
1233   }
1234   MachineOperand::printOperandOffset(OS, getOffset());
1235   if (getSize() > 0 && getAlign() != getSize())
1236     OS << ", align " << getAlign().value();
1237   if (getAlign() != getBaseAlign())
1238     OS << ", basealign " << getBaseAlign().value();
1239   auto AAInfo = getAAInfo();
1240   if (AAInfo.TBAA) {
1241     OS << ", !tbaa ";
1242     AAInfo.TBAA->printAsOperand(OS, MST);
1243   }
1244   if (AAInfo.Scope) {
1245     OS << ", !alias.scope ";
1246     AAInfo.Scope->printAsOperand(OS, MST);
1247   }
1248   if (AAInfo.NoAlias) {
1249     OS << ", !noalias ";
1250     AAInfo.NoAlias->printAsOperand(OS, MST);
1251   }
1252   if (getRanges()) {
1253     OS << ", !range ";
1254     getRanges()->printAsOperand(OS, MST);
1255   }
1256   // FIXME: Implement addrspace printing/parsing in MIR.
1257   // For now, print this even though parsing it is not available in MIR.
1258   if (unsigned AS = getAddrSpace())
1259     OS << ", addrspace " << AS;
1260 
1261   OS << ')';
1262 }
1263