1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the class that prints out the LLVM IR and machine 10 // functions using the MIR serialization format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MIRPrinter.h" 15 #include "llvm/ADT/DenseMap.h" 16 #include "llvm/ADT/None.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallBitVector.h" 19 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/ADT/StringRef.h" 22 #include "llvm/ADT/Twine.h" 23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 24 #include "llvm/CodeGen/MIRYamlMapping.h" 25 #include "llvm/CodeGen/MachineBasicBlock.h" 26 #include "llvm/CodeGen/MachineConstantPool.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstr.h" 30 #include "llvm/CodeGen/MachineJumpTableInfo.h" 31 #include "llvm/CodeGen/MachineMemOperand.h" 32 #include "llvm/CodeGen/MachineOperand.h" 33 #include "llvm/CodeGen/MachineRegisterInfo.h" 34 #include "llvm/CodeGen/PseudoSourceValue.h" 35 #include "llvm/CodeGen/TargetInstrInfo.h" 36 #include "llvm/CodeGen/TargetRegisterInfo.h" 37 #include "llvm/CodeGen/TargetSubtargetInfo.h" 38 #include "llvm/CodeGen/TargetFrameLowering.h" 39 #include "llvm/IR/BasicBlock.h" 40 #include "llvm/IR/Constants.h" 41 #include "llvm/IR/DebugInfo.h" 42 #include "llvm/IR/DebugLoc.h" 43 #include "llvm/IR/Function.h" 44 #include "llvm/IR/GlobalValue.h" 45 #include "llvm/IR/IRPrintingPasses.h" 46 #include "llvm/IR/InstrTypes.h" 47 #include "llvm/IR/Instructions.h" 48 #include "llvm/IR/Intrinsics.h" 49 #include "llvm/IR/Module.h" 50 #include "llvm/IR/ModuleSlotTracker.h" 51 #include "llvm/IR/Value.h" 52 #include "llvm/MC/LaneBitmask.h" 53 #include "llvm/MC/MCContext.h" 54 #include "llvm/MC/MCDwarf.h" 55 #include "llvm/MC/MCSymbol.h" 56 #include "llvm/Support/AtomicOrdering.h" 57 #include "llvm/Support/BranchProbability.h" 58 #include "llvm/Support/Casting.h" 59 #include "llvm/Support/CommandLine.h" 60 #include "llvm/Support/ErrorHandling.h" 61 #include "llvm/Support/Format.h" 62 #include "llvm/Support/LowLevelTypeImpl.h" 63 #include "llvm/Support/YAMLTraits.h" 64 #include "llvm/Support/raw_ostream.h" 65 #include "llvm/Target/TargetIntrinsicInfo.h" 66 #include "llvm/Target/TargetMachine.h" 67 #include <algorithm> 68 #include <cassert> 69 #include <cinttypes> 70 #include <cstdint> 71 #include <iterator> 72 #include <string> 73 #include <utility> 74 #include <vector> 75 76 using namespace llvm; 77 78 static cl::opt<bool> SimplifyMIR( 79 "simplify-mir", cl::Hidden, 80 cl::desc("Leave out unnecessary information when printing MIR")); 81 82 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true), 83 cl::desc("Print MIR debug-locations")); 84 85 namespace { 86 87 /// This structure describes how to print out stack object references. 88 struct FrameIndexOperand { 89 std::string Name; 90 unsigned ID; 91 bool IsFixed; 92 93 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed) 94 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {} 95 96 /// Return an ordinary stack object reference. 97 static FrameIndexOperand create(StringRef Name, unsigned ID) { 98 return FrameIndexOperand(Name, ID, /*IsFixed=*/false); 99 } 100 101 /// Return a fixed stack object reference. 102 static FrameIndexOperand createFixed(unsigned ID) { 103 return FrameIndexOperand("", ID, /*IsFixed=*/true); 104 } 105 }; 106 107 } // end anonymous namespace 108 109 namespace llvm { 110 111 /// This class prints out the machine functions using the MIR serialization 112 /// format. 113 class MIRPrinter { 114 raw_ostream &OS; 115 DenseMap<const uint32_t *, unsigned> RegisterMaskIds; 116 /// Maps from stack object indices to operand indices which will be used when 117 /// printing frame index machine operands. 118 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping; 119 120 public: 121 MIRPrinter(raw_ostream &OS) : OS(OS) {} 122 123 void print(const MachineFunction &MF); 124 125 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, 126 const TargetRegisterInfo *TRI); 127 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI, 128 const MachineFrameInfo &MFI); 129 void convert(yaml::MachineFunction &MF, 130 const MachineConstantPool &ConstantPool); 131 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI, 132 const MachineJumpTableInfo &JTI); 133 void convertStackObjects(yaml::MachineFunction &YMF, 134 const MachineFunction &MF, ModuleSlotTracker &MST); 135 void convertCallSiteObjects(yaml::MachineFunction &YMF, 136 const MachineFunction &MF, 137 ModuleSlotTracker &MST); 138 139 private: 140 void initRegisterMaskIds(const MachineFunction &MF); 141 }; 142 143 /// This class prints out the machine instructions using the MIR serialization 144 /// format. 145 class MIPrinter { 146 raw_ostream &OS; 147 ModuleSlotTracker &MST; 148 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds; 149 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping; 150 /// Synchronization scope names registered with LLVMContext. 151 SmallVector<StringRef, 8> SSNs; 152 153 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const; 154 bool canPredictSuccessors(const MachineBasicBlock &MBB) const; 155 156 public: 157 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST, 158 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds, 159 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping) 160 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds), 161 StackObjectOperandMapping(StackObjectOperandMapping) {} 162 163 void print(const MachineBasicBlock &MBB); 164 165 void print(const MachineInstr &MI); 166 void printStackObjectReference(int FrameIndex); 167 void print(const MachineInstr &MI, unsigned OpIdx, 168 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, 169 bool ShouldPrintRegisterTies, LLT TypeToPrint, 170 bool PrintDef = true); 171 }; 172 173 } // end namespace llvm 174 175 namespace llvm { 176 namespace yaml { 177 178 /// This struct serializes the LLVM IR module. 179 template <> struct BlockScalarTraits<Module> { 180 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) { 181 Mod.print(OS, nullptr); 182 } 183 184 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) { 185 llvm_unreachable("LLVM Module is supposed to be parsed separately"); 186 return ""; 187 } 188 }; 189 190 } // end namespace yaml 191 } // end namespace llvm 192 193 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, 194 const TargetRegisterInfo *TRI) { 195 raw_string_ostream OS(Dest.Value); 196 OS << printReg(Reg, TRI); 197 } 198 199 void MIRPrinter::print(const MachineFunction &MF) { 200 initRegisterMaskIds(MF); 201 202 yaml::MachineFunction YamlMF; 203 YamlMF.Name = MF.getName(); 204 YamlMF.Alignment = MF.getAlignment(); 205 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); 206 YamlMF.HasWinCFI = MF.hasWinCFI(); 207 208 YamlMF.Legalized = MF.getProperties().hasProperty( 209 MachineFunctionProperties::Property::Legalized); 210 YamlMF.RegBankSelected = MF.getProperties().hasProperty( 211 MachineFunctionProperties::Property::RegBankSelected); 212 YamlMF.Selected = MF.getProperties().hasProperty( 213 MachineFunctionProperties::Property::Selected); 214 YamlMF.FailedISel = MF.getProperties().hasProperty( 215 MachineFunctionProperties::Property::FailedISel); 216 217 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); 218 ModuleSlotTracker MST(MF.getFunction().getParent()); 219 MST.incorporateFunction(MF.getFunction()); 220 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo()); 221 convertStackObjects(YamlMF, MF, MST); 222 convertCallSiteObjects(YamlMF, MF, MST); 223 if (const auto *ConstantPool = MF.getConstantPool()) 224 convert(YamlMF, *ConstantPool); 225 if (const auto *JumpTableInfo = MF.getJumpTableInfo()) 226 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo); 227 228 const TargetMachine &TM = MF.getTarget(); 229 YamlMF.MachineFuncInfo = 230 std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF)); 231 232 raw_string_ostream StrOS(YamlMF.Body.Value.Value); 233 bool IsNewlineNeeded = false; 234 for (const auto &MBB : MF) { 235 if (IsNewlineNeeded) 236 StrOS << "\n"; 237 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) 238 .print(MBB); 239 IsNewlineNeeded = true; 240 } 241 StrOS.flush(); 242 yaml::Output Out(OS); 243 if (!SimplifyMIR) 244 Out.setWriteDefaultValues(true); 245 Out << YamlMF; 246 } 247 248 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, 249 const TargetRegisterInfo *TRI) { 250 assert(RegMask && "Can't print an empty register mask"); 251 OS << StringRef("CustomRegMask("); 252 253 bool IsRegInRegMaskFound = false; 254 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) { 255 // Check whether the register is asserted in regmask. 256 if (RegMask[I / 32] & (1u << (I % 32))) { 257 if (IsRegInRegMaskFound) 258 OS << ','; 259 OS << printReg(I, TRI); 260 IsRegInRegMaskFound = true; 261 } 262 } 263 264 OS << ')'; 265 } 266 267 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest, 268 const MachineRegisterInfo &RegInfo, 269 const TargetRegisterInfo *TRI) { 270 raw_string_ostream OS(Dest.Value); 271 OS << printRegClassOrBank(Reg, RegInfo, TRI); 272 } 273 274 template <typename T> 275 static void 276 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar, 277 T &Object, ModuleSlotTracker &MST) { 278 std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value, 279 &Object.DebugExpr.Value, 280 &Object.DebugLoc.Value}}; 281 std::array<const Metadata *, 3> Metas{{DebugVar.Var, 282 DebugVar.Expr, 283 DebugVar.Loc}}; 284 for (unsigned i = 0; i < 3; ++i) { 285 raw_string_ostream StrOS(*Outputs[i]); 286 Metas[i]->printAsOperand(StrOS, MST); 287 } 288 } 289 290 void MIRPrinter::convert(yaml::MachineFunction &MF, 291 const MachineRegisterInfo &RegInfo, 292 const TargetRegisterInfo *TRI) { 293 MF.TracksRegLiveness = RegInfo.tracksLiveness(); 294 295 // Print the virtual register definitions. 296 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { 297 unsigned Reg = Register::index2VirtReg(I); 298 yaml::VirtualRegisterDefinition VReg; 299 VReg.ID = I; 300 if (RegInfo.getVRegName(Reg) != "") 301 continue; 302 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); 303 unsigned PreferredReg = RegInfo.getSimpleHint(Reg); 304 if (PreferredReg) 305 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); 306 MF.VirtualRegisters.push_back(VReg); 307 } 308 309 // Print the live ins. 310 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { 311 yaml::MachineFunctionLiveIn LiveIn; 312 printRegMIR(LI.first, LiveIn.Register, TRI); 313 if (LI.second) 314 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); 315 MF.LiveIns.push_back(LiveIn); 316 } 317 318 // Prints the callee saved registers. 319 if (RegInfo.isUpdatedCSRsInitialized()) { 320 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs(); 321 std::vector<yaml::FlowStringValue> CalleeSavedRegisters; 322 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { 323 yaml::FlowStringValue Reg; 324 printRegMIR(*I, Reg, TRI); 325 CalleeSavedRegisters.push_back(Reg); 326 } 327 MF.CalleeSavedRegisters = CalleeSavedRegisters; 328 } 329 } 330 331 void MIRPrinter::convert(ModuleSlotTracker &MST, 332 yaml::MachineFrameInfo &YamlMFI, 333 const MachineFrameInfo &MFI) { 334 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken(); 335 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken(); 336 YamlMFI.HasStackMap = MFI.hasStackMap(); 337 YamlMFI.HasPatchPoint = MFI.hasPatchPoint(); 338 YamlMFI.StackSize = MFI.getStackSize(); 339 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment(); 340 YamlMFI.MaxAlignment = MFI.getMaxAlign().value(); 341 YamlMFI.AdjustsStack = MFI.adjustsStack(); 342 YamlMFI.HasCalls = MFI.hasCalls(); 343 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed() 344 ? MFI.getMaxCallFrameSize() : ~0u; 345 YamlMFI.CVBytesOfCalleeSavedRegisters = 346 MFI.getCVBytesOfCalleeSavedRegisters(); 347 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment(); 348 YamlMFI.HasVAStart = MFI.hasVAStart(); 349 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); 350 YamlMFI.LocalFrameSize = MFI.getLocalFrameSize(); 351 if (MFI.getSavePoint()) { 352 raw_string_ostream StrOS(YamlMFI.SavePoint.Value); 353 StrOS << printMBBReference(*MFI.getSavePoint()); 354 } 355 if (MFI.getRestorePoint()) { 356 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value); 357 StrOS << printMBBReference(*MFI.getRestorePoint()); 358 } 359 } 360 361 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, 362 const MachineFunction &MF, 363 ModuleSlotTracker &MST) { 364 const MachineFrameInfo &MFI = MF.getFrameInfo(); 365 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 366 // Process fixed stack objects. 367 unsigned ID = 0; 368 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I, ++ID) { 369 if (MFI.isDeadObjectIndex(I)) 370 continue; 371 372 yaml::FixedMachineStackObject YamlObject; 373 YamlObject.ID = ID; 374 YamlObject.Type = MFI.isSpillSlotObjectIndex(I) 375 ? yaml::FixedMachineStackObject::SpillSlot 376 : yaml::FixedMachineStackObject::DefaultType; 377 YamlObject.Offset = MFI.getObjectOffset(I); 378 YamlObject.Size = MFI.getObjectSize(I); 379 YamlObject.Alignment = MFI.getObjectAlign(I); 380 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I); 381 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I); 382 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I); 383 YMF.FixedStackObjects.push_back(YamlObject); 384 StackObjectOperandMapping.insert( 385 std::make_pair(I, FrameIndexOperand::createFixed(ID))); 386 } 387 388 // Process ordinary stack objects. 389 ID = 0; 390 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I, ++ID) { 391 if (MFI.isDeadObjectIndex(I)) 392 continue; 393 394 yaml::MachineStackObject YamlObject; 395 YamlObject.ID = ID; 396 if (const auto *Alloca = MFI.getObjectAllocation(I)) 397 YamlObject.Name.Value = std::string( 398 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>"); 399 YamlObject.Type = MFI.isSpillSlotObjectIndex(I) 400 ? yaml::MachineStackObject::SpillSlot 401 : MFI.isVariableSizedObjectIndex(I) 402 ? yaml::MachineStackObject::VariableSized 403 : yaml::MachineStackObject::DefaultType; 404 YamlObject.Offset = MFI.getObjectOffset(I); 405 YamlObject.Size = MFI.getObjectSize(I); 406 YamlObject.Alignment = MFI.getObjectAlign(I); 407 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I); 408 409 YMF.StackObjects.push_back(YamlObject); 410 StackObjectOperandMapping.insert(std::make_pair( 411 I, FrameIndexOperand::create(YamlObject.Name.Value, ID))); 412 } 413 414 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { 415 if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(CSInfo.getFrameIdx())) 416 continue; 417 418 yaml::StringValue Reg; 419 printRegMIR(CSInfo.getReg(), Reg, TRI); 420 if (!CSInfo.isSpilledToReg()) { 421 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx()); 422 assert(StackObjectInfo != StackObjectOperandMapping.end() && 423 "Invalid stack object index"); 424 const FrameIndexOperand &StackObject = StackObjectInfo->second; 425 if (StackObject.IsFixed) { 426 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg; 427 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored = 428 CSInfo.isRestored(); 429 } else { 430 YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg; 431 YMF.StackObjects[StackObject.ID].CalleeSavedRestored = 432 CSInfo.isRestored(); 433 } 434 } 435 } 436 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) { 437 auto LocalObject = MFI.getLocalFrameObjectMap(I); 438 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first); 439 assert(StackObjectInfo != StackObjectOperandMapping.end() && 440 "Invalid stack object index"); 441 const FrameIndexOperand &StackObject = StackObjectInfo->second; 442 assert(!StackObject.IsFixed && "Expected a locally mapped stack object"); 443 YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second; 444 } 445 446 // Print the stack object references in the frame information class after 447 // converting the stack objects. 448 if (MFI.hasStackProtectorIndex()) { 449 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value); 450 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) 451 .printStackObjectReference(MFI.getStackProtectorIndex()); 452 } 453 454 // Print the debug variable information. 455 for (const MachineFunction::VariableDbgInfo &DebugVar : 456 MF.getVariableDbgInfo()) { 457 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot); 458 assert(StackObjectInfo != StackObjectOperandMapping.end() && 459 "Invalid stack object index"); 460 const FrameIndexOperand &StackObject = StackObjectInfo->second; 461 if (StackObject.IsFixed) { 462 auto &Object = YMF.FixedStackObjects[StackObject.ID]; 463 printStackObjectDbgInfo(DebugVar, Object, MST); 464 } else { 465 auto &Object = YMF.StackObjects[StackObject.ID]; 466 printStackObjectDbgInfo(DebugVar, Object, MST); 467 } 468 } 469 } 470 471 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF, 472 const MachineFunction &MF, 473 ModuleSlotTracker &MST) { 474 const auto *TRI = MF.getSubtarget().getRegisterInfo(); 475 for (auto CSInfo : MF.getCallSitesInfo()) { 476 yaml::CallSiteInfo YmlCS; 477 yaml::CallSiteInfo::MachineInstrLoc CallLocation; 478 479 // Prepare instruction position. 480 MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator(); 481 CallLocation.BlockNum = CallI->getParent()->getNumber(); 482 // Get call instruction offset from the beginning of block. 483 CallLocation.Offset = 484 std::distance(CallI->getParent()->instr_begin(), CallI); 485 YmlCS.CallLocation = CallLocation; 486 // Construct call arguments and theirs forwarding register info. 487 for (auto ArgReg : CSInfo.second) { 488 yaml::CallSiteInfo::ArgRegPair YmlArgReg; 489 YmlArgReg.ArgNo = ArgReg.ArgNo; 490 printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI); 491 YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg); 492 } 493 YMF.CallSitesInfo.push_back(YmlCS); 494 } 495 496 // Sort call info by position of call instructions. 497 llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(), 498 [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) { 499 if (A.CallLocation.BlockNum == B.CallLocation.BlockNum) 500 return A.CallLocation.Offset < B.CallLocation.Offset; 501 return A.CallLocation.BlockNum < B.CallLocation.BlockNum; 502 }); 503 } 504 505 void MIRPrinter::convert(yaml::MachineFunction &MF, 506 const MachineConstantPool &ConstantPool) { 507 unsigned ID = 0; 508 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) { 509 std::string Str; 510 raw_string_ostream StrOS(Str); 511 if (Constant.isMachineConstantPoolEntry()) { 512 Constant.Val.MachineCPVal->print(StrOS); 513 } else { 514 Constant.Val.ConstVal->printAsOperand(StrOS); 515 } 516 517 yaml::MachineConstantPoolValue YamlConstant; 518 YamlConstant.ID = ID++; 519 YamlConstant.Value = StrOS.str(); 520 YamlConstant.Alignment = Constant.getAlign(); 521 YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry(); 522 523 MF.Constants.push_back(YamlConstant); 524 } 525 } 526 527 void MIRPrinter::convert(ModuleSlotTracker &MST, 528 yaml::MachineJumpTable &YamlJTI, 529 const MachineJumpTableInfo &JTI) { 530 YamlJTI.Kind = JTI.getEntryKind(); 531 unsigned ID = 0; 532 for (const auto &Table : JTI.getJumpTables()) { 533 std::string Str; 534 yaml::MachineJumpTable::Entry Entry; 535 Entry.ID = ID++; 536 for (const auto *MBB : Table.MBBs) { 537 raw_string_ostream StrOS(Str); 538 StrOS << printMBBReference(*MBB); 539 Entry.Blocks.push_back(StrOS.str()); 540 Str.clear(); 541 } 542 YamlJTI.Entries.push_back(Entry); 543 } 544 } 545 546 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) { 547 const auto *TRI = MF.getSubtarget().getRegisterInfo(); 548 unsigned I = 0; 549 for (const uint32_t *Mask : TRI->getRegMasks()) 550 RegisterMaskIds.insert(std::make_pair(Mask, I++)); 551 } 552 553 void llvm::guessSuccessors(const MachineBasicBlock &MBB, 554 SmallVectorImpl<MachineBasicBlock*> &Result, 555 bool &IsFallthrough) { 556 SmallPtrSet<MachineBasicBlock*,8> Seen; 557 558 for (const MachineInstr &MI : MBB) { 559 if (MI.isPHI()) 560 continue; 561 for (const MachineOperand &MO : MI.operands()) { 562 if (!MO.isMBB()) 563 continue; 564 MachineBasicBlock *Succ = MO.getMBB(); 565 auto RP = Seen.insert(Succ); 566 if (RP.second) 567 Result.push_back(Succ); 568 } 569 } 570 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr(); 571 IsFallthrough = I == MBB.end() || !I->isBarrier(); 572 } 573 574 bool 575 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const { 576 if (MBB.succ_size() <= 1) 577 return true; 578 if (!MBB.hasSuccessorProbabilities()) 579 return true; 580 581 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(), 582 MBB.Probs.end()); 583 BranchProbability::normalizeProbabilities(Normalized.begin(), 584 Normalized.end()); 585 SmallVector<BranchProbability,8> Equal(Normalized.size()); 586 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end()); 587 588 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin()); 589 } 590 591 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const { 592 SmallVector<MachineBasicBlock*,8> GuessedSuccs; 593 bool GuessedFallthrough; 594 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough); 595 if (GuessedFallthrough) { 596 const MachineFunction &MF = *MBB.getParent(); 597 MachineFunction::const_iterator NextI = std::next(MBB.getIterator()); 598 if (NextI != MF.end()) { 599 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI); 600 if (!is_contained(GuessedSuccs, Next)) 601 GuessedSuccs.push_back(Next); 602 } 603 } 604 if (GuessedSuccs.size() != MBB.succ_size()) 605 return false; 606 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin()); 607 } 608 609 void MIPrinter::print(const MachineBasicBlock &MBB) { 610 assert(MBB.getNumber() >= 0 && "Invalid MBB number"); 611 OS << "bb." << MBB.getNumber(); 612 bool HasAttributes = false; 613 if (const auto *BB = MBB.getBasicBlock()) { 614 if (BB->hasName()) { 615 OS << "." << BB->getName(); 616 } else { 617 HasAttributes = true; 618 OS << " ("; 619 int Slot = MST.getLocalSlot(BB); 620 if (Slot == -1) 621 OS << "<ir-block badref>"; 622 else 623 OS << (Twine("%ir-block.") + Twine(Slot)).str(); 624 } 625 } 626 if (MBB.hasAddressTaken()) { 627 OS << (HasAttributes ? ", " : " ("); 628 OS << "address-taken"; 629 HasAttributes = true; 630 } 631 if (MBB.isEHPad()) { 632 OS << (HasAttributes ? ", " : " ("); 633 OS << "landing-pad"; 634 HasAttributes = true; 635 } 636 if (MBB.isEHFuncletEntry()) { 637 OS << (HasAttributes ? ", " : " ("); 638 OS << "ehfunclet-entry"; 639 HasAttributes = true; 640 } 641 if (MBB.getAlignment() != Align(1)) { 642 OS << (HasAttributes ? ", " : " ("); 643 OS << "align " << MBB.getAlignment().value(); 644 HasAttributes = true; 645 } 646 if (MBB.getSectionID() != MBBSectionID(0)) { 647 OS << (HasAttributes ? ", " : " ("); 648 OS << "bbsections "; 649 switch (MBB.getSectionID().Type) { 650 case MBBSectionID::SectionType::Exception: 651 OS << "Exception"; 652 break; 653 case MBBSectionID::SectionType::Cold: 654 OS << "Cold"; 655 break; 656 default: 657 OS << MBB.getSectionID().Number; 658 } 659 HasAttributes = true; 660 } 661 if (HasAttributes) 662 OS << ")"; 663 OS << ":\n"; 664 665 bool HasLineAttributes = false; 666 // Print the successors 667 bool canPredictProbs = canPredictBranchProbabilities(MBB); 668 // Even if the list of successors is empty, if we cannot guess it, 669 // we need to print it to tell the parser that the list is empty. 670 // This is needed, because MI model unreachable as empty blocks 671 // with an empty successor list. If the parser would see that 672 // without the successor list, it would guess the code would 673 // fallthrough. 674 if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs || 675 !canPredictSuccessors(MBB)) { 676 OS.indent(2) << "successors: "; 677 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) { 678 if (I != MBB.succ_begin()) 679 OS << ", "; 680 OS << printMBBReference(**I); 681 if (!SimplifyMIR || !canPredictProbs) 682 OS << '(' 683 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator()) 684 << ')'; 685 } 686 OS << "\n"; 687 HasLineAttributes = true; 688 } 689 690 // Print the live in registers. 691 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 692 if (MRI.tracksLiveness() && !MBB.livein_empty()) { 693 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 694 OS.indent(2) << "liveins: "; 695 bool First = true; 696 for (const auto &LI : MBB.liveins()) { 697 if (!First) 698 OS << ", "; 699 First = false; 700 OS << printReg(LI.PhysReg, &TRI); 701 if (!LI.LaneMask.all()) 702 OS << ":0x" << PrintLaneMask(LI.LaneMask); 703 } 704 OS << "\n"; 705 HasLineAttributes = true; 706 } 707 708 if (HasLineAttributes) 709 OS << "\n"; 710 bool IsInBundle = false; 711 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) { 712 const MachineInstr &MI = *I; 713 if (IsInBundle && !MI.isInsideBundle()) { 714 OS.indent(2) << "}\n"; 715 IsInBundle = false; 716 } 717 OS.indent(IsInBundle ? 4 : 2); 718 print(MI); 719 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) { 720 OS << " {"; 721 IsInBundle = true; 722 } 723 OS << "\n"; 724 } 725 if (IsInBundle) 726 OS.indent(2) << "}\n"; 727 } 728 729 void MIPrinter::print(const MachineInstr &MI) { 730 const auto *MF = MI.getMF(); 731 const auto &MRI = MF->getRegInfo(); 732 const auto &SubTarget = MF->getSubtarget(); 733 const auto *TRI = SubTarget.getRegisterInfo(); 734 assert(TRI && "Expected target register info"); 735 const auto *TII = SubTarget.getInstrInfo(); 736 assert(TII && "Expected target instruction info"); 737 if (MI.isCFIInstruction()) 738 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); 739 740 SmallBitVector PrintedTypes(8); 741 bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); 742 unsigned I = 0, E = MI.getNumOperands(); 743 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && 744 !MI.getOperand(I).isImplicit(); 745 ++I) { 746 if (I) 747 OS << ", "; 748 print(MI, I, TRI, TII, ShouldPrintRegisterTies, 749 MI.getTypeToPrint(I, PrintedTypes, MRI), 750 /*PrintDef=*/false); 751 } 752 753 if (I) 754 OS << " = "; 755 if (MI.getFlag(MachineInstr::FrameSetup)) 756 OS << "frame-setup "; 757 if (MI.getFlag(MachineInstr::FrameDestroy)) 758 OS << "frame-destroy "; 759 if (MI.getFlag(MachineInstr::FmNoNans)) 760 OS << "nnan "; 761 if (MI.getFlag(MachineInstr::FmNoInfs)) 762 OS << "ninf "; 763 if (MI.getFlag(MachineInstr::FmNsz)) 764 OS << "nsz "; 765 if (MI.getFlag(MachineInstr::FmArcp)) 766 OS << "arcp "; 767 if (MI.getFlag(MachineInstr::FmContract)) 768 OS << "contract "; 769 if (MI.getFlag(MachineInstr::FmAfn)) 770 OS << "afn "; 771 if (MI.getFlag(MachineInstr::FmReassoc)) 772 OS << "reassoc "; 773 if (MI.getFlag(MachineInstr::NoUWrap)) 774 OS << "nuw "; 775 if (MI.getFlag(MachineInstr::NoSWrap)) 776 OS << "nsw "; 777 if (MI.getFlag(MachineInstr::IsExact)) 778 OS << "exact "; 779 if (MI.getFlag(MachineInstr::NoFPExcept)) 780 OS << "nofpexcept "; 781 if (MI.getFlag(MachineInstr::NoMerge)) 782 OS << "nomerge "; 783 784 OS << TII->getName(MI.getOpcode()); 785 if (I < E) 786 OS << ' '; 787 788 bool NeedComma = false; 789 for (; I < E; ++I) { 790 if (NeedComma) 791 OS << ", "; 792 print(MI, I, TRI, TII, ShouldPrintRegisterTies, 793 MI.getTypeToPrint(I, PrintedTypes, MRI)); 794 NeedComma = true; 795 } 796 797 // Print any optional symbols attached to this instruction as-if they were 798 // operands. 799 if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) { 800 if (NeedComma) 801 OS << ','; 802 OS << " pre-instr-symbol "; 803 MachineOperand::printSymbol(OS, *PreInstrSymbol); 804 NeedComma = true; 805 } 806 if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) { 807 if (NeedComma) 808 OS << ','; 809 OS << " post-instr-symbol "; 810 MachineOperand::printSymbol(OS, *PostInstrSymbol); 811 NeedComma = true; 812 } 813 if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) { 814 if (NeedComma) 815 OS << ','; 816 OS << " heap-alloc-marker "; 817 HeapAllocMarker->printAsOperand(OS, MST); 818 NeedComma = true; 819 } 820 821 if (PrintLocations) { 822 if (const DebugLoc &DL = MI.getDebugLoc()) { 823 if (NeedComma) 824 OS << ','; 825 OS << " debug-location "; 826 DL->printAsOperand(OS, MST); 827 } 828 } 829 830 if (!MI.memoperands_empty()) { 831 OS << " :: "; 832 const LLVMContext &Context = MF->getFunction().getContext(); 833 const MachineFrameInfo &MFI = MF->getFrameInfo(); 834 bool NeedComma = false; 835 for (const auto *Op : MI.memoperands()) { 836 if (NeedComma) 837 OS << ", "; 838 Op->print(OS, MST, SSNs, Context, &MFI, TII); 839 NeedComma = true; 840 } 841 } 842 } 843 844 void MIPrinter::printStackObjectReference(int FrameIndex) { 845 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex); 846 assert(ObjectInfo != StackObjectOperandMapping.end() && 847 "Invalid frame index"); 848 const FrameIndexOperand &Operand = ObjectInfo->second; 849 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed, 850 Operand.Name); 851 } 852 853 static std::string formatOperandComment(std::string Comment) { 854 if (Comment.empty()) 855 return Comment; 856 return std::string(" /* " + Comment + " */"); 857 } 858 859 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, 860 const TargetRegisterInfo *TRI, 861 const TargetInstrInfo *TII, 862 bool ShouldPrintRegisterTies, LLT TypeToPrint, 863 bool PrintDef) { 864 const MachineOperand &Op = MI.getOperand(OpIdx); 865 std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI); 866 867 switch (Op.getType()) { 868 case MachineOperand::MO_Immediate: 869 if (MI.isOperandSubregIdx(OpIdx)) { 870 MachineOperand::printTargetFlags(OS, Op); 871 MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI); 872 break; 873 } 874 LLVM_FALLTHROUGH; 875 case MachineOperand::MO_Register: 876 case MachineOperand::MO_CImmediate: 877 case MachineOperand::MO_FPImmediate: 878 case MachineOperand::MO_MachineBasicBlock: 879 case MachineOperand::MO_ConstantPoolIndex: 880 case MachineOperand::MO_TargetIndex: 881 case MachineOperand::MO_JumpTableIndex: 882 case MachineOperand::MO_ExternalSymbol: 883 case MachineOperand::MO_GlobalAddress: 884 case MachineOperand::MO_RegisterLiveOut: 885 case MachineOperand::MO_Metadata: 886 case MachineOperand::MO_MCSymbol: 887 case MachineOperand::MO_CFIIndex: 888 case MachineOperand::MO_IntrinsicID: 889 case MachineOperand::MO_Predicate: 890 case MachineOperand::MO_BlockAddress: 891 case MachineOperand::MO_ShuffleMask: { 892 unsigned TiedOperandIdx = 0; 893 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) 894 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); 895 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); 896 Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false, 897 ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII); 898 OS << formatOperandComment(MOComment); 899 break; 900 } 901 case MachineOperand::MO_FrameIndex: 902 printStackObjectReference(Op.getIndex()); 903 break; 904 case MachineOperand::MO_RegisterMask: { 905 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask()); 906 if (RegMaskInfo != RegisterMaskIds.end()) 907 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower(); 908 else 909 printCustomRegMask(Op.getRegMask(), OS, TRI); 910 break; 911 } 912 } 913 } 914 915 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V, 916 ModuleSlotTracker &MST) { 917 if (isa<GlobalValue>(V)) { 918 V.printAsOperand(OS, /*PrintType=*/false, MST); 919 return; 920 } 921 if (isa<Constant>(V)) { 922 // Machine memory operands can load/store to/from constant value pointers. 923 OS << '`'; 924 V.printAsOperand(OS, /*PrintType=*/true, MST); 925 OS << '`'; 926 return; 927 } 928 OS << "%ir."; 929 if (V.hasName()) { 930 printLLVMNameWithoutPrefix(OS, V.getName()); 931 return; 932 } 933 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1; 934 MachineOperand::printIRSlotNumber(OS, Slot); 935 } 936 937 void llvm::printMIR(raw_ostream &OS, const Module &M) { 938 yaml::Output Out(OS); 939 Out << const_cast<Module &>(M); 940 } 941 942 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) { 943 MIRPrinter Printer(OS); 944 Printer.print(MF); 945 } 946