1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #define DEBUG_TYPE "legalizer" 30 31 using namespace llvm; 32 using namespace LegalizeActions; 33 using namespace MIPatternMatch; 34 35 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 36 /// 37 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 38 /// with any leftover piece as type \p LeftoverTy 39 /// 40 /// Returns -1 in the first element of the pair if the breakdown is not 41 /// satisfiable. 42 static std::pair<int, int> 43 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 44 assert(!LeftoverTy.isValid() && "this is an out argument"); 45 46 unsigned Size = OrigTy.getSizeInBits(); 47 unsigned NarrowSize = NarrowTy.getSizeInBits(); 48 unsigned NumParts = Size / NarrowSize; 49 unsigned LeftoverSize = Size - NumParts * NarrowSize; 50 assert(Size > NarrowSize); 51 52 if (LeftoverSize == 0) 53 return {NumParts, 0}; 54 55 if (NarrowTy.isVector()) { 56 unsigned EltSize = OrigTy.getScalarSizeInBits(); 57 if (LeftoverSize % EltSize != 0) 58 return {-1, -1}; 59 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 60 } else { 61 LeftoverTy = LLT::scalar(LeftoverSize); 62 } 63 64 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 65 return std::make_pair(NumParts, NumLeftover); 66 } 67 68 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 69 70 if (!Ty.isScalar()) 71 return nullptr; 72 73 switch (Ty.getSizeInBits()) { 74 case 16: 75 return Type::getHalfTy(Ctx); 76 case 32: 77 return Type::getFloatTy(Ctx); 78 case 64: 79 return Type::getDoubleTy(Ctx); 80 case 80: 81 return Type::getX86_FP80Ty(Ctx); 82 case 128: 83 return Type::getFP128Ty(Ctx); 84 default: 85 return nullptr; 86 } 87 } 88 89 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 90 GISelChangeObserver &Observer, 91 MachineIRBuilder &Builder) 92 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 93 LI(*MF.getSubtarget().getLegalizerInfo()), 94 TLI(*MF.getSubtarget().getTargetLowering()) { } 95 96 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 97 GISelChangeObserver &Observer, 98 MachineIRBuilder &B) 99 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 100 TLI(*MF.getSubtarget().getTargetLowering()) { } 101 102 LegalizerHelper::LegalizeResult 103 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { 104 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 105 106 MIRBuilder.setInstrAndDebugLoc(MI); 107 108 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 109 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 110 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 111 auto Step = LI.getAction(MI, MRI); 112 switch (Step.Action) { 113 case Legal: 114 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 115 return AlreadyLegal; 116 case Libcall: 117 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 118 return libcall(MI); 119 case NarrowScalar: 120 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 121 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 122 case WidenScalar: 123 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 124 return widenScalar(MI, Step.TypeIdx, Step.NewType); 125 case Bitcast: 126 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 127 return bitcast(MI, Step.TypeIdx, Step.NewType); 128 case Lower: 129 LLVM_DEBUG(dbgs() << ".. Lower\n"); 130 return lower(MI, Step.TypeIdx, Step.NewType); 131 case FewerElements: 132 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 133 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 134 case MoreElements: 135 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 136 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 137 case Custom: 138 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 139 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 140 default: 141 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 142 return UnableToLegalize; 143 } 144 } 145 146 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 147 SmallVectorImpl<Register> &VRegs) { 148 for (int i = 0; i < NumParts; ++i) 149 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 150 MIRBuilder.buildUnmerge(VRegs, Reg); 151 } 152 153 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 154 LLT MainTy, LLT &LeftoverTy, 155 SmallVectorImpl<Register> &VRegs, 156 SmallVectorImpl<Register> &LeftoverRegs) { 157 assert(!LeftoverTy.isValid() && "this is an out argument"); 158 159 unsigned RegSize = RegTy.getSizeInBits(); 160 unsigned MainSize = MainTy.getSizeInBits(); 161 unsigned NumParts = RegSize / MainSize; 162 unsigned LeftoverSize = RegSize - NumParts * MainSize; 163 164 // Use an unmerge when possible. 165 if (LeftoverSize == 0) { 166 for (unsigned I = 0; I < NumParts; ++I) 167 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 168 MIRBuilder.buildUnmerge(VRegs, Reg); 169 return true; 170 } 171 172 if (MainTy.isVector()) { 173 unsigned EltSize = MainTy.getScalarSizeInBits(); 174 if (LeftoverSize % EltSize != 0) 175 return false; 176 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 177 } else { 178 LeftoverTy = LLT::scalar(LeftoverSize); 179 } 180 181 // For irregular sizes, extract the individual parts. 182 for (unsigned I = 0; I != NumParts; ++I) { 183 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 184 VRegs.push_back(NewReg); 185 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 186 } 187 188 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 189 Offset += LeftoverSize) { 190 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 191 LeftoverRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, Offset); 193 } 194 195 return true; 196 } 197 198 void LegalizerHelper::insertParts(Register DstReg, 199 LLT ResultTy, LLT PartTy, 200 ArrayRef<Register> PartRegs, 201 LLT LeftoverTy, 202 ArrayRef<Register> LeftoverRegs) { 203 if (!LeftoverTy.isValid()) { 204 assert(LeftoverRegs.empty()); 205 206 if (!ResultTy.isVector()) { 207 MIRBuilder.buildMerge(DstReg, PartRegs); 208 return; 209 } 210 211 if (PartTy.isVector()) 212 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 213 else 214 MIRBuilder.buildBuildVector(DstReg, PartRegs); 215 return; 216 } 217 218 unsigned PartSize = PartTy.getSizeInBits(); 219 unsigned LeftoverPartSize = LeftoverTy.getSizeInBits(); 220 221 Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy); 222 MIRBuilder.buildUndef(CurResultReg); 223 224 unsigned Offset = 0; 225 for (Register PartReg : PartRegs) { 226 Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy); 227 MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset); 228 CurResultReg = NewResultReg; 229 Offset += PartSize; 230 } 231 232 for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) { 233 // Use the original output register for the final insert to avoid a copy. 234 Register NewResultReg = (I + 1 == E) ? 235 DstReg : MRI.createGenericVirtualRegister(ResultTy); 236 237 MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset); 238 CurResultReg = NewResultReg; 239 Offset += LeftoverPartSize; 240 } 241 } 242 243 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 244 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 245 const MachineInstr &MI) { 246 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 247 248 const int StartIdx = Regs.size(); 249 const int NumResults = MI.getNumOperands() - 1; 250 Regs.resize(Regs.size() + NumResults); 251 for (int I = 0; I != NumResults; ++I) 252 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 253 } 254 255 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 256 LLT GCDTy, Register SrcReg) { 257 LLT SrcTy = MRI.getType(SrcReg); 258 if (SrcTy == GCDTy) { 259 // If the source already evenly divides the result type, we don't need to do 260 // anything. 261 Parts.push_back(SrcReg); 262 } else { 263 // Need to split into common type sized pieces. 264 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 265 getUnmergeResults(Parts, *Unmerge); 266 } 267 } 268 269 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 270 LLT NarrowTy, Register SrcReg) { 271 LLT SrcTy = MRI.getType(SrcReg); 272 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 273 extractGCDType(Parts, GCDTy, SrcReg); 274 return GCDTy; 275 } 276 277 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 278 SmallVectorImpl<Register> &VRegs, 279 unsigned PadStrategy) { 280 LLT LCMTy = getLCMType(DstTy, NarrowTy); 281 282 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 283 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 284 int NumOrigSrc = VRegs.size(); 285 286 Register PadReg; 287 288 // Get a value we can use to pad the source value if the sources won't evenly 289 // cover the result type. 290 if (NumOrigSrc < NumParts * NumSubParts) { 291 if (PadStrategy == TargetOpcode::G_ZEXT) 292 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 293 else if (PadStrategy == TargetOpcode::G_ANYEXT) 294 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 295 else { 296 assert(PadStrategy == TargetOpcode::G_SEXT); 297 298 // Shift the sign bit of the low register through the high register. 299 auto ShiftAmt = 300 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 301 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 302 } 303 } 304 305 // Registers for the final merge to be produced. 306 SmallVector<Register, 4> Remerge(NumParts); 307 308 // Registers needed for intermediate merges, which will be merged into a 309 // source for Remerge. 310 SmallVector<Register, 4> SubMerge(NumSubParts); 311 312 // Once we've fully read off the end of the original source bits, we can reuse 313 // the same high bits for remaining padding elements. 314 Register AllPadReg; 315 316 // Build merges to the LCM type to cover the original result type. 317 for (int I = 0; I != NumParts; ++I) { 318 bool AllMergePartsArePadding = true; 319 320 // Build the requested merges to the requested type. 321 for (int J = 0; J != NumSubParts; ++J) { 322 int Idx = I * NumSubParts + J; 323 if (Idx >= NumOrigSrc) { 324 SubMerge[J] = PadReg; 325 continue; 326 } 327 328 SubMerge[J] = VRegs[Idx]; 329 330 // There are meaningful bits here we can't reuse later. 331 AllMergePartsArePadding = false; 332 } 333 334 // If we've filled up a complete piece with padding bits, we can directly 335 // emit the natural sized constant if applicable, rather than a merge of 336 // smaller constants. 337 if (AllMergePartsArePadding && !AllPadReg) { 338 if (PadStrategy == TargetOpcode::G_ANYEXT) 339 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 340 else if (PadStrategy == TargetOpcode::G_ZEXT) 341 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 342 343 // If this is a sign extension, we can't materialize a trivial constant 344 // with the right type and have to produce a merge. 345 } 346 347 if (AllPadReg) { 348 // Avoid creating additional instructions if we're just adding additional 349 // copies of padding bits. 350 Remerge[I] = AllPadReg; 351 continue; 352 } 353 354 if (NumSubParts == 1) 355 Remerge[I] = SubMerge[0]; 356 else 357 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 358 359 // In the sign extend padding case, re-use the first all-signbit merge. 360 if (AllMergePartsArePadding && !AllPadReg) 361 AllPadReg = Remerge[I]; 362 } 363 364 VRegs = std::move(Remerge); 365 return LCMTy; 366 } 367 368 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 369 ArrayRef<Register> RemergeRegs) { 370 LLT DstTy = MRI.getType(DstReg); 371 372 // Create the merge to the widened source, and extract the relevant bits into 373 // the result. 374 375 if (DstTy == LCMTy) { 376 MIRBuilder.buildMerge(DstReg, RemergeRegs); 377 return; 378 } 379 380 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 381 if (DstTy.isScalar() && LCMTy.isScalar()) { 382 MIRBuilder.buildTrunc(DstReg, Remerge); 383 return; 384 } 385 386 if (LCMTy.isVector()) { 387 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 388 SmallVector<Register, 8> UnmergeDefs(NumDefs); 389 UnmergeDefs[0] = DstReg; 390 for (unsigned I = 1; I != NumDefs; ++I) 391 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 392 393 MIRBuilder.buildUnmerge(UnmergeDefs, 394 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 395 return; 396 } 397 398 llvm_unreachable("unhandled case"); 399 } 400 401 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 402 #define RTLIBCASE_INT(LibcallPrefix) \ 403 do { \ 404 switch (Size) { \ 405 case 32: \ 406 return RTLIB::LibcallPrefix##32; \ 407 case 64: \ 408 return RTLIB::LibcallPrefix##64; \ 409 case 128: \ 410 return RTLIB::LibcallPrefix##128; \ 411 default: \ 412 llvm_unreachable("unexpected size"); \ 413 } \ 414 } while (0) 415 416 #define RTLIBCASE(LibcallPrefix) \ 417 do { \ 418 switch (Size) { \ 419 case 32: \ 420 return RTLIB::LibcallPrefix##32; \ 421 case 64: \ 422 return RTLIB::LibcallPrefix##64; \ 423 case 80: \ 424 return RTLIB::LibcallPrefix##80; \ 425 case 128: \ 426 return RTLIB::LibcallPrefix##128; \ 427 default: \ 428 llvm_unreachable("unexpected size"); \ 429 } \ 430 } while (0) 431 432 switch (Opcode) { 433 case TargetOpcode::G_SDIV: 434 RTLIBCASE_INT(SDIV_I); 435 case TargetOpcode::G_UDIV: 436 RTLIBCASE_INT(UDIV_I); 437 case TargetOpcode::G_SREM: 438 RTLIBCASE_INT(SREM_I); 439 case TargetOpcode::G_UREM: 440 RTLIBCASE_INT(UREM_I); 441 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 442 RTLIBCASE_INT(CTLZ_I); 443 case TargetOpcode::G_FADD: 444 RTLIBCASE(ADD_F); 445 case TargetOpcode::G_FSUB: 446 RTLIBCASE(SUB_F); 447 case TargetOpcode::G_FMUL: 448 RTLIBCASE(MUL_F); 449 case TargetOpcode::G_FDIV: 450 RTLIBCASE(DIV_F); 451 case TargetOpcode::G_FEXP: 452 RTLIBCASE(EXP_F); 453 case TargetOpcode::G_FEXP2: 454 RTLIBCASE(EXP2_F); 455 case TargetOpcode::G_FREM: 456 RTLIBCASE(REM_F); 457 case TargetOpcode::G_FPOW: 458 RTLIBCASE(POW_F); 459 case TargetOpcode::G_FMA: 460 RTLIBCASE(FMA_F); 461 case TargetOpcode::G_FSIN: 462 RTLIBCASE(SIN_F); 463 case TargetOpcode::G_FCOS: 464 RTLIBCASE(COS_F); 465 case TargetOpcode::G_FLOG10: 466 RTLIBCASE(LOG10_F); 467 case TargetOpcode::G_FLOG: 468 RTLIBCASE(LOG_F); 469 case TargetOpcode::G_FLOG2: 470 RTLIBCASE(LOG2_F); 471 case TargetOpcode::G_FCEIL: 472 RTLIBCASE(CEIL_F); 473 case TargetOpcode::G_FFLOOR: 474 RTLIBCASE(FLOOR_F); 475 case TargetOpcode::G_FMINNUM: 476 RTLIBCASE(FMIN_F); 477 case TargetOpcode::G_FMAXNUM: 478 RTLIBCASE(FMAX_F); 479 case TargetOpcode::G_FSQRT: 480 RTLIBCASE(SQRT_F); 481 case TargetOpcode::G_FRINT: 482 RTLIBCASE(RINT_F); 483 case TargetOpcode::G_FNEARBYINT: 484 RTLIBCASE(NEARBYINT_F); 485 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 486 RTLIBCASE(ROUNDEVEN_F); 487 } 488 llvm_unreachable("Unknown libcall function"); 489 } 490 491 /// True if an instruction is in tail position in its caller. Intended for 492 /// legalizing libcalls as tail calls when possible. 493 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 494 MachineInstr &MI) { 495 MachineBasicBlock &MBB = *MI.getParent(); 496 const Function &F = MBB.getParent()->getFunction(); 497 498 // Conservatively require the attributes of the call to match those of 499 // the return. Ignore NoAlias and NonNull because they don't affect the 500 // call sequence. 501 AttributeList CallerAttrs = F.getAttributes(); 502 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 503 .removeAttribute(Attribute::NoAlias) 504 .removeAttribute(Attribute::NonNull) 505 .hasAttributes()) 506 return false; 507 508 // It's not safe to eliminate the sign / zero extension of the return value. 509 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 510 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 511 return false; 512 513 // Only tail call if the following instruction is a standard return. 514 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 515 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 516 return false; 517 518 return true; 519 } 520 521 LegalizerHelper::LegalizeResult 522 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 523 const CallLowering::ArgInfo &Result, 524 ArrayRef<CallLowering::ArgInfo> Args, 525 const CallingConv::ID CC) { 526 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 527 528 CallLowering::CallLoweringInfo Info; 529 Info.CallConv = CC; 530 Info.Callee = MachineOperand::CreateES(Name); 531 Info.OrigRet = Result; 532 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 533 if (!CLI.lowerCall(MIRBuilder, Info)) 534 return LegalizerHelper::UnableToLegalize; 535 536 return LegalizerHelper::Legalized; 537 } 538 539 LegalizerHelper::LegalizeResult 540 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 541 const CallLowering::ArgInfo &Result, 542 ArrayRef<CallLowering::ArgInfo> Args) { 543 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 544 const char *Name = TLI.getLibcallName(Libcall); 545 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 546 return createLibcall(MIRBuilder, Name, Result, Args, CC); 547 } 548 549 // Useful for libcalls where all operands have the same type. 550 static LegalizerHelper::LegalizeResult 551 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 552 Type *OpType) { 553 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 554 555 SmallVector<CallLowering::ArgInfo, 3> Args; 556 for (unsigned i = 1; i < MI.getNumOperands(); i++) 557 Args.push_back({MI.getOperand(i).getReg(), OpType}); 558 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, 559 Args); 560 } 561 562 LegalizerHelper::LegalizeResult 563 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 564 MachineInstr &MI) { 565 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 566 567 SmallVector<CallLowering::ArgInfo, 3> Args; 568 // Add all the args, except for the last which is an imm denoting 'tail'. 569 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 570 Register Reg = MI.getOperand(i).getReg(); 571 572 // Need derive an IR type for call lowering. 573 LLT OpLLT = MRI.getType(Reg); 574 Type *OpTy = nullptr; 575 if (OpLLT.isPointer()) 576 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 577 else 578 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 579 Args.push_back({Reg, OpTy}); 580 } 581 582 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 583 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 584 RTLIB::Libcall RTLibcall; 585 switch (MI.getOpcode()) { 586 case TargetOpcode::G_MEMCPY: 587 RTLibcall = RTLIB::MEMCPY; 588 break; 589 case TargetOpcode::G_MEMMOVE: 590 RTLibcall = RTLIB::MEMMOVE; 591 break; 592 case TargetOpcode::G_MEMSET: 593 RTLibcall = RTLIB::MEMSET; 594 break; 595 default: 596 return LegalizerHelper::UnableToLegalize; 597 } 598 const char *Name = TLI.getLibcallName(RTLibcall); 599 600 CallLowering::CallLoweringInfo Info; 601 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 602 Info.Callee = MachineOperand::CreateES(Name); 603 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); 604 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 605 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 606 607 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 608 if (!CLI.lowerCall(MIRBuilder, Info)) 609 return LegalizerHelper::UnableToLegalize; 610 611 if (Info.LoweredTailCall) { 612 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 613 // We must have a return following the call (or debug insts) to get past 614 // isLibCallInTailPosition. 615 do { 616 MachineInstr *Next = MI.getNextNode(); 617 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 618 "Expected instr following MI to be return or debug inst?"); 619 // We lowered a tail call, so the call is now the return from the block. 620 // Delete the old return. 621 Next->eraseFromParent(); 622 } while (MI.getNextNode()); 623 } 624 625 return LegalizerHelper::Legalized; 626 } 627 628 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 629 Type *FromType) { 630 auto ToMVT = MVT::getVT(ToType); 631 auto FromMVT = MVT::getVT(FromType); 632 633 switch (Opcode) { 634 case TargetOpcode::G_FPEXT: 635 return RTLIB::getFPEXT(FromMVT, ToMVT); 636 case TargetOpcode::G_FPTRUNC: 637 return RTLIB::getFPROUND(FromMVT, ToMVT); 638 case TargetOpcode::G_FPTOSI: 639 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 640 case TargetOpcode::G_FPTOUI: 641 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 642 case TargetOpcode::G_SITOFP: 643 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 644 case TargetOpcode::G_UITOFP: 645 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 646 } 647 llvm_unreachable("Unsupported libcall function"); 648 } 649 650 static LegalizerHelper::LegalizeResult 651 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 652 Type *FromType) { 653 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 654 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, 655 {{MI.getOperand(1).getReg(), FromType}}); 656 } 657 658 LegalizerHelper::LegalizeResult 659 LegalizerHelper::libcall(MachineInstr &MI) { 660 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 661 unsigned Size = LLTy.getSizeInBits(); 662 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 663 664 switch (MI.getOpcode()) { 665 default: 666 return UnableToLegalize; 667 case TargetOpcode::G_SDIV: 668 case TargetOpcode::G_UDIV: 669 case TargetOpcode::G_SREM: 670 case TargetOpcode::G_UREM: 671 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 672 Type *HLTy = IntegerType::get(Ctx, Size); 673 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 674 if (Status != Legalized) 675 return Status; 676 break; 677 } 678 case TargetOpcode::G_FADD: 679 case TargetOpcode::G_FSUB: 680 case TargetOpcode::G_FMUL: 681 case TargetOpcode::G_FDIV: 682 case TargetOpcode::G_FMA: 683 case TargetOpcode::G_FPOW: 684 case TargetOpcode::G_FREM: 685 case TargetOpcode::G_FCOS: 686 case TargetOpcode::G_FSIN: 687 case TargetOpcode::G_FLOG10: 688 case TargetOpcode::G_FLOG: 689 case TargetOpcode::G_FLOG2: 690 case TargetOpcode::G_FEXP: 691 case TargetOpcode::G_FEXP2: 692 case TargetOpcode::G_FCEIL: 693 case TargetOpcode::G_FFLOOR: 694 case TargetOpcode::G_FMINNUM: 695 case TargetOpcode::G_FMAXNUM: 696 case TargetOpcode::G_FSQRT: 697 case TargetOpcode::G_FRINT: 698 case TargetOpcode::G_FNEARBYINT: 699 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 700 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 701 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 702 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 703 return UnableToLegalize; 704 } 705 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 706 if (Status != Legalized) 707 return Status; 708 break; 709 } 710 case TargetOpcode::G_FPEXT: 711 case TargetOpcode::G_FPTRUNC: { 712 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 713 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 714 if (!FromTy || !ToTy) 715 return UnableToLegalize; 716 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPTOSI: 722 case TargetOpcode::G_FPTOUI: { 723 // FIXME: Support other types 724 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 725 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 726 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 727 return UnableToLegalize; 728 LegalizeResult Status = conversionLibcall( 729 MI, MIRBuilder, 730 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 731 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 732 if (Status != Legalized) 733 return Status; 734 break; 735 } 736 case TargetOpcode::G_SITOFP: 737 case TargetOpcode::G_UITOFP: { 738 // FIXME: Support other types 739 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 740 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 741 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 742 return UnableToLegalize; 743 LegalizeResult Status = conversionLibcall( 744 MI, MIRBuilder, 745 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 746 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 747 if (Status != Legalized) 748 return Status; 749 break; 750 } 751 case TargetOpcode::G_MEMCPY: 752 case TargetOpcode::G_MEMMOVE: 753 case TargetOpcode::G_MEMSET: { 754 LegalizeResult Result = createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI); 755 MI.eraseFromParent(); 756 return Result; 757 } 758 } 759 760 MI.eraseFromParent(); 761 return Legalized; 762 } 763 764 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 765 unsigned TypeIdx, 766 LLT NarrowTy) { 767 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 768 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 769 770 switch (MI.getOpcode()) { 771 default: 772 return UnableToLegalize; 773 case TargetOpcode::G_IMPLICIT_DEF: { 774 Register DstReg = MI.getOperand(0).getReg(); 775 LLT DstTy = MRI.getType(DstReg); 776 777 // If SizeOp0 is not an exact multiple of NarrowSize, emit 778 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 779 // FIXME: Although this would also be legal for the general case, it causes 780 // a lot of regressions in the emitted code (superfluous COPYs, artifact 781 // combines not being hit). This seems to be a problem related to the 782 // artifact combiner. 783 if (SizeOp0 % NarrowSize != 0) { 784 LLT ImplicitTy = NarrowTy; 785 if (DstTy.isVector()) 786 ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy); 787 788 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 789 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 790 791 MI.eraseFromParent(); 792 return Legalized; 793 } 794 795 int NumParts = SizeOp0 / NarrowSize; 796 797 SmallVector<Register, 2> DstRegs; 798 for (int i = 0; i < NumParts; ++i) 799 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 800 801 if (DstTy.isVector()) 802 MIRBuilder.buildBuildVector(DstReg, DstRegs); 803 else 804 MIRBuilder.buildMerge(DstReg, DstRegs); 805 MI.eraseFromParent(); 806 return Legalized; 807 } 808 case TargetOpcode::G_CONSTANT: { 809 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 810 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 811 unsigned TotalSize = Ty.getSizeInBits(); 812 unsigned NarrowSize = NarrowTy.getSizeInBits(); 813 int NumParts = TotalSize / NarrowSize; 814 815 SmallVector<Register, 4> PartRegs; 816 for (int I = 0; I != NumParts; ++I) { 817 unsigned Offset = I * NarrowSize; 818 auto K = MIRBuilder.buildConstant(NarrowTy, 819 Val.lshr(Offset).trunc(NarrowSize)); 820 PartRegs.push_back(K.getReg(0)); 821 } 822 823 LLT LeftoverTy; 824 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 825 SmallVector<Register, 1> LeftoverRegs; 826 if (LeftoverBits != 0) { 827 LeftoverTy = LLT::scalar(LeftoverBits); 828 auto K = MIRBuilder.buildConstant( 829 LeftoverTy, 830 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 831 LeftoverRegs.push_back(K.getReg(0)); 832 } 833 834 insertParts(MI.getOperand(0).getReg(), 835 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 836 837 MI.eraseFromParent(); 838 return Legalized; 839 } 840 case TargetOpcode::G_SEXT: 841 case TargetOpcode::G_ZEXT: 842 case TargetOpcode::G_ANYEXT: 843 return narrowScalarExt(MI, TypeIdx, NarrowTy); 844 case TargetOpcode::G_TRUNC: { 845 if (TypeIdx != 1) 846 return UnableToLegalize; 847 848 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 849 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 850 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 851 return UnableToLegalize; 852 } 853 854 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 855 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 856 MI.eraseFromParent(); 857 return Legalized; 858 } 859 860 case TargetOpcode::G_FREEZE: 861 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 862 863 case TargetOpcode::G_ADD: { 864 // FIXME: add support for when SizeOp0 isn't an exact multiple of 865 // NarrowSize. 866 if (SizeOp0 % NarrowSize != 0) 867 return UnableToLegalize; 868 // Expand in terms of carry-setting/consuming G_ADDE instructions. 869 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 870 871 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 872 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 873 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 874 875 Register CarryIn; 876 for (int i = 0; i < NumParts; ++i) { 877 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 878 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 879 880 if (i == 0) 881 MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]); 882 else { 883 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i], 884 Src2Regs[i], CarryIn); 885 } 886 887 DstRegs.push_back(DstReg); 888 CarryIn = CarryOut; 889 } 890 Register DstReg = MI.getOperand(0).getReg(); 891 if(MRI.getType(DstReg).isVector()) 892 MIRBuilder.buildBuildVector(DstReg, DstRegs); 893 else 894 MIRBuilder.buildMerge(DstReg, DstRegs); 895 MI.eraseFromParent(); 896 return Legalized; 897 } 898 case TargetOpcode::G_SUB: { 899 // FIXME: add support for when SizeOp0 isn't an exact multiple of 900 // NarrowSize. 901 if (SizeOp0 % NarrowSize != 0) 902 return UnableToLegalize; 903 904 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 905 906 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 907 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 908 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 909 910 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 911 Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 912 MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut}, 913 {Src1Regs[0], Src2Regs[0]}); 914 DstRegs.push_back(DstReg); 915 Register BorrowIn = BorrowOut; 916 for (int i = 1; i < NumParts; ++i) { 917 DstReg = MRI.createGenericVirtualRegister(NarrowTy); 918 BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 919 920 MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut}, 921 {Src1Regs[i], Src2Regs[i], BorrowIn}); 922 923 DstRegs.push_back(DstReg); 924 BorrowIn = BorrowOut; 925 } 926 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 927 MI.eraseFromParent(); 928 return Legalized; 929 } 930 case TargetOpcode::G_MUL: 931 case TargetOpcode::G_UMULH: 932 return narrowScalarMul(MI, NarrowTy); 933 case TargetOpcode::G_EXTRACT: 934 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 935 case TargetOpcode::G_INSERT: 936 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 937 case TargetOpcode::G_LOAD: { 938 auto &MMO = **MI.memoperands_begin(); 939 Register DstReg = MI.getOperand(0).getReg(); 940 LLT DstTy = MRI.getType(DstReg); 941 if (DstTy.isVector()) 942 return UnableToLegalize; 943 944 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 945 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 946 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 947 MIRBuilder.buildAnyExt(DstReg, TmpReg); 948 MI.eraseFromParent(); 949 return Legalized; 950 } 951 952 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 953 } 954 case TargetOpcode::G_ZEXTLOAD: 955 case TargetOpcode::G_SEXTLOAD: { 956 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 957 Register DstReg = MI.getOperand(0).getReg(); 958 Register PtrReg = MI.getOperand(1).getReg(); 959 960 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 961 auto &MMO = **MI.memoperands_begin(); 962 unsigned MemSize = MMO.getSizeInBits(); 963 964 if (MemSize == NarrowSize) { 965 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 966 } else if (MemSize < NarrowSize) { 967 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 968 } else if (MemSize > NarrowSize) { 969 // FIXME: Need to split the load. 970 return UnableToLegalize; 971 } 972 973 if (ZExt) 974 MIRBuilder.buildZExt(DstReg, TmpReg); 975 else 976 MIRBuilder.buildSExt(DstReg, TmpReg); 977 978 MI.eraseFromParent(); 979 return Legalized; 980 } 981 case TargetOpcode::G_STORE: { 982 const auto &MMO = **MI.memoperands_begin(); 983 984 Register SrcReg = MI.getOperand(0).getReg(); 985 LLT SrcTy = MRI.getType(SrcReg); 986 if (SrcTy.isVector()) 987 return UnableToLegalize; 988 989 int NumParts = SizeOp0 / NarrowSize; 990 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 991 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 992 if (SrcTy.isVector() && LeftoverBits != 0) 993 return UnableToLegalize; 994 995 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 996 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 997 auto &MMO = **MI.memoperands_begin(); 998 MIRBuilder.buildTrunc(TmpReg, SrcReg); 999 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 1000 MI.eraseFromParent(); 1001 return Legalized; 1002 } 1003 1004 return reduceLoadStoreWidth(MI, 0, NarrowTy); 1005 } 1006 case TargetOpcode::G_SELECT: 1007 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 1008 case TargetOpcode::G_AND: 1009 case TargetOpcode::G_OR: 1010 case TargetOpcode::G_XOR: { 1011 // Legalize bitwise operation: 1012 // A = BinOp<Ty> B, C 1013 // into: 1014 // B1, ..., BN = G_UNMERGE_VALUES B 1015 // C1, ..., CN = G_UNMERGE_VALUES C 1016 // A1 = BinOp<Ty/N> B1, C2 1017 // ... 1018 // AN = BinOp<Ty/N> BN, CN 1019 // A = G_MERGE_VALUES A1, ..., AN 1020 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 1021 } 1022 case TargetOpcode::G_SHL: 1023 case TargetOpcode::G_LSHR: 1024 case TargetOpcode::G_ASHR: 1025 return narrowScalarShift(MI, TypeIdx, NarrowTy); 1026 case TargetOpcode::G_CTLZ: 1027 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1028 case TargetOpcode::G_CTTZ: 1029 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1030 case TargetOpcode::G_CTPOP: 1031 if (TypeIdx == 1) 1032 switch (MI.getOpcode()) { 1033 case TargetOpcode::G_CTLZ: 1034 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1035 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 1036 case TargetOpcode::G_CTTZ: 1037 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1038 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 1039 case TargetOpcode::G_CTPOP: 1040 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 1041 default: 1042 return UnableToLegalize; 1043 } 1044 1045 Observer.changingInstr(MI); 1046 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1047 Observer.changedInstr(MI); 1048 return Legalized; 1049 case TargetOpcode::G_INTTOPTR: 1050 if (TypeIdx != 1) 1051 return UnableToLegalize; 1052 1053 Observer.changingInstr(MI); 1054 narrowScalarSrc(MI, NarrowTy, 1); 1055 Observer.changedInstr(MI); 1056 return Legalized; 1057 case TargetOpcode::G_PTRTOINT: 1058 if (TypeIdx != 0) 1059 return UnableToLegalize; 1060 1061 Observer.changingInstr(MI); 1062 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1063 Observer.changedInstr(MI); 1064 return Legalized; 1065 case TargetOpcode::G_PHI: { 1066 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1067 // NarrowSize. 1068 if (SizeOp0 % NarrowSize != 0) 1069 return UnableToLegalize; 1070 1071 unsigned NumParts = SizeOp0 / NarrowSize; 1072 SmallVector<Register, 2> DstRegs(NumParts); 1073 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1074 Observer.changingInstr(MI); 1075 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1076 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1077 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1078 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1079 SrcRegs[i / 2]); 1080 } 1081 MachineBasicBlock &MBB = *MI.getParent(); 1082 MIRBuilder.setInsertPt(MBB, MI); 1083 for (unsigned i = 0; i < NumParts; ++i) { 1084 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1085 MachineInstrBuilder MIB = 1086 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1087 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1088 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1089 } 1090 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1091 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1092 Observer.changedInstr(MI); 1093 MI.eraseFromParent(); 1094 return Legalized; 1095 } 1096 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1097 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1098 if (TypeIdx != 2) 1099 return UnableToLegalize; 1100 1101 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1102 Observer.changingInstr(MI); 1103 narrowScalarSrc(MI, NarrowTy, OpIdx); 1104 Observer.changedInstr(MI); 1105 return Legalized; 1106 } 1107 case TargetOpcode::G_ICMP: { 1108 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1109 if (NarrowSize * 2 != SrcSize) 1110 return UnableToLegalize; 1111 1112 Observer.changingInstr(MI); 1113 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1114 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1115 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1116 1117 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1118 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1119 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1120 1121 CmpInst::Predicate Pred = 1122 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1123 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1124 1125 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1126 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1127 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1128 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1129 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1130 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1131 } else { 1132 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1133 MachineInstrBuilder CmpHEQ = 1134 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1135 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1136 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1137 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1138 } 1139 Observer.changedInstr(MI); 1140 MI.eraseFromParent(); 1141 return Legalized; 1142 } 1143 case TargetOpcode::G_SEXT_INREG: { 1144 if (TypeIdx != 0) 1145 return UnableToLegalize; 1146 1147 int64_t SizeInBits = MI.getOperand(2).getImm(); 1148 1149 // So long as the new type has more bits than the bits we're extending we 1150 // don't need to break it apart. 1151 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1152 Observer.changingInstr(MI); 1153 // We don't lose any non-extension bits by truncating the src and 1154 // sign-extending the dst. 1155 MachineOperand &MO1 = MI.getOperand(1); 1156 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1157 MO1.setReg(TruncMIB.getReg(0)); 1158 1159 MachineOperand &MO2 = MI.getOperand(0); 1160 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1161 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1162 MIRBuilder.buildSExt(MO2, DstExt); 1163 MO2.setReg(DstExt); 1164 Observer.changedInstr(MI); 1165 return Legalized; 1166 } 1167 1168 // Break it apart. Components below the extension point are unmodified. The 1169 // component containing the extension point becomes a narrower SEXT_INREG. 1170 // Components above it are ashr'd from the component containing the 1171 // extension point. 1172 if (SizeOp0 % NarrowSize != 0) 1173 return UnableToLegalize; 1174 int NumParts = SizeOp0 / NarrowSize; 1175 1176 // List the registers where the destination will be scattered. 1177 SmallVector<Register, 2> DstRegs; 1178 // List the registers where the source will be split. 1179 SmallVector<Register, 2> SrcRegs; 1180 1181 // Create all the temporary registers. 1182 for (int i = 0; i < NumParts; ++i) { 1183 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1184 1185 SrcRegs.push_back(SrcReg); 1186 } 1187 1188 // Explode the big arguments into smaller chunks. 1189 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1190 1191 Register AshrCstReg = 1192 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1193 .getReg(0); 1194 Register FullExtensionReg = 0; 1195 Register PartialExtensionReg = 0; 1196 1197 // Do the operation on each small part. 1198 for (int i = 0; i < NumParts; ++i) { 1199 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1200 DstRegs.push_back(SrcRegs[i]); 1201 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1202 assert(PartialExtensionReg && 1203 "Expected to visit partial extension before full"); 1204 if (FullExtensionReg) { 1205 DstRegs.push_back(FullExtensionReg); 1206 continue; 1207 } 1208 DstRegs.push_back( 1209 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1210 .getReg(0)); 1211 FullExtensionReg = DstRegs.back(); 1212 } else { 1213 DstRegs.push_back( 1214 MIRBuilder 1215 .buildInstr( 1216 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1217 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1218 .getReg(0)); 1219 PartialExtensionReg = DstRegs.back(); 1220 } 1221 } 1222 1223 // Gather the destination registers into the final destination. 1224 Register DstReg = MI.getOperand(0).getReg(); 1225 MIRBuilder.buildMerge(DstReg, DstRegs); 1226 MI.eraseFromParent(); 1227 return Legalized; 1228 } 1229 case TargetOpcode::G_BSWAP: 1230 case TargetOpcode::G_BITREVERSE: { 1231 if (SizeOp0 % NarrowSize != 0) 1232 return UnableToLegalize; 1233 1234 Observer.changingInstr(MI); 1235 SmallVector<Register, 2> SrcRegs, DstRegs; 1236 unsigned NumParts = SizeOp0 / NarrowSize; 1237 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1238 1239 for (unsigned i = 0; i < NumParts; ++i) { 1240 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1241 {SrcRegs[NumParts - 1 - i]}); 1242 DstRegs.push_back(DstPart.getReg(0)); 1243 } 1244 1245 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1246 1247 Observer.changedInstr(MI); 1248 MI.eraseFromParent(); 1249 return Legalized; 1250 } 1251 case TargetOpcode::G_PTR_ADD: 1252 case TargetOpcode::G_PTRMASK: { 1253 if (TypeIdx != 1) 1254 return UnableToLegalize; 1255 Observer.changingInstr(MI); 1256 narrowScalarSrc(MI, NarrowTy, 2); 1257 Observer.changedInstr(MI); 1258 return Legalized; 1259 } 1260 case TargetOpcode::G_FPTOUI: { 1261 if (TypeIdx != 0) 1262 return UnableToLegalize; 1263 Observer.changingInstr(MI); 1264 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1265 Observer.changedInstr(MI); 1266 return Legalized; 1267 } 1268 case TargetOpcode::G_FPTOSI: { 1269 if (TypeIdx != 0) 1270 return UnableToLegalize; 1271 Observer.changingInstr(MI); 1272 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT); 1273 Observer.changedInstr(MI); 1274 return Legalized; 1275 } 1276 case TargetOpcode::G_FPEXT: 1277 if (TypeIdx != 0) 1278 return UnableToLegalize; 1279 Observer.changingInstr(MI); 1280 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1281 Observer.changedInstr(MI); 1282 return Legalized; 1283 } 1284 } 1285 1286 Register LegalizerHelper::coerceToScalar(Register Val) { 1287 LLT Ty = MRI.getType(Val); 1288 if (Ty.isScalar()) 1289 return Val; 1290 1291 const DataLayout &DL = MIRBuilder.getDataLayout(); 1292 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1293 if (Ty.isPointer()) { 1294 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1295 return Register(); 1296 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1297 } 1298 1299 Register NewVal = Val; 1300 1301 assert(Ty.isVector()); 1302 LLT EltTy = Ty.getElementType(); 1303 if (EltTy.isPointer()) 1304 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1305 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1306 } 1307 1308 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1309 unsigned OpIdx, unsigned ExtOpcode) { 1310 MachineOperand &MO = MI.getOperand(OpIdx); 1311 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1312 MO.setReg(ExtB.getReg(0)); 1313 } 1314 1315 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1316 unsigned OpIdx) { 1317 MachineOperand &MO = MI.getOperand(OpIdx); 1318 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1319 MO.setReg(ExtB.getReg(0)); 1320 } 1321 1322 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1323 unsigned OpIdx, unsigned TruncOpcode) { 1324 MachineOperand &MO = MI.getOperand(OpIdx); 1325 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1326 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1327 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1328 MO.setReg(DstExt); 1329 } 1330 1331 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1332 unsigned OpIdx, unsigned ExtOpcode) { 1333 MachineOperand &MO = MI.getOperand(OpIdx); 1334 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1335 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1336 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1337 MO.setReg(DstTrunc); 1338 } 1339 1340 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1341 unsigned OpIdx) { 1342 MachineOperand &MO = MI.getOperand(OpIdx); 1343 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1344 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1345 } 1346 1347 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1348 unsigned OpIdx) { 1349 MachineOperand &MO = MI.getOperand(OpIdx); 1350 1351 LLT OldTy = MRI.getType(MO.getReg()); 1352 unsigned OldElts = OldTy.getNumElements(); 1353 unsigned NewElts = MoreTy.getNumElements(); 1354 1355 unsigned NumParts = NewElts / OldElts; 1356 1357 // Use concat_vectors if the result is a multiple of the number of elements. 1358 if (NumParts * OldElts == NewElts) { 1359 SmallVector<Register, 8> Parts; 1360 Parts.push_back(MO.getReg()); 1361 1362 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1363 for (unsigned I = 1; I != NumParts; ++I) 1364 Parts.push_back(ImpDef); 1365 1366 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1367 MO.setReg(Concat.getReg(0)); 1368 return; 1369 } 1370 1371 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1372 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1373 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1374 MO.setReg(MoreReg); 1375 } 1376 1377 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1378 MachineOperand &Op = MI.getOperand(OpIdx); 1379 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1380 } 1381 1382 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1383 MachineOperand &MO = MI.getOperand(OpIdx); 1384 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1385 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1386 MIRBuilder.buildBitcast(MO, CastDst); 1387 MO.setReg(CastDst); 1388 } 1389 1390 LegalizerHelper::LegalizeResult 1391 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1392 LLT WideTy) { 1393 if (TypeIdx != 1) 1394 return UnableToLegalize; 1395 1396 Register DstReg = MI.getOperand(0).getReg(); 1397 LLT DstTy = MRI.getType(DstReg); 1398 if (DstTy.isVector()) 1399 return UnableToLegalize; 1400 1401 Register Src1 = MI.getOperand(1).getReg(); 1402 LLT SrcTy = MRI.getType(Src1); 1403 const int DstSize = DstTy.getSizeInBits(); 1404 const int SrcSize = SrcTy.getSizeInBits(); 1405 const int WideSize = WideTy.getSizeInBits(); 1406 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1407 1408 unsigned NumOps = MI.getNumOperands(); 1409 unsigned NumSrc = MI.getNumOperands() - 1; 1410 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1411 1412 if (WideSize >= DstSize) { 1413 // Directly pack the bits in the target type. 1414 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1415 1416 for (unsigned I = 2; I != NumOps; ++I) { 1417 const unsigned Offset = (I - 1) * PartSize; 1418 1419 Register SrcReg = MI.getOperand(I).getReg(); 1420 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1421 1422 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1423 1424 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1425 MRI.createGenericVirtualRegister(WideTy); 1426 1427 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1428 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1429 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1430 ResultReg = NextResult; 1431 } 1432 1433 if (WideSize > DstSize) 1434 MIRBuilder.buildTrunc(DstReg, ResultReg); 1435 else if (DstTy.isPointer()) 1436 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1437 1438 MI.eraseFromParent(); 1439 return Legalized; 1440 } 1441 1442 // Unmerge the original values to the GCD type, and recombine to the next 1443 // multiple greater than the original type. 1444 // 1445 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1446 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1447 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1448 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1449 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1450 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1451 // %12:_(s12) = G_MERGE_VALUES %10, %11 1452 // 1453 // Padding with undef if necessary: 1454 // 1455 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1456 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1457 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1458 // %7:_(s2) = G_IMPLICIT_DEF 1459 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1460 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1461 // %10:_(s12) = G_MERGE_VALUES %8, %9 1462 1463 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1464 LLT GCDTy = LLT::scalar(GCD); 1465 1466 SmallVector<Register, 8> Parts; 1467 SmallVector<Register, 8> NewMergeRegs; 1468 SmallVector<Register, 8> Unmerges; 1469 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1470 1471 // Decompose the original operands if they don't evenly divide. 1472 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1473 Register SrcReg = MI.getOperand(I).getReg(); 1474 if (GCD == SrcSize) { 1475 Unmerges.push_back(SrcReg); 1476 } else { 1477 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1478 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1479 Unmerges.push_back(Unmerge.getReg(J)); 1480 } 1481 } 1482 1483 // Pad with undef to the next size that is a multiple of the requested size. 1484 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1485 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1486 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1487 Unmerges.push_back(UndefReg); 1488 } 1489 1490 const int PartsPerGCD = WideSize / GCD; 1491 1492 // Build merges of each piece. 1493 ArrayRef<Register> Slicer(Unmerges); 1494 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1495 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1496 NewMergeRegs.push_back(Merge.getReg(0)); 1497 } 1498 1499 // A truncate may be necessary if the requested type doesn't evenly divide the 1500 // original result type. 1501 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1502 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1503 } else { 1504 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1505 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1506 } 1507 1508 MI.eraseFromParent(); 1509 return Legalized; 1510 } 1511 1512 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1513 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1514 LLT OrigTy = MRI.getType(OrigReg); 1515 LLT LCMTy = getLCMType(WideTy, OrigTy); 1516 1517 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1518 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1519 1520 Register UnmergeSrc = WideReg; 1521 1522 // Create a merge to the LCM type, padding with undef 1523 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1524 // => 1525 // %1:_(<4 x s32>) = G_FOO 1526 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1527 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1528 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1529 if (NumMergeParts > 1) { 1530 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1531 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1532 MergeParts[0] = WideReg; 1533 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1534 } 1535 1536 // Unmerge to the original register and pad with dead defs. 1537 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1538 UnmergeResults[0] = OrigReg; 1539 for (int I = 1; I != NumUnmergeParts; ++I) 1540 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1541 1542 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1543 return WideReg; 1544 } 1545 1546 LegalizerHelper::LegalizeResult 1547 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1548 LLT WideTy) { 1549 if (TypeIdx != 0) 1550 return UnableToLegalize; 1551 1552 int NumDst = MI.getNumOperands() - 1; 1553 Register SrcReg = MI.getOperand(NumDst).getReg(); 1554 LLT SrcTy = MRI.getType(SrcReg); 1555 if (SrcTy.isVector()) 1556 return UnableToLegalize; 1557 1558 Register Dst0Reg = MI.getOperand(0).getReg(); 1559 LLT DstTy = MRI.getType(Dst0Reg); 1560 if (!DstTy.isScalar()) 1561 return UnableToLegalize; 1562 1563 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1564 if (SrcTy.isPointer()) { 1565 const DataLayout &DL = MIRBuilder.getDataLayout(); 1566 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1567 LLVM_DEBUG( 1568 dbgs() << "Not casting non-integral address space integer\n"); 1569 return UnableToLegalize; 1570 } 1571 1572 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1573 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1574 } 1575 1576 // Widen SrcTy to WideTy. This does not affect the result, but since the 1577 // user requested this size, it is probably better handled than SrcTy and 1578 // should reduce the total number of legalization artifacts 1579 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1580 SrcTy = WideTy; 1581 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1582 } 1583 1584 // Theres no unmerge type to target. Directly extract the bits from the 1585 // source type 1586 unsigned DstSize = DstTy.getSizeInBits(); 1587 1588 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1589 for (int I = 1; I != NumDst; ++I) { 1590 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1591 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1592 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1593 } 1594 1595 MI.eraseFromParent(); 1596 return Legalized; 1597 } 1598 1599 // Extend the source to a wider type. 1600 LLT LCMTy = getLCMType(SrcTy, WideTy); 1601 1602 Register WideSrc = SrcReg; 1603 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1604 // TODO: If this is an integral address space, cast to integer and anyext. 1605 if (SrcTy.isPointer()) { 1606 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1607 return UnableToLegalize; 1608 } 1609 1610 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1611 } 1612 1613 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1614 1615 // Create a sequence of unmerges and merges to the original results. Since we 1616 // may have widened the source, we will need to pad the results with dead defs 1617 // to cover the source register. 1618 // e.g. widen s48 to s64: 1619 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1620 // 1621 // => 1622 // %4:_(s192) = G_ANYEXT %0:_(s96) 1623 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1624 // ; unpack to GCD type, with extra dead defs 1625 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1626 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1627 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1628 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1629 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1630 const LLT GCDTy = getGCDType(WideTy, DstTy); 1631 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1632 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1633 1634 // Directly unmerge to the destination without going through a GCD type 1635 // if possible 1636 if (PartsPerRemerge == 1) { 1637 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1638 1639 for (int I = 0; I != NumUnmerge; ++I) { 1640 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1641 1642 for (int J = 0; J != PartsPerUnmerge; ++J) { 1643 int Idx = I * PartsPerUnmerge + J; 1644 if (Idx < NumDst) 1645 MIB.addDef(MI.getOperand(Idx).getReg()); 1646 else { 1647 // Create dead def for excess components. 1648 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1649 } 1650 } 1651 1652 MIB.addUse(Unmerge.getReg(I)); 1653 } 1654 } else { 1655 SmallVector<Register, 16> Parts; 1656 for (int J = 0; J != NumUnmerge; ++J) 1657 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1658 1659 SmallVector<Register, 8> RemergeParts; 1660 for (int I = 0; I != NumDst; ++I) { 1661 for (int J = 0; J < PartsPerRemerge; ++J) { 1662 const int Idx = I * PartsPerRemerge + J; 1663 RemergeParts.emplace_back(Parts[Idx]); 1664 } 1665 1666 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1667 RemergeParts.clear(); 1668 } 1669 } 1670 1671 MI.eraseFromParent(); 1672 return Legalized; 1673 } 1674 1675 LegalizerHelper::LegalizeResult 1676 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1677 LLT WideTy) { 1678 Register DstReg = MI.getOperand(0).getReg(); 1679 Register SrcReg = MI.getOperand(1).getReg(); 1680 LLT SrcTy = MRI.getType(SrcReg); 1681 1682 LLT DstTy = MRI.getType(DstReg); 1683 unsigned Offset = MI.getOperand(2).getImm(); 1684 1685 if (TypeIdx == 0) { 1686 if (SrcTy.isVector() || DstTy.isVector()) 1687 return UnableToLegalize; 1688 1689 SrcOp Src(SrcReg); 1690 if (SrcTy.isPointer()) { 1691 // Extracts from pointers can be handled only if they are really just 1692 // simple integers. 1693 const DataLayout &DL = MIRBuilder.getDataLayout(); 1694 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1695 return UnableToLegalize; 1696 1697 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1698 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1699 SrcTy = SrcAsIntTy; 1700 } 1701 1702 if (DstTy.isPointer()) 1703 return UnableToLegalize; 1704 1705 if (Offset == 0) { 1706 // Avoid a shift in the degenerate case. 1707 MIRBuilder.buildTrunc(DstReg, 1708 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1709 MI.eraseFromParent(); 1710 return Legalized; 1711 } 1712 1713 // Do a shift in the source type. 1714 LLT ShiftTy = SrcTy; 1715 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1716 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1717 ShiftTy = WideTy; 1718 } 1719 1720 auto LShr = MIRBuilder.buildLShr( 1721 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1722 MIRBuilder.buildTrunc(DstReg, LShr); 1723 MI.eraseFromParent(); 1724 return Legalized; 1725 } 1726 1727 if (SrcTy.isScalar()) { 1728 Observer.changingInstr(MI); 1729 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1730 Observer.changedInstr(MI); 1731 return Legalized; 1732 } 1733 1734 if (!SrcTy.isVector()) 1735 return UnableToLegalize; 1736 1737 if (DstTy != SrcTy.getElementType()) 1738 return UnableToLegalize; 1739 1740 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1741 return UnableToLegalize; 1742 1743 Observer.changingInstr(MI); 1744 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1745 1746 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1747 Offset); 1748 widenScalarDst(MI, WideTy.getScalarType(), 0); 1749 Observer.changedInstr(MI); 1750 return Legalized; 1751 } 1752 1753 LegalizerHelper::LegalizeResult 1754 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1755 LLT WideTy) { 1756 if (TypeIdx != 0 || WideTy.isVector()) 1757 return UnableToLegalize; 1758 Observer.changingInstr(MI); 1759 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1760 widenScalarDst(MI, WideTy); 1761 Observer.changedInstr(MI); 1762 return Legalized; 1763 } 1764 1765 LegalizerHelper::LegalizeResult 1766 LegalizerHelper::widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx, 1767 LLT WideTy) { 1768 if (TypeIdx == 1) 1769 return UnableToLegalize; // TODO 1770 unsigned Op = MI.getOpcode(); 1771 unsigned Opcode = Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_SADDO 1772 ? TargetOpcode::G_ADD 1773 : TargetOpcode::G_SUB; 1774 unsigned ExtOpcode = 1775 Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_USUBO 1776 ? TargetOpcode::G_ZEXT 1777 : TargetOpcode::G_SEXT; 1778 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1779 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1780 // Do the arithmetic in the larger type. 1781 auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}); 1782 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1783 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1784 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1785 // There is no overflow if the ExtOp is the same as NewOp. 1786 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1787 // Now trunc the NewOp to the original result. 1788 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1789 MI.eraseFromParent(); 1790 return Legalized; 1791 } 1792 1793 LegalizerHelper::LegalizeResult 1794 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1795 LLT WideTy) { 1796 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1797 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1798 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1799 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1800 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1801 // We can convert this to: 1802 // 1. Any extend iN to iM 1803 // 2. SHL by M-N 1804 // 3. [US][ADD|SUB|SHL]SAT 1805 // 4. L/ASHR by M-N 1806 // 1807 // It may be more efficient to lower this to a min and a max operation in 1808 // the higher precision arithmetic if the promoted operation isn't legal, 1809 // but this decision is up to the target's lowering request. 1810 Register DstReg = MI.getOperand(0).getReg(); 1811 1812 unsigned NewBits = WideTy.getScalarSizeInBits(); 1813 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1814 1815 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1816 // must not left shift the RHS to preserve the shift amount. 1817 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1818 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1819 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1820 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1821 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1822 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1823 1824 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1825 {ShiftL, ShiftR}, MI.getFlags()); 1826 1827 // Use a shift that will preserve the number of sign bits when the trunc is 1828 // folded away. 1829 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1830 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1831 1832 MIRBuilder.buildTrunc(DstReg, Result); 1833 MI.eraseFromParent(); 1834 return Legalized; 1835 } 1836 1837 LegalizerHelper::LegalizeResult 1838 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1839 switch (MI.getOpcode()) { 1840 default: 1841 return UnableToLegalize; 1842 case TargetOpcode::G_EXTRACT: 1843 return widenScalarExtract(MI, TypeIdx, WideTy); 1844 case TargetOpcode::G_INSERT: 1845 return widenScalarInsert(MI, TypeIdx, WideTy); 1846 case TargetOpcode::G_MERGE_VALUES: 1847 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1848 case TargetOpcode::G_UNMERGE_VALUES: 1849 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1850 case TargetOpcode::G_SADDO: 1851 case TargetOpcode::G_SSUBO: 1852 case TargetOpcode::G_UADDO: 1853 case TargetOpcode::G_USUBO: 1854 return widenScalarAddoSubo(MI, TypeIdx, WideTy); 1855 case TargetOpcode::G_SADDSAT: 1856 case TargetOpcode::G_SSUBSAT: 1857 case TargetOpcode::G_SSHLSAT: 1858 case TargetOpcode::G_UADDSAT: 1859 case TargetOpcode::G_USUBSAT: 1860 case TargetOpcode::G_USHLSAT: 1861 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1862 case TargetOpcode::G_CTTZ: 1863 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1864 case TargetOpcode::G_CTLZ: 1865 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1866 case TargetOpcode::G_CTPOP: { 1867 if (TypeIdx == 0) { 1868 Observer.changingInstr(MI); 1869 widenScalarDst(MI, WideTy, 0); 1870 Observer.changedInstr(MI); 1871 return Legalized; 1872 } 1873 1874 Register SrcReg = MI.getOperand(1).getReg(); 1875 1876 // First ZEXT the input. 1877 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1878 LLT CurTy = MRI.getType(SrcReg); 1879 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1880 // The count is the same in the larger type except if the original 1881 // value was zero. This can be handled by setting the bit just off 1882 // the top of the original type. 1883 auto TopBit = 1884 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1885 MIBSrc = MIRBuilder.buildOr( 1886 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1887 } 1888 1889 // Perform the operation at the larger size. 1890 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1891 // This is already the correct result for CTPOP and CTTZs 1892 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1893 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1894 // The correct result is NewOp - (Difference in widety and current ty). 1895 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1896 MIBNewOp = MIRBuilder.buildSub( 1897 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1898 } 1899 1900 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1901 MI.eraseFromParent(); 1902 return Legalized; 1903 } 1904 case TargetOpcode::G_BSWAP: { 1905 Observer.changingInstr(MI); 1906 Register DstReg = MI.getOperand(0).getReg(); 1907 1908 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1909 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1910 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1911 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1912 1913 MI.getOperand(0).setReg(DstExt); 1914 1915 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1916 1917 LLT Ty = MRI.getType(DstReg); 1918 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1919 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1920 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1921 1922 MIRBuilder.buildTrunc(DstReg, ShrReg); 1923 Observer.changedInstr(MI); 1924 return Legalized; 1925 } 1926 case TargetOpcode::G_BITREVERSE: { 1927 Observer.changingInstr(MI); 1928 1929 Register DstReg = MI.getOperand(0).getReg(); 1930 LLT Ty = MRI.getType(DstReg); 1931 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1932 1933 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1934 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1935 MI.getOperand(0).setReg(DstExt); 1936 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1937 1938 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 1939 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1940 MIRBuilder.buildTrunc(DstReg, Shift); 1941 Observer.changedInstr(MI); 1942 return Legalized; 1943 } 1944 case TargetOpcode::G_FREEZE: 1945 Observer.changingInstr(MI); 1946 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1947 widenScalarDst(MI, WideTy); 1948 Observer.changedInstr(MI); 1949 return Legalized; 1950 1951 case TargetOpcode::G_ADD: 1952 case TargetOpcode::G_AND: 1953 case TargetOpcode::G_MUL: 1954 case TargetOpcode::G_OR: 1955 case TargetOpcode::G_XOR: 1956 case TargetOpcode::G_SUB: 1957 // Perform operation at larger width (any extension is fines here, high bits 1958 // don't affect the result) and then truncate the result back to the 1959 // original type. 1960 Observer.changingInstr(MI); 1961 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1962 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 1963 widenScalarDst(MI, WideTy); 1964 Observer.changedInstr(MI); 1965 return Legalized; 1966 1967 case TargetOpcode::G_SHL: 1968 Observer.changingInstr(MI); 1969 1970 if (TypeIdx == 0) { 1971 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1972 widenScalarDst(MI, WideTy); 1973 } else { 1974 assert(TypeIdx == 1); 1975 // The "number of bits to shift" operand must preserve its value as an 1976 // unsigned integer: 1977 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 1978 } 1979 1980 Observer.changedInstr(MI); 1981 return Legalized; 1982 1983 case TargetOpcode::G_SDIV: 1984 case TargetOpcode::G_SREM: 1985 case TargetOpcode::G_SMIN: 1986 case TargetOpcode::G_SMAX: 1987 Observer.changingInstr(MI); 1988 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 1989 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 1990 widenScalarDst(MI, WideTy); 1991 Observer.changedInstr(MI); 1992 return Legalized; 1993 1994 case TargetOpcode::G_ASHR: 1995 case TargetOpcode::G_LSHR: 1996 Observer.changingInstr(MI); 1997 1998 if (TypeIdx == 0) { 1999 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2000 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2001 2002 widenScalarSrc(MI, WideTy, 1, CvtOp); 2003 widenScalarDst(MI, WideTy); 2004 } else { 2005 assert(TypeIdx == 1); 2006 // The "number of bits to shift" operand must preserve its value as an 2007 // unsigned integer: 2008 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2009 } 2010 2011 Observer.changedInstr(MI); 2012 return Legalized; 2013 case TargetOpcode::G_UDIV: 2014 case TargetOpcode::G_UREM: 2015 case TargetOpcode::G_UMIN: 2016 case TargetOpcode::G_UMAX: 2017 Observer.changingInstr(MI); 2018 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2019 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2020 widenScalarDst(MI, WideTy); 2021 Observer.changedInstr(MI); 2022 return Legalized; 2023 2024 case TargetOpcode::G_SELECT: 2025 Observer.changingInstr(MI); 2026 if (TypeIdx == 0) { 2027 // Perform operation at larger width (any extension is fine here, high 2028 // bits don't affect the result) and then truncate the result back to the 2029 // original type. 2030 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2031 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2032 widenScalarDst(MI, WideTy); 2033 } else { 2034 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2035 // Explicit extension is required here since high bits affect the result. 2036 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2037 } 2038 Observer.changedInstr(MI); 2039 return Legalized; 2040 2041 case TargetOpcode::G_FPTOSI: 2042 case TargetOpcode::G_FPTOUI: 2043 Observer.changingInstr(MI); 2044 2045 if (TypeIdx == 0) 2046 widenScalarDst(MI, WideTy); 2047 else 2048 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2049 2050 Observer.changedInstr(MI); 2051 return Legalized; 2052 case TargetOpcode::G_SITOFP: 2053 Observer.changingInstr(MI); 2054 2055 if (TypeIdx == 0) 2056 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2057 else 2058 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2059 2060 Observer.changedInstr(MI); 2061 return Legalized; 2062 case TargetOpcode::G_UITOFP: 2063 Observer.changingInstr(MI); 2064 2065 if (TypeIdx == 0) 2066 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2067 else 2068 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2069 2070 Observer.changedInstr(MI); 2071 return Legalized; 2072 case TargetOpcode::G_LOAD: 2073 case TargetOpcode::G_SEXTLOAD: 2074 case TargetOpcode::G_ZEXTLOAD: 2075 Observer.changingInstr(MI); 2076 widenScalarDst(MI, WideTy); 2077 Observer.changedInstr(MI); 2078 return Legalized; 2079 2080 case TargetOpcode::G_STORE: { 2081 if (TypeIdx != 0) 2082 return UnableToLegalize; 2083 2084 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2085 if (!Ty.isScalar()) 2086 return UnableToLegalize; 2087 2088 Observer.changingInstr(MI); 2089 2090 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2091 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2092 widenScalarSrc(MI, WideTy, 0, ExtType); 2093 2094 Observer.changedInstr(MI); 2095 return Legalized; 2096 } 2097 case TargetOpcode::G_CONSTANT: { 2098 MachineOperand &SrcMO = MI.getOperand(1); 2099 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2100 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2101 MRI.getType(MI.getOperand(0).getReg())); 2102 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2103 ExtOpc == TargetOpcode::G_ANYEXT) && 2104 "Illegal Extend"); 2105 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2106 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2107 ? SrcVal.sext(WideTy.getSizeInBits()) 2108 : SrcVal.zext(WideTy.getSizeInBits()); 2109 Observer.changingInstr(MI); 2110 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2111 2112 widenScalarDst(MI, WideTy); 2113 Observer.changedInstr(MI); 2114 return Legalized; 2115 } 2116 case TargetOpcode::G_FCONSTANT: { 2117 MachineOperand &SrcMO = MI.getOperand(1); 2118 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2119 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2120 bool LosesInfo; 2121 switch (WideTy.getSizeInBits()) { 2122 case 32: 2123 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2124 &LosesInfo); 2125 break; 2126 case 64: 2127 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2128 &LosesInfo); 2129 break; 2130 default: 2131 return UnableToLegalize; 2132 } 2133 2134 assert(!LosesInfo && "extend should always be lossless"); 2135 2136 Observer.changingInstr(MI); 2137 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2138 2139 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2140 Observer.changedInstr(MI); 2141 return Legalized; 2142 } 2143 case TargetOpcode::G_IMPLICIT_DEF: { 2144 Observer.changingInstr(MI); 2145 widenScalarDst(MI, WideTy); 2146 Observer.changedInstr(MI); 2147 return Legalized; 2148 } 2149 case TargetOpcode::G_BRCOND: 2150 Observer.changingInstr(MI); 2151 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2152 Observer.changedInstr(MI); 2153 return Legalized; 2154 2155 case TargetOpcode::G_FCMP: 2156 Observer.changingInstr(MI); 2157 if (TypeIdx == 0) 2158 widenScalarDst(MI, WideTy); 2159 else { 2160 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2161 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2162 } 2163 Observer.changedInstr(MI); 2164 return Legalized; 2165 2166 case TargetOpcode::G_ICMP: 2167 Observer.changingInstr(MI); 2168 if (TypeIdx == 0) 2169 widenScalarDst(MI, WideTy); 2170 else { 2171 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2172 MI.getOperand(1).getPredicate())) 2173 ? TargetOpcode::G_SEXT 2174 : TargetOpcode::G_ZEXT; 2175 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2176 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2177 } 2178 Observer.changedInstr(MI); 2179 return Legalized; 2180 2181 case TargetOpcode::G_PTR_ADD: 2182 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2183 Observer.changingInstr(MI); 2184 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2185 Observer.changedInstr(MI); 2186 return Legalized; 2187 2188 case TargetOpcode::G_PHI: { 2189 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2190 2191 Observer.changingInstr(MI); 2192 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2193 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2194 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2195 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2196 } 2197 2198 MachineBasicBlock &MBB = *MI.getParent(); 2199 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2200 widenScalarDst(MI, WideTy); 2201 Observer.changedInstr(MI); 2202 return Legalized; 2203 } 2204 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2205 if (TypeIdx == 0) { 2206 Register VecReg = MI.getOperand(1).getReg(); 2207 LLT VecTy = MRI.getType(VecReg); 2208 Observer.changingInstr(MI); 2209 2210 widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(), 2211 WideTy.getSizeInBits()), 2212 1, TargetOpcode::G_SEXT); 2213 2214 widenScalarDst(MI, WideTy, 0); 2215 Observer.changedInstr(MI); 2216 return Legalized; 2217 } 2218 2219 if (TypeIdx != 2) 2220 return UnableToLegalize; 2221 Observer.changingInstr(MI); 2222 // TODO: Probably should be zext 2223 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2224 Observer.changedInstr(MI); 2225 return Legalized; 2226 } 2227 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2228 if (TypeIdx == 1) { 2229 Observer.changingInstr(MI); 2230 2231 Register VecReg = MI.getOperand(1).getReg(); 2232 LLT VecTy = MRI.getType(VecReg); 2233 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy); 2234 2235 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2236 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2237 widenScalarDst(MI, WideVecTy, 0); 2238 Observer.changedInstr(MI); 2239 return Legalized; 2240 } 2241 2242 if (TypeIdx == 2) { 2243 Observer.changingInstr(MI); 2244 // TODO: Probably should be zext 2245 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2246 Observer.changedInstr(MI); 2247 return Legalized; 2248 } 2249 2250 return UnableToLegalize; 2251 } 2252 case TargetOpcode::G_FADD: 2253 case TargetOpcode::G_FMUL: 2254 case TargetOpcode::G_FSUB: 2255 case TargetOpcode::G_FMA: 2256 case TargetOpcode::G_FMAD: 2257 case TargetOpcode::G_FNEG: 2258 case TargetOpcode::G_FABS: 2259 case TargetOpcode::G_FCANONICALIZE: 2260 case TargetOpcode::G_FMINNUM: 2261 case TargetOpcode::G_FMAXNUM: 2262 case TargetOpcode::G_FMINNUM_IEEE: 2263 case TargetOpcode::G_FMAXNUM_IEEE: 2264 case TargetOpcode::G_FMINIMUM: 2265 case TargetOpcode::G_FMAXIMUM: 2266 case TargetOpcode::G_FDIV: 2267 case TargetOpcode::G_FREM: 2268 case TargetOpcode::G_FCEIL: 2269 case TargetOpcode::G_FFLOOR: 2270 case TargetOpcode::G_FCOS: 2271 case TargetOpcode::G_FSIN: 2272 case TargetOpcode::G_FLOG10: 2273 case TargetOpcode::G_FLOG: 2274 case TargetOpcode::G_FLOG2: 2275 case TargetOpcode::G_FRINT: 2276 case TargetOpcode::G_FNEARBYINT: 2277 case TargetOpcode::G_FSQRT: 2278 case TargetOpcode::G_FEXP: 2279 case TargetOpcode::G_FEXP2: 2280 case TargetOpcode::G_FPOW: 2281 case TargetOpcode::G_INTRINSIC_TRUNC: 2282 case TargetOpcode::G_INTRINSIC_ROUND: 2283 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2284 assert(TypeIdx == 0); 2285 Observer.changingInstr(MI); 2286 2287 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2288 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2289 2290 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2291 Observer.changedInstr(MI); 2292 return Legalized; 2293 case TargetOpcode::G_FPOWI: { 2294 if (TypeIdx != 0) 2295 return UnableToLegalize; 2296 Observer.changingInstr(MI); 2297 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2298 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2299 Observer.changedInstr(MI); 2300 return Legalized; 2301 } 2302 case TargetOpcode::G_INTTOPTR: 2303 if (TypeIdx != 1) 2304 return UnableToLegalize; 2305 2306 Observer.changingInstr(MI); 2307 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2308 Observer.changedInstr(MI); 2309 return Legalized; 2310 case TargetOpcode::G_PTRTOINT: 2311 if (TypeIdx != 0) 2312 return UnableToLegalize; 2313 2314 Observer.changingInstr(MI); 2315 widenScalarDst(MI, WideTy, 0); 2316 Observer.changedInstr(MI); 2317 return Legalized; 2318 case TargetOpcode::G_BUILD_VECTOR: { 2319 Observer.changingInstr(MI); 2320 2321 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2322 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2323 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2324 2325 // Avoid changing the result vector type if the source element type was 2326 // requested. 2327 if (TypeIdx == 1) { 2328 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2329 } else { 2330 widenScalarDst(MI, WideTy, 0); 2331 } 2332 2333 Observer.changedInstr(MI); 2334 return Legalized; 2335 } 2336 case TargetOpcode::G_SEXT_INREG: 2337 if (TypeIdx != 0) 2338 return UnableToLegalize; 2339 2340 Observer.changingInstr(MI); 2341 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2342 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2343 Observer.changedInstr(MI); 2344 return Legalized; 2345 case TargetOpcode::G_PTRMASK: { 2346 if (TypeIdx != 1) 2347 return UnableToLegalize; 2348 Observer.changingInstr(MI); 2349 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2350 Observer.changedInstr(MI); 2351 return Legalized; 2352 } 2353 } 2354 } 2355 2356 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2357 MachineIRBuilder &B, Register Src, LLT Ty) { 2358 auto Unmerge = B.buildUnmerge(Ty, Src); 2359 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2360 Pieces.push_back(Unmerge.getReg(I)); 2361 } 2362 2363 LegalizerHelper::LegalizeResult 2364 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2365 Register Dst = MI.getOperand(0).getReg(); 2366 Register Src = MI.getOperand(1).getReg(); 2367 LLT DstTy = MRI.getType(Dst); 2368 LLT SrcTy = MRI.getType(Src); 2369 2370 if (SrcTy.isVector()) { 2371 LLT SrcEltTy = SrcTy.getElementType(); 2372 SmallVector<Register, 8> SrcRegs; 2373 2374 if (DstTy.isVector()) { 2375 int NumDstElt = DstTy.getNumElements(); 2376 int NumSrcElt = SrcTy.getNumElements(); 2377 2378 LLT DstEltTy = DstTy.getElementType(); 2379 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2380 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2381 2382 // If there's an element size mismatch, insert intermediate casts to match 2383 // the result element type. 2384 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2385 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2386 // 2387 // => 2388 // 2389 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2390 // %3:_(<2 x s8>) = G_BITCAST %2 2391 // %4:_(<2 x s8>) = G_BITCAST %3 2392 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2393 DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy); 2394 SrcPartTy = SrcEltTy; 2395 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2396 // 2397 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2398 // 2399 // => 2400 // 2401 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2402 // %3:_(s16) = G_BITCAST %2 2403 // %4:_(s16) = G_BITCAST %3 2404 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2405 SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy); 2406 DstCastTy = DstEltTy; 2407 } 2408 2409 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2410 for (Register &SrcReg : SrcRegs) 2411 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2412 } else 2413 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2414 2415 MIRBuilder.buildMerge(Dst, SrcRegs); 2416 MI.eraseFromParent(); 2417 return Legalized; 2418 } 2419 2420 if (DstTy.isVector()) { 2421 SmallVector<Register, 8> SrcRegs; 2422 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2423 MIRBuilder.buildMerge(Dst, SrcRegs); 2424 MI.eraseFromParent(); 2425 return Legalized; 2426 } 2427 2428 return UnableToLegalize; 2429 } 2430 2431 /// Figure out the bit offset into a register when coercing a vector index for 2432 /// the wide element type. This is only for the case when promoting vector to 2433 /// one with larger elements. 2434 // 2435 /// 2436 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2437 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2438 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2439 Register Idx, 2440 unsigned NewEltSize, 2441 unsigned OldEltSize) { 2442 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2443 LLT IdxTy = B.getMRI()->getType(Idx); 2444 2445 // Now figure out the amount we need to shift to get the target bits. 2446 auto OffsetMask = B.buildConstant( 2447 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2448 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2449 return B.buildShl(IdxTy, OffsetIdx, 2450 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2451 } 2452 2453 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2454 /// is casting to a vector with a smaller element size, perform multiple element 2455 /// extracts and merge the results. If this is coercing to a vector with larger 2456 /// elements, index the bitcasted vector and extract the target element with bit 2457 /// operations. This is intended to force the indexing in the native register 2458 /// size for architectures that can dynamically index the register file. 2459 LegalizerHelper::LegalizeResult 2460 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2461 LLT CastTy) { 2462 if (TypeIdx != 1) 2463 return UnableToLegalize; 2464 2465 Register Dst = MI.getOperand(0).getReg(); 2466 Register SrcVec = MI.getOperand(1).getReg(); 2467 Register Idx = MI.getOperand(2).getReg(); 2468 LLT SrcVecTy = MRI.getType(SrcVec); 2469 LLT IdxTy = MRI.getType(Idx); 2470 2471 LLT SrcEltTy = SrcVecTy.getElementType(); 2472 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2473 unsigned OldNumElts = SrcVecTy.getNumElements(); 2474 2475 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2476 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2477 2478 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2479 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2480 if (NewNumElts > OldNumElts) { 2481 // Decreasing the vector element size 2482 // 2483 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2484 // => 2485 // v4i32:castx = bitcast x:v2i64 2486 // 2487 // i64 = bitcast 2488 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2489 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2490 // 2491 if (NewNumElts % OldNumElts != 0) 2492 return UnableToLegalize; 2493 2494 // Type of the intermediate result vector. 2495 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2496 LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy); 2497 2498 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2499 2500 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2501 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2502 2503 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2504 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2505 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2506 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2507 NewOps[I] = Elt.getReg(0); 2508 } 2509 2510 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2511 MIRBuilder.buildBitcast(Dst, NewVec); 2512 MI.eraseFromParent(); 2513 return Legalized; 2514 } 2515 2516 if (NewNumElts < OldNumElts) { 2517 if (NewEltSize % OldEltSize != 0) 2518 return UnableToLegalize; 2519 2520 // This only depends on powers of 2 because we use bit tricks to figure out 2521 // the bit offset we need to shift to get the target element. A general 2522 // expansion could emit division/multiply. 2523 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2524 return UnableToLegalize; 2525 2526 // Increasing the vector element size. 2527 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2528 // 2529 // => 2530 // 2531 // %cast = G_BITCAST %vec 2532 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2533 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2534 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2535 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2536 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2537 // %elt = G_TRUNC %elt_bits 2538 2539 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2540 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2541 2542 // Divide to get the index in the wider element type. 2543 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2544 2545 Register WideElt = CastVec; 2546 if (CastTy.isVector()) { 2547 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2548 ScaledIdx).getReg(0); 2549 } 2550 2551 // Compute the bit offset into the register of the target element. 2552 Register OffsetBits = getBitcastWiderVectorElementOffset( 2553 MIRBuilder, Idx, NewEltSize, OldEltSize); 2554 2555 // Shift the wide element to get the target element. 2556 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2557 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2558 MI.eraseFromParent(); 2559 return Legalized; 2560 } 2561 2562 return UnableToLegalize; 2563 } 2564 2565 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2566 /// TargetReg, while preserving other bits in \p TargetReg. 2567 /// 2568 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2569 static Register buildBitFieldInsert(MachineIRBuilder &B, 2570 Register TargetReg, Register InsertReg, 2571 Register OffsetBits) { 2572 LLT TargetTy = B.getMRI()->getType(TargetReg); 2573 LLT InsertTy = B.getMRI()->getType(InsertReg); 2574 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2575 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2576 2577 // Produce a bitmask of the value to insert 2578 auto EltMask = B.buildConstant( 2579 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2580 InsertTy.getSizeInBits())); 2581 // Shift it into position 2582 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2583 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2584 2585 // Clear out the bits in the wide element 2586 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2587 2588 // The value to insert has all zeros already, so stick it into the masked 2589 // wide element. 2590 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2591 } 2592 2593 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2594 /// is increasing the element size, perform the indexing in the target element 2595 /// type, and use bit operations to insert at the element position. This is 2596 /// intended for architectures that can dynamically index the register file and 2597 /// want to force indexing in the native register size. 2598 LegalizerHelper::LegalizeResult 2599 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2600 LLT CastTy) { 2601 if (TypeIdx != 0) 2602 return UnableToLegalize; 2603 2604 Register Dst = MI.getOperand(0).getReg(); 2605 Register SrcVec = MI.getOperand(1).getReg(); 2606 Register Val = MI.getOperand(2).getReg(); 2607 Register Idx = MI.getOperand(3).getReg(); 2608 2609 LLT VecTy = MRI.getType(Dst); 2610 LLT IdxTy = MRI.getType(Idx); 2611 2612 LLT VecEltTy = VecTy.getElementType(); 2613 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2614 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2615 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2616 2617 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2618 unsigned OldNumElts = VecTy.getNumElements(); 2619 2620 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2621 if (NewNumElts < OldNumElts) { 2622 if (NewEltSize % OldEltSize != 0) 2623 return UnableToLegalize; 2624 2625 // This only depends on powers of 2 because we use bit tricks to figure out 2626 // the bit offset we need to shift to get the target element. A general 2627 // expansion could emit division/multiply. 2628 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2629 return UnableToLegalize; 2630 2631 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2632 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2633 2634 // Divide to get the index in the wider element type. 2635 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2636 2637 Register ExtractedElt = CastVec; 2638 if (CastTy.isVector()) { 2639 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2640 ScaledIdx).getReg(0); 2641 } 2642 2643 // Compute the bit offset into the register of the target element. 2644 Register OffsetBits = getBitcastWiderVectorElementOffset( 2645 MIRBuilder, Idx, NewEltSize, OldEltSize); 2646 2647 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2648 Val, OffsetBits); 2649 if (CastTy.isVector()) { 2650 InsertedElt = MIRBuilder.buildInsertVectorElement( 2651 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2652 } 2653 2654 MIRBuilder.buildBitcast(Dst, InsertedElt); 2655 MI.eraseFromParent(); 2656 return Legalized; 2657 } 2658 2659 return UnableToLegalize; 2660 } 2661 2662 LegalizerHelper::LegalizeResult 2663 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2664 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2665 Register DstReg = MI.getOperand(0).getReg(); 2666 Register PtrReg = MI.getOperand(1).getReg(); 2667 LLT DstTy = MRI.getType(DstReg); 2668 auto &MMO = **MI.memoperands_begin(); 2669 2670 if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { 2671 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2672 // This load needs splitting into power of 2 sized loads. 2673 if (DstTy.isVector()) 2674 return UnableToLegalize; 2675 if (isPowerOf2_32(DstTy.getSizeInBits())) 2676 return UnableToLegalize; // Don't know what we're being asked to do. 2677 2678 // Our strategy here is to generate anyextending loads for the smaller 2679 // types up to next power-2 result type, and then combine the two larger 2680 // result values together, before truncating back down to the non-pow-2 2681 // type. 2682 // E.g. v1 = i24 load => 2683 // v2 = i32 zextload (2 byte) 2684 // v3 = i32 load (1 byte) 2685 // v4 = i32 shl v3, 16 2686 // v5 = i32 or v4, v2 2687 // v1 = i24 trunc v5 2688 // By doing this we generate the correct truncate which should get 2689 // combined away as an artifact with a matching extend. 2690 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2691 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2692 2693 MachineFunction &MF = MIRBuilder.getMF(); 2694 MachineMemOperand *LargeMMO = 2695 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2696 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2697 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2698 2699 LLT PtrTy = MRI.getType(PtrReg); 2700 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2701 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2702 Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2703 Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2704 auto LargeLoad = MIRBuilder.buildLoadInstr( 2705 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); 2706 2707 auto OffsetCst = MIRBuilder.buildConstant( 2708 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2709 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2710 auto SmallPtr = 2711 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2712 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0), 2713 *SmallMMO); 2714 2715 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2716 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2717 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2718 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)}); 2719 MI.eraseFromParent(); 2720 return Legalized; 2721 } 2722 2723 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); 2724 MI.eraseFromParent(); 2725 return Legalized; 2726 } 2727 2728 if (DstTy.isScalar()) { 2729 Register TmpReg = 2730 MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits())); 2731 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 2732 switch (MI.getOpcode()) { 2733 default: 2734 llvm_unreachable("Unexpected opcode"); 2735 case TargetOpcode::G_LOAD: 2736 MIRBuilder.buildAnyExtOrTrunc(DstReg, TmpReg); 2737 break; 2738 case TargetOpcode::G_SEXTLOAD: 2739 MIRBuilder.buildSExt(DstReg, TmpReg); 2740 break; 2741 case TargetOpcode::G_ZEXTLOAD: 2742 MIRBuilder.buildZExt(DstReg, TmpReg); 2743 break; 2744 } 2745 2746 MI.eraseFromParent(); 2747 return Legalized; 2748 } 2749 2750 return UnableToLegalize; 2751 } 2752 2753 LegalizerHelper::LegalizeResult 2754 LegalizerHelper::lowerStore(MachineInstr &MI) { 2755 // Lower a non-power of 2 store into multiple pow-2 stores. 2756 // E.g. split an i24 store into an i16 store + i8 store. 2757 // We do this by first extending the stored value to the next largest power 2758 // of 2 type, and then using truncating stores to store the components. 2759 // By doing this, likewise with G_LOAD, generate an extend that can be 2760 // artifact-combined away instead of leaving behind extracts. 2761 Register SrcReg = MI.getOperand(0).getReg(); 2762 Register PtrReg = MI.getOperand(1).getReg(); 2763 LLT SrcTy = MRI.getType(SrcReg); 2764 MachineMemOperand &MMO = **MI.memoperands_begin(); 2765 if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) 2766 return UnableToLegalize; 2767 if (SrcTy.isVector()) 2768 return UnableToLegalize; 2769 if (isPowerOf2_32(SrcTy.getSizeInBits())) 2770 return UnableToLegalize; // Don't know what we're being asked to do. 2771 2772 // Extend to the next pow-2. 2773 const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits())); 2774 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2775 2776 // Obtain the smaller value by shifting away the larger value. 2777 uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits()); 2778 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2779 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2780 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2781 2782 // Generate the PtrAdd and truncating stores. 2783 LLT PtrTy = MRI.getType(PtrReg); 2784 auto OffsetCst = MIRBuilder.buildConstant( 2785 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2786 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2787 auto SmallPtr = 2788 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2789 2790 MachineFunction &MF = MIRBuilder.getMF(); 2791 MachineMemOperand *LargeMMO = 2792 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2793 MachineMemOperand *SmallMMO = 2794 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2795 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO); 2796 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO); 2797 MI.eraseFromParent(); 2798 return Legalized; 2799 } 2800 2801 LegalizerHelper::LegalizeResult 2802 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2803 switch (MI.getOpcode()) { 2804 case TargetOpcode::G_LOAD: { 2805 if (TypeIdx != 0) 2806 return UnableToLegalize; 2807 2808 Observer.changingInstr(MI); 2809 bitcastDst(MI, CastTy, 0); 2810 Observer.changedInstr(MI); 2811 return Legalized; 2812 } 2813 case TargetOpcode::G_STORE: { 2814 if (TypeIdx != 0) 2815 return UnableToLegalize; 2816 2817 Observer.changingInstr(MI); 2818 bitcastSrc(MI, CastTy, 0); 2819 Observer.changedInstr(MI); 2820 return Legalized; 2821 } 2822 case TargetOpcode::G_SELECT: { 2823 if (TypeIdx != 0) 2824 return UnableToLegalize; 2825 2826 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2827 LLVM_DEBUG( 2828 dbgs() << "bitcast action not implemented for vector select\n"); 2829 return UnableToLegalize; 2830 } 2831 2832 Observer.changingInstr(MI); 2833 bitcastSrc(MI, CastTy, 2); 2834 bitcastSrc(MI, CastTy, 3); 2835 bitcastDst(MI, CastTy, 0); 2836 Observer.changedInstr(MI); 2837 return Legalized; 2838 } 2839 case TargetOpcode::G_AND: 2840 case TargetOpcode::G_OR: 2841 case TargetOpcode::G_XOR: { 2842 Observer.changingInstr(MI); 2843 bitcastSrc(MI, CastTy, 1); 2844 bitcastSrc(MI, CastTy, 2); 2845 bitcastDst(MI, CastTy, 0); 2846 Observer.changedInstr(MI); 2847 return Legalized; 2848 } 2849 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2850 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2851 case TargetOpcode::G_INSERT_VECTOR_ELT: 2852 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2853 default: 2854 return UnableToLegalize; 2855 } 2856 } 2857 2858 // Legalize an instruction by changing the opcode in place. 2859 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2860 Observer.changingInstr(MI); 2861 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2862 Observer.changedInstr(MI); 2863 } 2864 2865 LegalizerHelper::LegalizeResult 2866 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 2867 using namespace TargetOpcode; 2868 2869 switch(MI.getOpcode()) { 2870 default: 2871 return UnableToLegalize; 2872 case TargetOpcode::G_BITCAST: 2873 return lowerBitcast(MI); 2874 case TargetOpcode::G_SREM: 2875 case TargetOpcode::G_UREM: { 2876 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2877 auto Quot = 2878 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 2879 {MI.getOperand(1), MI.getOperand(2)}); 2880 2881 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 2882 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 2883 MI.eraseFromParent(); 2884 return Legalized; 2885 } 2886 case TargetOpcode::G_SADDO: 2887 case TargetOpcode::G_SSUBO: 2888 return lowerSADDO_SSUBO(MI); 2889 case TargetOpcode::G_UMULH: 2890 case TargetOpcode::G_SMULH: 2891 return lowerSMULH_UMULH(MI); 2892 case TargetOpcode::G_SMULO: 2893 case TargetOpcode::G_UMULO: { 2894 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 2895 // result. 2896 Register Res = MI.getOperand(0).getReg(); 2897 Register Overflow = MI.getOperand(1).getReg(); 2898 Register LHS = MI.getOperand(2).getReg(); 2899 Register RHS = MI.getOperand(3).getReg(); 2900 LLT Ty = MRI.getType(Res); 2901 2902 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 2903 ? TargetOpcode::G_SMULH 2904 : TargetOpcode::G_UMULH; 2905 2906 Observer.changingInstr(MI); 2907 const auto &TII = MIRBuilder.getTII(); 2908 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 2909 MI.RemoveOperand(1); 2910 Observer.changedInstr(MI); 2911 2912 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 2913 auto Zero = MIRBuilder.buildConstant(Ty, 0); 2914 2915 // Move insert point forward so we can use the Res register if needed. 2916 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2917 2918 // For *signed* multiply, overflow is detected by checking: 2919 // (hi != (lo >> bitwidth-1)) 2920 if (Opcode == TargetOpcode::G_SMULH) { 2921 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 2922 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 2923 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 2924 } else { 2925 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 2926 } 2927 return Legalized; 2928 } 2929 case TargetOpcode::G_FNEG: { 2930 Register Res = MI.getOperand(0).getReg(); 2931 LLT Ty = MRI.getType(Res); 2932 2933 // TODO: Handle vector types once we are able to 2934 // represent them. 2935 if (Ty.isVector()) 2936 return UnableToLegalize; 2937 auto SignMask = 2938 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 2939 Register SubByReg = MI.getOperand(1).getReg(); 2940 MIRBuilder.buildXor(Res, SubByReg, SignMask); 2941 MI.eraseFromParent(); 2942 return Legalized; 2943 } 2944 case TargetOpcode::G_FSUB: { 2945 Register Res = MI.getOperand(0).getReg(); 2946 LLT Ty = MRI.getType(Res); 2947 2948 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 2949 // First, check if G_FNEG is marked as Lower. If so, we may 2950 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 2951 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 2952 return UnableToLegalize; 2953 Register LHS = MI.getOperand(1).getReg(); 2954 Register RHS = MI.getOperand(2).getReg(); 2955 Register Neg = MRI.createGenericVirtualRegister(Ty); 2956 MIRBuilder.buildFNeg(Neg, RHS); 2957 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 2958 MI.eraseFromParent(); 2959 return Legalized; 2960 } 2961 case TargetOpcode::G_FMAD: 2962 return lowerFMad(MI); 2963 case TargetOpcode::G_FFLOOR: 2964 return lowerFFloor(MI); 2965 case TargetOpcode::G_INTRINSIC_ROUND: 2966 return lowerIntrinsicRound(MI); 2967 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 2968 // Since round even is the assumed rounding mode for unconstrained FP 2969 // operations, rint and roundeven are the same operation. 2970 changeOpcode(MI, TargetOpcode::G_FRINT); 2971 return Legalized; 2972 } 2973 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 2974 Register OldValRes = MI.getOperand(0).getReg(); 2975 Register SuccessRes = MI.getOperand(1).getReg(); 2976 Register Addr = MI.getOperand(2).getReg(); 2977 Register CmpVal = MI.getOperand(3).getReg(); 2978 Register NewVal = MI.getOperand(4).getReg(); 2979 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 2980 **MI.memoperands_begin()); 2981 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 2982 MI.eraseFromParent(); 2983 return Legalized; 2984 } 2985 case TargetOpcode::G_LOAD: 2986 case TargetOpcode::G_SEXTLOAD: 2987 case TargetOpcode::G_ZEXTLOAD: 2988 return lowerLoad(MI); 2989 case TargetOpcode::G_STORE: 2990 return lowerStore(MI); 2991 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 2992 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 2993 case TargetOpcode::G_CTLZ: 2994 case TargetOpcode::G_CTTZ: 2995 case TargetOpcode::G_CTPOP: 2996 return lowerBitCount(MI); 2997 case G_UADDO: { 2998 Register Res = MI.getOperand(0).getReg(); 2999 Register CarryOut = MI.getOperand(1).getReg(); 3000 Register LHS = MI.getOperand(2).getReg(); 3001 Register RHS = MI.getOperand(3).getReg(); 3002 3003 MIRBuilder.buildAdd(Res, LHS, RHS); 3004 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3005 3006 MI.eraseFromParent(); 3007 return Legalized; 3008 } 3009 case G_UADDE: { 3010 Register Res = MI.getOperand(0).getReg(); 3011 Register CarryOut = MI.getOperand(1).getReg(); 3012 Register LHS = MI.getOperand(2).getReg(); 3013 Register RHS = MI.getOperand(3).getReg(); 3014 Register CarryIn = MI.getOperand(4).getReg(); 3015 LLT Ty = MRI.getType(Res); 3016 3017 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3018 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3019 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3020 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3021 3022 MI.eraseFromParent(); 3023 return Legalized; 3024 } 3025 case G_USUBO: { 3026 Register Res = MI.getOperand(0).getReg(); 3027 Register BorrowOut = MI.getOperand(1).getReg(); 3028 Register LHS = MI.getOperand(2).getReg(); 3029 Register RHS = MI.getOperand(3).getReg(); 3030 3031 MIRBuilder.buildSub(Res, LHS, RHS); 3032 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3033 3034 MI.eraseFromParent(); 3035 return Legalized; 3036 } 3037 case G_USUBE: { 3038 Register Res = MI.getOperand(0).getReg(); 3039 Register BorrowOut = MI.getOperand(1).getReg(); 3040 Register LHS = MI.getOperand(2).getReg(); 3041 Register RHS = MI.getOperand(3).getReg(); 3042 Register BorrowIn = MI.getOperand(4).getReg(); 3043 const LLT CondTy = MRI.getType(BorrowOut); 3044 const LLT Ty = MRI.getType(Res); 3045 3046 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3047 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3048 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3049 3050 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3051 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3052 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3053 3054 MI.eraseFromParent(); 3055 return Legalized; 3056 } 3057 case G_UITOFP: 3058 return lowerUITOFP(MI); 3059 case G_SITOFP: 3060 return lowerSITOFP(MI); 3061 case G_FPTOUI: 3062 return lowerFPTOUI(MI); 3063 case G_FPTOSI: 3064 return lowerFPTOSI(MI); 3065 case G_FPTRUNC: 3066 return lowerFPTRUNC(MI); 3067 case G_FPOWI: 3068 return lowerFPOWI(MI); 3069 case G_SMIN: 3070 case G_SMAX: 3071 case G_UMIN: 3072 case G_UMAX: 3073 return lowerMinMax(MI); 3074 case G_FCOPYSIGN: 3075 return lowerFCopySign(MI); 3076 case G_FMINNUM: 3077 case G_FMAXNUM: 3078 return lowerFMinNumMaxNum(MI); 3079 case G_MERGE_VALUES: 3080 return lowerMergeValues(MI); 3081 case G_UNMERGE_VALUES: 3082 return lowerUnmergeValues(MI); 3083 case TargetOpcode::G_SEXT_INREG: { 3084 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3085 int64_t SizeInBits = MI.getOperand(2).getImm(); 3086 3087 Register DstReg = MI.getOperand(0).getReg(); 3088 Register SrcReg = MI.getOperand(1).getReg(); 3089 LLT DstTy = MRI.getType(DstReg); 3090 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3091 3092 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3093 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3094 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3095 MI.eraseFromParent(); 3096 return Legalized; 3097 } 3098 case G_EXTRACT_VECTOR_ELT: 3099 case G_INSERT_VECTOR_ELT: 3100 return lowerExtractInsertVectorElt(MI); 3101 case G_SHUFFLE_VECTOR: 3102 return lowerShuffleVector(MI); 3103 case G_DYN_STACKALLOC: 3104 return lowerDynStackAlloc(MI); 3105 case G_EXTRACT: 3106 return lowerExtract(MI); 3107 case G_INSERT: 3108 return lowerInsert(MI); 3109 case G_BSWAP: 3110 return lowerBswap(MI); 3111 case G_BITREVERSE: 3112 return lowerBitreverse(MI); 3113 case G_READ_REGISTER: 3114 case G_WRITE_REGISTER: 3115 return lowerReadWriteRegister(MI); 3116 case G_UADDSAT: 3117 case G_USUBSAT: { 3118 // Try to make a reasonable guess about which lowering strategy to use. The 3119 // target can override this with custom lowering and calling the 3120 // implementation functions. 3121 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3122 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3123 return lowerAddSubSatToMinMax(MI); 3124 return lowerAddSubSatToAddoSubo(MI); 3125 } 3126 case G_SADDSAT: 3127 case G_SSUBSAT: { 3128 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3129 3130 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3131 // since it's a shorter expansion. However, we would need to figure out the 3132 // preferred boolean type for the carry out for the query. 3133 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3134 return lowerAddSubSatToMinMax(MI); 3135 return lowerAddSubSatToAddoSubo(MI); 3136 } 3137 case G_SSHLSAT: 3138 case G_USHLSAT: 3139 return lowerShlSat(MI); 3140 case G_ABS: { 3141 // Expand %res = G_ABS %a into: 3142 // %v1 = G_ASHR %a, scalar_size-1 3143 // %v2 = G_ADD %a, %v1 3144 // %res = G_XOR %v2, %v1 3145 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3146 Register OpReg = MI.getOperand(1).getReg(); 3147 auto ShiftAmt = 3148 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 3149 auto Shift = 3150 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 3151 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 3152 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 3153 MI.eraseFromParent(); 3154 return Legalized; 3155 } 3156 case G_SELECT: 3157 return lowerSelect(MI); 3158 } 3159 } 3160 3161 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3162 Align MinAlign) const { 3163 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3164 // datalayout for the preferred alignment. Also there should be a target hook 3165 // for this to allow targets to reduce the alignment and ignore the 3166 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3167 // the type. 3168 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3169 } 3170 3171 MachineInstrBuilder 3172 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3173 MachinePointerInfo &PtrInfo) { 3174 MachineFunction &MF = MIRBuilder.getMF(); 3175 const DataLayout &DL = MIRBuilder.getDataLayout(); 3176 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3177 3178 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3179 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3180 3181 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3182 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3183 } 3184 3185 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3186 LLT VecTy) { 3187 int64_t IdxVal; 3188 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3189 return IdxReg; 3190 3191 LLT IdxTy = B.getMRI()->getType(IdxReg); 3192 unsigned NElts = VecTy.getNumElements(); 3193 if (isPowerOf2_32(NElts)) { 3194 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3195 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3196 } 3197 3198 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3199 .getReg(0); 3200 } 3201 3202 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3203 Register Index) { 3204 LLT EltTy = VecTy.getElementType(); 3205 3206 // Calculate the element offset and add it to the pointer. 3207 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3208 assert(EltSize * 8 == EltTy.getSizeInBits() && 3209 "Converting bits to bytes lost precision"); 3210 3211 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3212 3213 LLT IdxTy = MRI.getType(Index); 3214 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3215 MIRBuilder.buildConstant(IdxTy, EltSize)); 3216 3217 LLT PtrTy = MRI.getType(VecPtr); 3218 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3219 } 3220 3221 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3222 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3223 Register DstReg = MI.getOperand(0).getReg(); 3224 LLT DstTy = MRI.getType(DstReg); 3225 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3226 3227 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3228 3229 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3230 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3231 3232 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3233 MI.eraseFromParent(); 3234 return Legalized; 3235 } 3236 3237 // Handle splitting vector operations which need to have the same number of 3238 // elements in each type index, but each type index may have a different element 3239 // type. 3240 // 3241 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3242 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3243 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3244 // 3245 // Also handles some irregular breakdown cases, e.g. 3246 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3247 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3248 // s64 = G_SHL s64, s32 3249 LegalizerHelper::LegalizeResult 3250 LegalizerHelper::fewerElementsVectorMultiEltType( 3251 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3252 if (TypeIdx != 0) 3253 return UnableToLegalize; 3254 3255 const LLT NarrowTy0 = NarrowTyArg; 3256 const unsigned NewNumElts = 3257 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1; 3258 3259 const Register DstReg = MI.getOperand(0).getReg(); 3260 LLT DstTy = MRI.getType(DstReg); 3261 LLT LeftoverTy0; 3262 3263 // All of the operands need to have the same number of elements, so if we can 3264 // determine a type breakdown for the result type, we can for all of the 3265 // source types. 3266 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3267 if (NumParts < 0) 3268 return UnableToLegalize; 3269 3270 SmallVector<MachineInstrBuilder, 4> NewInsts; 3271 3272 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3273 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3274 3275 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3276 Register SrcReg = MI.getOperand(I).getReg(); 3277 LLT SrcTyI = MRI.getType(SrcReg); 3278 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType()); 3279 LLT LeftoverTyI; 3280 3281 // Split this operand into the requested typed registers, and any leftover 3282 // required to reproduce the original type. 3283 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3284 LeftoverRegs)) 3285 return UnableToLegalize; 3286 3287 if (I == 1) { 3288 // For the first operand, create an instruction for each part and setup 3289 // the result. 3290 for (Register PartReg : PartRegs) { 3291 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3292 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3293 .addDef(PartDstReg) 3294 .addUse(PartReg)); 3295 DstRegs.push_back(PartDstReg); 3296 } 3297 3298 for (Register LeftoverReg : LeftoverRegs) { 3299 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3300 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3301 .addDef(PartDstReg) 3302 .addUse(LeftoverReg)); 3303 LeftoverDstRegs.push_back(PartDstReg); 3304 } 3305 } else { 3306 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3307 3308 // Add the newly created operand splits to the existing instructions. The 3309 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3310 // pieces. 3311 unsigned InstCount = 0; 3312 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3313 NewInsts[InstCount++].addUse(PartRegs[J]); 3314 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3315 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3316 } 3317 3318 PartRegs.clear(); 3319 LeftoverRegs.clear(); 3320 } 3321 3322 // Insert the newly built operations and rebuild the result register. 3323 for (auto &MIB : NewInsts) 3324 MIRBuilder.insertInstr(MIB); 3325 3326 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3327 3328 MI.eraseFromParent(); 3329 return Legalized; 3330 } 3331 3332 LegalizerHelper::LegalizeResult 3333 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3334 LLT NarrowTy) { 3335 if (TypeIdx != 0) 3336 return UnableToLegalize; 3337 3338 Register DstReg = MI.getOperand(0).getReg(); 3339 Register SrcReg = MI.getOperand(1).getReg(); 3340 LLT DstTy = MRI.getType(DstReg); 3341 LLT SrcTy = MRI.getType(SrcReg); 3342 3343 LLT NarrowTy0 = NarrowTy; 3344 LLT NarrowTy1; 3345 unsigned NumParts; 3346 3347 if (NarrowTy.isVector()) { 3348 // Uneven breakdown not handled. 3349 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3350 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3351 return UnableToLegalize; 3352 3353 NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType()); 3354 } else { 3355 NumParts = DstTy.getNumElements(); 3356 NarrowTy1 = SrcTy.getElementType(); 3357 } 3358 3359 SmallVector<Register, 4> SrcRegs, DstRegs; 3360 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3361 3362 for (unsigned I = 0; I < NumParts; ++I) { 3363 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3364 MachineInstr *NewInst = 3365 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3366 3367 NewInst->setFlags(MI.getFlags()); 3368 DstRegs.push_back(DstReg); 3369 } 3370 3371 if (NarrowTy.isVector()) 3372 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3373 else 3374 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3375 3376 MI.eraseFromParent(); 3377 return Legalized; 3378 } 3379 3380 LegalizerHelper::LegalizeResult 3381 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3382 LLT NarrowTy) { 3383 Register DstReg = MI.getOperand(0).getReg(); 3384 Register Src0Reg = MI.getOperand(2).getReg(); 3385 LLT DstTy = MRI.getType(DstReg); 3386 LLT SrcTy = MRI.getType(Src0Reg); 3387 3388 unsigned NumParts; 3389 LLT NarrowTy0, NarrowTy1; 3390 3391 if (TypeIdx == 0) { 3392 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3393 unsigned OldElts = DstTy.getNumElements(); 3394 3395 NarrowTy0 = NarrowTy; 3396 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3397 NarrowTy1 = NarrowTy.isVector() ? 3398 LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) : 3399 SrcTy.getElementType(); 3400 3401 } else { 3402 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3403 unsigned OldElts = SrcTy.getNumElements(); 3404 3405 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3406 NarrowTy.getNumElements(); 3407 NarrowTy0 = LLT::vector(NarrowTy.getNumElements(), 3408 DstTy.getScalarSizeInBits()); 3409 NarrowTy1 = NarrowTy; 3410 } 3411 3412 // FIXME: Don't know how to handle the situation where the small vectors 3413 // aren't all the same size yet. 3414 if (NarrowTy1.isVector() && 3415 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3416 return UnableToLegalize; 3417 3418 CmpInst::Predicate Pred 3419 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3420 3421 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3422 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3423 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3424 3425 for (unsigned I = 0; I < NumParts; ++I) { 3426 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3427 DstRegs.push_back(DstReg); 3428 3429 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3430 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3431 else { 3432 MachineInstr *NewCmp 3433 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3434 NewCmp->setFlags(MI.getFlags()); 3435 } 3436 } 3437 3438 if (NarrowTy1.isVector()) 3439 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3440 else 3441 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3442 3443 MI.eraseFromParent(); 3444 return Legalized; 3445 } 3446 3447 LegalizerHelper::LegalizeResult 3448 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3449 LLT NarrowTy) { 3450 Register DstReg = MI.getOperand(0).getReg(); 3451 Register CondReg = MI.getOperand(1).getReg(); 3452 3453 unsigned NumParts = 0; 3454 LLT NarrowTy0, NarrowTy1; 3455 3456 LLT DstTy = MRI.getType(DstReg); 3457 LLT CondTy = MRI.getType(CondReg); 3458 unsigned Size = DstTy.getSizeInBits(); 3459 3460 assert(TypeIdx == 0 || CondTy.isVector()); 3461 3462 if (TypeIdx == 0) { 3463 NarrowTy0 = NarrowTy; 3464 NarrowTy1 = CondTy; 3465 3466 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3467 // FIXME: Don't know how to handle the situation where the small vectors 3468 // aren't all the same size yet. 3469 if (Size % NarrowSize != 0) 3470 return UnableToLegalize; 3471 3472 NumParts = Size / NarrowSize; 3473 3474 // Need to break down the condition type 3475 if (CondTy.isVector()) { 3476 if (CondTy.getNumElements() == NumParts) 3477 NarrowTy1 = CondTy.getElementType(); 3478 else 3479 NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts, 3480 CondTy.getScalarSizeInBits()); 3481 } 3482 } else { 3483 NumParts = CondTy.getNumElements(); 3484 if (NarrowTy.isVector()) { 3485 // TODO: Handle uneven breakdown. 3486 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3487 return UnableToLegalize; 3488 3489 return UnableToLegalize; 3490 } else { 3491 NarrowTy0 = DstTy.getElementType(); 3492 NarrowTy1 = NarrowTy; 3493 } 3494 } 3495 3496 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3497 if (CondTy.isVector()) 3498 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3499 3500 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3501 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3502 3503 for (unsigned i = 0; i < NumParts; ++i) { 3504 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3505 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3506 Src1Regs[i], Src2Regs[i]); 3507 DstRegs.push_back(DstReg); 3508 } 3509 3510 if (NarrowTy0.isVector()) 3511 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3512 else 3513 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3514 3515 MI.eraseFromParent(); 3516 return Legalized; 3517 } 3518 3519 LegalizerHelper::LegalizeResult 3520 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3521 LLT NarrowTy) { 3522 const Register DstReg = MI.getOperand(0).getReg(); 3523 LLT PhiTy = MRI.getType(DstReg); 3524 LLT LeftoverTy; 3525 3526 // All of the operands need to have the same number of elements, so if we can 3527 // determine a type breakdown for the result type, we can for all of the 3528 // source types. 3529 int NumParts, NumLeftover; 3530 std::tie(NumParts, NumLeftover) 3531 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3532 if (NumParts < 0) 3533 return UnableToLegalize; 3534 3535 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3536 SmallVector<MachineInstrBuilder, 4> NewInsts; 3537 3538 const int TotalNumParts = NumParts + NumLeftover; 3539 3540 // Insert the new phis in the result block first. 3541 for (int I = 0; I != TotalNumParts; ++I) { 3542 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3543 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3544 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3545 .addDef(PartDstReg)); 3546 if (I < NumParts) 3547 DstRegs.push_back(PartDstReg); 3548 else 3549 LeftoverDstRegs.push_back(PartDstReg); 3550 } 3551 3552 MachineBasicBlock *MBB = MI.getParent(); 3553 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3554 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3555 3556 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3557 3558 // Insert code to extract the incoming values in each predecessor block. 3559 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3560 PartRegs.clear(); 3561 LeftoverRegs.clear(); 3562 3563 Register SrcReg = MI.getOperand(I).getReg(); 3564 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3565 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3566 3567 LLT Unused; 3568 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3569 LeftoverRegs)) 3570 return UnableToLegalize; 3571 3572 // Add the newly created operand splits to the existing instructions. The 3573 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3574 // pieces. 3575 for (int J = 0; J != TotalNumParts; ++J) { 3576 MachineInstrBuilder MIB = NewInsts[J]; 3577 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3578 MIB.addMBB(&OpMBB); 3579 } 3580 } 3581 3582 MI.eraseFromParent(); 3583 return Legalized; 3584 } 3585 3586 LegalizerHelper::LegalizeResult 3587 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3588 unsigned TypeIdx, 3589 LLT NarrowTy) { 3590 if (TypeIdx != 1) 3591 return UnableToLegalize; 3592 3593 const int NumDst = MI.getNumOperands() - 1; 3594 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3595 LLT SrcTy = MRI.getType(SrcReg); 3596 3597 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3598 3599 // TODO: Create sequence of extracts. 3600 if (DstTy == NarrowTy) 3601 return UnableToLegalize; 3602 3603 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3604 if (DstTy == GCDTy) { 3605 // This would just be a copy of the same unmerge. 3606 // TODO: Create extracts, pad with undef and create intermediate merges. 3607 return UnableToLegalize; 3608 } 3609 3610 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3611 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3612 const int PartsPerUnmerge = NumDst / NumUnmerge; 3613 3614 for (int I = 0; I != NumUnmerge; ++I) { 3615 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3616 3617 for (int J = 0; J != PartsPerUnmerge; ++J) 3618 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3619 MIB.addUse(Unmerge.getReg(I)); 3620 } 3621 3622 MI.eraseFromParent(); 3623 return Legalized; 3624 } 3625 3626 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3627 // a vector 3628 // 3629 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3630 // undef as necessary. 3631 // 3632 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3633 // -> <2 x s16> 3634 // 3635 // %4:_(s16) = G_IMPLICIT_DEF 3636 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3637 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3638 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3639 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3640 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3641 LegalizerHelper::LegalizeResult 3642 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3643 LLT NarrowTy) { 3644 Register DstReg = MI.getOperand(0).getReg(); 3645 LLT DstTy = MRI.getType(DstReg); 3646 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3647 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3648 3649 // Break into a common type 3650 SmallVector<Register, 16> Parts; 3651 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3652 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3653 3654 // Build the requested new merge, padding with undef. 3655 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3656 TargetOpcode::G_ANYEXT); 3657 3658 // Pack into the original result register. 3659 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3660 3661 MI.eraseFromParent(); 3662 return Legalized; 3663 } 3664 3665 LegalizerHelper::LegalizeResult 3666 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3667 unsigned TypeIdx, 3668 LLT NarrowVecTy) { 3669 Register DstReg = MI.getOperand(0).getReg(); 3670 Register SrcVec = MI.getOperand(1).getReg(); 3671 Register InsertVal; 3672 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3673 3674 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3675 if (IsInsert) 3676 InsertVal = MI.getOperand(2).getReg(); 3677 3678 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3679 3680 // TODO: Handle total scalarization case. 3681 if (!NarrowVecTy.isVector()) 3682 return UnableToLegalize; 3683 3684 LLT VecTy = MRI.getType(SrcVec); 3685 3686 // If the index is a constant, we can really break this down as you would 3687 // expect, and index into the target size pieces. 3688 int64_t IdxVal; 3689 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 3690 // Avoid out of bounds indexing the pieces. 3691 if (IdxVal >= VecTy.getNumElements()) { 3692 MIRBuilder.buildUndef(DstReg); 3693 MI.eraseFromParent(); 3694 return Legalized; 3695 } 3696 3697 SmallVector<Register, 8> VecParts; 3698 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3699 3700 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3701 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3702 TargetOpcode::G_ANYEXT); 3703 3704 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3705 3706 LLT IdxTy = MRI.getType(Idx); 3707 int64_t PartIdx = IdxVal / NewNumElts; 3708 auto NewIdx = 3709 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3710 3711 if (IsInsert) { 3712 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3713 3714 // Use the adjusted index to insert into one of the subvectors. 3715 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3716 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3717 VecParts[PartIdx] = InsertPart.getReg(0); 3718 3719 // Recombine the inserted subvector with the others to reform the result 3720 // vector. 3721 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3722 } else { 3723 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3724 } 3725 3726 MI.eraseFromParent(); 3727 return Legalized; 3728 } 3729 3730 // With a variable index, we can't perform the operation in a smaller type, so 3731 // we're forced to expand this. 3732 // 3733 // TODO: We could emit a chain of compare/select to figure out which piece to 3734 // index. 3735 return lowerExtractInsertVectorElt(MI); 3736 } 3737 3738 LegalizerHelper::LegalizeResult 3739 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3740 LLT NarrowTy) { 3741 // FIXME: Don't know how to handle secondary types yet. 3742 if (TypeIdx != 0) 3743 return UnableToLegalize; 3744 3745 MachineMemOperand *MMO = *MI.memoperands_begin(); 3746 3747 // This implementation doesn't work for atomics. Give up instead of doing 3748 // something invalid. 3749 if (MMO->getOrdering() != AtomicOrdering::NotAtomic || 3750 MMO->getFailureOrdering() != AtomicOrdering::NotAtomic) 3751 return UnableToLegalize; 3752 3753 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3754 Register ValReg = MI.getOperand(0).getReg(); 3755 Register AddrReg = MI.getOperand(1).getReg(); 3756 LLT ValTy = MRI.getType(ValReg); 3757 3758 // FIXME: Do we need a distinct NarrowMemory legalize action? 3759 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3760 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3761 return UnableToLegalize; 3762 } 3763 3764 int NumParts = -1; 3765 int NumLeftover = -1; 3766 LLT LeftoverTy; 3767 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3768 if (IsLoad) { 3769 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3770 } else { 3771 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3772 NarrowLeftoverRegs)) { 3773 NumParts = NarrowRegs.size(); 3774 NumLeftover = NarrowLeftoverRegs.size(); 3775 } 3776 } 3777 3778 if (NumParts == -1) 3779 return UnableToLegalize; 3780 3781 LLT PtrTy = MRI.getType(AddrReg); 3782 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3783 3784 unsigned TotalSize = ValTy.getSizeInBits(); 3785 3786 // Split the load/store into PartTy sized pieces starting at Offset. If this 3787 // is a load, return the new registers in ValRegs. For a store, each elements 3788 // of ValRegs should be PartTy. Returns the next offset that needs to be 3789 // handled. 3790 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3791 unsigned Offset) -> unsigned { 3792 MachineFunction &MF = MIRBuilder.getMF(); 3793 unsigned PartSize = PartTy.getSizeInBits(); 3794 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3795 Offset += PartSize, ++Idx) { 3796 unsigned ByteSize = PartSize / 8; 3797 unsigned ByteOffset = Offset / 8; 3798 Register NewAddrReg; 3799 3800 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3801 3802 MachineMemOperand *NewMMO = 3803 MF.getMachineMemOperand(MMO, ByteOffset, ByteSize); 3804 3805 if (IsLoad) { 3806 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3807 ValRegs.push_back(Dst); 3808 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3809 } else { 3810 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3811 } 3812 } 3813 3814 return Offset; 3815 }; 3816 3817 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 3818 3819 // Handle the rest of the register if this isn't an even type breakdown. 3820 if (LeftoverTy.isValid()) 3821 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 3822 3823 if (IsLoad) { 3824 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 3825 LeftoverTy, NarrowLeftoverRegs); 3826 } 3827 3828 MI.eraseFromParent(); 3829 return Legalized; 3830 } 3831 3832 LegalizerHelper::LegalizeResult 3833 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 3834 LLT NarrowTy) { 3835 assert(TypeIdx == 0 && "only one type index expected"); 3836 3837 const unsigned Opc = MI.getOpcode(); 3838 const int NumOps = MI.getNumOperands() - 1; 3839 const Register DstReg = MI.getOperand(0).getReg(); 3840 const unsigned Flags = MI.getFlags(); 3841 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 3842 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 3843 3844 assert(NumOps <= 3 && "expected instruction with 1 result and 1-3 sources"); 3845 3846 // First of all check whether we are narrowing (changing the element type) 3847 // or reducing the vector elements 3848 const LLT DstTy = MRI.getType(DstReg); 3849 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 3850 3851 SmallVector<Register, 8> ExtractedRegs[3]; 3852 SmallVector<Register, 8> Parts; 3853 3854 unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3855 3856 // Break down all the sources into NarrowTy pieces we can operate on. This may 3857 // involve creating merges to a wider type, padded with undef. 3858 for (int I = 0; I != NumOps; ++I) { 3859 Register SrcReg = MI.getOperand(I + 1).getReg(); 3860 LLT SrcTy = MRI.getType(SrcReg); 3861 3862 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 3863 // For fewerElements, this is a smaller vector with the same element type. 3864 LLT OpNarrowTy; 3865 if (IsNarrow) { 3866 OpNarrowTy = NarrowScalarTy; 3867 3868 // In case of narrowing, we need to cast vectors to scalars for this to 3869 // work properly 3870 // FIXME: Can we do without the bitcast here if we're narrowing? 3871 if (SrcTy.isVector()) { 3872 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 3873 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 3874 } 3875 } else { 3876 OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType()); 3877 } 3878 3879 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 3880 3881 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 3882 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 3883 TargetOpcode::G_ANYEXT); 3884 } 3885 3886 SmallVector<Register, 8> ResultRegs; 3887 3888 // Input operands for each sub-instruction. 3889 SmallVector<SrcOp, 4> InputRegs(NumOps, Register()); 3890 3891 int NumParts = ExtractedRegs[0].size(); 3892 const unsigned DstSize = DstTy.getSizeInBits(); 3893 const LLT DstScalarTy = LLT::scalar(DstSize); 3894 3895 // Narrowing needs to use scalar types 3896 LLT DstLCMTy, NarrowDstTy; 3897 if (IsNarrow) { 3898 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 3899 NarrowDstTy = NarrowScalarTy; 3900 } else { 3901 DstLCMTy = getLCMType(DstTy, NarrowTy); 3902 NarrowDstTy = NarrowTy; 3903 } 3904 3905 // We widened the source registers to satisfy merge/unmerge size 3906 // constraints. We'll have some extra fully undef parts. 3907 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 3908 3909 for (int I = 0; I != NumRealParts; ++I) { 3910 // Emit this instruction on each of the split pieces. 3911 for (int J = 0; J != NumOps; ++J) 3912 InputRegs[J] = ExtractedRegs[J][I]; 3913 3914 auto Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 3915 ResultRegs.push_back(Inst.getReg(0)); 3916 } 3917 3918 // Fill out the widened result with undef instead of creating instructions 3919 // with undef inputs. 3920 int NumUndefParts = NumParts - NumRealParts; 3921 if (NumUndefParts != 0) 3922 ResultRegs.append(NumUndefParts, 3923 MIRBuilder.buildUndef(NarrowDstTy).getReg(0)); 3924 3925 // Extract the possibly padded result. Use a scratch register if we need to do 3926 // a final bitcast, otherwise use the original result register. 3927 Register MergeDstReg; 3928 if (IsNarrow && DstTy.isVector()) 3929 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 3930 else 3931 MergeDstReg = DstReg; 3932 3933 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs); 3934 3935 // Recast to vector if we narrowed a vector 3936 if (IsNarrow && DstTy.isVector()) 3937 MIRBuilder.buildBitcast(DstReg, MergeDstReg); 3938 3939 MI.eraseFromParent(); 3940 return Legalized; 3941 } 3942 3943 LegalizerHelper::LegalizeResult 3944 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 3945 LLT NarrowTy) { 3946 Register DstReg = MI.getOperand(0).getReg(); 3947 Register SrcReg = MI.getOperand(1).getReg(); 3948 int64_t Imm = MI.getOperand(2).getImm(); 3949 3950 LLT DstTy = MRI.getType(DstReg); 3951 3952 SmallVector<Register, 8> Parts; 3953 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 3954 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 3955 3956 for (Register &R : Parts) 3957 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 3958 3959 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3960 3961 MI.eraseFromParent(); 3962 return Legalized; 3963 } 3964 3965 LegalizerHelper::LegalizeResult 3966 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 3967 LLT NarrowTy) { 3968 using namespace TargetOpcode; 3969 3970 switch (MI.getOpcode()) { 3971 case G_IMPLICIT_DEF: 3972 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 3973 case G_TRUNC: 3974 case G_AND: 3975 case G_OR: 3976 case G_XOR: 3977 case G_ADD: 3978 case G_SUB: 3979 case G_MUL: 3980 case G_PTR_ADD: 3981 case G_SMULH: 3982 case G_UMULH: 3983 case G_FADD: 3984 case G_FMUL: 3985 case G_FSUB: 3986 case G_FNEG: 3987 case G_FABS: 3988 case G_FCANONICALIZE: 3989 case G_FDIV: 3990 case G_FREM: 3991 case G_FMA: 3992 case G_FMAD: 3993 case G_FPOW: 3994 case G_FEXP: 3995 case G_FEXP2: 3996 case G_FLOG: 3997 case G_FLOG2: 3998 case G_FLOG10: 3999 case G_FNEARBYINT: 4000 case G_FCEIL: 4001 case G_FFLOOR: 4002 case G_FRINT: 4003 case G_INTRINSIC_ROUND: 4004 case G_INTRINSIC_ROUNDEVEN: 4005 case G_INTRINSIC_TRUNC: 4006 case G_FCOS: 4007 case G_FSIN: 4008 case G_FSQRT: 4009 case G_BSWAP: 4010 case G_BITREVERSE: 4011 case G_SDIV: 4012 case G_UDIV: 4013 case G_SREM: 4014 case G_UREM: 4015 case G_SMIN: 4016 case G_SMAX: 4017 case G_UMIN: 4018 case G_UMAX: 4019 case G_FMINNUM: 4020 case G_FMAXNUM: 4021 case G_FMINNUM_IEEE: 4022 case G_FMAXNUM_IEEE: 4023 case G_FMINIMUM: 4024 case G_FMAXIMUM: 4025 case G_FSHL: 4026 case G_FSHR: 4027 case G_FREEZE: 4028 case G_SADDSAT: 4029 case G_SSUBSAT: 4030 case G_UADDSAT: 4031 case G_USUBSAT: 4032 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4033 case G_SHL: 4034 case G_LSHR: 4035 case G_ASHR: 4036 case G_SSHLSAT: 4037 case G_USHLSAT: 4038 case G_CTLZ: 4039 case G_CTLZ_ZERO_UNDEF: 4040 case G_CTTZ: 4041 case G_CTTZ_ZERO_UNDEF: 4042 case G_CTPOP: 4043 case G_FCOPYSIGN: 4044 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4045 case G_ZEXT: 4046 case G_SEXT: 4047 case G_ANYEXT: 4048 case G_FPEXT: 4049 case G_FPTRUNC: 4050 case G_SITOFP: 4051 case G_UITOFP: 4052 case G_FPTOSI: 4053 case G_FPTOUI: 4054 case G_INTTOPTR: 4055 case G_PTRTOINT: 4056 case G_ADDRSPACE_CAST: 4057 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4058 case G_ICMP: 4059 case G_FCMP: 4060 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4061 case G_SELECT: 4062 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4063 case G_PHI: 4064 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4065 case G_UNMERGE_VALUES: 4066 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4067 case G_BUILD_VECTOR: 4068 assert(TypeIdx == 0 && "not a vector type index"); 4069 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4070 case G_CONCAT_VECTORS: 4071 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4072 return UnableToLegalize; 4073 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4074 case G_EXTRACT_VECTOR_ELT: 4075 case G_INSERT_VECTOR_ELT: 4076 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4077 case G_LOAD: 4078 case G_STORE: 4079 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4080 case G_SEXT_INREG: 4081 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4082 default: 4083 return UnableToLegalize; 4084 } 4085 } 4086 4087 LegalizerHelper::LegalizeResult 4088 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4089 const LLT HalfTy, const LLT AmtTy) { 4090 4091 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4092 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4093 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4094 4095 if (Amt.isNullValue()) { 4096 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4097 MI.eraseFromParent(); 4098 return Legalized; 4099 } 4100 4101 LLT NVT = HalfTy; 4102 unsigned NVTBits = HalfTy.getSizeInBits(); 4103 unsigned VTBits = 2 * NVTBits; 4104 4105 SrcOp Lo(Register(0)), Hi(Register(0)); 4106 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4107 if (Amt.ugt(VTBits)) { 4108 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4109 } else if (Amt.ugt(NVTBits)) { 4110 Lo = MIRBuilder.buildConstant(NVT, 0); 4111 Hi = MIRBuilder.buildShl(NVT, InL, 4112 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4113 } else if (Amt == NVTBits) { 4114 Lo = MIRBuilder.buildConstant(NVT, 0); 4115 Hi = InL; 4116 } else { 4117 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4118 auto OrLHS = 4119 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4120 auto OrRHS = MIRBuilder.buildLShr( 4121 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4122 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4123 } 4124 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4125 if (Amt.ugt(VTBits)) { 4126 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4127 } else if (Amt.ugt(NVTBits)) { 4128 Lo = MIRBuilder.buildLShr(NVT, InH, 4129 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4130 Hi = MIRBuilder.buildConstant(NVT, 0); 4131 } else if (Amt == NVTBits) { 4132 Lo = InH; 4133 Hi = MIRBuilder.buildConstant(NVT, 0); 4134 } else { 4135 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4136 4137 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4138 auto OrRHS = MIRBuilder.buildShl( 4139 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4140 4141 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4142 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4143 } 4144 } else { 4145 if (Amt.ugt(VTBits)) { 4146 Hi = Lo = MIRBuilder.buildAShr( 4147 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4148 } else if (Amt.ugt(NVTBits)) { 4149 Lo = MIRBuilder.buildAShr(NVT, InH, 4150 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4151 Hi = MIRBuilder.buildAShr(NVT, InH, 4152 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4153 } else if (Amt == NVTBits) { 4154 Lo = InH; 4155 Hi = MIRBuilder.buildAShr(NVT, InH, 4156 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4157 } else { 4158 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4159 4160 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4161 auto OrRHS = MIRBuilder.buildShl( 4162 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4163 4164 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4165 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4166 } 4167 } 4168 4169 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4170 MI.eraseFromParent(); 4171 4172 return Legalized; 4173 } 4174 4175 // TODO: Optimize if constant shift amount. 4176 LegalizerHelper::LegalizeResult 4177 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4178 LLT RequestedTy) { 4179 if (TypeIdx == 1) { 4180 Observer.changingInstr(MI); 4181 narrowScalarSrc(MI, RequestedTy, 2); 4182 Observer.changedInstr(MI); 4183 return Legalized; 4184 } 4185 4186 Register DstReg = MI.getOperand(0).getReg(); 4187 LLT DstTy = MRI.getType(DstReg); 4188 if (DstTy.isVector()) 4189 return UnableToLegalize; 4190 4191 Register Amt = MI.getOperand(2).getReg(); 4192 LLT ShiftAmtTy = MRI.getType(Amt); 4193 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4194 if (DstEltSize % 2 != 0) 4195 return UnableToLegalize; 4196 4197 // Ignore the input type. We can only go to exactly half the size of the 4198 // input. If that isn't small enough, the resulting pieces will be further 4199 // legalized. 4200 const unsigned NewBitSize = DstEltSize / 2; 4201 const LLT HalfTy = LLT::scalar(NewBitSize); 4202 const LLT CondTy = LLT::scalar(1); 4203 4204 if (const MachineInstr *KShiftAmt = 4205 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4206 return narrowScalarShiftByConstant( 4207 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4208 } 4209 4210 // TODO: Expand with known bits. 4211 4212 // Handle the fully general expansion by an unknown amount. 4213 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4214 4215 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4216 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4217 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4218 4219 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4220 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4221 4222 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4223 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4224 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4225 4226 Register ResultRegs[2]; 4227 switch (MI.getOpcode()) { 4228 case TargetOpcode::G_SHL: { 4229 // Short: ShAmt < NewBitSize 4230 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4231 4232 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4233 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4234 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4235 4236 // Long: ShAmt >= NewBitSize 4237 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4238 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4239 4240 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4241 auto Hi = MIRBuilder.buildSelect( 4242 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4243 4244 ResultRegs[0] = Lo.getReg(0); 4245 ResultRegs[1] = Hi.getReg(0); 4246 break; 4247 } 4248 case TargetOpcode::G_LSHR: 4249 case TargetOpcode::G_ASHR: { 4250 // Short: ShAmt < NewBitSize 4251 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4252 4253 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4254 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4255 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4256 4257 // Long: ShAmt >= NewBitSize 4258 MachineInstrBuilder HiL; 4259 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4260 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4261 } else { 4262 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4263 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4264 } 4265 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4266 {InH, AmtExcess}); // Lo from Hi part. 4267 4268 auto Lo = MIRBuilder.buildSelect( 4269 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4270 4271 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4272 4273 ResultRegs[0] = Lo.getReg(0); 4274 ResultRegs[1] = Hi.getReg(0); 4275 break; 4276 } 4277 default: 4278 llvm_unreachable("not a shift"); 4279 } 4280 4281 MIRBuilder.buildMerge(DstReg, ResultRegs); 4282 MI.eraseFromParent(); 4283 return Legalized; 4284 } 4285 4286 LegalizerHelper::LegalizeResult 4287 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4288 LLT MoreTy) { 4289 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4290 4291 Observer.changingInstr(MI); 4292 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4293 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4294 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4295 moreElementsVectorSrc(MI, MoreTy, I); 4296 } 4297 4298 MachineBasicBlock &MBB = *MI.getParent(); 4299 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4300 moreElementsVectorDst(MI, MoreTy, 0); 4301 Observer.changedInstr(MI); 4302 return Legalized; 4303 } 4304 4305 LegalizerHelper::LegalizeResult 4306 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4307 LLT MoreTy) { 4308 unsigned Opc = MI.getOpcode(); 4309 switch (Opc) { 4310 case TargetOpcode::G_IMPLICIT_DEF: 4311 case TargetOpcode::G_LOAD: { 4312 if (TypeIdx != 0) 4313 return UnableToLegalize; 4314 Observer.changingInstr(MI); 4315 moreElementsVectorDst(MI, MoreTy, 0); 4316 Observer.changedInstr(MI); 4317 return Legalized; 4318 } 4319 case TargetOpcode::G_STORE: 4320 if (TypeIdx != 0) 4321 return UnableToLegalize; 4322 Observer.changingInstr(MI); 4323 moreElementsVectorSrc(MI, MoreTy, 0); 4324 Observer.changedInstr(MI); 4325 return Legalized; 4326 case TargetOpcode::G_AND: 4327 case TargetOpcode::G_OR: 4328 case TargetOpcode::G_XOR: 4329 case TargetOpcode::G_SMIN: 4330 case TargetOpcode::G_SMAX: 4331 case TargetOpcode::G_UMIN: 4332 case TargetOpcode::G_UMAX: 4333 case TargetOpcode::G_FMINNUM: 4334 case TargetOpcode::G_FMAXNUM: 4335 case TargetOpcode::G_FMINNUM_IEEE: 4336 case TargetOpcode::G_FMAXNUM_IEEE: 4337 case TargetOpcode::G_FMINIMUM: 4338 case TargetOpcode::G_FMAXIMUM: { 4339 Observer.changingInstr(MI); 4340 moreElementsVectorSrc(MI, MoreTy, 1); 4341 moreElementsVectorSrc(MI, MoreTy, 2); 4342 moreElementsVectorDst(MI, MoreTy, 0); 4343 Observer.changedInstr(MI); 4344 return Legalized; 4345 } 4346 case TargetOpcode::G_EXTRACT: 4347 if (TypeIdx != 1) 4348 return UnableToLegalize; 4349 Observer.changingInstr(MI); 4350 moreElementsVectorSrc(MI, MoreTy, 1); 4351 Observer.changedInstr(MI); 4352 return Legalized; 4353 case TargetOpcode::G_INSERT: 4354 case TargetOpcode::G_FREEZE: 4355 if (TypeIdx != 0) 4356 return UnableToLegalize; 4357 Observer.changingInstr(MI); 4358 moreElementsVectorSrc(MI, MoreTy, 1); 4359 moreElementsVectorDst(MI, MoreTy, 0); 4360 Observer.changedInstr(MI); 4361 return Legalized; 4362 case TargetOpcode::G_SELECT: 4363 if (TypeIdx != 0) 4364 return UnableToLegalize; 4365 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4366 return UnableToLegalize; 4367 4368 Observer.changingInstr(MI); 4369 moreElementsVectorSrc(MI, MoreTy, 2); 4370 moreElementsVectorSrc(MI, MoreTy, 3); 4371 moreElementsVectorDst(MI, MoreTy, 0); 4372 Observer.changedInstr(MI); 4373 return Legalized; 4374 case TargetOpcode::G_UNMERGE_VALUES: { 4375 if (TypeIdx != 1) 4376 return UnableToLegalize; 4377 4378 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4379 int NumDst = MI.getNumOperands() - 1; 4380 moreElementsVectorSrc(MI, MoreTy, NumDst); 4381 4382 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4383 for (int I = 0; I != NumDst; ++I) 4384 MIB.addDef(MI.getOperand(I).getReg()); 4385 4386 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4387 for (int I = NumDst; I != NewNumDst; ++I) 4388 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4389 4390 MIB.addUse(MI.getOperand(NumDst).getReg()); 4391 MI.eraseFromParent(); 4392 return Legalized; 4393 } 4394 case TargetOpcode::G_PHI: 4395 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4396 default: 4397 return UnableToLegalize; 4398 } 4399 } 4400 4401 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4402 ArrayRef<Register> Src1Regs, 4403 ArrayRef<Register> Src2Regs, 4404 LLT NarrowTy) { 4405 MachineIRBuilder &B = MIRBuilder; 4406 unsigned SrcParts = Src1Regs.size(); 4407 unsigned DstParts = DstRegs.size(); 4408 4409 unsigned DstIdx = 0; // Low bits of the result. 4410 Register FactorSum = 4411 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4412 DstRegs[DstIdx] = FactorSum; 4413 4414 unsigned CarrySumPrevDstIdx; 4415 SmallVector<Register, 4> Factors; 4416 4417 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4418 // Collect low parts of muls for DstIdx. 4419 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4420 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4421 MachineInstrBuilder Mul = 4422 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4423 Factors.push_back(Mul.getReg(0)); 4424 } 4425 // Collect high parts of muls from previous DstIdx. 4426 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4427 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4428 MachineInstrBuilder Umulh = 4429 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4430 Factors.push_back(Umulh.getReg(0)); 4431 } 4432 // Add CarrySum from additions calculated for previous DstIdx. 4433 if (DstIdx != 1) { 4434 Factors.push_back(CarrySumPrevDstIdx); 4435 } 4436 4437 Register CarrySum; 4438 // Add all factors and accumulate all carries into CarrySum. 4439 if (DstIdx != DstParts - 1) { 4440 MachineInstrBuilder Uaddo = 4441 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4442 FactorSum = Uaddo.getReg(0); 4443 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4444 for (unsigned i = 2; i < Factors.size(); ++i) { 4445 MachineInstrBuilder Uaddo = 4446 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4447 FactorSum = Uaddo.getReg(0); 4448 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4449 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4450 } 4451 } else { 4452 // Since value for the next index is not calculated, neither is CarrySum. 4453 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4454 for (unsigned i = 2; i < Factors.size(); ++i) 4455 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4456 } 4457 4458 CarrySumPrevDstIdx = CarrySum; 4459 DstRegs[DstIdx] = FactorSum; 4460 Factors.clear(); 4461 } 4462 } 4463 4464 LegalizerHelper::LegalizeResult 4465 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 4466 Register DstReg = MI.getOperand(0).getReg(); 4467 Register Src1 = MI.getOperand(1).getReg(); 4468 Register Src2 = MI.getOperand(2).getReg(); 4469 4470 LLT Ty = MRI.getType(DstReg); 4471 if (Ty.isVector()) 4472 return UnableToLegalize; 4473 4474 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 4475 unsigned DstSize = Ty.getSizeInBits(); 4476 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4477 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 4478 return UnableToLegalize; 4479 4480 unsigned NumDstParts = DstSize / NarrowSize; 4481 unsigned NumSrcParts = SrcSize / NarrowSize; 4482 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 4483 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 4484 4485 SmallVector<Register, 2> Src1Parts, Src2Parts; 4486 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 4487 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 4488 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 4489 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 4490 4491 // Take only high half of registers if this is high mul. 4492 ArrayRef<Register> DstRegs( 4493 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 4494 MIRBuilder.buildMerge(DstReg, DstRegs); 4495 MI.eraseFromParent(); 4496 return Legalized; 4497 } 4498 4499 LegalizerHelper::LegalizeResult 4500 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 4501 LLT NarrowTy) { 4502 if (TypeIdx != 1) 4503 return UnableToLegalize; 4504 4505 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4506 4507 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 4508 // FIXME: add support for when SizeOp1 isn't an exact multiple of 4509 // NarrowSize. 4510 if (SizeOp1 % NarrowSize != 0) 4511 return UnableToLegalize; 4512 int NumParts = SizeOp1 / NarrowSize; 4513 4514 SmallVector<Register, 2> SrcRegs, DstRegs; 4515 SmallVector<uint64_t, 2> Indexes; 4516 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4517 4518 Register OpReg = MI.getOperand(0).getReg(); 4519 uint64_t OpStart = MI.getOperand(2).getImm(); 4520 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4521 for (int i = 0; i < NumParts; ++i) { 4522 unsigned SrcStart = i * NarrowSize; 4523 4524 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 4525 // No part of the extract uses this subregister, ignore it. 4526 continue; 4527 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4528 // The entire subregister is extracted, forward the value. 4529 DstRegs.push_back(SrcRegs[i]); 4530 continue; 4531 } 4532 4533 // OpSegStart is where this destination segment would start in OpReg if it 4534 // extended infinitely in both directions. 4535 int64_t ExtractOffset; 4536 uint64_t SegSize; 4537 if (OpStart < SrcStart) { 4538 ExtractOffset = 0; 4539 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 4540 } else { 4541 ExtractOffset = OpStart - SrcStart; 4542 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 4543 } 4544 4545 Register SegReg = SrcRegs[i]; 4546 if (ExtractOffset != 0 || SegSize != NarrowSize) { 4547 // A genuine extract is needed. 4548 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4549 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 4550 } 4551 4552 DstRegs.push_back(SegReg); 4553 } 4554 4555 Register DstReg = MI.getOperand(0).getReg(); 4556 if (MRI.getType(DstReg).isVector()) 4557 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4558 else if (DstRegs.size() > 1) 4559 MIRBuilder.buildMerge(DstReg, DstRegs); 4560 else 4561 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 4562 MI.eraseFromParent(); 4563 return Legalized; 4564 } 4565 4566 LegalizerHelper::LegalizeResult 4567 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 4568 LLT NarrowTy) { 4569 // FIXME: Don't know how to handle secondary types yet. 4570 if (TypeIdx != 0) 4571 return UnableToLegalize; 4572 4573 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 4574 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4575 4576 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4577 // NarrowSize. 4578 if (SizeOp0 % NarrowSize != 0) 4579 return UnableToLegalize; 4580 4581 int NumParts = SizeOp0 / NarrowSize; 4582 4583 SmallVector<Register, 2> SrcRegs, DstRegs; 4584 SmallVector<uint64_t, 2> Indexes; 4585 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4586 4587 Register OpReg = MI.getOperand(2).getReg(); 4588 uint64_t OpStart = MI.getOperand(3).getImm(); 4589 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4590 for (int i = 0; i < NumParts; ++i) { 4591 unsigned DstStart = i * NarrowSize; 4592 4593 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 4594 // No part of the insert affects this subregister, forward the original. 4595 DstRegs.push_back(SrcRegs[i]); 4596 continue; 4597 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4598 // The entire subregister is defined by this insert, forward the new 4599 // value. 4600 DstRegs.push_back(OpReg); 4601 continue; 4602 } 4603 4604 // OpSegStart is where this destination segment would start in OpReg if it 4605 // extended infinitely in both directions. 4606 int64_t ExtractOffset, InsertOffset; 4607 uint64_t SegSize; 4608 if (OpStart < DstStart) { 4609 InsertOffset = 0; 4610 ExtractOffset = DstStart - OpStart; 4611 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 4612 } else { 4613 InsertOffset = OpStart - DstStart; 4614 ExtractOffset = 0; 4615 SegSize = 4616 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 4617 } 4618 4619 Register SegReg = OpReg; 4620 if (ExtractOffset != 0 || SegSize != OpSize) { 4621 // A genuine extract is needed. 4622 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4623 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 4624 } 4625 4626 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4627 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset); 4628 DstRegs.push_back(DstReg); 4629 } 4630 4631 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered"); 4632 Register DstReg = MI.getOperand(0).getReg(); 4633 if(MRI.getType(DstReg).isVector()) 4634 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4635 else 4636 MIRBuilder.buildMerge(DstReg, DstRegs); 4637 MI.eraseFromParent(); 4638 return Legalized; 4639 } 4640 4641 LegalizerHelper::LegalizeResult 4642 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 4643 LLT NarrowTy) { 4644 Register DstReg = MI.getOperand(0).getReg(); 4645 LLT DstTy = MRI.getType(DstReg); 4646 4647 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 4648 4649 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4650 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 4651 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4652 LLT LeftoverTy; 4653 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 4654 Src0Regs, Src0LeftoverRegs)) 4655 return UnableToLegalize; 4656 4657 LLT Unused; 4658 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 4659 Src1Regs, Src1LeftoverRegs)) 4660 llvm_unreachable("inconsistent extractParts result"); 4661 4662 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4663 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 4664 {Src0Regs[I], Src1Regs[I]}); 4665 DstRegs.push_back(Inst.getReg(0)); 4666 } 4667 4668 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4669 auto Inst = MIRBuilder.buildInstr( 4670 MI.getOpcode(), 4671 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 4672 DstLeftoverRegs.push_back(Inst.getReg(0)); 4673 } 4674 4675 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4676 LeftoverTy, DstLeftoverRegs); 4677 4678 MI.eraseFromParent(); 4679 return Legalized; 4680 } 4681 4682 LegalizerHelper::LegalizeResult 4683 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 4684 LLT NarrowTy) { 4685 if (TypeIdx != 0) 4686 return UnableToLegalize; 4687 4688 Register DstReg = MI.getOperand(0).getReg(); 4689 Register SrcReg = MI.getOperand(1).getReg(); 4690 4691 LLT DstTy = MRI.getType(DstReg); 4692 if (DstTy.isVector()) 4693 return UnableToLegalize; 4694 4695 SmallVector<Register, 8> Parts; 4696 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4697 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 4698 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4699 4700 MI.eraseFromParent(); 4701 return Legalized; 4702 } 4703 4704 LegalizerHelper::LegalizeResult 4705 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 4706 LLT NarrowTy) { 4707 if (TypeIdx != 0) 4708 return UnableToLegalize; 4709 4710 Register CondReg = MI.getOperand(1).getReg(); 4711 LLT CondTy = MRI.getType(CondReg); 4712 if (CondTy.isVector()) // TODO: Handle vselect 4713 return UnableToLegalize; 4714 4715 Register DstReg = MI.getOperand(0).getReg(); 4716 LLT DstTy = MRI.getType(DstReg); 4717 4718 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4719 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4720 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 4721 LLT LeftoverTy; 4722 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 4723 Src1Regs, Src1LeftoverRegs)) 4724 return UnableToLegalize; 4725 4726 LLT Unused; 4727 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 4728 Src2Regs, Src2LeftoverRegs)) 4729 llvm_unreachable("inconsistent extractParts result"); 4730 4731 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4732 auto Select = MIRBuilder.buildSelect(NarrowTy, 4733 CondReg, Src1Regs[I], Src2Regs[I]); 4734 DstRegs.push_back(Select.getReg(0)); 4735 } 4736 4737 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4738 auto Select = MIRBuilder.buildSelect( 4739 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 4740 DstLeftoverRegs.push_back(Select.getReg(0)); 4741 } 4742 4743 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4744 LeftoverTy, DstLeftoverRegs); 4745 4746 MI.eraseFromParent(); 4747 return Legalized; 4748 } 4749 4750 LegalizerHelper::LegalizeResult 4751 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 4752 LLT NarrowTy) { 4753 if (TypeIdx != 1) 4754 return UnableToLegalize; 4755 4756 Register DstReg = MI.getOperand(0).getReg(); 4757 Register SrcReg = MI.getOperand(1).getReg(); 4758 LLT DstTy = MRI.getType(DstReg); 4759 LLT SrcTy = MRI.getType(SrcReg); 4760 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4761 4762 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4763 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 4764 4765 MachineIRBuilder &B = MIRBuilder; 4766 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4767 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 4768 auto C_0 = B.buildConstant(NarrowTy, 0); 4769 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4770 UnmergeSrc.getReg(1), C_0); 4771 auto LoCTLZ = IsUndef ? 4772 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 4773 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 4774 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4775 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 4776 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 4777 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 4778 4779 MI.eraseFromParent(); 4780 return Legalized; 4781 } 4782 4783 return UnableToLegalize; 4784 } 4785 4786 LegalizerHelper::LegalizeResult 4787 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 4788 LLT NarrowTy) { 4789 if (TypeIdx != 1) 4790 return UnableToLegalize; 4791 4792 Register DstReg = MI.getOperand(0).getReg(); 4793 Register SrcReg = MI.getOperand(1).getReg(); 4794 LLT DstTy = MRI.getType(DstReg); 4795 LLT SrcTy = MRI.getType(SrcReg); 4796 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4797 4798 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4799 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 4800 4801 MachineIRBuilder &B = MIRBuilder; 4802 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4803 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 4804 auto C_0 = B.buildConstant(NarrowTy, 0); 4805 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4806 UnmergeSrc.getReg(0), C_0); 4807 auto HiCTTZ = IsUndef ? 4808 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 4809 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 4810 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4811 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 4812 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 4813 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 4814 4815 MI.eraseFromParent(); 4816 return Legalized; 4817 } 4818 4819 return UnableToLegalize; 4820 } 4821 4822 LegalizerHelper::LegalizeResult 4823 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 4824 LLT NarrowTy) { 4825 if (TypeIdx != 1) 4826 return UnableToLegalize; 4827 4828 Register DstReg = MI.getOperand(0).getReg(); 4829 LLT DstTy = MRI.getType(DstReg); 4830 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 4831 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4832 4833 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4834 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 4835 4836 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 4837 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 4838 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 4839 4840 MI.eraseFromParent(); 4841 return Legalized; 4842 } 4843 4844 return UnableToLegalize; 4845 } 4846 4847 LegalizerHelper::LegalizeResult 4848 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 4849 unsigned Opc = MI.getOpcode(); 4850 const auto &TII = MIRBuilder.getTII(); 4851 auto isSupported = [this](const LegalityQuery &Q) { 4852 auto QAction = LI.getAction(Q).Action; 4853 return QAction == Legal || QAction == Libcall || QAction == Custom; 4854 }; 4855 switch (Opc) { 4856 default: 4857 return UnableToLegalize; 4858 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 4859 // This trivially expands to CTLZ. 4860 Observer.changingInstr(MI); 4861 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 4862 Observer.changedInstr(MI); 4863 return Legalized; 4864 } 4865 case TargetOpcode::G_CTLZ: { 4866 Register DstReg = MI.getOperand(0).getReg(); 4867 Register SrcReg = MI.getOperand(1).getReg(); 4868 LLT DstTy = MRI.getType(DstReg); 4869 LLT SrcTy = MRI.getType(SrcReg); 4870 unsigned Len = SrcTy.getSizeInBits(); 4871 4872 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 4873 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 4874 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 4875 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 4876 auto ICmp = MIRBuilder.buildICmp( 4877 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 4878 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 4879 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 4880 MI.eraseFromParent(); 4881 return Legalized; 4882 } 4883 // for now, we do this: 4884 // NewLen = NextPowerOf2(Len); 4885 // x = x | (x >> 1); 4886 // x = x | (x >> 2); 4887 // ... 4888 // x = x | (x >>16); 4889 // x = x | (x >>32); // for 64-bit input 4890 // Upto NewLen/2 4891 // return Len - popcount(x); 4892 // 4893 // Ref: "Hacker's Delight" by Henry Warren 4894 Register Op = SrcReg; 4895 unsigned NewLen = PowerOf2Ceil(Len); 4896 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 4897 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 4898 auto MIBOp = MIRBuilder.buildOr( 4899 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 4900 Op = MIBOp.getReg(0); 4901 } 4902 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 4903 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 4904 MIBPop); 4905 MI.eraseFromParent(); 4906 return Legalized; 4907 } 4908 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 4909 // This trivially expands to CTTZ. 4910 Observer.changingInstr(MI); 4911 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 4912 Observer.changedInstr(MI); 4913 return Legalized; 4914 } 4915 case TargetOpcode::G_CTTZ: { 4916 Register DstReg = MI.getOperand(0).getReg(); 4917 Register SrcReg = MI.getOperand(1).getReg(); 4918 LLT DstTy = MRI.getType(DstReg); 4919 LLT SrcTy = MRI.getType(SrcReg); 4920 4921 unsigned Len = SrcTy.getSizeInBits(); 4922 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 4923 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 4924 // zero. 4925 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 4926 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 4927 auto ICmp = MIRBuilder.buildICmp( 4928 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 4929 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 4930 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 4931 MI.eraseFromParent(); 4932 return Legalized; 4933 } 4934 // for now, we use: { return popcount(~x & (x - 1)); } 4935 // unless the target has ctlz but not ctpop, in which case we use: 4936 // { return 32 - nlz(~x & (x-1)); } 4937 // Ref: "Hacker's Delight" by Henry Warren 4938 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 4939 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 4940 auto MIBTmp = MIRBuilder.buildAnd( 4941 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 4942 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 4943 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 4944 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 4945 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 4946 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 4947 MI.eraseFromParent(); 4948 return Legalized; 4949 } 4950 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 4951 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 4952 return Legalized; 4953 } 4954 case TargetOpcode::G_CTPOP: { 4955 Register SrcReg = MI.getOperand(1).getReg(); 4956 LLT Ty = MRI.getType(SrcReg); 4957 unsigned Size = Ty.getSizeInBits(); 4958 MachineIRBuilder &B = MIRBuilder; 4959 4960 // Count set bits in blocks of 2 bits. Default approach would be 4961 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 4962 // We use following formula instead: 4963 // B2Count = val - { (val >> 1) & 0x55555555 } 4964 // since it gives same result in blocks of 2 with one instruction less. 4965 auto C_1 = B.buildConstant(Ty, 1); 4966 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 4967 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 4968 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 4969 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 4970 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 4971 4972 // In order to get count in blocks of 4 add values from adjacent block of 2. 4973 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 4974 auto C_2 = B.buildConstant(Ty, 2); 4975 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 4976 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 4977 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 4978 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 4979 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 4980 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 4981 4982 // For count in blocks of 8 bits we don't have to mask high 4 bits before 4983 // addition since count value sits in range {0,...,8} and 4 bits are enough 4984 // to hold such binary values. After addition high 4 bits still hold count 4985 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 4986 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 4987 auto C_4 = B.buildConstant(Ty, 4); 4988 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 4989 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 4990 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 4991 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 4992 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 4993 4994 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 4995 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 4996 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 4997 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 4998 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 4999 5000 // Shift count result from 8 high bits to low bits. 5001 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5002 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5003 5004 MI.eraseFromParent(); 5005 return Legalized; 5006 } 5007 } 5008 } 5009 5010 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5011 // representation. 5012 LegalizerHelper::LegalizeResult 5013 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5014 Register Dst = MI.getOperand(0).getReg(); 5015 Register Src = MI.getOperand(1).getReg(); 5016 const LLT S64 = LLT::scalar(64); 5017 const LLT S32 = LLT::scalar(32); 5018 const LLT S1 = LLT::scalar(1); 5019 5020 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5021 5022 // unsigned cul2f(ulong u) { 5023 // uint lz = clz(u); 5024 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5025 // u = (u << lz) & 0x7fffffffffffffffUL; 5026 // ulong t = u & 0xffffffffffUL; 5027 // uint v = (e << 23) | (uint)(u >> 40); 5028 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5029 // return as_float(v + r); 5030 // } 5031 5032 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5033 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5034 5035 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5036 5037 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5038 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5039 5040 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5041 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5042 5043 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5044 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5045 5046 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5047 5048 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5049 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5050 5051 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5052 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5053 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5054 5055 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5056 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5057 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5058 auto One = MIRBuilder.buildConstant(S32, 1); 5059 5060 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5061 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5062 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5063 MIRBuilder.buildAdd(Dst, V, R); 5064 5065 MI.eraseFromParent(); 5066 return Legalized; 5067 } 5068 5069 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5070 Register Dst = MI.getOperand(0).getReg(); 5071 Register Src = MI.getOperand(1).getReg(); 5072 LLT DstTy = MRI.getType(Dst); 5073 LLT SrcTy = MRI.getType(Src); 5074 5075 if (SrcTy == LLT::scalar(1)) { 5076 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5077 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5078 MIRBuilder.buildSelect(Dst, Src, True, False); 5079 MI.eraseFromParent(); 5080 return Legalized; 5081 } 5082 5083 if (SrcTy != LLT::scalar(64)) 5084 return UnableToLegalize; 5085 5086 if (DstTy == LLT::scalar(32)) { 5087 // TODO: SelectionDAG has several alternative expansions to port which may 5088 // be more reasonble depending on the available instructions. If a target 5089 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5090 // intermediate type, this is probably worse. 5091 return lowerU64ToF32BitOps(MI); 5092 } 5093 5094 return UnableToLegalize; 5095 } 5096 5097 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5098 Register Dst = MI.getOperand(0).getReg(); 5099 Register Src = MI.getOperand(1).getReg(); 5100 LLT DstTy = MRI.getType(Dst); 5101 LLT SrcTy = MRI.getType(Src); 5102 5103 const LLT S64 = LLT::scalar(64); 5104 const LLT S32 = LLT::scalar(32); 5105 const LLT S1 = LLT::scalar(1); 5106 5107 if (SrcTy == S1) { 5108 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5109 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5110 MIRBuilder.buildSelect(Dst, Src, True, False); 5111 MI.eraseFromParent(); 5112 return Legalized; 5113 } 5114 5115 if (SrcTy != S64) 5116 return UnableToLegalize; 5117 5118 if (DstTy == S32) { 5119 // signed cl2f(long l) { 5120 // long s = l >> 63; 5121 // float r = cul2f((l + s) ^ s); 5122 // return s ? -r : r; 5123 // } 5124 Register L = Src; 5125 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5126 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5127 5128 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5129 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5130 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5131 5132 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5133 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5134 MIRBuilder.buildConstant(S64, 0)); 5135 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5136 MI.eraseFromParent(); 5137 return Legalized; 5138 } 5139 5140 return UnableToLegalize; 5141 } 5142 5143 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5144 Register Dst = MI.getOperand(0).getReg(); 5145 Register Src = MI.getOperand(1).getReg(); 5146 LLT DstTy = MRI.getType(Dst); 5147 LLT SrcTy = MRI.getType(Src); 5148 const LLT S64 = LLT::scalar(64); 5149 const LLT S32 = LLT::scalar(32); 5150 5151 if (SrcTy != S64 && SrcTy != S32) 5152 return UnableToLegalize; 5153 if (DstTy != S32 && DstTy != S64) 5154 return UnableToLegalize; 5155 5156 // FPTOSI gives same result as FPTOUI for positive signed integers. 5157 // FPTOUI needs to deal with fp values that convert to unsigned integers 5158 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 5159 5160 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 5161 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 5162 : APFloat::IEEEdouble(), 5163 APInt::getNullValue(SrcTy.getSizeInBits())); 5164 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 5165 5166 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 5167 5168 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 5169 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 5170 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 5171 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 5172 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 5173 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 5174 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 5175 5176 const LLT S1 = LLT::scalar(1); 5177 5178 MachineInstrBuilder FCMP = 5179 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 5180 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 5181 5182 MI.eraseFromParent(); 5183 return Legalized; 5184 } 5185 5186 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 5187 Register Dst = MI.getOperand(0).getReg(); 5188 Register Src = MI.getOperand(1).getReg(); 5189 LLT DstTy = MRI.getType(Dst); 5190 LLT SrcTy = MRI.getType(Src); 5191 const LLT S64 = LLT::scalar(64); 5192 const LLT S32 = LLT::scalar(32); 5193 5194 // FIXME: Only f32 to i64 conversions are supported. 5195 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 5196 return UnableToLegalize; 5197 5198 // Expand f32 -> i64 conversion 5199 // This algorithm comes from compiler-rt's implementation of fixsfdi: 5200 // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c 5201 5202 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 5203 5204 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 5205 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 5206 5207 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 5208 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 5209 5210 auto SignMask = MIRBuilder.buildConstant(SrcTy, 5211 APInt::getSignMask(SrcEltBits)); 5212 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 5213 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 5214 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 5215 Sign = MIRBuilder.buildSExt(DstTy, Sign); 5216 5217 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 5218 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 5219 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 5220 5221 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 5222 R = MIRBuilder.buildZExt(DstTy, R); 5223 5224 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 5225 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 5226 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 5227 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 5228 5229 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 5230 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 5231 5232 const LLT S1 = LLT::scalar(1); 5233 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 5234 S1, Exponent, ExponentLoBit); 5235 5236 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 5237 5238 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 5239 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 5240 5241 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 5242 5243 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 5244 S1, Exponent, ZeroSrcTy); 5245 5246 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 5247 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 5248 5249 MI.eraseFromParent(); 5250 return Legalized; 5251 } 5252 5253 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 5254 LegalizerHelper::LegalizeResult 5255 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 5256 Register Dst = MI.getOperand(0).getReg(); 5257 Register Src = MI.getOperand(1).getReg(); 5258 5259 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 5260 return UnableToLegalize; 5261 5262 const unsigned ExpMask = 0x7ff; 5263 const unsigned ExpBiasf64 = 1023; 5264 const unsigned ExpBiasf16 = 15; 5265 const LLT S32 = LLT::scalar(32); 5266 const LLT S1 = LLT::scalar(1); 5267 5268 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 5269 Register U = Unmerge.getReg(0); 5270 Register UH = Unmerge.getReg(1); 5271 5272 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 5273 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 5274 5275 // Subtract the fp64 exponent bias (1023) to get the real exponent and 5276 // add the f16 bias (15) to get the biased exponent for the f16 format. 5277 E = MIRBuilder.buildAdd( 5278 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 5279 5280 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 5281 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 5282 5283 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 5284 MIRBuilder.buildConstant(S32, 0x1ff)); 5285 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 5286 5287 auto Zero = MIRBuilder.buildConstant(S32, 0); 5288 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 5289 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 5290 M = MIRBuilder.buildOr(S32, M, Lo40Set); 5291 5292 // (M != 0 ? 0x0200 : 0) | 0x7c00; 5293 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 5294 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 5295 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 5296 5297 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 5298 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 5299 5300 // N = M | (E << 12); 5301 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 5302 auto N = MIRBuilder.buildOr(S32, M, EShl12); 5303 5304 // B = clamp(1-E, 0, 13); 5305 auto One = MIRBuilder.buildConstant(S32, 1); 5306 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 5307 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 5308 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 5309 5310 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 5311 MIRBuilder.buildConstant(S32, 0x1000)); 5312 5313 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 5314 auto D0 = MIRBuilder.buildShl(S32, D, B); 5315 5316 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 5317 D0, SigSetHigh); 5318 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 5319 D = MIRBuilder.buildOr(S32, D, D1); 5320 5321 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 5322 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 5323 5324 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 5325 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 5326 5327 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 5328 MIRBuilder.buildConstant(S32, 3)); 5329 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 5330 5331 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 5332 MIRBuilder.buildConstant(S32, 5)); 5333 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 5334 5335 V1 = MIRBuilder.buildOr(S32, V0, V1); 5336 V = MIRBuilder.buildAdd(S32, V, V1); 5337 5338 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 5339 E, MIRBuilder.buildConstant(S32, 30)); 5340 V = MIRBuilder.buildSelect(S32, CmpEGt30, 5341 MIRBuilder.buildConstant(S32, 0x7c00), V); 5342 5343 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 5344 E, MIRBuilder.buildConstant(S32, 1039)); 5345 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 5346 5347 // Extract the sign bit. 5348 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 5349 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 5350 5351 // Insert the sign bit 5352 V = MIRBuilder.buildOr(S32, Sign, V); 5353 5354 MIRBuilder.buildTrunc(Dst, V); 5355 MI.eraseFromParent(); 5356 return Legalized; 5357 } 5358 5359 LegalizerHelper::LegalizeResult 5360 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 5361 Register Dst = MI.getOperand(0).getReg(); 5362 Register Src = MI.getOperand(1).getReg(); 5363 5364 LLT DstTy = MRI.getType(Dst); 5365 LLT SrcTy = MRI.getType(Src); 5366 const LLT S64 = LLT::scalar(64); 5367 const LLT S16 = LLT::scalar(16); 5368 5369 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 5370 return lowerFPTRUNC_F64_TO_F16(MI); 5371 5372 return UnableToLegalize; 5373 } 5374 5375 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 5376 // multiplication tree. 5377 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 5378 Register Dst = MI.getOperand(0).getReg(); 5379 Register Src0 = MI.getOperand(1).getReg(); 5380 Register Src1 = MI.getOperand(2).getReg(); 5381 LLT Ty = MRI.getType(Dst); 5382 5383 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 5384 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 5385 MI.eraseFromParent(); 5386 return Legalized; 5387 } 5388 5389 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 5390 switch (Opc) { 5391 case TargetOpcode::G_SMIN: 5392 return CmpInst::ICMP_SLT; 5393 case TargetOpcode::G_SMAX: 5394 return CmpInst::ICMP_SGT; 5395 case TargetOpcode::G_UMIN: 5396 return CmpInst::ICMP_ULT; 5397 case TargetOpcode::G_UMAX: 5398 return CmpInst::ICMP_UGT; 5399 default: 5400 llvm_unreachable("not in integer min/max"); 5401 } 5402 } 5403 5404 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 5405 Register Dst = MI.getOperand(0).getReg(); 5406 Register Src0 = MI.getOperand(1).getReg(); 5407 Register Src1 = MI.getOperand(2).getReg(); 5408 5409 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 5410 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 5411 5412 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 5413 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 5414 5415 MI.eraseFromParent(); 5416 return Legalized; 5417 } 5418 5419 LegalizerHelper::LegalizeResult 5420 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 5421 Register Dst = MI.getOperand(0).getReg(); 5422 Register Src0 = MI.getOperand(1).getReg(); 5423 Register Src1 = MI.getOperand(2).getReg(); 5424 5425 const LLT Src0Ty = MRI.getType(Src0); 5426 const LLT Src1Ty = MRI.getType(Src1); 5427 5428 const int Src0Size = Src0Ty.getScalarSizeInBits(); 5429 const int Src1Size = Src1Ty.getScalarSizeInBits(); 5430 5431 auto SignBitMask = MIRBuilder.buildConstant( 5432 Src0Ty, APInt::getSignMask(Src0Size)); 5433 5434 auto NotSignBitMask = MIRBuilder.buildConstant( 5435 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 5436 5437 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask); 5438 MachineInstr *Or; 5439 5440 if (Src0Ty == Src1Ty) { 5441 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask); 5442 Or = MIRBuilder.buildOr(Dst, And0, And1); 5443 } else if (Src0Size > Src1Size) { 5444 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 5445 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 5446 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 5447 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask); 5448 Or = MIRBuilder.buildOr(Dst, And0, And1); 5449 } else { 5450 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 5451 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 5452 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 5453 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask); 5454 Or = MIRBuilder.buildOr(Dst, And0, And1); 5455 } 5456 5457 // Be careful about setting nsz/nnan/ninf on every instruction, since the 5458 // constants are a nan and -0.0, but the final result should preserve 5459 // everything. 5460 if (unsigned Flags = MI.getFlags()) 5461 Or->setFlags(Flags); 5462 5463 MI.eraseFromParent(); 5464 return Legalized; 5465 } 5466 5467 LegalizerHelper::LegalizeResult 5468 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 5469 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 5470 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 5471 5472 Register Dst = MI.getOperand(0).getReg(); 5473 Register Src0 = MI.getOperand(1).getReg(); 5474 Register Src1 = MI.getOperand(2).getReg(); 5475 LLT Ty = MRI.getType(Dst); 5476 5477 if (!MI.getFlag(MachineInstr::FmNoNans)) { 5478 // Insert canonicalizes if it's possible we need to quiet to get correct 5479 // sNaN behavior. 5480 5481 // Note this must be done here, and not as an optimization combine in the 5482 // absence of a dedicate quiet-snan instruction as we're using an 5483 // omni-purpose G_FCANONICALIZE. 5484 if (!isKnownNeverSNaN(Src0, MRI)) 5485 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 5486 5487 if (!isKnownNeverSNaN(Src1, MRI)) 5488 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 5489 } 5490 5491 // If there are no nans, it's safe to simply replace this with the non-IEEE 5492 // version. 5493 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 5494 MI.eraseFromParent(); 5495 return Legalized; 5496 } 5497 5498 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 5499 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 5500 Register DstReg = MI.getOperand(0).getReg(); 5501 LLT Ty = MRI.getType(DstReg); 5502 unsigned Flags = MI.getFlags(); 5503 5504 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 5505 Flags); 5506 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 5507 MI.eraseFromParent(); 5508 return Legalized; 5509 } 5510 5511 LegalizerHelper::LegalizeResult 5512 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 5513 Register DstReg = MI.getOperand(0).getReg(); 5514 Register X = MI.getOperand(1).getReg(); 5515 const unsigned Flags = MI.getFlags(); 5516 const LLT Ty = MRI.getType(DstReg); 5517 const LLT CondTy = Ty.changeElementSize(1); 5518 5519 // round(x) => 5520 // t = trunc(x); 5521 // d = fabs(x - t); 5522 // o = copysign(1.0f, x); 5523 // return t + (d >= 0.5 ? o : 0.0); 5524 5525 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 5526 5527 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 5528 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 5529 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5530 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 5531 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 5532 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 5533 5534 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 5535 Flags); 5536 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 5537 5538 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 5539 5540 MI.eraseFromParent(); 5541 return Legalized; 5542 } 5543 5544 LegalizerHelper::LegalizeResult 5545 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 5546 Register DstReg = MI.getOperand(0).getReg(); 5547 Register SrcReg = MI.getOperand(1).getReg(); 5548 unsigned Flags = MI.getFlags(); 5549 LLT Ty = MRI.getType(DstReg); 5550 const LLT CondTy = Ty.changeElementSize(1); 5551 5552 // result = trunc(src); 5553 // if (src < 0.0 && src != result) 5554 // result += -1.0. 5555 5556 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 5557 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5558 5559 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 5560 SrcReg, Zero, Flags); 5561 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 5562 SrcReg, Trunc, Flags); 5563 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 5564 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 5565 5566 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 5567 MI.eraseFromParent(); 5568 return Legalized; 5569 } 5570 5571 LegalizerHelper::LegalizeResult 5572 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 5573 const unsigned NumOps = MI.getNumOperands(); 5574 Register DstReg = MI.getOperand(0).getReg(); 5575 Register Src0Reg = MI.getOperand(1).getReg(); 5576 LLT DstTy = MRI.getType(DstReg); 5577 LLT SrcTy = MRI.getType(Src0Reg); 5578 unsigned PartSize = SrcTy.getSizeInBits(); 5579 5580 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 5581 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 5582 5583 for (unsigned I = 2; I != NumOps; ++I) { 5584 const unsigned Offset = (I - 1) * PartSize; 5585 5586 Register SrcReg = MI.getOperand(I).getReg(); 5587 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 5588 5589 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 5590 MRI.createGenericVirtualRegister(WideTy); 5591 5592 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 5593 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 5594 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 5595 ResultReg = NextResult; 5596 } 5597 5598 if (DstTy.isPointer()) { 5599 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 5600 DstTy.getAddressSpace())) { 5601 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 5602 return UnableToLegalize; 5603 } 5604 5605 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 5606 } 5607 5608 MI.eraseFromParent(); 5609 return Legalized; 5610 } 5611 5612 LegalizerHelper::LegalizeResult 5613 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 5614 const unsigned NumDst = MI.getNumOperands() - 1; 5615 Register SrcReg = MI.getOperand(NumDst).getReg(); 5616 Register Dst0Reg = MI.getOperand(0).getReg(); 5617 LLT DstTy = MRI.getType(Dst0Reg); 5618 if (DstTy.isPointer()) 5619 return UnableToLegalize; // TODO 5620 5621 SrcReg = coerceToScalar(SrcReg); 5622 if (!SrcReg) 5623 return UnableToLegalize; 5624 5625 // Expand scalarizing unmerge as bitcast to integer and shift. 5626 LLT IntTy = MRI.getType(SrcReg); 5627 5628 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 5629 5630 const unsigned DstSize = DstTy.getSizeInBits(); 5631 unsigned Offset = DstSize; 5632 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 5633 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 5634 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 5635 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 5636 } 5637 5638 MI.eraseFromParent(); 5639 return Legalized; 5640 } 5641 5642 /// Lower a vector extract or insert by writing the vector to a stack temporary 5643 /// and reloading the element or vector. 5644 /// 5645 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 5646 /// => 5647 /// %stack_temp = G_FRAME_INDEX 5648 /// G_STORE %vec, %stack_temp 5649 /// %idx = clamp(%idx, %vec.getNumElements()) 5650 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 5651 /// %dst = G_LOAD %element_ptr 5652 LegalizerHelper::LegalizeResult 5653 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 5654 Register DstReg = MI.getOperand(0).getReg(); 5655 Register SrcVec = MI.getOperand(1).getReg(); 5656 Register InsertVal; 5657 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 5658 InsertVal = MI.getOperand(2).getReg(); 5659 5660 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 5661 5662 LLT VecTy = MRI.getType(SrcVec); 5663 LLT EltTy = VecTy.getElementType(); 5664 if (!EltTy.isByteSized()) { // Not implemented. 5665 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 5666 return UnableToLegalize; 5667 } 5668 5669 unsigned EltBytes = EltTy.getSizeInBytes(); 5670 Align VecAlign = getStackTemporaryAlignment(VecTy); 5671 Align EltAlign; 5672 5673 MachinePointerInfo PtrInfo; 5674 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 5675 VecAlign, PtrInfo); 5676 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 5677 5678 // Get the pointer to the element, and be sure not to hit undefined behavior 5679 // if the index is out of bounds. 5680 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 5681 5682 int64_t IdxVal; 5683 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 5684 int64_t Offset = IdxVal * EltBytes; 5685 PtrInfo = PtrInfo.getWithOffset(Offset); 5686 EltAlign = commonAlignment(VecAlign, Offset); 5687 } else { 5688 // We lose information with a variable offset. 5689 EltAlign = getStackTemporaryAlignment(EltTy); 5690 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 5691 } 5692 5693 if (InsertVal) { 5694 // Write the inserted element 5695 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 5696 5697 // Reload the whole vector. 5698 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 5699 } else { 5700 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 5701 } 5702 5703 MI.eraseFromParent(); 5704 return Legalized; 5705 } 5706 5707 LegalizerHelper::LegalizeResult 5708 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 5709 Register DstReg = MI.getOperand(0).getReg(); 5710 Register Src0Reg = MI.getOperand(1).getReg(); 5711 Register Src1Reg = MI.getOperand(2).getReg(); 5712 LLT Src0Ty = MRI.getType(Src0Reg); 5713 LLT DstTy = MRI.getType(DstReg); 5714 LLT IdxTy = LLT::scalar(32); 5715 5716 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 5717 5718 if (DstTy.isScalar()) { 5719 if (Src0Ty.isVector()) 5720 return UnableToLegalize; 5721 5722 // This is just a SELECT. 5723 assert(Mask.size() == 1 && "Expected a single mask element"); 5724 Register Val; 5725 if (Mask[0] < 0 || Mask[0] > 1) 5726 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 5727 else 5728 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 5729 MIRBuilder.buildCopy(DstReg, Val); 5730 MI.eraseFromParent(); 5731 return Legalized; 5732 } 5733 5734 Register Undef; 5735 SmallVector<Register, 32> BuildVec; 5736 LLT EltTy = DstTy.getElementType(); 5737 5738 for (int Idx : Mask) { 5739 if (Idx < 0) { 5740 if (!Undef.isValid()) 5741 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 5742 BuildVec.push_back(Undef); 5743 continue; 5744 } 5745 5746 if (Src0Ty.isScalar()) { 5747 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 5748 } else { 5749 int NumElts = Src0Ty.getNumElements(); 5750 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 5751 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 5752 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 5753 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 5754 BuildVec.push_back(Extract.getReg(0)); 5755 } 5756 } 5757 5758 MIRBuilder.buildBuildVector(DstReg, BuildVec); 5759 MI.eraseFromParent(); 5760 return Legalized; 5761 } 5762 5763 LegalizerHelper::LegalizeResult 5764 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 5765 const auto &MF = *MI.getMF(); 5766 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 5767 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 5768 return UnableToLegalize; 5769 5770 Register Dst = MI.getOperand(0).getReg(); 5771 Register AllocSize = MI.getOperand(1).getReg(); 5772 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 5773 5774 LLT PtrTy = MRI.getType(Dst); 5775 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 5776 5777 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 5778 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 5779 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 5780 5781 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 5782 // have to generate an extra instruction to negate the alloc and then use 5783 // G_PTR_ADD to add the negative offset. 5784 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 5785 if (Alignment > Align(1)) { 5786 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 5787 AlignMask.negate(); 5788 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 5789 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 5790 } 5791 5792 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 5793 MIRBuilder.buildCopy(SPReg, SPTmp); 5794 MIRBuilder.buildCopy(Dst, SPTmp); 5795 5796 MI.eraseFromParent(); 5797 return Legalized; 5798 } 5799 5800 LegalizerHelper::LegalizeResult 5801 LegalizerHelper::lowerExtract(MachineInstr &MI) { 5802 Register Dst = MI.getOperand(0).getReg(); 5803 Register Src = MI.getOperand(1).getReg(); 5804 unsigned Offset = MI.getOperand(2).getImm(); 5805 5806 LLT DstTy = MRI.getType(Dst); 5807 LLT SrcTy = MRI.getType(Src); 5808 5809 if (DstTy.isScalar() && 5810 (SrcTy.isScalar() || 5811 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 5812 LLT SrcIntTy = SrcTy; 5813 if (!SrcTy.isScalar()) { 5814 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 5815 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 5816 } 5817 5818 if (Offset == 0) 5819 MIRBuilder.buildTrunc(Dst, Src); 5820 else { 5821 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 5822 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 5823 MIRBuilder.buildTrunc(Dst, Shr); 5824 } 5825 5826 MI.eraseFromParent(); 5827 return Legalized; 5828 } 5829 5830 return UnableToLegalize; 5831 } 5832 5833 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 5834 Register Dst = MI.getOperand(0).getReg(); 5835 Register Src = MI.getOperand(1).getReg(); 5836 Register InsertSrc = MI.getOperand(2).getReg(); 5837 uint64_t Offset = MI.getOperand(3).getImm(); 5838 5839 LLT DstTy = MRI.getType(Src); 5840 LLT InsertTy = MRI.getType(InsertSrc); 5841 5842 if (InsertTy.isVector() || 5843 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 5844 return UnableToLegalize; 5845 5846 const DataLayout &DL = MIRBuilder.getDataLayout(); 5847 if ((DstTy.isPointer() && 5848 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 5849 (InsertTy.isPointer() && 5850 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 5851 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 5852 return UnableToLegalize; 5853 } 5854 5855 LLT IntDstTy = DstTy; 5856 5857 if (!DstTy.isScalar()) { 5858 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 5859 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 5860 } 5861 5862 if (!InsertTy.isScalar()) { 5863 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 5864 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 5865 } 5866 5867 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 5868 if (Offset != 0) { 5869 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 5870 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 5871 } 5872 5873 APInt MaskVal = APInt::getBitsSetWithWrap( 5874 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 5875 5876 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 5877 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 5878 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 5879 5880 MIRBuilder.buildCast(Dst, Or); 5881 MI.eraseFromParent(); 5882 return Legalized; 5883 } 5884 5885 LegalizerHelper::LegalizeResult 5886 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 5887 Register Dst0 = MI.getOperand(0).getReg(); 5888 Register Dst1 = MI.getOperand(1).getReg(); 5889 Register LHS = MI.getOperand(2).getReg(); 5890 Register RHS = MI.getOperand(3).getReg(); 5891 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 5892 5893 LLT Ty = MRI.getType(Dst0); 5894 LLT BoolTy = MRI.getType(Dst1); 5895 5896 if (IsAdd) 5897 MIRBuilder.buildAdd(Dst0, LHS, RHS); 5898 else 5899 MIRBuilder.buildSub(Dst0, LHS, RHS); 5900 5901 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 5902 5903 auto Zero = MIRBuilder.buildConstant(Ty, 0); 5904 5905 // For an addition, the result should be less than one of the operands (LHS) 5906 // if and only if the other operand (RHS) is negative, otherwise there will 5907 // be overflow. 5908 // For a subtraction, the result should be less than one of the operands 5909 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 5910 // otherwise there will be overflow. 5911 auto ResultLowerThanLHS = 5912 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 5913 auto ConditionRHS = MIRBuilder.buildICmp( 5914 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 5915 5916 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 5917 MI.eraseFromParent(); 5918 return Legalized; 5919 } 5920 5921 LegalizerHelper::LegalizeResult 5922 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 5923 Register Res = MI.getOperand(0).getReg(); 5924 Register LHS = MI.getOperand(1).getReg(); 5925 Register RHS = MI.getOperand(2).getReg(); 5926 LLT Ty = MRI.getType(Res); 5927 bool IsSigned; 5928 bool IsAdd; 5929 unsigned BaseOp; 5930 switch (MI.getOpcode()) { 5931 default: 5932 llvm_unreachable("unexpected addsat/subsat opcode"); 5933 case TargetOpcode::G_UADDSAT: 5934 IsSigned = false; 5935 IsAdd = true; 5936 BaseOp = TargetOpcode::G_ADD; 5937 break; 5938 case TargetOpcode::G_SADDSAT: 5939 IsSigned = true; 5940 IsAdd = true; 5941 BaseOp = TargetOpcode::G_ADD; 5942 break; 5943 case TargetOpcode::G_USUBSAT: 5944 IsSigned = false; 5945 IsAdd = false; 5946 BaseOp = TargetOpcode::G_SUB; 5947 break; 5948 case TargetOpcode::G_SSUBSAT: 5949 IsSigned = true; 5950 IsAdd = false; 5951 BaseOp = TargetOpcode::G_SUB; 5952 break; 5953 } 5954 5955 if (IsSigned) { 5956 // sadd.sat(a, b) -> 5957 // hi = 0x7fffffff - smax(a, 0) 5958 // lo = 0x80000000 - smin(a, 0) 5959 // a + smin(smax(lo, b), hi) 5960 // ssub.sat(a, b) -> 5961 // lo = smax(a, -1) - 0x7fffffff 5962 // hi = smin(a, -1) - 0x80000000 5963 // a - smin(smax(lo, b), hi) 5964 // TODO: AMDGPU can use a "median of 3" instruction here: 5965 // a +/- med3(lo, b, hi) 5966 uint64_t NumBits = Ty.getScalarSizeInBits(); 5967 auto MaxVal = 5968 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 5969 auto MinVal = 5970 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 5971 MachineInstrBuilder Hi, Lo; 5972 if (IsAdd) { 5973 auto Zero = MIRBuilder.buildConstant(Ty, 0); 5974 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 5975 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 5976 } else { 5977 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 5978 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 5979 MaxVal); 5980 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 5981 MinVal); 5982 } 5983 auto RHSClamped = 5984 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 5985 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 5986 } else { 5987 // uadd.sat(a, b) -> a + umin(~a, b) 5988 // usub.sat(a, b) -> a - umin(a, b) 5989 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 5990 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 5991 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 5992 } 5993 5994 MI.eraseFromParent(); 5995 return Legalized; 5996 } 5997 5998 LegalizerHelper::LegalizeResult 5999 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6000 Register Res = MI.getOperand(0).getReg(); 6001 Register LHS = MI.getOperand(1).getReg(); 6002 Register RHS = MI.getOperand(2).getReg(); 6003 LLT Ty = MRI.getType(Res); 6004 LLT BoolTy = Ty.changeElementSize(1); 6005 bool IsSigned; 6006 bool IsAdd; 6007 unsigned OverflowOp; 6008 switch (MI.getOpcode()) { 6009 default: 6010 llvm_unreachable("unexpected addsat/subsat opcode"); 6011 case TargetOpcode::G_UADDSAT: 6012 IsSigned = false; 6013 IsAdd = true; 6014 OverflowOp = TargetOpcode::G_UADDO; 6015 break; 6016 case TargetOpcode::G_SADDSAT: 6017 IsSigned = true; 6018 IsAdd = true; 6019 OverflowOp = TargetOpcode::G_SADDO; 6020 break; 6021 case TargetOpcode::G_USUBSAT: 6022 IsSigned = false; 6023 IsAdd = false; 6024 OverflowOp = TargetOpcode::G_USUBO; 6025 break; 6026 case TargetOpcode::G_SSUBSAT: 6027 IsSigned = true; 6028 IsAdd = false; 6029 OverflowOp = TargetOpcode::G_SSUBO; 6030 break; 6031 } 6032 6033 auto OverflowRes = 6034 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6035 Register Tmp = OverflowRes.getReg(0); 6036 Register Ov = OverflowRes.getReg(1); 6037 MachineInstrBuilder Clamp; 6038 if (IsSigned) { 6039 // sadd.sat(a, b) -> 6040 // {tmp, ov} = saddo(a, b) 6041 // ov ? (tmp >>s 31) + 0x80000000 : r 6042 // ssub.sat(a, b) -> 6043 // {tmp, ov} = ssubo(a, b) 6044 // ov ? (tmp >>s 31) + 0x80000000 : r 6045 uint64_t NumBits = Ty.getScalarSizeInBits(); 6046 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6047 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6048 auto MinVal = 6049 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6050 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6051 } else { 6052 // uadd.sat(a, b) -> 6053 // {tmp, ov} = uaddo(a, b) 6054 // ov ? 0xffffffff : tmp 6055 // usub.sat(a, b) -> 6056 // {tmp, ov} = usubo(a, b) 6057 // ov ? 0 : tmp 6058 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6059 } 6060 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6061 6062 MI.eraseFromParent(); 6063 return Legalized; 6064 } 6065 6066 LegalizerHelper::LegalizeResult 6067 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6068 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6069 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6070 "Expected shlsat opcode!"); 6071 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6072 Register Res = MI.getOperand(0).getReg(); 6073 Register LHS = MI.getOperand(1).getReg(); 6074 Register RHS = MI.getOperand(2).getReg(); 6075 LLT Ty = MRI.getType(Res); 6076 LLT BoolTy = Ty.changeElementSize(1); 6077 6078 unsigned BW = Ty.getScalarSizeInBits(); 6079 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6080 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6081 : MIRBuilder.buildLShr(Ty, Result, RHS); 6082 6083 MachineInstrBuilder SatVal; 6084 if (IsSigned) { 6085 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6086 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6087 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6088 MIRBuilder.buildConstant(Ty, 0)); 6089 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6090 } else { 6091 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6092 } 6093 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6094 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6095 6096 MI.eraseFromParent(); 6097 return Legalized; 6098 } 6099 6100 LegalizerHelper::LegalizeResult 6101 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6102 Register Dst = MI.getOperand(0).getReg(); 6103 Register Src = MI.getOperand(1).getReg(); 6104 const LLT Ty = MRI.getType(Src); 6105 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6106 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6107 6108 // Swap most and least significant byte, set remaining bytes in Res to zero. 6109 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6110 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6111 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6112 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6113 6114 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6115 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6116 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6117 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6118 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6119 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6120 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6121 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6122 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6123 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6124 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6125 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6126 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6127 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6128 } 6129 Res.getInstr()->getOperand(0).setReg(Dst); 6130 6131 MI.eraseFromParent(); 6132 return Legalized; 6133 } 6134 6135 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6136 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6137 MachineInstrBuilder Src, APInt Mask) { 6138 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6139 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6140 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6141 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6142 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6143 return B.buildOr(Dst, LHS, RHS); 6144 } 6145 6146 LegalizerHelper::LegalizeResult 6147 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6148 Register Dst = MI.getOperand(0).getReg(); 6149 Register Src = MI.getOperand(1).getReg(); 6150 const LLT Ty = MRI.getType(Src); 6151 unsigned Size = Ty.getSizeInBits(); 6152 6153 MachineInstrBuilder BSWAP = 6154 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 6155 6156 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 6157 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 6158 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 6159 MachineInstrBuilder Swap4 = 6160 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 6161 6162 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 6163 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 6164 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 6165 MachineInstrBuilder Swap2 = 6166 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 6167 6168 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 6169 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 6170 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 6171 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 6172 6173 MI.eraseFromParent(); 6174 return Legalized; 6175 } 6176 6177 LegalizerHelper::LegalizeResult 6178 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 6179 MachineFunction &MF = MIRBuilder.getMF(); 6180 6181 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 6182 int NameOpIdx = IsRead ? 1 : 0; 6183 int ValRegIndex = IsRead ? 0 : 1; 6184 6185 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 6186 const LLT Ty = MRI.getType(ValReg); 6187 const MDString *RegStr = cast<MDString>( 6188 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 6189 6190 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 6191 if (!PhysReg.isValid()) 6192 return UnableToLegalize; 6193 6194 if (IsRead) 6195 MIRBuilder.buildCopy(ValReg, PhysReg); 6196 else 6197 MIRBuilder.buildCopy(PhysReg, ValReg); 6198 6199 MI.eraseFromParent(); 6200 return Legalized; 6201 } 6202 6203 LegalizerHelper::LegalizeResult 6204 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 6205 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 6206 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 6207 Register Result = MI.getOperand(0).getReg(); 6208 LLT OrigTy = MRI.getType(Result); 6209 auto SizeInBits = OrigTy.getScalarSizeInBits(); 6210 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 6211 6212 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 6213 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 6214 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 6215 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 6216 6217 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 6218 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 6219 MIRBuilder.buildTrunc(Result, Shifted); 6220 6221 MI.eraseFromParent(); 6222 return Legalized; 6223 } 6224 6225 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 6226 // Implement vector G_SELECT in terms of XOR, AND, OR. 6227 Register DstReg = MI.getOperand(0).getReg(); 6228 Register MaskReg = MI.getOperand(1).getReg(); 6229 Register Op1Reg = MI.getOperand(2).getReg(); 6230 Register Op2Reg = MI.getOperand(3).getReg(); 6231 LLT DstTy = MRI.getType(DstReg); 6232 LLT MaskTy = MRI.getType(MaskReg); 6233 LLT Op1Ty = MRI.getType(Op1Reg); 6234 if (!DstTy.isVector()) 6235 return UnableToLegalize; 6236 6237 // Vector selects can have a scalar predicate. If so, splat into a vector and 6238 // finish for later legalization attempts to try again. 6239 if (MaskTy.isScalar()) { 6240 Register MaskElt = MaskReg; 6241 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 6242 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 6243 // Generate a vector splat idiom to be pattern matched later. 6244 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 6245 Observer.changingInstr(MI); 6246 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 6247 Observer.changedInstr(MI); 6248 return Legalized; 6249 } 6250 6251 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 6252 return UnableToLegalize; 6253 } 6254 6255 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 6256 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 6257 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 6258 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 6259 MI.eraseFromParent(); 6260 return Legalized; 6261 } 6262