1 //===-- lib/CodeGen/GlobalISel/InlineAsmLowering.cpp ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file implements the lowering from LLVM IR inline asm to MIR INLINEASM 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h" 15 #include "llvm/CodeGen/Analysis.h" 16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 17 #include "llvm/CodeGen/GlobalISel/Utils.h" 18 #include "llvm/CodeGen/MachineOperand.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/IR/Instructions.h" 23 #include "llvm/IR/LLVMContext.h" 24 #include "llvm/IR/Module.h" 25 26 #define DEBUG_TYPE "inline-asm-lowering" 27 28 using namespace llvm; 29 30 void InlineAsmLowering::anchor() {} 31 32 namespace { 33 34 /// GISelAsmOperandInfo - This contains information for each constraint that we 35 /// are lowering. 36 class GISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 37 public: 38 /// Regs - If this is a register or register class operand, this 39 /// contains the set of assigned registers corresponding to the operand. 40 SmallVector<Register, 1> Regs; 41 42 explicit GISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &Info) 43 : TargetLowering::AsmOperandInfo(Info) {} 44 }; 45 46 using GISelAsmOperandInfoVector = SmallVector<GISelAsmOperandInfo, 16>; 47 48 class ExtraFlags { 49 unsigned Flags = 0; 50 51 public: 52 explicit ExtraFlags(const CallBase &CB) { 53 const InlineAsm *IA = cast<InlineAsm>(CB.getCalledOperand()); 54 if (IA->hasSideEffects()) 55 Flags |= InlineAsm::Extra_HasSideEffects; 56 if (IA->isAlignStack()) 57 Flags |= InlineAsm::Extra_IsAlignStack; 58 if (CB.isConvergent()) 59 Flags |= InlineAsm::Extra_IsConvergent; 60 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 61 } 62 63 void update(const TargetLowering::AsmOperandInfo &OpInfo) { 64 // Ideally, we would only check against memory constraints. However, the 65 // meaning of an Other constraint can be target-specific and we can't easily 66 // reason about it. Therefore, be conservative and set MayLoad/MayStore 67 // for Other constraints as well. 68 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 69 OpInfo.ConstraintType == TargetLowering::C_Other) { 70 if (OpInfo.Type == InlineAsm::isInput) 71 Flags |= InlineAsm::Extra_MayLoad; 72 else if (OpInfo.Type == InlineAsm::isOutput) 73 Flags |= InlineAsm::Extra_MayStore; 74 else if (OpInfo.Type == InlineAsm::isClobber) 75 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 76 } 77 } 78 79 unsigned get() const { return Flags; } 80 }; 81 82 } // namespace 83 84 /// Assign virtual/physical registers for the specified register operand. 85 static void getRegistersForValue(MachineFunction &MF, 86 MachineIRBuilder &MIRBuilder, 87 GISelAsmOperandInfo &OpInfo, 88 GISelAsmOperandInfo &RefOpInfo) { 89 90 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering(); 91 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 92 93 // No work to do for memory operations. 94 if (OpInfo.ConstraintType == TargetLowering::C_Memory) 95 return; 96 97 // If this is a constraint for a single physreg, or a constraint for a 98 // register class, find it. 99 Register AssignedReg; 100 const TargetRegisterClass *RC; 101 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( 102 &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT); 103 // RC is unset only on failure. Return immediately. 104 if (!RC) 105 return; 106 107 // No need to allocate a matching input constraint since the constraint it's 108 // matching to has already been allocated. 109 if (OpInfo.isMatchingInputConstraint()) 110 return; 111 112 // Initialize NumRegs. 113 unsigned NumRegs = 1; 114 if (OpInfo.ConstraintVT != MVT::Other) 115 NumRegs = 116 TLI.getNumRegisters(MF.getFunction().getContext(), OpInfo.ConstraintVT); 117 118 // If this is a constraint for a specific physical register, but the type of 119 // the operand requires more than one register to be passed, we allocate the 120 // required amount of physical registers, starting from the selected physical 121 // register. 122 // For this, first retrieve a register iterator for the given register class 123 TargetRegisterClass::iterator I = RC->begin(); 124 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 125 126 // Advance the iterator to the assigned register (if set) 127 if (AssignedReg) { 128 for (; *I != AssignedReg; ++I) 129 assert(I != RC->end() && "AssignedReg should be a member of provided RC"); 130 } 131 132 // Finally, assign the registers. If the AssignedReg isn't set, create virtual 133 // registers with the provided register class 134 for (; NumRegs; --NumRegs, ++I) { 135 assert(I != RC->end() && "Ran out of registers to allocate!"); 136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); 137 OpInfo.Regs.push_back(R); 138 } 139 } 140 141 /// Return an integer indicating how general CT is. 142 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 143 switch (CT) { 144 case TargetLowering::C_Immediate: 145 case TargetLowering::C_Other: 146 case TargetLowering::C_Unknown: 147 return 0; 148 case TargetLowering::C_Register: 149 return 1; 150 case TargetLowering::C_RegisterClass: 151 return 2; 152 case TargetLowering::C_Memory: 153 return 3; 154 } 155 llvm_unreachable("Invalid constraint type"); 156 } 157 158 static void chooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 159 const TargetLowering *TLI) { 160 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 161 unsigned BestIdx = 0; 162 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 163 int BestGenerality = -1; 164 165 // Loop over the options, keeping track of the most general one. 166 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 167 TargetLowering::ConstraintType CType = 168 TLI->getConstraintType(OpInfo.Codes[i]); 169 170 // Indirect 'other' or 'immediate' constraints are not allowed. 171 if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory || 172 CType == TargetLowering::C_Register || 173 CType == TargetLowering::C_RegisterClass)) 174 continue; 175 176 // If this is an 'other' or 'immediate' constraint, see if the operand is 177 // valid for it. For example, on X86 we might have an 'rI' constraint. If 178 // the operand is an integer in the range [0..31] we want to use I (saving a 179 // load of a register), otherwise we must use 'r'. 180 if (CType == TargetLowering::C_Other || 181 CType == TargetLowering::C_Immediate) { 182 assert(OpInfo.Codes[i].size() == 1 && 183 "Unhandled multi-letter 'other' constraint"); 184 // FIXME: prefer immediate constraints if the target allows it 185 } 186 187 // Things with matching constraints can only be registers, per gcc 188 // documentation. This mainly affects "g" constraints. 189 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 190 continue; 191 192 // This constraint letter is more general than the previous one, use it. 193 int Generality = getConstraintGenerality(CType); 194 if (Generality > BestGenerality) { 195 BestType = CType; 196 BestIdx = i; 197 BestGenerality = Generality; 198 } 199 } 200 201 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 202 OpInfo.ConstraintType = BestType; 203 } 204 205 static void computeConstraintToUse(const TargetLowering *TLI, 206 TargetLowering::AsmOperandInfo &OpInfo) { 207 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 208 209 // Single-letter constraints ('r') are very common. 210 if (OpInfo.Codes.size() == 1) { 211 OpInfo.ConstraintCode = OpInfo.Codes[0]; 212 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode); 213 } else { 214 chooseConstraint(OpInfo, TLI); 215 } 216 217 // 'X' matches anything. 218 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 219 // Labels and constants are handled elsewhere ('X' is the only thing 220 // that matches labels). For Functions, the type here is the type of 221 // the result, which is not what we want to look at; leave them alone. 222 Value *Val = OpInfo.CallOperandVal; 223 if (isa<BasicBlock>(Val) || isa<ConstantInt>(Val) || isa<Function>(Val)) 224 return; 225 226 // Otherwise, try to resolve it to something we know about by looking at 227 // the actual operand type. 228 if (const char *Repl = TLI->LowerXConstraint(OpInfo.ConstraintVT)) { 229 OpInfo.ConstraintCode = Repl; 230 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode); 231 } 232 } 233 } 234 235 static unsigned getNumOpRegs(const MachineInstr &I, unsigned OpIdx) { 236 unsigned Flag = I.getOperand(OpIdx).getImm(); 237 return InlineAsm::getNumOperandRegisters(Flag); 238 } 239 240 static bool buildAnyextOrCopy(Register Dst, Register Src, 241 MachineIRBuilder &MIRBuilder) { 242 const TargetRegisterInfo *TRI = 243 MIRBuilder.getMF().getSubtarget().getRegisterInfo(); 244 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 245 246 auto SrcTy = MRI->getType(Src); 247 if (!SrcTy.isValid()) { 248 LLVM_DEBUG(dbgs() << "Source type for copy is not valid\n"); 249 return false; 250 } 251 unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI); 252 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI); 253 254 if (DstSize < SrcSize) { 255 LLVM_DEBUG(dbgs() << "Input can't fit in destination reg class\n"); 256 return false; 257 } 258 259 // Attempt to anyext small scalar sources. 260 if (DstSize > SrcSize) { 261 if (!SrcTy.isScalar()) { 262 LLVM_DEBUG(dbgs() << "Can't extend non-scalar input to size of" 263 "destination register class\n"); 264 return false; 265 } 266 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0); 267 } 268 269 MIRBuilder.buildCopy(Dst, Src); 270 return true; 271 } 272 273 bool InlineAsmLowering::lowerInlineAsm( 274 MachineIRBuilder &MIRBuilder, const CallBase &Call, 275 std::function<ArrayRef<Register>(const Value &Val)> GetOrCreateVRegs) 276 const { 277 const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand()); 278 279 /// ConstraintOperands - Information about all of the constraints. 280 GISelAsmOperandInfoVector ConstraintOperands; 281 282 MachineFunction &MF = MIRBuilder.getMF(); 283 const Function &F = MF.getFunction(); 284 const DataLayout &DL = F.getParent()->getDataLayout(); 285 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 286 287 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 288 289 TargetLowering::AsmOperandInfoVector TargetConstraints = 290 TLI->ParseConstraints(DL, TRI, Call); 291 292 ExtraFlags ExtraInfo(Call); 293 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 294 unsigned ResNo = 0; // ResNo - The result number of the next output. 295 for (auto &T : TargetConstraints) { 296 ConstraintOperands.push_back(GISelAsmOperandInfo(T)); 297 GISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 298 299 // Compute the value type for each operand. 300 if (OpInfo.Type == InlineAsm::isInput || 301 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) { 302 303 OpInfo.CallOperandVal = const_cast<Value *>(Call.getArgOperand(ArgNo++)); 304 305 if (isa<BasicBlock>(OpInfo.CallOperandVal)) { 306 LLVM_DEBUG(dbgs() << "Basic block input operands not supported yet\n"); 307 return false; 308 } 309 310 Type *OpTy = OpInfo.CallOperandVal->getType(); 311 312 // If this is an indirect operand, the operand is a pointer to the 313 // accessed type. 314 if (OpInfo.isIndirect) { 315 PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 316 if (!PtrTy) 317 report_fatal_error("Indirect operand for inline asm not a pointer!"); 318 OpTy = PtrTy->getElementType(); 319 } 320 321 // FIXME: Support aggregate input operands 322 if (!OpTy->isSingleValueType()) { 323 LLVM_DEBUG( 324 dbgs() << "Aggregate input operands are not supported yet\n"); 325 return false; 326 } 327 328 OpInfo.ConstraintVT = TLI->getValueType(DL, OpTy, true).getSimpleVT(); 329 330 } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) { 331 assert(!Call.getType()->isVoidTy() && "Bad inline asm!"); 332 if (StructType *STy = dyn_cast<StructType>(Call.getType())) { 333 OpInfo.ConstraintVT = 334 TLI->getSimpleValueType(DL, STy->getElementType(ResNo)); 335 } else { 336 assert(ResNo == 0 && "Asm only has one result!"); 337 OpInfo.ConstraintVT = TLI->getSimpleValueType(DL, Call.getType()); 338 } 339 ++ResNo; 340 } else { 341 OpInfo.ConstraintVT = MVT::Other; 342 } 343 344 // Compute the constraint code and ConstraintType to use. 345 computeConstraintToUse(TLI, OpInfo); 346 347 // The selected constraint type might expose new sideeffects 348 ExtraInfo.update(OpInfo); 349 } 350 351 // At this point, all operand types are decided. 352 // Create the MachineInstr, but don't insert it yet since input 353 // operands still need to insert instructions before this one 354 auto Inst = MIRBuilder.buildInstrNoInsert(TargetOpcode::INLINEASM) 355 .addExternalSymbol(IA->getAsmString().c_str()) 356 .addImm(ExtraInfo.get()); 357 358 // Starting from this operand: flag followed by register(s) will be added as 359 // operands to Inst for each constraint. Used for matching input constraints. 360 unsigned StartIdx = Inst->getNumOperands(); 361 362 // Collects the output operands for later processing 363 GISelAsmOperandInfoVector OutputOperands; 364 365 for (auto &OpInfo : ConstraintOperands) { 366 GISelAsmOperandInfo &RefOpInfo = 367 OpInfo.isMatchingInputConstraint() 368 ? ConstraintOperands[OpInfo.getMatchedOperand()] 369 : OpInfo; 370 371 // Assign registers for register operands 372 getRegistersForValue(MF, MIRBuilder, OpInfo, RefOpInfo); 373 374 switch (OpInfo.Type) { 375 case InlineAsm::isOutput: 376 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 377 unsigned ConstraintID = 378 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode); 379 assert(ConstraintID != InlineAsm::Constraint_Unknown && 380 "Failed to convert memory constraint code to constraint id."); 381 382 // Add information to the INLINEASM instruction to know about this 383 // output. 384 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 385 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); 386 Inst.addImm(OpFlags); 387 ArrayRef<Register> SourceRegs = 388 GetOrCreateVRegs(*OpInfo.CallOperandVal); 389 assert( 390 SourceRegs.size() == 1 && 391 "Expected the memory output to fit into a single virtual register"); 392 Inst.addReg(SourceRegs[0]); 393 } else { 394 // Otherwise, this outputs to a register (directly for C_Register / 395 // C_RegisterClass. Find a register that we can use. 396 assert(OpInfo.ConstraintType == TargetLowering::C_Register || 397 OpInfo.ConstraintType == TargetLowering::C_RegisterClass); 398 399 if (OpInfo.Regs.empty()) { 400 LLVM_DEBUG(dbgs() 401 << "Couldn't allocate output register for constraint\n"); 402 return false; 403 } 404 405 // Add information to the INLINEASM instruction to know that this 406 // register is set. 407 unsigned Flag = InlineAsm::getFlagWord( 408 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber 409 : InlineAsm::Kind_RegDef, 410 OpInfo.Regs.size()); 411 if (OpInfo.Regs.front().isVirtual()) { 412 // Put the register class of the virtual registers in the flag word. 413 // That way, later passes can recompute register class constraints for 414 // inline assembly as well as normal instructions. Don't do this for 415 // tied operands that can use the regclass information from the def. 416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); 417 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 418 } 419 420 Inst.addImm(Flag); 421 422 for (Register Reg : OpInfo.Regs) { 423 Inst.addReg(Reg, 424 RegState::Define | getImplRegState(Reg.isPhysical()) | 425 (OpInfo.isEarlyClobber ? RegState::EarlyClobber : 0)); 426 } 427 428 // Remember this output operand for later processing 429 OutputOperands.push_back(OpInfo); 430 } 431 432 break; 433 case InlineAsm::isInput: { 434 if (OpInfo.isMatchingInputConstraint()) { 435 unsigned DefIdx = OpInfo.getMatchedOperand(); 436 // Find operand with register def that corresponds to DefIdx. 437 unsigned InstFlagIdx = StartIdx; 438 for (unsigned i = 0; i < DefIdx; ++i) 439 InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1; 440 assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag"); 441 442 unsigned MatchedOperandFlag = Inst->getOperand(InstFlagIdx).getImm(); 443 if (InlineAsm::isMemKind(MatchedOperandFlag)) { 444 LLVM_DEBUG(dbgs() << "Matching input constraint to mem operand not " 445 "supported. This should be target specific.\n"); 446 return false; 447 } 448 if (!InlineAsm::isRegDefKind(MatchedOperandFlag) && 449 !InlineAsm::isRegDefEarlyClobberKind(MatchedOperandFlag)) { 450 LLVM_DEBUG(dbgs() << "Unknown matching constraint\n"); 451 return false; 452 } 453 454 // We want to tie input to register in next operand. 455 unsigned DefRegIdx = InstFlagIdx + 1; 456 Register Def = Inst->getOperand(DefRegIdx).getReg(); 457 458 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); 459 assert(SrcRegs.size() == 1 && "Single register is expected here"); 460 461 // When Def is physreg: use given input. 462 Register In = SrcRegs[0]; 463 // When Def is vreg: copy input to new vreg with same reg class as Def. 464 if (Def.isVirtual()) { 465 In = MRI->createVirtualRegister(MRI->getRegClass(Def)); 466 if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) 467 return false; 468 } 469 470 // Add Flag and input register operand (In) to Inst. Tie In to Def. 471 unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1); 472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx); 473 Inst.addImm(Flag); 474 Inst.addReg(In); 475 Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1); 476 break; 477 } 478 479 if (OpInfo.ConstraintType == TargetLowering::C_Other && 480 OpInfo.isIndirect) { 481 LLVM_DEBUG(dbgs() << "Indirect input operands with unknown constraint " 482 "not supported yet\n"); 483 return false; 484 } 485 486 if (OpInfo.ConstraintType == TargetLowering::C_Immediate || 487 OpInfo.ConstraintType == TargetLowering::C_Other) { 488 489 std::vector<MachineOperand> Ops; 490 if (!lowerAsmOperandForConstraint(OpInfo.CallOperandVal, 491 OpInfo.ConstraintCode, Ops, 492 MIRBuilder)) { 493 LLVM_DEBUG(dbgs() << "Don't support constraint: " 494 << OpInfo.ConstraintCode << " yet\n"); 495 return false; 496 } 497 498 assert(Ops.size() > 0 && 499 "Expected constraint to be lowered to at least one operand"); 500 501 // Add information to the INLINEASM node to know about this input. 502 unsigned OpFlags = 503 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 504 Inst.addImm(OpFlags); 505 Inst.add(Ops); 506 break; 507 } 508 509 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 510 511 if (!OpInfo.isIndirect) { 512 LLVM_DEBUG(dbgs() 513 << "Cannot indirectify memory input operands yet\n"); 514 return false; 515 } 516 517 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 518 519 unsigned ConstraintID = 520 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode); 521 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 522 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); 523 Inst.addImm(OpFlags); 524 ArrayRef<Register> SourceRegs = 525 GetOrCreateVRegs(*OpInfo.CallOperandVal); 526 assert( 527 SourceRegs.size() == 1 && 528 "Expected the memory input to fit into a single virtual register"); 529 Inst.addReg(SourceRegs[0]); 530 break; 531 } 532 533 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 534 OpInfo.ConstraintType == TargetLowering::C_Register) && 535 "Unknown constraint type!"); 536 537 if (OpInfo.isIndirect) { 538 LLVM_DEBUG(dbgs() << "Can't handle indirect register inputs yet " 539 "for constraint '" 540 << OpInfo.ConstraintCode << "'\n"); 541 return false; 542 } 543 544 // Copy the input into the appropriate registers. 545 if (OpInfo.Regs.empty()) { 546 LLVM_DEBUG( 547 dbgs() 548 << "Couldn't allocate input register for register constraint\n"); 549 return false; 550 } 551 552 unsigned NumRegs = OpInfo.Regs.size(); 553 ArrayRef<Register> SourceRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); 554 assert(NumRegs == SourceRegs.size() && 555 "Expected the number of input registers to match the number of " 556 "source registers"); 557 558 if (NumRegs > 1) { 559 LLVM_DEBUG(dbgs() << "Input operands with multiple input registers are " 560 "not supported yet\n"); 561 return false; 562 } 563 564 unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs); 565 Inst.addImm(Flag); 566 if (!buildAnyextOrCopy(OpInfo.Regs[0], SourceRegs[0], MIRBuilder)) 567 return false; 568 Inst.addReg(OpInfo.Regs[0]); 569 break; 570 } 571 572 case InlineAsm::isClobber: { 573 574 unsigned NumRegs = OpInfo.Regs.size(); 575 if (NumRegs > 0) { 576 unsigned Flag = 577 InlineAsm::getFlagWord(InlineAsm::Kind_Clobber, NumRegs); 578 Inst.addImm(Flag); 579 580 for (Register Reg : OpInfo.Regs) { 581 Inst.addReg(Reg, RegState::Define | RegState::EarlyClobber | 582 getImplRegState(Reg.isPhysical())); 583 } 584 } 585 break; 586 } 587 } 588 } 589 590 if (const MDNode *SrcLoc = Call.getMetadata("srcloc")) 591 Inst.addMetadata(SrcLoc); 592 593 // All inputs are handled, insert the instruction now 594 MIRBuilder.insertInstr(Inst); 595 596 // Finally, copy the output operands into the output registers 597 ArrayRef<Register> ResRegs = GetOrCreateVRegs(Call); 598 if (ResRegs.size() != OutputOperands.size()) { 599 LLVM_DEBUG(dbgs() << "Expected the number of output registers to match the " 600 "number of destination registers\n"); 601 return false; 602 } 603 for (unsigned int i = 0, e = ResRegs.size(); i < e; i++) { 604 GISelAsmOperandInfo &OpInfo = OutputOperands[i]; 605 606 if (OpInfo.Regs.empty()) 607 continue; 608 609 switch (OpInfo.ConstraintType) { 610 case TargetLowering::C_Register: 611 case TargetLowering::C_RegisterClass: { 612 if (OpInfo.Regs.size() > 1) { 613 LLVM_DEBUG(dbgs() << "Output operands with multiple defining " 614 "registers are not supported yet\n"); 615 return false; 616 } 617 618 Register SrcReg = OpInfo.Regs[0]; 619 unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); 620 if (MRI->getType(ResRegs[i]).getSizeInBits() < SrcSize) { 621 // First copy the non-typed virtual register into a generic virtual 622 // register 623 Register Tmp1Reg = 624 MRI->createGenericVirtualRegister(LLT::scalar(SrcSize)); 625 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); 626 // Need to truncate the result of the register 627 MIRBuilder.buildTrunc(ResRegs[i], Tmp1Reg); 628 } else { 629 MIRBuilder.buildCopy(ResRegs[i], SrcReg); 630 } 631 break; 632 } 633 case TargetLowering::C_Immediate: 634 case TargetLowering::C_Other: 635 LLVM_DEBUG( 636 dbgs() << "Cannot lower target specific output constraints yet\n"); 637 return false; 638 case TargetLowering::C_Memory: 639 break; // Already handled. 640 case TargetLowering::C_Unknown: 641 LLVM_DEBUG(dbgs() << "Unexpected unknown constraint\n"); 642 return false; 643 } 644 } 645 646 return true; 647 } 648 649 bool InlineAsmLowering::lowerAsmOperandForConstraint( 650 Value *Val, StringRef Constraint, std::vector<MachineOperand> &Ops, 651 MachineIRBuilder &MIRBuilder) const { 652 if (Constraint.size() > 1) 653 return false; 654 655 char ConstraintLetter = Constraint[0]; 656 switch (ConstraintLetter) { 657 default: 658 return false; 659 case 'i': // Simple Integer or Relocatable Constant 660 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 661 assert(CI->getBitWidth() <= 64 && 662 "expected immediate to fit into 64-bits"); 663 // Boolean constants should be zero-extended, others are sign-extended 664 bool IsBool = CI->getBitWidth() == 1; 665 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); 666 Ops.push_back(MachineOperand::CreateImm(ExtVal)); 667 return true; 668 } 669 return false; 670 } 671 } 672