1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains support for writing dwarf debug info into asm files. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "DwarfExpression.h" 14 #include "DwarfCompileUnit.h" 15 #include "llvm/ADT/APInt.h" 16 #include "llvm/ADT/SmallBitVector.h" 17 #include "llvm/BinaryFormat/Dwarf.h" 18 #include "llvm/CodeGen/TargetRegisterInfo.h" 19 #include "llvm/IR/DebugInfoMetadata.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <algorithm> 22 #include <cassert> 23 #include <cstdint> 24 25 using namespace llvm; 26 27 void DwarfExpression::emitConstu(uint64_t Value) { 28 if (Value < 32) 29 emitOp(dwarf::DW_OP_lit0 + Value); 30 else if (Value == std::numeric_limits<uint64_t>::max()) { 31 // Only do this for 64-bit values as the DWARF expression stack uses 32 // target-address-size values. 33 emitOp(dwarf::DW_OP_lit0); 34 emitOp(dwarf::DW_OP_not); 35 } else { 36 emitOp(dwarf::DW_OP_constu); 37 emitUnsigned(Value); 38 } 39 } 40 41 void DwarfExpression::addReg(int DwarfReg, const char *Comment) { 42 assert(DwarfReg >= 0 && "invalid negative dwarf register number"); 43 assert((isUnknownLocation() || isRegisterLocation()) && 44 "location description already locked down"); 45 LocationKind = Register; 46 if (DwarfReg < 32) { 47 emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment); 48 } else { 49 emitOp(dwarf::DW_OP_regx, Comment); 50 emitUnsigned(DwarfReg); 51 } 52 } 53 54 void DwarfExpression::addBReg(int DwarfReg, int Offset) { 55 assert(DwarfReg >= 0 && "invalid negative dwarf register number"); 56 assert(!isRegisterLocation() && "location description already locked down"); 57 if (DwarfReg < 32) { 58 emitOp(dwarf::DW_OP_breg0 + DwarfReg); 59 } else { 60 emitOp(dwarf::DW_OP_bregx); 61 emitUnsigned(DwarfReg); 62 } 63 emitSigned(Offset); 64 } 65 66 void DwarfExpression::addFBReg(int Offset) { 67 emitOp(dwarf::DW_OP_fbreg); 68 emitSigned(Offset); 69 } 70 71 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) { 72 if (!SizeInBits) 73 return; 74 75 const unsigned SizeOfByte = 8; 76 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) { 77 emitOp(dwarf::DW_OP_bit_piece); 78 emitUnsigned(SizeInBits); 79 emitUnsigned(OffsetInBits); 80 } else { 81 emitOp(dwarf::DW_OP_piece); 82 unsigned ByteSize = SizeInBits / SizeOfByte; 83 emitUnsigned(ByteSize); 84 } 85 this->OffsetInBits += SizeInBits; 86 } 87 88 void DwarfExpression::addShr(unsigned ShiftBy) { 89 emitConstu(ShiftBy); 90 emitOp(dwarf::DW_OP_shr); 91 } 92 93 void DwarfExpression::addAnd(unsigned Mask) { 94 emitConstu(Mask); 95 emitOp(dwarf::DW_OP_and); 96 } 97 98 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI, 99 unsigned MachineReg, unsigned MaxSize) { 100 if (!TRI.isPhysicalRegister(MachineReg)) { 101 if (isFrameRegister(TRI, MachineReg)) { 102 DwarfRegs.push_back({-1, 0, nullptr}); 103 return true; 104 } 105 return false; 106 } 107 108 int Reg = TRI.getDwarfRegNum(MachineReg, false); 109 110 // If this is a valid register number, emit it. 111 if (Reg >= 0) { 112 DwarfRegs.push_back({Reg, 0, nullptr}); 113 return true; 114 } 115 116 // Walk up the super-register chain until we find a valid number. 117 // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0. 118 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { 119 Reg = TRI.getDwarfRegNum(*SR, false); 120 if (Reg >= 0) { 121 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); 122 unsigned Size = TRI.getSubRegIdxSize(Idx); 123 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); 124 DwarfRegs.push_back({Reg, 0, "super-register"}); 125 // Use a DW_OP_bit_piece to describe the sub-register. 126 setSubRegisterPiece(Size, RegOffset); 127 return true; 128 } 129 } 130 131 // Otherwise, attempt to find a covering set of sub-register numbers. 132 // For example, Q0 on ARM is a composition of D0+D1. 133 unsigned CurPos = 0; 134 // The size of the register in bits. 135 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); 136 unsigned RegSize = TRI.getRegSizeInBits(*RC); 137 // Keep track of the bits in the register we already emitted, so we 138 // can avoid emitting redundant aliasing subregs. Because this is 139 // just doing a greedy scan of all subregisters, it is possible that 140 // this doesn't find a combination of subregisters that fully cover 141 // the register (even though one may exist). 142 SmallBitVector Coverage(RegSize, false); 143 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { 144 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); 145 unsigned Size = TRI.getSubRegIdxSize(Idx); 146 unsigned Offset = TRI.getSubRegIdxOffset(Idx); 147 Reg = TRI.getDwarfRegNum(*SR, false); 148 if (Reg < 0) 149 continue; 150 151 // Intersection between the bits we already emitted and the bits 152 // covered by this subregister. 153 SmallBitVector CurSubReg(RegSize, false); 154 CurSubReg.set(Offset, Offset + Size); 155 156 // If this sub-register has a DWARF number and we haven't covered 157 // its range, emit a DWARF piece for it. 158 if (CurSubReg.test(Coverage)) { 159 // Emit a piece for any gap in the coverage. 160 if (Offset > CurPos) 161 DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"}); 162 DwarfRegs.push_back( 163 {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"}); 164 if (Offset >= MaxSize) 165 break; 166 167 // Mark it as emitted. 168 Coverage.set(Offset, Offset + Size); 169 CurPos = Offset + Size; 170 } 171 } 172 // Failed to find any DWARF encoding. 173 if (CurPos == 0) 174 return false; 175 // Found a partial or complete DWARF encoding. 176 if (CurPos < RegSize) 177 DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"}); 178 return true; 179 } 180 181 void DwarfExpression::addStackValue() { 182 if (DwarfVersion >= 4) 183 emitOp(dwarf::DW_OP_stack_value); 184 } 185 186 void DwarfExpression::addSignedConstant(int64_t Value) { 187 assert(isImplicitLocation() || isUnknownLocation()); 188 LocationKind = Implicit; 189 emitOp(dwarf::DW_OP_consts); 190 emitSigned(Value); 191 } 192 193 void DwarfExpression::addUnsignedConstant(uint64_t Value) { 194 assert(isImplicitLocation() || isUnknownLocation()); 195 LocationKind = Implicit; 196 emitConstu(Value); 197 } 198 199 void DwarfExpression::addUnsignedConstant(const APInt &Value) { 200 assert(isImplicitLocation() || isUnknownLocation()); 201 LocationKind = Implicit; 202 203 unsigned Size = Value.getBitWidth(); 204 const uint64_t *Data = Value.getRawData(); 205 206 // Chop it up into 64-bit pieces, because that's the maximum that 207 // addUnsignedConstant takes. 208 unsigned Offset = 0; 209 while (Offset < Size) { 210 addUnsignedConstant(*Data++); 211 if (Offset == 0 && Size <= 64) 212 break; 213 addStackValue(); 214 addOpPiece(std::min(Size - Offset, 64u), Offset); 215 Offset += 64; 216 } 217 } 218 219 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI, 220 DIExpressionCursor &ExprCursor, 221 unsigned MachineReg, 222 unsigned FragmentOffsetInBits) { 223 auto Fragment = ExprCursor.getFragmentInfo(); 224 if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) { 225 LocationKind = Unknown; 226 return false; 227 } 228 229 bool HasComplexExpression = false; 230 auto Op = ExprCursor.peek(); 231 if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment) 232 HasComplexExpression = true; 233 234 // If the register can only be described by a complex expression (i.e., 235 // multiple subregisters) it doesn't safely compose with another complex 236 // expression. For example, it is not possible to apply a DW_OP_deref 237 // operation to multiple DW_OP_pieces. 238 if (HasComplexExpression && DwarfRegs.size() > 1) { 239 DwarfRegs.clear(); 240 LocationKind = Unknown; 241 return false; 242 } 243 244 // Handle simple register locations. 245 if (!isMemoryLocation() && !HasComplexExpression) { 246 for (auto &Reg : DwarfRegs) { 247 if (Reg.DwarfRegNo >= 0) 248 addReg(Reg.DwarfRegNo, Reg.Comment); 249 addOpPiece(Reg.Size); 250 } 251 252 if (isEntryValue() && DwarfVersion >= 4) 253 emitOp(dwarf::DW_OP_stack_value); 254 255 DwarfRegs.clear(); 256 return true; 257 } 258 259 // Don't emit locations that cannot be expressed without DW_OP_stack_value. 260 if (DwarfVersion < 4) 261 if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool { 262 return Op.getOp() == dwarf::DW_OP_stack_value; 263 })) { 264 DwarfRegs.clear(); 265 LocationKind = Unknown; 266 return false; 267 } 268 269 assert(DwarfRegs.size() == 1); 270 auto Reg = DwarfRegs[0]; 271 bool FBReg = isFrameRegister(TRI, MachineReg); 272 int SignedOffset = 0; 273 assert(Reg.Size == 0 && "subregister has same size as superregister"); 274 275 // Pattern-match combinations for which more efficient representations exist. 276 // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset]. 277 if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) { 278 SignedOffset = Op->getArg(0); 279 ExprCursor.take(); 280 } 281 282 // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset] 283 // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset] 284 // If Reg is a subregister we need to mask it out before subtracting. 285 if (Op && Op->getOp() == dwarf::DW_OP_constu) { 286 auto N = ExprCursor.peekNext(); 287 if (N && (N->getOp() == dwarf::DW_OP_plus || 288 (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) { 289 int Offset = Op->getArg(0); 290 SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset; 291 ExprCursor.consume(2); 292 } 293 } 294 295 if (FBReg) 296 addFBReg(SignedOffset); 297 else 298 addBReg(Reg.DwarfRegNo, SignedOffset); 299 DwarfRegs.clear(); 300 return true; 301 } 302 303 void DwarfExpression::addEntryValueExpression(DIExpressionCursor &ExprCursor) { 304 auto Op = ExprCursor.take(); 305 assert(Op && Op->getOp() == dwarf::DW_OP_entry_value); 306 assert(!isMemoryLocation() && 307 "We don't support entry values of memory locations yet"); 308 309 if (DwarfVersion >= 5) 310 emitOp(dwarf::DW_OP_entry_value); 311 else 312 emitOp(dwarf::DW_OP_GNU_entry_value); 313 emitUnsigned(Op->getArg(0)); 314 } 315 316 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?". 317 static bool isMemoryLocation(DIExpressionCursor ExprCursor) { 318 while (ExprCursor) { 319 auto Op = ExprCursor.take(); 320 switch (Op->getOp()) { 321 case dwarf::DW_OP_deref: 322 case dwarf::DW_OP_LLVM_fragment: 323 break; 324 default: 325 return false; 326 } 327 } 328 return true; 329 } 330 331 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor, 332 unsigned FragmentOffsetInBits) { 333 // If we need to mask out a subregister, do it now, unless the next 334 // operation would emit an OpPiece anyway. 335 auto N = ExprCursor.peek(); 336 if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment)) 337 maskSubRegister(); 338 339 Optional<DIExpression::ExprOperand> PrevConvertOp = None; 340 341 while (ExprCursor) { 342 auto Op = ExprCursor.take(); 343 switch (Op->getOp()) { 344 case dwarf::DW_OP_LLVM_fragment: { 345 unsigned SizeInBits = Op->getArg(1); 346 unsigned FragmentOffset = Op->getArg(0); 347 // The fragment offset must have already been adjusted by emitting an 348 // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base 349 // location. 350 assert(OffsetInBits >= FragmentOffset && "fragment offset not added?"); 351 352 // If addMachineReg already emitted DW_OP_piece operations to represent 353 // a super-register by splicing together sub-registers, subtract the size 354 // of the pieces that was already emitted. 355 SizeInBits -= OffsetInBits - FragmentOffset; 356 357 // If addMachineReg requested a DW_OP_bit_piece to stencil out a 358 // sub-register that is smaller than the current fragment's size, use it. 359 if (SubRegisterSizeInBits) 360 SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits); 361 362 // Emit a DW_OP_stack_value for implicit location descriptions. 363 if (isImplicitLocation()) 364 addStackValue(); 365 366 // Emit the DW_OP_piece. 367 addOpPiece(SizeInBits, SubRegisterOffsetInBits); 368 setSubRegisterPiece(0, 0); 369 // Reset the location description kind. 370 LocationKind = Unknown; 371 return; 372 } 373 case dwarf::DW_OP_plus_uconst: 374 assert(!isRegisterLocation()); 375 emitOp(dwarf::DW_OP_plus_uconst); 376 emitUnsigned(Op->getArg(0)); 377 break; 378 case dwarf::DW_OP_plus: 379 case dwarf::DW_OP_minus: 380 case dwarf::DW_OP_mul: 381 case dwarf::DW_OP_div: 382 case dwarf::DW_OP_mod: 383 case dwarf::DW_OP_or: 384 case dwarf::DW_OP_and: 385 case dwarf::DW_OP_xor: 386 case dwarf::DW_OP_shl: 387 case dwarf::DW_OP_shr: 388 case dwarf::DW_OP_shra: 389 case dwarf::DW_OP_lit0: 390 case dwarf::DW_OP_not: 391 case dwarf::DW_OP_dup: 392 emitOp(Op->getOp()); 393 break; 394 case dwarf::DW_OP_deref: 395 assert(!isRegisterLocation()); 396 if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor)) 397 // Turning this into a memory location description makes the deref 398 // implicit. 399 LocationKind = Memory; 400 else 401 emitOp(dwarf::DW_OP_deref); 402 break; 403 case dwarf::DW_OP_constu: 404 assert(!isRegisterLocation()); 405 emitConstu(Op->getArg(0)); 406 break; 407 case dwarf::DW_OP_LLVM_convert: { 408 unsigned BitSize = Op->getArg(0); 409 dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1)); 410 if (DwarfVersion >= 5) { 411 emitOp(dwarf::DW_OP_convert); 412 // Reuse the base_type if we already have one in this CU otherwise we 413 // create a new one. 414 unsigned I = 0, E = CU.ExprRefedBaseTypes.size(); 415 for (; I != E; ++I) 416 if (CU.ExprRefedBaseTypes[I].BitSize == BitSize && 417 CU.ExprRefedBaseTypes[I].Encoding == Encoding) 418 break; 419 420 if (I == E) 421 CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding); 422 423 // If targeting a location-list; simply emit the index into the raw 424 // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been 425 // fitted with means to extract it later. 426 // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef 427 // (containing the index and a resolve mechanism during emit) into the 428 // DIE value list. 429 emitBaseTypeRef(I); 430 } else { 431 if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) { 432 if (Encoding == dwarf::DW_ATE_signed) 433 emitLegacySExt(PrevConvertOp->getArg(0)); 434 else if (Encoding == dwarf::DW_ATE_unsigned) 435 emitLegacyZExt(PrevConvertOp->getArg(0)); 436 PrevConvertOp = None; 437 } else { 438 PrevConvertOp = Op; 439 } 440 } 441 break; 442 } 443 case dwarf::DW_OP_stack_value: 444 LocationKind = Implicit; 445 break; 446 case dwarf::DW_OP_swap: 447 assert(!isRegisterLocation()); 448 emitOp(dwarf::DW_OP_swap); 449 break; 450 case dwarf::DW_OP_xderef: 451 assert(!isRegisterLocation()); 452 emitOp(dwarf::DW_OP_xderef); 453 break; 454 case dwarf::DW_OP_deref_size: 455 emitOp(dwarf::DW_OP_deref_size); 456 emitData1(Op->getArg(0)); 457 break; 458 case dwarf::DW_OP_LLVM_tag_offset: 459 TagOffset = Op->getArg(0); 460 break; 461 default: 462 llvm_unreachable("unhandled opcode found in expression"); 463 } 464 } 465 466 if (isImplicitLocation()) 467 // Turn this into an implicit location description. 468 addStackValue(); 469 } 470 471 /// add masking operations to stencil out a subregister. 472 void DwarfExpression::maskSubRegister() { 473 assert(SubRegisterSizeInBits && "no subregister was registered"); 474 if (SubRegisterOffsetInBits > 0) 475 addShr(SubRegisterOffsetInBits); 476 uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL; 477 addAnd(Mask); 478 } 479 480 void DwarfExpression::finalize() { 481 assert(DwarfRegs.size() == 0 && "dwarf registers not emitted"); 482 // Emit any outstanding DW_OP_piece operations to mask out subregisters. 483 if (SubRegisterSizeInBits == 0) 484 return; 485 // Don't emit a DW_OP_piece for a subregister at offset 0. 486 if (SubRegisterOffsetInBits == 0) 487 return; 488 addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); 489 } 490 491 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) { 492 if (!Expr || !Expr->isFragment()) 493 return; 494 495 uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits; 496 assert(FragmentOffset >= OffsetInBits && 497 "overlapping or duplicate fragments"); 498 if (FragmentOffset > OffsetInBits) 499 addOpPiece(FragmentOffset - OffsetInBits); 500 OffsetInBits = FragmentOffset; 501 } 502 503 void DwarfExpression::emitLegacySExt(unsigned FromBits) { 504 // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X 505 emitOp(dwarf::DW_OP_dup); 506 emitOp(dwarf::DW_OP_constu); 507 emitUnsigned(FromBits - 1); 508 emitOp(dwarf::DW_OP_shr); 509 emitOp(dwarf::DW_OP_lit0); 510 emitOp(dwarf::DW_OP_not); 511 emitOp(dwarf::DW_OP_mul); 512 emitOp(dwarf::DW_OP_constu); 513 emitUnsigned(FromBits); 514 emitOp(dwarf::DW_OP_shl); 515 emitOp(dwarf::DW_OP_or); 516 } 517 518 void DwarfExpression::emitLegacyZExt(unsigned FromBits) { 519 // (X & (1 << FromBits - 1)) 520 emitOp(dwarf::DW_OP_constu); 521 emitUnsigned((1ULL << FromBits) - 1); 522 emitOp(dwarf::DW_OP_and); 523 } 524