xref: /freebsd/contrib/llvm-project/llvm/lib/Analysis/InstructionPrecedenceTracking.cpp (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric //===-- InstructionPrecedenceTracking.cpp -----------------------*- C++ -*-===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric // Implements a class that is able to define some instructions as "special"
9*0b57cec5SDimitry Andric // (e.g. as having implicit control flow, or writing memory, or having another
10*0b57cec5SDimitry Andric // interesting property) and then efficiently answers queries of the types:
11*0b57cec5SDimitry Andric // 1. Are there any special instructions in the block of interest?
12*0b57cec5SDimitry Andric // 2. Return first of the special instructions in the given block;
13*0b57cec5SDimitry Andric // 3. Check if the given instruction is preceeded by the first special
14*0b57cec5SDimitry Andric //    instruction in the same block.
15*0b57cec5SDimitry Andric // The class provides caching that allows to answer these queries quickly. The
16*0b57cec5SDimitry Andric // user must make sure that the cached data is invalidated properly whenever
17*0b57cec5SDimitry Andric // a content of some tracked block is changed.
18*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
19*0b57cec5SDimitry Andric 
20*0b57cec5SDimitry Andric #include "llvm/Analysis/InstructionPrecedenceTracking.h"
21*0b57cec5SDimitry Andric #include "llvm/Analysis/ValueTracking.h"
22*0b57cec5SDimitry Andric #include "llvm/IR/PatternMatch.h"
23*0b57cec5SDimitry Andric 
24*0b57cec5SDimitry Andric using namespace llvm;
25*0b57cec5SDimitry Andric 
26*0b57cec5SDimitry Andric #ifndef NDEBUG
27*0b57cec5SDimitry Andric static cl::opt<bool> ExpensiveAsserts(
28*0b57cec5SDimitry Andric     "ipt-expensive-asserts",
29*0b57cec5SDimitry Andric     cl::desc("Perform expensive assert validation on every query to Instruction"
30*0b57cec5SDimitry Andric              " Precedence Tracking"),
31*0b57cec5SDimitry Andric     cl::init(false), cl::Hidden);
32*0b57cec5SDimitry Andric #endif
33*0b57cec5SDimitry Andric 
34*0b57cec5SDimitry Andric const Instruction *InstructionPrecedenceTracking::getFirstSpecialInstruction(
35*0b57cec5SDimitry Andric     const BasicBlock *BB) {
36*0b57cec5SDimitry Andric #ifndef NDEBUG
37*0b57cec5SDimitry Andric   // If there is a bug connected to invalid cache, turn on ExpensiveAsserts to
38*0b57cec5SDimitry Andric   // catch this situation as early as possible.
39*0b57cec5SDimitry Andric   if (ExpensiveAsserts)
40*0b57cec5SDimitry Andric     validateAll();
41*0b57cec5SDimitry Andric   else
42*0b57cec5SDimitry Andric     validate(BB);
43*0b57cec5SDimitry Andric #endif
44*0b57cec5SDimitry Andric 
45*0b57cec5SDimitry Andric   if (FirstSpecialInsts.find(BB) == FirstSpecialInsts.end()) {
46*0b57cec5SDimitry Andric     fill(BB);
47*0b57cec5SDimitry Andric     assert(FirstSpecialInsts.find(BB) != FirstSpecialInsts.end() && "Must be!");
48*0b57cec5SDimitry Andric   }
49*0b57cec5SDimitry Andric   return FirstSpecialInsts[BB];
50*0b57cec5SDimitry Andric }
51*0b57cec5SDimitry Andric 
52*0b57cec5SDimitry Andric bool InstructionPrecedenceTracking::hasSpecialInstructions(
53*0b57cec5SDimitry Andric     const BasicBlock *BB) {
54*0b57cec5SDimitry Andric   return getFirstSpecialInstruction(BB) != nullptr;
55*0b57cec5SDimitry Andric }
56*0b57cec5SDimitry Andric 
57*0b57cec5SDimitry Andric bool InstructionPrecedenceTracking::isPreceededBySpecialInstruction(
58*0b57cec5SDimitry Andric     const Instruction *Insn) {
59*0b57cec5SDimitry Andric   const Instruction *MaybeFirstSpecial =
60*0b57cec5SDimitry Andric       getFirstSpecialInstruction(Insn->getParent());
61*0b57cec5SDimitry Andric   return MaybeFirstSpecial && OI.dominates(MaybeFirstSpecial, Insn);
62*0b57cec5SDimitry Andric }
63*0b57cec5SDimitry Andric 
64*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::fill(const BasicBlock *BB) {
65*0b57cec5SDimitry Andric   FirstSpecialInsts.erase(BB);
66*0b57cec5SDimitry Andric   for (auto &I : *BB)
67*0b57cec5SDimitry Andric     if (isSpecialInstruction(&I)) {
68*0b57cec5SDimitry Andric       FirstSpecialInsts[BB] = &I;
69*0b57cec5SDimitry Andric       return;
70*0b57cec5SDimitry Andric     }
71*0b57cec5SDimitry Andric 
72*0b57cec5SDimitry Andric   // Mark this block as having no special instructions.
73*0b57cec5SDimitry Andric   FirstSpecialInsts[BB] = nullptr;
74*0b57cec5SDimitry Andric }
75*0b57cec5SDimitry Andric 
76*0b57cec5SDimitry Andric #ifndef NDEBUG
77*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::validate(const BasicBlock *BB) const {
78*0b57cec5SDimitry Andric   auto It = FirstSpecialInsts.find(BB);
79*0b57cec5SDimitry Andric   // Bail if we don't have anything cached for this block.
80*0b57cec5SDimitry Andric   if (It == FirstSpecialInsts.end())
81*0b57cec5SDimitry Andric     return;
82*0b57cec5SDimitry Andric 
83*0b57cec5SDimitry Andric   for (const Instruction &Insn : *BB)
84*0b57cec5SDimitry Andric     if (isSpecialInstruction(&Insn)) {
85*0b57cec5SDimitry Andric       assert(It->second == &Insn &&
86*0b57cec5SDimitry Andric              "Cached first special instruction is wrong!");
87*0b57cec5SDimitry Andric       return;
88*0b57cec5SDimitry Andric     }
89*0b57cec5SDimitry Andric 
90*0b57cec5SDimitry Andric   assert(It->second == nullptr &&
91*0b57cec5SDimitry Andric          "Block is marked as having special instructions but in fact it  has "
92*0b57cec5SDimitry Andric          "none!");
93*0b57cec5SDimitry Andric }
94*0b57cec5SDimitry Andric 
95*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::validateAll() const {
96*0b57cec5SDimitry Andric   // Check that for every known block the cached value is correct.
97*0b57cec5SDimitry Andric   for (auto &It : FirstSpecialInsts)
98*0b57cec5SDimitry Andric     validate(It.first);
99*0b57cec5SDimitry Andric }
100*0b57cec5SDimitry Andric #endif
101*0b57cec5SDimitry Andric 
102*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::insertInstructionTo(const Instruction *Inst,
103*0b57cec5SDimitry Andric                                                         const BasicBlock *BB) {
104*0b57cec5SDimitry Andric   if (isSpecialInstruction(Inst))
105*0b57cec5SDimitry Andric     FirstSpecialInsts.erase(BB);
106*0b57cec5SDimitry Andric   OI.invalidateBlock(BB);
107*0b57cec5SDimitry Andric }
108*0b57cec5SDimitry Andric 
109*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::removeInstruction(const Instruction *Inst) {
110*0b57cec5SDimitry Andric   if (isSpecialInstruction(Inst))
111*0b57cec5SDimitry Andric     FirstSpecialInsts.erase(Inst->getParent());
112*0b57cec5SDimitry Andric   OI.invalidateBlock(Inst->getParent());
113*0b57cec5SDimitry Andric }
114*0b57cec5SDimitry Andric 
115*0b57cec5SDimitry Andric void InstructionPrecedenceTracking::clear() {
116*0b57cec5SDimitry Andric   for (auto It : FirstSpecialInsts)
117*0b57cec5SDimitry Andric     OI.invalidateBlock(It.first);
118*0b57cec5SDimitry Andric   FirstSpecialInsts.clear();
119*0b57cec5SDimitry Andric #ifndef NDEBUG
120*0b57cec5SDimitry Andric   // The map should be valid after clearing (at least empty).
121*0b57cec5SDimitry Andric   validateAll();
122*0b57cec5SDimitry Andric #endif
123*0b57cec5SDimitry Andric }
124*0b57cec5SDimitry Andric 
125*0b57cec5SDimitry Andric bool ImplicitControlFlowTracking::isSpecialInstruction(
126*0b57cec5SDimitry Andric     const Instruction *Insn) const {
127*0b57cec5SDimitry Andric   // If a block's instruction doesn't always pass the control to its successor
128*0b57cec5SDimitry Andric   // instruction, mark the block as having implicit control flow. We use them
129*0b57cec5SDimitry Andric   // to avoid wrong assumptions of sort "if A is executed and B post-dominates
130*0b57cec5SDimitry Andric   // A, then B is also executed". This is not true is there is an implicit
131*0b57cec5SDimitry Andric   // control flow instruction (e.g. a guard) between them.
132*0b57cec5SDimitry Andric   //
133*0b57cec5SDimitry Andric   // TODO: Currently, isGuaranteedToTransferExecutionToSuccessor returns false
134*0b57cec5SDimitry Andric   // for volatile stores and loads because they can trap. The discussion on
135*0b57cec5SDimitry Andric   // whether or not it is correct is still ongoing. We might want to get rid
136*0b57cec5SDimitry Andric   // of this logic in the future. Anyways, trapping instructions shouldn't
137*0b57cec5SDimitry Andric   // introduce implicit control flow, so we explicitly allow them here. This
138*0b57cec5SDimitry Andric   // must be removed once isGuaranteedToTransferExecutionToSuccessor is fixed.
139*0b57cec5SDimitry Andric   if (isGuaranteedToTransferExecutionToSuccessor(Insn))
140*0b57cec5SDimitry Andric     return false;
141*0b57cec5SDimitry Andric   if (isa<LoadInst>(Insn)) {
142*0b57cec5SDimitry Andric     assert(cast<LoadInst>(Insn)->isVolatile() &&
143*0b57cec5SDimitry Andric            "Non-volatile load should transfer execution to successor!");
144*0b57cec5SDimitry Andric     return false;
145*0b57cec5SDimitry Andric   }
146*0b57cec5SDimitry Andric   if (isa<StoreInst>(Insn)) {
147*0b57cec5SDimitry Andric     assert(cast<StoreInst>(Insn)->isVolatile() &&
148*0b57cec5SDimitry Andric            "Non-volatile store should transfer execution to successor!");
149*0b57cec5SDimitry Andric     return false;
150*0b57cec5SDimitry Andric   }
151*0b57cec5SDimitry Andric   return true;
152*0b57cec5SDimitry Andric }
153*0b57cec5SDimitry Andric 
154*0b57cec5SDimitry Andric bool MemoryWriteTracking::isSpecialInstruction(
155*0b57cec5SDimitry Andric     const Instruction *Insn) const {
156*0b57cec5SDimitry Andric   using namespace PatternMatch;
157*0b57cec5SDimitry Andric   if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>()))
158*0b57cec5SDimitry Andric     return false;
159*0b57cec5SDimitry Andric   return Insn->mayWriteToMemory();
160*0b57cec5SDimitry Andric }
161