1//===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the AARCH64-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13let TargetPrefix = "aarch64" in { 14 15def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 16 [IntrNoFree, IntrWillReturn]>; 17def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 18 [IntrNoFree, IntrWillReturn]>; 19def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 20 [IntrNoFree, IntrWillReturn]>; 21def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 22 [IntrNoFree, IntrWillReturn]>; 23 24def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], 25 [IntrNoFree, IntrWillReturn]>; 26def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], 27 [IntrNoFree, IntrWillReturn]>; 28def int_aarch64_stxp : Intrinsic<[llvm_i32_ty], 29 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty], 30 [IntrNoFree, IntrWillReturn]>; 31def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty], 32 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty], 33 [IntrNoFree, IntrWillReturn]>; 34 35def int_aarch64_clrex : Intrinsic<[]>; 36 37def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 38 LLVMMatchType<0>], [IntrNoMem]>; 39def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 40 LLVMMatchType<0>], [IntrNoMem]>; 41 42def int_aarch64_fjcvtzs : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>; 43 44def int_aarch64_cls: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 45def int_aarch64_cls64: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>; 46 47def int_aarch64_frint32z 48 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ], [ LLVMMatchType<0> ], 49 [ IntrNoMem ]>; 50def int_aarch64_frint64z 51 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ], [ LLVMMatchType<0> ], 52 [ IntrNoMem ]>; 53def int_aarch64_frint32x 54 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ], [ LLVMMatchType<0> ], 55 [ IntrNoMem ]>; 56def int_aarch64_frint64x 57 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ], [ LLVMMatchType<0> ], 58 [ IntrNoMem ]>; 59 60//===----------------------------------------------------------------------===// 61// HINT 62 63def int_aarch64_hint : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>; 64 65def int_aarch64_break : Intrinsic<[], [llvm_i32_ty], 66 [IntrNoMem, IntrHasSideEffects, IntrNoReturn, IntrCold, ImmArg<ArgIndex<0>>]>; 67 68 69def int_aarch64_prefetch : Intrinsic<[], 70 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 71 [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly<ArgIndex<0>>, 72 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>> 73 ]>, 74 ClangBuiltin<"__builtin_arm_prefetch">; 75 76//===----------------------------------------------------------------------===// 77// Data Barrier Instructions 78 79def int_aarch64_dmb : ClangBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">, 80 Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; 81def int_aarch64_dsb : ClangBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">, 82 Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; 83def int_aarch64_isb : ClangBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, 84 Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; 85 86// A space-consuming intrinsic primarily for testing block and jump table 87// placements. The first argument is the number of bytes this "instruction" 88// takes up, the second and return value are essentially chains, used to force 89// ordering during ISel. 90def int_aarch64_space : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty], []>; 91 92} 93 94//===----------------------------------------------------------------------===// 95// Advanced SIMD (NEON) 96 97let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 98 class AdvSIMD_2Scalar_Float_Intrinsic 99 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 100 [IntrNoMem]>; 101 102 class AdvSIMD_FPToIntRounding_Intrinsic 103 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; 104 105 class AdvSIMD_1IntArg_Intrinsic 106 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; 107 class AdvSIMD_1FloatArg_Intrinsic 108 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; 109 class AdvSIMD_1VectorArg_Intrinsic 110 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; 111 class AdvSIMD_1VectorArg_Expand_Intrinsic 112 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 113 class AdvSIMD_1VectorArg_Long_Intrinsic 114 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; 115 class AdvSIMD_1IntArg_Narrow_Intrinsic 116 : DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_any_ty], [IntrNoMem]>; 117 class AdvSIMD_1VectorArg_Narrow_Intrinsic 118 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>; 119 class AdvSIMD_1VectorArg_Int_Across_Intrinsic 120 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>; 121 class AdvSIMD_1VectorArg_Float_Across_Intrinsic 122 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>; 123 124 class AdvSIMD_2IntArg_Intrinsic 125 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 126 [IntrNoMem]>; 127 class AdvSIMD_2FloatArg_Intrinsic 128 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 129 [IntrNoMem]>; 130 class AdvSIMD_2VectorArg_Intrinsic 131 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 132 [IntrNoMem]>; 133 class AdvSIMD_2VectorArg_Compare_Intrinsic 134 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], 135 [IntrNoMem]>; 136 class AdvSIMD_2Arg_FloatCompare_Intrinsic 137 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>], 138 [IntrNoMem]>; 139 class AdvSIMD_2VectorArg_Long_Intrinsic 140 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 141 [LLVMTruncatedType<0>, LLVMTruncatedType<0>], 142 [IntrNoMem]>; 143 class AdvSIMD_2VectorArg_Wide_Intrinsic 144 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 145 [LLVMMatchType<0>, LLVMTruncatedType<0>], 146 [IntrNoMem]>; 147 class AdvSIMD_2VectorArg_Narrow_Intrinsic 148 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 149 [LLVMExtendedType<0>, LLVMExtendedType<0>], 150 [IntrNoMem]>; 151 class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic 152 : DefaultAttrsIntrinsic<[llvm_anyint_ty], 153 [LLVMExtendedType<0>, llvm_i32_ty], 154 [IntrNoMem]>; 155 class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic 156 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 157 [llvm_anyvector_ty], 158 [IntrNoMem]>; 159 class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic 160 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 161 [LLVMTruncatedType<0>], 162 [IntrNoMem]>; 163 class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic 164 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 165 [LLVMTruncatedType<0>, llvm_i32_ty], 166 [IntrNoMem]>; 167 class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic 168 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 169 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty], 170 [IntrNoMem]>; 171 class AdvSIMD_2VectorArg_Lane_Intrinsic 172 : DefaultAttrsIntrinsic<[llvm_anyint_ty], 173 [LLVMMatchType<0>, llvm_anyint_ty, llvm_i32_ty], 174 [IntrNoMem]>; 175 176 class AdvSIMD_3IntArg_Intrinsic 177 : DefaultAttrsIntrinsic<[llvm_anyint_ty], 178 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 179 [IntrNoMem]>; 180 class AdvSIMD_3VectorArg_Intrinsic 181 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 182 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 183 [IntrNoMem]>; 184 class AdvSIMD_3VectorArg_Scalar_Intrinsic 185 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 186 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], 187 [IntrNoMem]>; 188 class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic 189 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 190 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, 191 LLVMMatchType<1>], [IntrNoMem]>; 192 class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic 193 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 194 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty], 195 [IntrNoMem]>; 196 class AdvSIMD_CvtFxToFP_Intrinsic 197 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], 198 [IntrNoMem]>; 199 class AdvSIMD_CvtFPToFx_Intrinsic 200 : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], 201 [IntrNoMem]>; 202 203 class AdvSIMD_1Arg_Intrinsic 204 : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>; 205 206 class AdvSIMD_Dot_Intrinsic 207 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 208 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], 209 [IntrNoMem]>; 210 211 class AdvSIMD_FP16FML_Intrinsic 212 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 213 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], 214 [IntrNoMem]>; 215 216 class AdvSIMD_MatMul_Intrinsic 217 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 218 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], 219 [IntrNoMem]>; 220 221 class AdvSIMD_FML_Intrinsic 222 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 223 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], 224 [IntrNoMem]>; 225 226 class AdvSIMD_BF16FML_Intrinsic 227 : DefaultAttrsIntrinsic<[llvm_v4f32_ty], 228 [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty], 229 [IntrNoMem]>; 230} 231 232// Arithmetic ops 233 234let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in { 235 // Vector Add Across Lanes 236 def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 237 def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 238 def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 239 240 // Vector Long Add Across Lanes 241 def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 242 def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 243 244 // Vector Halving Add 245 def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic; 246 def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic; 247 248 // Vector Rounding Halving Add 249 def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic; 250 def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic; 251 252 // Vector Saturating Add 253 def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic; 254 def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic; 255 def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic; 256 def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic; 257 258 // Vector Add High-Half 259 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that 260 // header is no longer supported. 261 def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 262 263 // Vector Rounding Add High-Half 264 def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 265 266 // Vector Saturating Doubling Multiply High 267 def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic; 268 def int_aarch64_neon_sqdmulh_lane : AdvSIMD_2VectorArg_Lane_Intrinsic; 269 def int_aarch64_neon_sqdmulh_laneq : AdvSIMD_2VectorArg_Lane_Intrinsic; 270 271 // Vector Saturating Rounding Doubling Multiply High 272 def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic; 273 def int_aarch64_neon_sqrdmulh_lane : AdvSIMD_2VectorArg_Lane_Intrinsic; 274 def int_aarch64_neon_sqrdmulh_laneq : AdvSIMD_2VectorArg_Lane_Intrinsic; 275 276 def int_aarch64_neon_sqrdmlah : AdvSIMD_3IntArg_Intrinsic; 277 def int_aarch64_neon_sqrdmlsh : AdvSIMD_3IntArg_Intrinsic; 278 279 // Vector Polynominal Multiply 280 def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic; 281 282 // Vector Long Multiply 283 def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic; 284 def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic; 285 def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic; 286 287 // 64-bit polynomial multiply really returns an i128, which is not legal. Fake 288 // it with a v16i8. 289 def int_aarch64_neon_pmull64 : 290 DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; 291 292 // Vector Extending Multiply 293 def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic { 294 let IntrProperties = [IntrNoMem, Commutative]; 295 } 296 297 // Vector Saturating Doubling Long Multiply 298 def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic; 299 def int_aarch64_neon_sqdmulls_scalar 300 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 301 302 // Vector Halving Subtract 303 def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic; 304 def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic; 305 306 // Vector Saturating Subtract 307 def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic; 308 def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic; 309 310 // Vector Subtract High-Half 311 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that 312 // header is no longer supported. 313 def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 314 315 // Vector Rounding Subtract High-Half 316 def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 317 318 // Vector Compare Absolute Greater-than-or-equal 319 def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic; 320 321 // Vector Compare Absolute Greater-than 322 def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic; 323 324 // Vector Absolute Difference 325 def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic; 326 def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic; 327 def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic; 328 329 // Scalar Absolute Difference 330 def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic; 331 332 // Vector Max 333 def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic; 334 def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic; 335 def int_aarch64_neon_fmax : AdvSIMD_2FloatArg_Intrinsic; 336 def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic; 337 338 // Vector Max Across Lanes 339 def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 340 def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 341 def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 342 def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 343 344 // Vector Min 345 def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic; 346 def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic; 347 def int_aarch64_neon_fmin : AdvSIMD_2FloatArg_Intrinsic; 348 def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic; 349 350 // Vector Min/Max Number 351 def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic; 352 def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic; 353 354 // Vector Min Across Lanes 355 def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 356 def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 357 def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 358 def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 359 360 // Pairwise Add 361 def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic; 362 def int_aarch64_neon_faddp : AdvSIMD_2VectorArg_Intrinsic; 363 364 // Long Pairwise Add 365 // FIXME: In theory, we shouldn't need intrinsics for saddlp or 366 // uaddlp, but tblgen's type inference currently can't handle the 367 // pattern fragments this ends up generating. 368 def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; 369 def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; 370 371 // Folding Maximum 372 def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic; 373 def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic; 374 def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic; 375 376 // Folding Minimum 377 def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic; 378 def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic; 379 def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic; 380 381 // Reciprocal Estimate/Step 382 def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic; 383 def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic; 384 385 // Reciprocal Exponent 386 def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic; 387 388 // Vector Saturating Shift Left 389 def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic; 390 def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic; 391 392 // Vector Rounding Shift Left 393 def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic; 394 def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic; 395 396 // Vector Saturating Rounding Shift Left 397 def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic; 398 def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic; 399 400 // Vector Signed->Unsigned Shift Left by Constant 401 def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic; 402 403 // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant 404 def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 405 406 // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const 407 def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 408 409 // Vector Narrowing Shift Right by Constant 410 def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 411 def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 412 413 // Vector Rounding Narrowing Shift Right by Constant 414 def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 415 416 // Vector Rounding Narrowing Saturating Shift Right by Constant 417 def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 418 def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 419 420 // Vector Shift Left 421 def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic; 422 def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic; 423 424 // Vector Widening Shift Left by Constant 425 def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic; 426 def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; 427 def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; 428 429 // Vector Shift Right by Constant and Insert 430 def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic; 431 432 // Vector Shift Left by Constant and Insert 433 def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic; 434 435 // Vector Saturating Narrow 436 def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic; 437 def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic; 438 def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; 439 def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; 440 441 // Vector Saturating Extract and Unsigned Narrow 442 def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic; 443 def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic; 444 445 // Vector Absolute Value 446 def int_aarch64_neon_abs : AdvSIMD_1Arg_Intrinsic; 447 448 // Vector Saturating Absolute Value 449 def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic; 450 451 // Vector Saturating Negation 452 def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic; 453 454 // Vector Count Leading Sign Bits 455 def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic; 456 457 // Vector Reciprocal Estimate 458 def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic; 459 def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic; 460 461 // Vector Square Root Estimate 462 def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic; 463 def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic; 464 465 // Vector Conversions Between Half-Precision and Single-Precision. 466 def int_aarch64_neon_vcvtfp2hf 467 : DefaultAttrsIntrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 468 def int_aarch64_neon_vcvthf2fp 469 : DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; 470 471 // Vector Conversions Between Floating-point and Fixed-point. 472 def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic; 473 def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic; 474 def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic; 475 def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic; 476 477 // Vector FP->Int Conversions 478 def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic; 479 def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic; 480 def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic; 481 def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic; 482 def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic; 483 def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic; 484 def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic; 485 def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic; 486 def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic; 487 def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic; 488 489 // v8.5-A Vector FP Rounding 490 def int_aarch64_neon_frint32x : AdvSIMD_1FloatArg_Intrinsic; 491 def int_aarch64_neon_frint32z : AdvSIMD_1FloatArg_Intrinsic; 492 def int_aarch64_neon_frint64x : AdvSIMD_1FloatArg_Intrinsic; 493 def int_aarch64_neon_frint64z : AdvSIMD_1FloatArg_Intrinsic; 494 495 // Scalar FP->Int conversions 496 497 // Vector FP Inexact Narrowing 498 def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic; 499 500 // Scalar FP Inexact Narrowing 501 def int_aarch64_sisd_fcvtxn : DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_double_ty], 502 [IntrNoMem]>; 503 504 // v8.2-A Dot Product 505 def int_aarch64_neon_udot : AdvSIMD_Dot_Intrinsic; 506 def int_aarch64_neon_sdot : AdvSIMD_Dot_Intrinsic; 507 508 // v8.6-A Matrix Multiply Intrinsics 509 def int_aarch64_neon_ummla : AdvSIMD_MatMul_Intrinsic; 510 def int_aarch64_neon_smmla : AdvSIMD_MatMul_Intrinsic; 511 def int_aarch64_neon_usmmla : AdvSIMD_MatMul_Intrinsic; 512 def int_aarch64_neon_usdot : AdvSIMD_Dot_Intrinsic; 513 def int_aarch64_neon_bfdot : AdvSIMD_Dot_Intrinsic; 514 def int_aarch64_neon_bfmmla 515 : DefaultAttrsIntrinsic<[llvm_v4f32_ty], 516 [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty], 517 [IntrNoMem]>; 518 def int_aarch64_neon_bfmlalb : AdvSIMD_BF16FML_Intrinsic; 519 def int_aarch64_neon_bfmlalt : AdvSIMD_BF16FML_Intrinsic; 520 521 522 // v8.6-A Bfloat Intrinsics 523 def int_aarch64_neon_bfcvt 524 : DefaultAttrsIntrinsic<[llvm_bfloat_ty], [llvm_float_ty], [IntrNoMem]>; 525 def int_aarch64_neon_bfcvtn 526 : DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 527 def int_aarch64_neon_bfcvtn2 528 : DefaultAttrsIntrinsic<[llvm_v8bf16_ty], 529 [llvm_v8bf16_ty, llvm_v4f32_ty], 530 [IntrNoMem]>; 531 532 // v8.2-A FP16 Fused Multiply-Add Long 533 def int_aarch64_neon_fmlal : AdvSIMD_FP16FML_Intrinsic; 534 def int_aarch64_neon_fmlsl : AdvSIMD_FP16FML_Intrinsic; 535 def int_aarch64_neon_fmlal2 : AdvSIMD_FP16FML_Intrinsic; 536 def int_aarch64_neon_fmlsl2 : AdvSIMD_FP16FML_Intrinsic; 537 538 // v8.3-A Floating-point complex add 539 def int_aarch64_neon_vcadd_rot90 : AdvSIMD_2VectorArg_Intrinsic; 540 def int_aarch64_neon_vcadd_rot270 : AdvSIMD_2VectorArg_Intrinsic; 541 542 def int_aarch64_neon_vcmla_rot0 : AdvSIMD_3VectorArg_Intrinsic; 543 def int_aarch64_neon_vcmla_rot90 : AdvSIMD_3VectorArg_Intrinsic; 544 def int_aarch64_neon_vcmla_rot180 : AdvSIMD_3VectorArg_Intrinsic; 545 def int_aarch64_neon_vcmla_rot270 : AdvSIMD_3VectorArg_Intrinsic; 546} 547 548let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 549 class AdvSIMD_2Vector2Index_Intrinsic 550 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 551 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty], 552 [IntrNoMem]>; 553} 554 555// Vector element to element moves 556def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic; 557 558let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 559 class AdvSIMD_1Vec_Load_Intrinsic 560 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyptr_ty], 561 [IntrReadMem, IntrArgMemOnly]>; 562 class AdvSIMD_1Vec_Store_Lane_Intrinsic 563 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], 564 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; 565 566 class AdvSIMD_2Vec_Load_Intrinsic 567 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, llvm_anyvector_ty], 568 [llvm_anyptr_ty], 569 [IntrReadMem, IntrArgMemOnly]>; 570 class AdvSIMD_2Vec_Load_Lane_Intrinsic 571 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>], 572 [LLVMMatchType<0>, llvm_anyvector_ty, 573 llvm_i64_ty, llvm_anyptr_ty], 574 [IntrReadMem, IntrArgMemOnly]>; 575 class AdvSIMD_2Vec_Store_Intrinsic 576 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 577 llvm_anyptr_ty], 578 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; 579 class AdvSIMD_2Vec_Store_Lane_Intrinsic 580 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 581 llvm_i64_ty, llvm_anyptr_ty], 582 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 583 584 class AdvSIMD_3Vec_Load_Intrinsic 585 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty], 586 [llvm_anyptr_ty], 587 [IntrReadMem, IntrArgMemOnly]>; 588 class AdvSIMD_3Vec_Load_Lane_Intrinsic 589 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 590 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, 591 llvm_i64_ty, llvm_anyptr_ty], 592 [IntrReadMem, IntrArgMemOnly]>; 593 class AdvSIMD_3Vec_Store_Intrinsic 594 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 595 LLVMMatchType<0>, llvm_anyptr_ty], 596 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 597 class AdvSIMD_3Vec_Store_Lane_Intrinsic 598 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, 599 LLVMMatchType<0>, LLVMMatchType<0>, 600 llvm_i64_ty, llvm_anyptr_ty], 601 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; 602 603 class AdvSIMD_4Vec_Load_Intrinsic 604 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, 605 LLVMMatchType<0>, llvm_anyvector_ty], 606 [llvm_anyptr_ty], 607 [IntrReadMem, IntrArgMemOnly]>; 608 class AdvSIMD_4Vec_Load_Lane_Intrinsic 609 : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, 610 LLVMMatchType<0>, LLVMMatchType<0>], 611 [LLVMMatchType<0>, LLVMMatchType<0>, 612 LLVMMatchType<0>, llvm_anyvector_ty, 613 llvm_i64_ty, llvm_anyptr_ty], 614 [IntrReadMem, IntrArgMemOnly]>; 615 class AdvSIMD_4Vec_Store_Intrinsic 616 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 617 LLVMMatchType<0>, LLVMMatchType<0>, 618 llvm_anyptr_ty], 619 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; 620 class AdvSIMD_4Vec_Store_Lane_Intrinsic 621 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 622 LLVMMatchType<0>, LLVMMatchType<0>, 623 llvm_i64_ty, llvm_anyptr_ty], 624 [IntrArgMemOnly, NoCapture<ArgIndex<5>>]>; 625} 626 627// Memory ops 628 629def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic; 630def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic; 631def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic; 632 633def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic; 634def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic; 635def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic; 636 637def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic; 638def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic; 639def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic; 640 641def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic; 642def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic; 643def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic; 644 645def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic; 646def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic; 647def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic; 648 649def int_aarch64_neon_st2 : AdvSIMD_2Vec_Store_Intrinsic; 650def int_aarch64_neon_st3 : AdvSIMD_3Vec_Store_Intrinsic; 651def int_aarch64_neon_st4 : AdvSIMD_4Vec_Store_Intrinsic; 652 653def int_aarch64_neon_st2lane : AdvSIMD_2Vec_Store_Lane_Intrinsic; 654def int_aarch64_neon_st3lane : AdvSIMD_3Vec_Store_Lane_Intrinsic; 655def int_aarch64_neon_st4lane : AdvSIMD_4Vec_Store_Lane_Intrinsic; 656 657let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 658 class AdvSIMD_Tbl1_Intrinsic 659 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>], 660 [IntrNoMem]>; 661 class AdvSIMD_Tbl2_Intrinsic 662 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 663 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; 664 class AdvSIMD_Tbl3_Intrinsic 665 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 666 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, 667 LLVMMatchType<0>], 668 [IntrNoMem]>; 669 class AdvSIMD_Tbl4_Intrinsic 670 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 671 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, 672 LLVMMatchType<0>], 673 [IntrNoMem]>; 674 675 class AdvSIMD_Tbx1_Intrinsic 676 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 677 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>], 678 [IntrNoMem]>; 679 class AdvSIMD_Tbx2_Intrinsic 680 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 681 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 682 LLVMMatchType<0>], 683 [IntrNoMem]>; 684 class AdvSIMD_Tbx3_Intrinsic 685 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 686 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 687 llvm_v16i8_ty, LLVMMatchType<0>], 688 [IntrNoMem]>; 689 class AdvSIMD_Tbx4_Intrinsic 690 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 691 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 692 llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], 693 [IntrNoMem]>; 694} 695def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic; 696def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic; 697def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic; 698def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic; 699 700def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic; 701def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic; 702def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic; 703def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic; 704 705let TargetPrefix = "aarch64" in { 706 class FPCR_Get_Intrinsic 707 : DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>; 708 class FPCR_Set_Intrinsic 709 : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>; 710 class RNDR_Intrinsic 711 : DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects]>; 712} 713 714// FPCR 715def int_aarch64_get_fpcr : FPCR_Get_Intrinsic; 716def int_aarch64_set_fpcr : FPCR_Set_Intrinsic; 717 718// Armv8.5-A Random number generation intrinsics 719def int_aarch64_rndr : RNDR_Intrinsic; 720def int_aarch64_rndrrs : RNDR_Intrinsic; 721 722let TargetPrefix = "aarch64" in { 723 class Crypto_AES_DataKey_Intrinsic 724 : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; 725 726 class Crypto_AES_Data_Intrinsic 727 : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; 728 729 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule 730 // (v4i32). 731 class Crypto_SHA_5Hash4Schedule_Intrinsic 732 : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], 733 [IntrNoMem]>; 734 735 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule 736 // (v4i32). 737 class Crypto_SHA_1Hash_Intrinsic 738 : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 739 740 // SHA intrinsic taking 8 words of the schedule 741 class Crypto_SHA_8Schedule_Intrinsic 742 : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; 743 744 // SHA intrinsic taking 12 words of the schedule 745 class Crypto_SHA_12Schedule_Intrinsic 746 : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 747 [IntrNoMem]>; 748 749 // SHA intrinsic taking 8 words of the hash and 4 of the schedule. 750 class Crypto_SHA_8Hash4Schedule_Intrinsic 751 : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 752 [IntrNoMem]>; 753 754 // SHA512 intrinsic taking 2 arguments 755 class Crypto_SHA512_2Arg_Intrinsic 756 : DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; 757 758 // SHA512 intrinsic taking 3 Arguments 759 class Crypto_SHA512_3Arg_Intrinsic 760 : DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], 761 [IntrNoMem]>; 762 763 // SHA3 Intrinsics taking 3 arguments 764 class Crypto_SHA3_3Arg_Intrinsic 765 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 766 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 767 [IntrNoMem]>; 768 769 // SHA3 Intrinsic taking 2 arguments 770 class Crypto_SHA3_2Arg_Intrinsic 771 : DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], 772 [IntrNoMem]>; 773 774 // SHA3 Intrinsic taking 3 Arguments 1 immediate 775 class Crypto_SHA3_2ArgImm_Intrinsic 776 : DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i64_ty], 777 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 778 779 class Crypto_SM3_3Vector_Intrinsic 780 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 781 [IntrNoMem]>; 782 783 class Crypto_SM3_3VectorIndexed_Intrinsic 784 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i64_ty], 785 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 786 787 class Crypto_SM4_2Vector_Intrinsic 788 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; 789} 790 791// AES 792def int_aarch64_crypto_aese : Crypto_AES_DataKey_Intrinsic; 793def int_aarch64_crypto_aesd : Crypto_AES_DataKey_Intrinsic; 794def int_aarch64_crypto_aesmc : Crypto_AES_Data_Intrinsic; 795def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic; 796 797// SHA1 798def int_aarch64_crypto_sha1c : Crypto_SHA_5Hash4Schedule_Intrinsic; 799def int_aarch64_crypto_sha1p : Crypto_SHA_5Hash4Schedule_Intrinsic; 800def int_aarch64_crypto_sha1m : Crypto_SHA_5Hash4Schedule_Intrinsic; 801def int_aarch64_crypto_sha1h : Crypto_SHA_1Hash_Intrinsic; 802 803def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic; 804def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic; 805 806// SHA256 807def int_aarch64_crypto_sha256h : Crypto_SHA_8Hash4Schedule_Intrinsic; 808def int_aarch64_crypto_sha256h2 : Crypto_SHA_8Hash4Schedule_Intrinsic; 809def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic; 810def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic; 811 812//SHA3 813def int_aarch64_crypto_eor3s : Crypto_SHA3_3Arg_Intrinsic; 814def int_aarch64_crypto_eor3u : Crypto_SHA3_3Arg_Intrinsic; 815def int_aarch64_crypto_bcaxs : Crypto_SHA3_3Arg_Intrinsic; 816def int_aarch64_crypto_bcaxu : Crypto_SHA3_3Arg_Intrinsic; 817def int_aarch64_crypto_rax1 : Crypto_SHA3_2Arg_Intrinsic; 818def int_aarch64_crypto_xar : Crypto_SHA3_2ArgImm_Intrinsic; 819 820// SHA512 821def int_aarch64_crypto_sha512h : Crypto_SHA512_3Arg_Intrinsic; 822def int_aarch64_crypto_sha512h2 : Crypto_SHA512_3Arg_Intrinsic; 823def int_aarch64_crypto_sha512su0 : Crypto_SHA512_2Arg_Intrinsic; 824def int_aarch64_crypto_sha512su1 : Crypto_SHA512_3Arg_Intrinsic; 825 826//SM3 & SM4 827def int_aarch64_crypto_sm3partw1 : Crypto_SM3_3Vector_Intrinsic; 828def int_aarch64_crypto_sm3partw2 : Crypto_SM3_3Vector_Intrinsic; 829def int_aarch64_crypto_sm3ss1 : Crypto_SM3_3Vector_Intrinsic; 830def int_aarch64_crypto_sm3tt1a : Crypto_SM3_3VectorIndexed_Intrinsic; 831def int_aarch64_crypto_sm3tt1b : Crypto_SM3_3VectorIndexed_Intrinsic; 832def int_aarch64_crypto_sm3tt2a : Crypto_SM3_3VectorIndexed_Intrinsic; 833def int_aarch64_crypto_sm3tt2b : Crypto_SM3_3VectorIndexed_Intrinsic; 834def int_aarch64_crypto_sm4e : Crypto_SM4_2Vector_Intrinsic; 835def int_aarch64_crypto_sm4ekey : Crypto_SM4_2Vector_Intrinsic; 836 837//===----------------------------------------------------------------------===// 838// CRC32 839 840let TargetPrefix = "aarch64" in { 841 842def int_aarch64_crc32b : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 843 [IntrNoMem]>; 844def int_aarch64_crc32cb : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 845 [IntrNoMem]>; 846def int_aarch64_crc32h : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 847 [IntrNoMem]>; 848def int_aarch64_crc32ch : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 849 [IntrNoMem]>; 850def int_aarch64_crc32w : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 851 [IntrNoMem]>; 852def int_aarch64_crc32cw : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 853 [IntrNoMem]>; 854def int_aarch64_crc32x : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], 855 [IntrNoMem]>; 856def int_aarch64_crc32cx : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], 857 [IntrNoMem]>; 858} 859 860//===----------------------------------------------------------------------===// 861// Memory Tagging Extensions (MTE) Intrinsics 862let TargetPrefix = "aarch64" in { 863def int_aarch64_irg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], 864 [IntrNoMem, IntrHasSideEffects]>; 865def int_aarch64_addg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], 866 [IntrNoMem]>; 867def int_aarch64_gmi : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], 868 [IntrNoMem]>; 869def int_aarch64_ldg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty], 870 [IntrReadMem]>; 871def int_aarch64_stg : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], 872 [IntrWriteMem]>; 873def int_aarch64_subp : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty], 874 [IntrNoMem]>; 875 876// The following are codegen-only intrinsics for stack instrumentation. 877 878// Generate a randomly tagged stack base pointer. 879def int_aarch64_irg_sp : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_i64_ty], 880 [IntrNoMem, IntrHasSideEffects]>; 881 882// Transfer pointer tag with offset. 883// ptr1 = tagp(ptr0, baseptr, tag_offset) returns a pointer where 884// * address is the address in ptr0 885// * tag is a function of (tag in baseptr, tag_offset). 886// ** Beware, this is not the same function as implemented by the ADDG instruction! 887// Backend optimizations may change tag_offset; the only guarantee is that calls 888// to tagp with the same pair of (baseptr, tag_offset) will produce pointers 889// with the same tag value, assuming the set of excluded tags has not changed. 890// Address bits in baseptr and tag bits in ptr0 are ignored. 891// When offset between ptr0 and baseptr is a compile time constant, this can be emitted as 892// ADDG ptr1, baseptr, (ptr0 - baseptr), tag_offset 893// It is intended that ptr0 is an alloca address, and baseptr is the direct output of llvm.aarch64.irg.sp. 894def int_aarch64_tagp : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>, llvm_ptr_ty, llvm_i64_ty], 895 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 896 897// Update allocation tags for the memory range to match the tag in the pointer argument. 898def int_aarch64_settag : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty], 899 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 900 901// Update allocation tags for the memory range to match the tag in the pointer argument, 902// and set memory contents to zero. 903def int_aarch64_settag_zero : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty], 904 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 905 906// Update allocation tags for 16-aligned, 16-sized memory region, and store a pair 8-byte values. 907def int_aarch64_stgp : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty], 908 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 909} 910 911//===----------------------------------------------------------------------===// 912// Memory Operations (MOPS) Intrinsics 913let TargetPrefix = "aarch64" in { 914 // Sizes are chosen to correspond to the llvm.memset intrinsic: ptr, i8, i64 915 def int_aarch64_mops_memset_tag : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i8_ty, llvm_i64_ty], 916 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 917} 918 919// Transactional Memory Extension (TME) Intrinsics 920let TargetPrefix = "aarch64" in { 921def int_aarch64_tstart : ClangBuiltin<"__builtin_arm_tstart">, 922 Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>; 923 924def int_aarch64_tcommit : ClangBuiltin<"__builtin_arm_tcommit">, Intrinsic<[], [], [IntrWillReturn]>; 925 926def int_aarch64_tcancel : ClangBuiltin<"__builtin_arm_tcancel">, 927 Intrinsic<[], [llvm_i64_ty], [IntrWillReturn, ImmArg<ArgIndex<0>>]>; 928 929def int_aarch64_ttest : ClangBuiltin<"__builtin_arm_ttest">, 930 Intrinsic<[llvm_i64_ty], [], 931 [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 932 933// Armv8.7-A load/store 64-byte intrinsics 934defvar data512 = !listsplat(llvm_i64_ty, 8); 935def int_aarch64_ld64b: Intrinsic<data512, [llvm_ptr_ty]>; 936def int_aarch64_st64b: Intrinsic<[], !listconcat([llvm_ptr_ty], data512)>; 937def int_aarch64_st64bv: Intrinsic<[llvm_i64_ty], !listconcat([llvm_ptr_ty], data512)>; 938def int_aarch64_st64bv0: Intrinsic<[llvm_i64_ty], !listconcat([llvm_ptr_ty], data512)>; 939 940} 941 942def llvm_nxv1i1_ty : LLVMType<nxv1i1>; 943def llvm_nxv2i1_ty : LLVMType<nxv2i1>; 944def llvm_nxv4i1_ty : LLVMType<nxv4i1>; 945def llvm_nxv8i1_ty : LLVMType<nxv8i1>; 946def llvm_nxv16i1_ty : LLVMType<nxv16i1>; 947def llvm_nxv16i8_ty : LLVMType<nxv16i8>; 948def llvm_nxv4i32_ty : LLVMType<nxv4i32>; 949def llvm_nxv2i64_ty : LLVMType<nxv2i64>; 950def llvm_nxv8f16_ty : LLVMType<nxv8f16>; 951def llvm_nxv8bf16_ty : LLVMType<nxv8bf16>; 952def llvm_nxv4f32_ty : LLVMType<nxv4f32>; 953def llvm_nxv2f64_ty : LLVMType<nxv2f64>; 954 955let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 956 957 class AdvSIMD_1Vec_PredLoad_Intrinsic 958 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 959 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 960 [IntrReadMem, IntrArgMemOnly]>; 961 962 class AdvSIMD_2Vec_PredLoad_Intrinsic 963 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 964 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 965 [IntrReadMem, IntrArgMemOnly]>; 966 967 class AdvSIMD_3Vec_PredLoad_Intrinsic 968 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>], 969 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 970 [IntrReadMem, IntrArgMemOnly]>; 971 972 class AdvSIMD_4Vec_PredLoad_Intrinsic 973 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, 974 LLVMMatchType<0>], 975 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 976 [IntrReadMem, IntrArgMemOnly]>; 977 978 class AdvSIMD_1Vec_PredLoad_WriteFFR_Intrinsic 979 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 980 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 981 [IntrInaccessibleMemOrArgMemOnly]>; 982 983 class AdvSIMD_1Vec_PredStore_Intrinsic 984 : DefaultAttrsIntrinsic<[], 985 [llvm_anyvector_ty, 986 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 987 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; 988 989 class AdvSIMD_2Vec_PredStore_Intrinsic 990 : DefaultAttrsIntrinsic<[], 991 [llvm_anyvector_ty, LLVMMatchType<0>, 992 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 993 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 994 995 class AdvSIMD_3Vec_PredStore_Intrinsic 996 : DefaultAttrsIntrinsic<[], 997 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, 998 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 999 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; 1000 1001 class AdvSIMD_4Vec_PredStore_Intrinsic 1002 : DefaultAttrsIntrinsic<[], 1003 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, 1004 LLVMMatchType<0>, 1005 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_ptr_ty], 1006 [IntrArgMemOnly, NoCapture<ArgIndex<5>>]>; 1007 1008 class AdvSIMD_SVE_Index_Intrinsic 1009 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1010 [LLVMVectorElementType<0>, 1011 LLVMVectorElementType<0>], 1012 [IntrNoMem]>; 1013 1014 class AdvSIMD_Merged1VectorArg_Intrinsic 1015 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1016 [LLVMMatchType<0>, 1017 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1018 LLVMMatchType<0>], 1019 [IntrNoMem]>; 1020 1021 class AdvSIMD_2VectorArgIndexed_Intrinsic 1022 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1023 [LLVMMatchType<0>, 1024 LLVMMatchType<0>, 1025 llvm_i32_ty], 1026 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1027 1028 class AdvSIMD_3VectorArgIndexed_Intrinsic 1029 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1030 [LLVMMatchType<0>, 1031 LLVMMatchType<0>, 1032 LLVMMatchType<0>, 1033 llvm_i32_ty], 1034 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1035 1036 class AdvSIMD_Pred1VectorArg_Intrinsic 1037 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1038 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1039 LLVMMatchType<0>], 1040 [IntrNoMem]>; 1041 1042 class AdvSIMD_Pred2VectorArg_Intrinsic 1043 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1044 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1045 LLVMMatchType<0>, 1046 LLVMMatchType<0>], 1047 [IntrNoMem]>; 1048 1049 class AdvSIMD_Pred3VectorArg_Intrinsic 1050 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1051 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1052 LLVMMatchType<0>, 1053 LLVMMatchType<0>, 1054 LLVMMatchType<0>], 1055 [IntrNoMem]>; 1056 1057 class AdvSIMD_SVE_Compare_Intrinsic 1058 : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 1059 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1060 llvm_anyvector_ty, 1061 LLVMMatchType<0>], 1062 [IntrNoMem]>; 1063 1064 class AdvSIMD_SVE_CompareWide_Intrinsic 1065 : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 1066 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1067 llvm_anyvector_ty, 1068 llvm_nxv2i64_ty], 1069 [IntrNoMem]>; 1070 1071 class AdvSIMD_SVE_Saturating_Intrinsic 1072 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1073 [LLVMMatchType<0>, 1074 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 1075 [IntrNoMem]>; 1076 1077 class AdvSIMD_SVE_SaturatingWithPattern_Intrinsic 1078 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1079 [LLVMMatchType<0>, 1080 llvm_i32_ty, 1081 llvm_i32_ty], 1082 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1083 1084 class AdvSIMD_SVE_Saturating_N_Intrinsic<LLVMType T> 1085 : DefaultAttrsIntrinsic<[T], 1086 [T, llvm_anyvector_ty], 1087 [IntrNoMem]>; 1088 1089 class AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<LLVMType T> 1090 : DefaultAttrsIntrinsic<[T], 1091 [T, llvm_i32_ty, llvm_i32_ty], 1092 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1093 1094 class AdvSIMD_SVE_CNT_Intrinsic 1095 : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>], 1096 [LLVMVectorOfBitcastsToInt<0>, 1097 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1098 llvm_anyvector_ty], 1099 [IntrNoMem]>; 1100 1101 class AdvSIMD_SVE_ReduceWithInit_Intrinsic 1102 : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], 1103 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1104 LLVMVectorElementType<0>, 1105 llvm_anyvector_ty], 1106 [IntrNoMem]>; 1107 1108 class AdvSIMD_SVE_ShiftByImm_Intrinsic 1109 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1110 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1111 LLVMMatchType<0>, 1112 llvm_i32_ty], 1113 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1114 1115 class AdvSIMD_SVE_ShiftWide_Intrinsic 1116 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1117 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1118 LLVMMatchType<0>, 1119 llvm_nxv2i64_ty], 1120 [IntrNoMem]>; 1121 1122 class AdvSIMD_SVE_Unpack_Intrinsic 1123 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1124 [LLVMSubdivide2VectorType<0>], 1125 [IntrNoMem]>; 1126 1127 class AdvSIMD_SVE_CADD_Intrinsic 1128 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1129 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1130 LLVMMatchType<0>, 1131 LLVMMatchType<0>, 1132 llvm_i32_ty], 1133 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1134 1135 class AdvSIMD_SVE_CMLA_Intrinsic 1136 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1137 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1138 LLVMMatchType<0>, 1139 LLVMMatchType<0>, 1140 LLVMMatchType<0>, 1141 llvm_i32_ty], 1142 [IntrNoMem, ImmArg<ArgIndex<4>>]>; 1143 1144 class AdvSIMD_SVE_CMLA_LANE_Intrinsic 1145 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1146 [LLVMMatchType<0>, 1147 LLVMMatchType<0>, 1148 LLVMMatchType<0>, 1149 llvm_i32_ty, 1150 llvm_i32_ty], 1151 [IntrNoMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1152 1153 class AdvSIMD_SVE_DUP_Intrinsic 1154 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1155 [LLVMMatchType<0>, 1156 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1157 LLVMVectorElementType<0>], 1158 [IntrNoMem]>; 1159 1160 class AdvSIMD_SVE_DUP_Unpred_Intrinsic 1161 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMVectorElementType<0>], 1162 [IntrNoMem]>; 1163 1164 class AdvSIMD_SVE_DUPQ_Intrinsic 1165 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1166 [LLVMMatchType<0>, 1167 llvm_i64_ty], 1168 [IntrNoMem]>; 1169 1170 class AdvSIMD_SVE_EXPA_Intrinsic 1171 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1172 [LLVMVectorOfBitcastsToInt<0>], 1173 [IntrNoMem]>; 1174 1175 class AdvSIMD_SVE_FCVT_Intrinsic 1176 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1177 [LLVMMatchType<0>, 1178 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1179 llvm_anyvector_ty], 1180 [IntrNoMem]>; 1181 1182 class AdvSIMD_SVE_FCVTZS_Intrinsic 1183 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1184 [LLVMVectorOfBitcastsToInt<0>, 1185 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1186 llvm_anyvector_ty], 1187 [IntrNoMem]>; 1188 1189 class AdvSIMD_SVE_INSR_Intrinsic 1190 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1191 [LLVMMatchType<0>, 1192 LLVMVectorElementType<0>], 1193 [IntrNoMem]>; 1194 1195 class AdvSIMD_SVE_PTRUE_Intrinsic 1196 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1197 [llvm_i32_ty], 1198 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1199 1200 class AdvSIMD_SVE_PUNPKHI_Intrinsic 1201 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>], 1202 [llvm_anyvector_ty], 1203 [IntrNoMem]>; 1204 1205 class AdvSIMD_SVE_SCALE_Intrinsic 1206 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1207 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1208 LLVMMatchType<0>, 1209 LLVMVectorOfBitcastsToInt<0>], 1210 [IntrNoMem]>; 1211 1212 class AdvSIMD_SVE_SCVTF_Intrinsic 1213 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1214 [LLVMMatchType<0>, 1215 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1216 llvm_anyvector_ty], 1217 [IntrNoMem]>; 1218 1219 class AdvSIMD_SVE_TSMUL_Intrinsic 1220 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1221 [LLVMMatchType<0>, 1222 LLVMVectorOfBitcastsToInt<0>], 1223 [IntrNoMem]>; 1224 1225 class AdvSIMD_SVE_CNTB_Intrinsic 1226 : DefaultAttrsIntrinsic<[llvm_i64_ty], 1227 [llvm_i32_ty], 1228 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1229 1230 class AdvSIMD_SVE_CNTP_Intrinsic 1231 : DefaultAttrsIntrinsic<[llvm_i64_ty], 1232 [llvm_anyvector_ty, LLVMMatchType<0>], 1233 [IntrNoMem]>; 1234 1235 class AdvSIMD_SVE_DOT_Intrinsic 1236 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1237 [LLVMMatchType<0>, 1238 LLVMSubdivide4VectorType<0>, 1239 LLVMSubdivide4VectorType<0>], 1240 [IntrNoMem]>; 1241 1242 class AdvSIMD_SVE_DOT_Indexed_Intrinsic 1243 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1244 [LLVMMatchType<0>, 1245 LLVMSubdivide4VectorType<0>, 1246 LLVMSubdivide4VectorType<0>, 1247 llvm_i32_ty], 1248 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1249 1250 class AdvSIMD_SVE_PTEST_Intrinsic 1251 : DefaultAttrsIntrinsic<[llvm_i1_ty], 1252 [llvm_anyvector_ty, 1253 LLVMMatchType<0>], 1254 [IntrNoMem]>; 1255 1256 class AdvSIMD_SVE_TBL_Intrinsic 1257 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1258 [LLVMMatchType<0>, 1259 LLVMVectorOfBitcastsToInt<0>], 1260 [IntrNoMem]>; 1261 1262 class AdvSIMD_SVE2_TBX_Intrinsic 1263 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1264 [LLVMMatchType<0>, 1265 LLVMMatchType<0>, 1266 LLVMVectorOfBitcastsToInt<0>], 1267 [IntrNoMem]>; 1268 1269 class SVE2_1VectorArg_Long_Intrinsic 1270 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1271 [LLVMSubdivide2VectorType<0>, 1272 llvm_i32_ty], 1273 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1274 1275 class SVE2_2VectorArg_Long_Intrinsic 1276 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1277 [LLVMSubdivide2VectorType<0>, 1278 LLVMSubdivide2VectorType<0>], 1279 [IntrNoMem]>; 1280 1281 class SVE2_2VectorArgIndexed_Long_Intrinsic 1282 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1283 [LLVMSubdivide2VectorType<0>, 1284 LLVMSubdivide2VectorType<0>, 1285 llvm_i32_ty], 1286 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1287 1288 class SVE2_2VectorArg_Wide_Intrinsic 1289 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1290 [LLVMMatchType<0>, 1291 LLVMSubdivide2VectorType<0>], 1292 [IntrNoMem]>; 1293 1294 class SVE2_2VectorArg_Pred_Long_Intrinsic 1295 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1296 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1297 LLVMMatchType<0>, 1298 LLVMSubdivide2VectorType<0>], 1299 [IntrNoMem]>; 1300 1301 class SVE2_3VectorArg_Long_Intrinsic 1302 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1303 [LLVMMatchType<0>, 1304 LLVMSubdivide2VectorType<0>, 1305 LLVMSubdivide2VectorType<0>], 1306 [IntrNoMem]>; 1307 1308 class SVE2_3VectorArgIndexed_Long_Intrinsic 1309 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1310 [LLVMMatchType<0>, 1311 LLVMSubdivide2VectorType<0>, 1312 LLVMSubdivide2VectorType<0>, 1313 llvm_i32_ty], 1314 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1315 1316 class SVE2_1VectorArg_Narrowing_Intrinsic 1317 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 1318 [llvm_anyvector_ty], 1319 [IntrNoMem]>; 1320 1321 class SVE2_Merged1VectorArg_Narrowing_Intrinsic 1322 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 1323 [LLVMSubdivide2VectorType<0>, 1324 llvm_anyvector_ty], 1325 [IntrNoMem]>; 1326 class SVE2_2VectorArg_Narrowing_Intrinsic 1327 : DefaultAttrsIntrinsic< 1328 [LLVMSubdivide2VectorType<0>], 1329 [llvm_anyvector_ty, LLVMMatchType<0>], 1330 [IntrNoMem]>; 1331 1332 class SVE2_Merged2VectorArg_Narrowing_Intrinsic 1333 : DefaultAttrsIntrinsic< 1334 [LLVMSubdivide2VectorType<0>], 1335 [LLVMSubdivide2VectorType<0>, llvm_anyvector_ty, LLVMMatchType<0>], 1336 [IntrNoMem]>; 1337 1338 class SVE2_1VectorArg_Imm_Narrowing_Intrinsic 1339 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 1340 [llvm_anyvector_ty, llvm_i32_ty], 1341 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1342 1343 class SVE2_2VectorArg_Imm_Narrowing_Intrinsic 1344 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 1345 [LLVMSubdivide2VectorType<0>, llvm_anyvector_ty, 1346 llvm_i32_ty], 1347 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1348 1349 class SVE2_CONFLICT_DETECT_Intrinsic 1350 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1351 [llvm_anyptr_ty, LLVMMatchType<1>], 1352 [IntrNoMem]>; 1353 1354 class SVE2_3VectorArg_Indexed_Intrinsic 1355 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1356 [LLVMMatchType<0>, 1357 LLVMSubdivide2VectorType<0>, 1358 LLVMSubdivide2VectorType<0>, 1359 llvm_i32_ty], 1360 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1361 1362 class AdvSIMD_SVE_CDOT_LANE_Intrinsic 1363 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1364 [LLVMMatchType<0>, 1365 LLVMSubdivide4VectorType<0>, 1366 LLVMSubdivide4VectorType<0>, 1367 llvm_i32_ty, 1368 llvm_i32_ty], 1369 [IntrNoMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1370 1371 // NOTE: There is no relationship between these intrinsics beyond an attempt 1372 // to reuse currently identical class definitions. 1373 class AdvSIMD_SVE_LOGB_Intrinsic : AdvSIMD_SVE_CNT_Intrinsic; 1374 class AdvSIMD_SVE2_CADD_Intrinsic : AdvSIMD_2VectorArgIndexed_Intrinsic; 1375 class AdvSIMD_SVE2_CMLA_Intrinsic : AdvSIMD_3VectorArgIndexed_Intrinsic; 1376 1377 // This class of intrinsics are not intended to be useful within LLVM IR but 1378 // are instead here to support some of the more regid parts of the ACLE. 1379 class Builtin_SVCVT<LLVMType OUT, LLVMType PRED, LLVMType IN> 1380 : DefaultAttrsIntrinsic<[OUT], [OUT, PRED, IN], [IntrNoMem]>; 1381} 1382 1383//===----------------------------------------------------------------------===// 1384// SVE 1385 1386let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 1387 1388class AdvSIMD_SVE_2SVBoolArg_Intrinsic 1389 : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], 1390 [llvm_nxv16i1_ty], 1391 [IntrNoMem]>; 1392 1393class AdvSIMD_SVE_3SVBoolArg_Intrinsic 1394 : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], 1395 [llvm_nxv16i1_ty, llvm_nxv16i1_ty], 1396 [IntrNoMem]>; 1397 1398class AdvSIMD_SVE_Reduce_Intrinsic 1399 : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], 1400 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1401 llvm_anyvector_ty], 1402 [IntrNoMem]>; 1403 1404class AdvSIMD_SVE_V128_Reduce_Intrinsic 1405 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1406 [LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, 1407 llvm_anyvector_ty], 1408 [IntrNoMem]>; 1409 1410 1411class AdvSIMD_SVE_SADDV_Reduce_Intrinsic 1412 : DefaultAttrsIntrinsic<[llvm_i64_ty], 1413 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1414 llvm_anyvector_ty], 1415 [IntrNoMem]>; 1416 1417class AdvSIMD_SVE_WHILE_Intrinsic 1418 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1419 [llvm_anyint_ty, LLVMMatchType<1>], 1420 [IntrNoMem]>; 1421 1422class AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic 1423 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1424 [ 1425 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1426 llvm_ptr_ty, 1427 LLVMScalarOrSameVectorWidth<0, llvm_i64_ty> 1428 ], 1429 [IntrReadMem, IntrArgMemOnly]>; 1430 1431class AdvSIMD_GatherLoad_SV_64b_Offsets_WriteFFR_Intrinsic 1432 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1433 [ 1434 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1435 llvm_ptr_ty, 1436 LLVMScalarOrSameVectorWidth<0, llvm_i64_ty> 1437 ], 1438 [IntrInaccessibleMemOrArgMemOnly]>; 1439 1440class AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic 1441 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1442 [ 1443 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1444 llvm_ptr_ty, 1445 LLVMScalarOrSameVectorWidth<0, llvm_i32_ty> 1446 ], 1447 [IntrReadMem, IntrArgMemOnly]>; 1448 1449class AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic 1450 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1451 [ 1452 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1453 llvm_ptr_ty, 1454 LLVMScalarOrSameVectorWidth<0, llvm_i32_ty> 1455 ], 1456 [IntrInaccessibleMemOrArgMemOnly]>; 1457 1458class AdvSIMD_GatherLoad_VS_Intrinsic 1459 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1460 [ 1461 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1462 llvm_anyvector_ty, 1463 llvm_i64_ty 1464 ], 1465 [IntrReadMem]>; 1466 1467class AdvSIMD_GatherLoadQ_VS_Intrinsic 1468 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1469 [ 1470 llvm_nxv1i1_ty, 1471 llvm_anyvector_ty, 1472 llvm_i64_ty 1473 ], 1474 [IntrReadMem]>; 1475 1476class AdvSIMD_GatherLoadQ_SV_Intrinsic 1477 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1478 [ 1479 llvm_nxv1i1_ty, 1480 llvm_ptr_ty, 1481 llvm_nxv2i64_ty 1482 ], 1483 [IntrReadMem, IntrArgMemOnly]>; 1484 1485class AdvSIMD_GatherLoad_VS_WriteFFR_Intrinsic 1486 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1487 [ 1488 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1489 llvm_anyvector_ty, 1490 llvm_i64_ty 1491 ], 1492 [IntrInaccessibleMemOrArgMemOnly]>; 1493 1494class AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic 1495 : DefaultAttrsIntrinsic<[], 1496 [ 1497 llvm_anyvector_ty, 1498 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1499 llvm_ptr_ty, 1500 LLVMScalarOrSameVectorWidth<0, llvm_i64_ty> 1501 ], 1502 [IntrWriteMem, IntrArgMemOnly]>; 1503 1504class AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic 1505 : DefaultAttrsIntrinsic<[], 1506 [ 1507 llvm_anyvector_ty, 1508 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1509 llvm_ptr_ty, 1510 LLVMScalarOrSameVectorWidth<0, llvm_i32_ty> 1511 ], 1512 [IntrWriteMem, IntrArgMemOnly]>; 1513 1514class AdvSIMD_ScatterStore_VS_Intrinsic 1515 : DefaultAttrsIntrinsic<[], 1516 [ 1517 llvm_anyvector_ty, 1518 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 1519 llvm_anyvector_ty, llvm_i64_ty 1520 ], 1521 [IntrWriteMem]>; 1522 1523class AdvSIMD_ScatterStoreQ_VS_Intrinsic 1524 : DefaultAttrsIntrinsic<[], 1525 [ 1526 llvm_anyvector_ty, 1527 llvm_nxv1i1_ty, 1528 llvm_anyvector_ty, 1529 llvm_i64_ty 1530 ], 1531 [IntrWriteMem]>; 1532 1533class AdvSIMD_ScatterStoreQ_SV_Intrinsic 1534 : DefaultAttrsIntrinsic<[], 1535 [ 1536 llvm_anyvector_ty, 1537 llvm_nxv1i1_ty, 1538 llvm_ptr_ty, 1539 llvm_nxv2i64_ty 1540 ], 1541 [IntrWriteMem, IntrArgMemOnly]>; 1542 1543class SVE_gather_prf_SV 1544 : DefaultAttrsIntrinsic<[], 1545 [ 1546 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate 1547 llvm_ptr_ty, // Base address 1548 llvm_anyvector_ty, // Offsets 1549 llvm_i32_ty // Prfop 1550 ], 1551 [IntrInaccessibleMemOrArgMemOnly, NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<3>>]>; 1552 1553class SVE_gather_prf_VS 1554 : DefaultAttrsIntrinsic<[], 1555 [ 1556 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate 1557 llvm_anyvector_ty, // Base addresses 1558 llvm_i64_ty, // Scalar offset 1559 llvm_i32_ty // Prfop 1560 ], 1561 [IntrInaccessibleMemOrArgMemOnly, ImmArg<ArgIndex<3>>]>; 1562 1563class SVE_MatMul_Intrinsic 1564 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 1565 [LLVMMatchType<0>, LLVMSubdivide4VectorType<0>, LLVMSubdivide4VectorType<0>], 1566 [IntrNoMem]>; 1567 1568class SVE_4Vec_BF16 1569 : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], 1570 [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty], 1571 [IntrNoMem]>; 1572 1573class SVE_4Vec_BF16_Indexed 1574 : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], 1575 [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty, llvm_i32_ty], 1576 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 1577 1578// 1579// Loads 1580// 1581 1582def int_aarch64_sve_ld1 : AdvSIMD_1Vec_PredLoad_Intrinsic; 1583 1584def int_aarch64_sve_ld2_sret : AdvSIMD_2Vec_PredLoad_Intrinsic; 1585def int_aarch64_sve_ld3_sret : AdvSIMD_3Vec_PredLoad_Intrinsic; 1586def int_aarch64_sve_ld4_sret : AdvSIMD_4Vec_PredLoad_Intrinsic; 1587 1588def int_aarch64_sve_ldnt1 : AdvSIMD_1Vec_PredLoad_Intrinsic; 1589def int_aarch64_sve_ldnf1 : AdvSIMD_1Vec_PredLoad_WriteFFR_Intrinsic; 1590def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredLoad_WriteFFR_Intrinsic; 1591 1592def int_aarch64_sve_ld1rq : AdvSIMD_1Vec_PredLoad_Intrinsic; 1593def int_aarch64_sve_ld1ro : AdvSIMD_1Vec_PredLoad_Intrinsic; 1594 1595// 1596// Stores 1597// 1598 1599def int_aarch64_sve_st1 : AdvSIMD_1Vec_PredStore_Intrinsic; 1600def int_aarch64_sve_st2 : AdvSIMD_2Vec_PredStore_Intrinsic; 1601def int_aarch64_sve_st3 : AdvSIMD_3Vec_PredStore_Intrinsic; 1602def int_aarch64_sve_st4 : AdvSIMD_4Vec_PredStore_Intrinsic; 1603 1604def int_aarch64_sve_stnt1 : AdvSIMD_1Vec_PredStore_Intrinsic; 1605 1606// 1607// Prefetches 1608// 1609 1610def int_aarch64_sve_prf 1611 : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i32_ty], 1612 [IntrArgMemOnly, ImmArg<ArgIndex<2>>]>; 1613 1614// Scalar + 32-bit scaled offset vector, zero extend, packed and 1615// unpacked. 1616def int_aarch64_sve_prfb_gather_uxtw_index : SVE_gather_prf_SV; 1617def int_aarch64_sve_prfh_gather_uxtw_index : SVE_gather_prf_SV; 1618def int_aarch64_sve_prfw_gather_uxtw_index : SVE_gather_prf_SV; 1619def int_aarch64_sve_prfd_gather_uxtw_index : SVE_gather_prf_SV; 1620 1621// Scalar + 32-bit scaled offset vector, sign extend, packed and 1622// unpacked. 1623def int_aarch64_sve_prfb_gather_sxtw_index : SVE_gather_prf_SV; 1624def int_aarch64_sve_prfw_gather_sxtw_index : SVE_gather_prf_SV; 1625def int_aarch64_sve_prfh_gather_sxtw_index : SVE_gather_prf_SV; 1626def int_aarch64_sve_prfd_gather_sxtw_index : SVE_gather_prf_SV; 1627 1628// Scalar + 64-bit scaled offset vector. 1629def int_aarch64_sve_prfb_gather_index : SVE_gather_prf_SV; 1630def int_aarch64_sve_prfh_gather_index : SVE_gather_prf_SV; 1631def int_aarch64_sve_prfw_gather_index : SVE_gather_prf_SV; 1632def int_aarch64_sve_prfd_gather_index : SVE_gather_prf_SV; 1633 1634// Vector + scalar. 1635def int_aarch64_sve_prfb_gather_scalar_offset : SVE_gather_prf_VS; 1636def int_aarch64_sve_prfh_gather_scalar_offset : SVE_gather_prf_VS; 1637def int_aarch64_sve_prfw_gather_scalar_offset : SVE_gather_prf_VS; 1638def int_aarch64_sve_prfd_gather_scalar_offset : SVE_gather_prf_VS; 1639 1640// 1641// Scalar to vector operations 1642// 1643 1644def int_aarch64_sve_dup : AdvSIMD_SVE_DUP_Intrinsic; 1645def int_aarch64_sve_dup_x : AdvSIMD_SVE_DUP_Unpred_Intrinsic; 1646 1647def int_aarch64_sve_index : AdvSIMD_SVE_Index_Intrinsic; 1648 1649// 1650// Address calculation 1651// 1652 1653def int_aarch64_sve_adrb : AdvSIMD_2VectorArg_Intrinsic; 1654def int_aarch64_sve_adrh : AdvSIMD_2VectorArg_Intrinsic; 1655def int_aarch64_sve_adrw : AdvSIMD_2VectorArg_Intrinsic; 1656def int_aarch64_sve_adrd : AdvSIMD_2VectorArg_Intrinsic; 1657 1658// 1659// Integer arithmetic 1660// 1661 1662def int_aarch64_sve_add : AdvSIMD_Pred2VectorArg_Intrinsic; 1663def int_aarch64_sve_add_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1664def int_aarch64_sve_sub : AdvSIMD_Pred2VectorArg_Intrinsic; 1665def int_aarch64_sve_sub_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1666def int_aarch64_sve_subr : AdvSIMD_Pred2VectorArg_Intrinsic; 1667 1668def int_aarch64_sve_pmul : AdvSIMD_2VectorArg_Intrinsic; 1669 1670def int_aarch64_sve_mul : AdvSIMD_Pred2VectorArg_Intrinsic; 1671def int_aarch64_sve_mul_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1672def int_aarch64_sve_mul_lane : AdvSIMD_2VectorArgIndexed_Intrinsic; 1673def int_aarch64_sve_smulh : AdvSIMD_Pred2VectorArg_Intrinsic; 1674def int_aarch64_sve_smulh_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1675def int_aarch64_sve_umulh : AdvSIMD_Pred2VectorArg_Intrinsic; 1676def int_aarch64_sve_umulh_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1677 1678def int_aarch64_sve_sdiv : AdvSIMD_Pred2VectorArg_Intrinsic; 1679def int_aarch64_sve_sdiv_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1680def int_aarch64_sve_udiv : AdvSIMD_Pred2VectorArg_Intrinsic; 1681def int_aarch64_sve_udiv_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1682def int_aarch64_sve_sdivr : AdvSIMD_Pred2VectorArg_Intrinsic; 1683def int_aarch64_sve_udivr : AdvSIMD_Pred2VectorArg_Intrinsic; 1684 1685def int_aarch64_sve_smax : AdvSIMD_Pred2VectorArg_Intrinsic; 1686def int_aarch64_sve_smax_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1687def int_aarch64_sve_umax : AdvSIMD_Pred2VectorArg_Intrinsic; 1688def int_aarch64_sve_umax_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1689def int_aarch64_sve_smin : AdvSIMD_Pred2VectorArg_Intrinsic; 1690def int_aarch64_sve_smin_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1691def int_aarch64_sve_umin : AdvSIMD_Pred2VectorArg_Intrinsic; 1692def int_aarch64_sve_umin_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1693def int_aarch64_sve_sabd : AdvSIMD_Pred2VectorArg_Intrinsic; 1694def int_aarch64_sve_sabd_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1695def int_aarch64_sve_uabd : AdvSIMD_Pred2VectorArg_Intrinsic; 1696def int_aarch64_sve_uabd_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1697 1698def int_aarch64_sve_mad : AdvSIMD_Pred3VectorArg_Intrinsic; 1699def int_aarch64_sve_msb : AdvSIMD_Pred3VectorArg_Intrinsic; 1700def int_aarch64_sve_mla : AdvSIMD_Pred3VectorArg_Intrinsic; 1701def int_aarch64_sve_mla_u : AdvSIMD_Pred3VectorArg_Intrinsic; 1702def int_aarch64_sve_mla_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 1703def int_aarch64_sve_mls : AdvSIMD_Pred3VectorArg_Intrinsic; 1704def int_aarch64_sve_mls_u : AdvSIMD_Pred3VectorArg_Intrinsic; 1705def int_aarch64_sve_mls_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 1706 1707def int_aarch64_sve_saddv : AdvSIMD_SVE_SADDV_Reduce_Intrinsic; 1708def int_aarch64_sve_uaddv : AdvSIMD_SVE_SADDV_Reduce_Intrinsic; 1709 1710def int_aarch64_sve_smaxv : AdvSIMD_SVE_Reduce_Intrinsic; 1711def int_aarch64_sve_umaxv : AdvSIMD_SVE_Reduce_Intrinsic; 1712def int_aarch64_sve_sminv : AdvSIMD_SVE_Reduce_Intrinsic; 1713def int_aarch64_sve_uminv : AdvSIMD_SVE_Reduce_Intrinsic; 1714 1715def int_aarch64_sve_orv : AdvSIMD_SVE_Reduce_Intrinsic; 1716def int_aarch64_sve_eorv : AdvSIMD_SVE_Reduce_Intrinsic; 1717def int_aarch64_sve_andv : AdvSIMD_SVE_Reduce_Intrinsic; 1718 1719def int_aarch64_sve_abs : AdvSIMD_Merged1VectorArg_Intrinsic; 1720def int_aarch64_sve_neg : AdvSIMD_Merged1VectorArg_Intrinsic; 1721 1722def int_aarch64_sve_sdot : AdvSIMD_SVE_DOT_Intrinsic; 1723def int_aarch64_sve_sdot_lane : AdvSIMD_SVE_DOT_Indexed_Intrinsic; 1724 1725def int_aarch64_sve_udot : AdvSIMD_SVE_DOT_Intrinsic; 1726def int_aarch64_sve_udot_lane : AdvSIMD_SVE_DOT_Indexed_Intrinsic; 1727 1728def int_aarch64_sve_sqadd_x : AdvSIMD_2VectorArg_Intrinsic; 1729def int_aarch64_sve_sqsub_x : AdvSIMD_2VectorArg_Intrinsic; 1730def int_aarch64_sve_uqadd_x : AdvSIMD_2VectorArg_Intrinsic; 1731def int_aarch64_sve_uqsub_x : AdvSIMD_2VectorArg_Intrinsic; 1732 1733def int_aarch64_sve_orqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1734def int_aarch64_sve_eorqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1735def int_aarch64_sve_andqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1736def int_aarch64_sve_smaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1737def int_aarch64_sve_umaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1738def int_aarch64_sve_sminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1739def int_aarch64_sve_uminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 1740 1741 1742// Shifts 1743 1744def int_aarch64_sve_asr : AdvSIMD_Pred2VectorArg_Intrinsic; 1745def int_aarch64_sve_asr_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1746def int_aarch64_sve_asr_wide : AdvSIMD_SVE_ShiftWide_Intrinsic; 1747def int_aarch64_sve_asrd : AdvSIMD_SVE_ShiftByImm_Intrinsic; 1748def int_aarch64_sve_insr : AdvSIMD_SVE_INSR_Intrinsic; 1749def int_aarch64_sve_lsl : AdvSIMD_Pred2VectorArg_Intrinsic; 1750def int_aarch64_sve_lsl_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1751def int_aarch64_sve_lsl_wide : AdvSIMD_SVE_ShiftWide_Intrinsic; 1752def int_aarch64_sve_lsr : AdvSIMD_Pred2VectorArg_Intrinsic; 1753def int_aarch64_sve_lsr_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1754def int_aarch64_sve_lsr_wide : AdvSIMD_SVE_ShiftWide_Intrinsic; 1755 1756// 1757// Integer comparisons 1758// 1759 1760def int_aarch64_sve_cmpeq : AdvSIMD_SVE_Compare_Intrinsic; 1761def int_aarch64_sve_cmpge : AdvSIMD_SVE_Compare_Intrinsic; 1762def int_aarch64_sve_cmpgt : AdvSIMD_SVE_Compare_Intrinsic; 1763def int_aarch64_sve_cmphi : AdvSIMD_SVE_Compare_Intrinsic; 1764def int_aarch64_sve_cmphs : AdvSIMD_SVE_Compare_Intrinsic; 1765def int_aarch64_sve_cmpne : AdvSIMD_SVE_Compare_Intrinsic; 1766 1767def int_aarch64_sve_cmpeq_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1768def int_aarch64_sve_cmpge_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1769def int_aarch64_sve_cmpgt_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1770def int_aarch64_sve_cmphi_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1771def int_aarch64_sve_cmphs_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1772def int_aarch64_sve_cmple_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1773def int_aarch64_sve_cmplo_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1774def int_aarch64_sve_cmpls_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1775def int_aarch64_sve_cmplt_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1776def int_aarch64_sve_cmpne_wide : AdvSIMD_SVE_CompareWide_Intrinsic; 1777 1778// 1779// Counting bits 1780// 1781 1782def int_aarch64_sve_cls : AdvSIMD_Merged1VectorArg_Intrinsic; 1783def int_aarch64_sve_clz : AdvSIMD_Merged1VectorArg_Intrinsic; 1784def int_aarch64_sve_cnt : AdvSIMD_SVE_CNT_Intrinsic; 1785 1786// 1787// Counting elements 1788// 1789 1790def int_aarch64_sve_cntb : AdvSIMD_SVE_CNTB_Intrinsic; 1791def int_aarch64_sve_cnth : AdvSIMD_SVE_CNTB_Intrinsic; 1792def int_aarch64_sve_cntw : AdvSIMD_SVE_CNTB_Intrinsic; 1793def int_aarch64_sve_cntd : AdvSIMD_SVE_CNTB_Intrinsic; 1794 1795def int_aarch64_sve_cntp : AdvSIMD_SVE_CNTP_Intrinsic; 1796 1797// 1798// FFR manipulation 1799// 1800 1801def int_aarch64_sve_rdffr : ClangBuiltin<"__builtin_sve_svrdffr">, DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], [], [IntrReadMem, IntrInaccessibleMemOnly]>; 1802def int_aarch64_sve_rdffr_z : ClangBuiltin<"__builtin_sve_svrdffr_z">, DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], [llvm_nxv16i1_ty], [IntrReadMem, IntrInaccessibleMemOnly]>; 1803def int_aarch64_sve_setffr : ClangBuiltin<"__builtin_sve_svsetffr">, DefaultAttrsIntrinsic<[], [], [IntrWriteMem, IntrInaccessibleMemOnly]>; 1804def int_aarch64_sve_wrffr : ClangBuiltin<"__builtin_sve_svwrffr">, DefaultAttrsIntrinsic<[], [llvm_nxv16i1_ty], [IntrWriteMem, IntrInaccessibleMemOnly]>; 1805 1806// 1807// Saturating scalar arithmetic 1808// 1809 1810def int_aarch64_sve_sqdech : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1811def int_aarch64_sve_sqdecw : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1812def int_aarch64_sve_sqdecd : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1813def int_aarch64_sve_sqdecp : AdvSIMD_SVE_Saturating_Intrinsic; 1814 1815def int_aarch64_sve_sqdecb_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1816def int_aarch64_sve_sqdecb_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1817def int_aarch64_sve_sqdech_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1818def int_aarch64_sve_sqdech_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1819def int_aarch64_sve_sqdecw_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1820def int_aarch64_sve_sqdecw_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1821def int_aarch64_sve_sqdecd_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1822def int_aarch64_sve_sqdecd_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1823def int_aarch64_sve_sqdecp_n32 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i32_ty>; 1824def int_aarch64_sve_sqdecp_n64 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i64_ty>; 1825 1826def int_aarch64_sve_sqinch : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1827def int_aarch64_sve_sqincw : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1828def int_aarch64_sve_sqincd : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1829def int_aarch64_sve_sqincp : AdvSIMD_SVE_Saturating_Intrinsic; 1830 1831def int_aarch64_sve_sqincb_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1832def int_aarch64_sve_sqincb_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1833def int_aarch64_sve_sqinch_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1834def int_aarch64_sve_sqinch_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1835def int_aarch64_sve_sqincw_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1836def int_aarch64_sve_sqincw_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1837def int_aarch64_sve_sqincd_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1838def int_aarch64_sve_sqincd_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1839def int_aarch64_sve_sqincp_n32 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i32_ty>; 1840def int_aarch64_sve_sqincp_n64 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i64_ty>; 1841 1842def int_aarch64_sve_uqdech : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1843def int_aarch64_sve_uqdecw : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1844def int_aarch64_sve_uqdecd : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1845def int_aarch64_sve_uqdecp : AdvSIMD_SVE_Saturating_Intrinsic; 1846 1847def int_aarch64_sve_uqdecb_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1848def int_aarch64_sve_uqdecb_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1849def int_aarch64_sve_uqdech_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1850def int_aarch64_sve_uqdech_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1851def int_aarch64_sve_uqdecw_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1852def int_aarch64_sve_uqdecw_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1853def int_aarch64_sve_uqdecd_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1854def int_aarch64_sve_uqdecd_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1855def int_aarch64_sve_uqdecp_n32 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i32_ty>; 1856def int_aarch64_sve_uqdecp_n64 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i64_ty>; 1857 1858def int_aarch64_sve_uqinch : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1859def int_aarch64_sve_uqincw : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1860def int_aarch64_sve_uqincd : AdvSIMD_SVE_SaturatingWithPattern_Intrinsic; 1861def int_aarch64_sve_uqincp : AdvSIMD_SVE_Saturating_Intrinsic; 1862 1863def int_aarch64_sve_uqincb_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1864def int_aarch64_sve_uqincb_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1865def int_aarch64_sve_uqinch_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1866def int_aarch64_sve_uqinch_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1867def int_aarch64_sve_uqincw_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1868def int_aarch64_sve_uqincw_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1869def int_aarch64_sve_uqincd_n32 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i32_ty>; 1870def int_aarch64_sve_uqincd_n64 : AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic<llvm_i64_ty>; 1871def int_aarch64_sve_uqincp_n32 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i32_ty>; 1872def int_aarch64_sve_uqincp_n64 : AdvSIMD_SVE_Saturating_N_Intrinsic<llvm_i64_ty>; 1873 1874// 1875// Reversal 1876// 1877 1878def int_aarch64_sve_rbit : AdvSIMD_Merged1VectorArg_Intrinsic; 1879def int_aarch64_sve_revb : AdvSIMD_Merged1VectorArg_Intrinsic; 1880def int_aarch64_sve_revh : AdvSIMD_Merged1VectorArg_Intrinsic; 1881def int_aarch64_sve_revw : AdvSIMD_Merged1VectorArg_Intrinsic; 1882 1883// 1884// Permutations and selection 1885// 1886 1887def int_aarch64_sve_clasta : AdvSIMD_Pred2VectorArg_Intrinsic; 1888def int_aarch64_sve_clasta_n : AdvSIMD_SVE_ReduceWithInit_Intrinsic; 1889def int_aarch64_sve_clastb : AdvSIMD_Pred2VectorArg_Intrinsic; 1890def int_aarch64_sve_clastb_n : AdvSIMD_SVE_ReduceWithInit_Intrinsic; 1891def int_aarch64_sve_compact : AdvSIMD_Pred1VectorArg_Intrinsic; 1892def int_aarch64_sve_dupq_lane : AdvSIMD_SVE_DUPQ_Intrinsic; 1893def int_aarch64_sve_ext : AdvSIMD_2VectorArgIndexed_Intrinsic; 1894def int_aarch64_sve_sel : AdvSIMD_Pred2VectorArg_Intrinsic; 1895def int_aarch64_sve_lasta : AdvSIMD_SVE_Reduce_Intrinsic; 1896def int_aarch64_sve_lastb : AdvSIMD_SVE_Reduce_Intrinsic; 1897def int_aarch64_sve_rev : AdvSIMD_1VectorArg_Intrinsic; 1898def int_aarch64_sve_rev_b16 : AdvSIMD_SVE_2SVBoolArg_Intrinsic; 1899def int_aarch64_sve_rev_b32 : AdvSIMD_SVE_2SVBoolArg_Intrinsic; 1900def int_aarch64_sve_rev_b64 : AdvSIMD_SVE_2SVBoolArg_Intrinsic; 1901def int_aarch64_sve_splice : AdvSIMD_Pred2VectorArg_Intrinsic; 1902def int_aarch64_sve_sunpkhi : AdvSIMD_SVE_Unpack_Intrinsic; 1903def int_aarch64_sve_sunpklo : AdvSIMD_SVE_Unpack_Intrinsic; 1904def int_aarch64_sve_tbl : AdvSIMD_SVE_TBL_Intrinsic; 1905def int_aarch64_sve_trn1 : AdvSIMD_2VectorArg_Intrinsic; 1906def int_aarch64_sve_trn1_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1907def int_aarch64_sve_trn1_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1908def int_aarch64_sve_trn1_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1909def int_aarch64_sve_trn2 : AdvSIMD_2VectorArg_Intrinsic; 1910def int_aarch64_sve_trn2_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1911def int_aarch64_sve_trn2_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1912def int_aarch64_sve_trn2_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1913def int_aarch64_sve_trn1q : AdvSIMD_2VectorArg_Intrinsic; 1914def int_aarch64_sve_trn2q : AdvSIMD_2VectorArg_Intrinsic; 1915def int_aarch64_sve_uunpkhi : AdvSIMD_SVE_Unpack_Intrinsic; 1916def int_aarch64_sve_uunpklo : AdvSIMD_SVE_Unpack_Intrinsic; 1917def int_aarch64_sve_uzp1 : AdvSIMD_2VectorArg_Intrinsic; 1918def int_aarch64_sve_uzp1_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1919def int_aarch64_sve_uzp1_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1920def int_aarch64_sve_uzp1_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1921def int_aarch64_sve_uzp2 : AdvSIMD_2VectorArg_Intrinsic; 1922def int_aarch64_sve_uzp2_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1923def int_aarch64_sve_uzp2_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1924def int_aarch64_sve_uzp2_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1925def int_aarch64_sve_uzp1q : AdvSIMD_2VectorArg_Intrinsic; 1926def int_aarch64_sve_uzp2q : AdvSIMD_2VectorArg_Intrinsic; 1927def int_aarch64_sve_zip1 : AdvSIMD_2VectorArg_Intrinsic; 1928def int_aarch64_sve_zip1_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1929def int_aarch64_sve_zip1_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1930def int_aarch64_sve_zip1_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1931def int_aarch64_sve_zip2 : AdvSIMD_2VectorArg_Intrinsic; 1932def int_aarch64_sve_zip2_b16 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1933def int_aarch64_sve_zip2_b32 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1934def int_aarch64_sve_zip2_b64 : AdvSIMD_SVE_3SVBoolArg_Intrinsic; 1935def int_aarch64_sve_zip1q : AdvSIMD_2VectorArg_Intrinsic; 1936def int_aarch64_sve_zip2q : AdvSIMD_2VectorArg_Intrinsic; 1937 1938// 1939// Logical operations 1940// 1941 1942def int_aarch64_sve_and : AdvSIMD_Pred2VectorArg_Intrinsic; 1943def int_aarch64_sve_and_u: AdvSIMD_Pred2VectorArg_Intrinsic; 1944def int_aarch64_sve_bic : AdvSIMD_Pred2VectorArg_Intrinsic; 1945def int_aarch64_sve_bic_u: AdvSIMD_Pred2VectorArg_Intrinsic; 1946def int_aarch64_sve_cnot : AdvSIMD_Merged1VectorArg_Intrinsic; 1947def int_aarch64_sve_eor : AdvSIMD_Pred2VectorArg_Intrinsic; 1948def int_aarch64_sve_eor_u: AdvSIMD_Pred2VectorArg_Intrinsic; 1949def int_aarch64_sve_not : AdvSIMD_Merged1VectorArg_Intrinsic; 1950def int_aarch64_sve_orr : AdvSIMD_Pred2VectorArg_Intrinsic; 1951def int_aarch64_sve_orr_u: AdvSIMD_Pred2VectorArg_Intrinsic; 1952 1953// 1954// Conversion 1955// 1956 1957def int_aarch64_sve_sxtb : AdvSIMD_Merged1VectorArg_Intrinsic; 1958def int_aarch64_sve_sxth : AdvSIMD_Merged1VectorArg_Intrinsic; 1959def int_aarch64_sve_sxtw : AdvSIMD_Merged1VectorArg_Intrinsic; 1960def int_aarch64_sve_uxtb : AdvSIMD_Merged1VectorArg_Intrinsic; 1961def int_aarch64_sve_uxth : AdvSIMD_Merged1VectorArg_Intrinsic; 1962def int_aarch64_sve_uxtw : AdvSIMD_Merged1VectorArg_Intrinsic; 1963 1964// 1965// While comparisons 1966// 1967 1968def int_aarch64_sve_whilele : AdvSIMD_SVE_WHILE_Intrinsic; 1969def int_aarch64_sve_whilelo : AdvSIMD_SVE_WHILE_Intrinsic; 1970def int_aarch64_sve_whilels : AdvSIMD_SVE_WHILE_Intrinsic; 1971def int_aarch64_sve_whilelt : AdvSIMD_SVE_WHILE_Intrinsic; 1972def int_aarch64_sve_whilege : AdvSIMD_SVE_WHILE_Intrinsic; 1973def int_aarch64_sve_whilegt : AdvSIMD_SVE_WHILE_Intrinsic; 1974def int_aarch64_sve_whilehs : AdvSIMD_SVE_WHILE_Intrinsic; 1975def int_aarch64_sve_whilehi : AdvSIMD_SVE_WHILE_Intrinsic; 1976 1977// 1978// Floating-point arithmetic 1979// 1980 1981def int_aarch64_sve_fabd : AdvSIMD_Pred2VectorArg_Intrinsic; 1982def int_aarch64_sve_fabd_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1983def int_aarch64_sve_fabs : AdvSIMD_Merged1VectorArg_Intrinsic; 1984def int_aarch64_sve_fadd : AdvSIMD_Pred2VectorArg_Intrinsic; 1985def int_aarch64_sve_fadd_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1986def int_aarch64_sve_fcadd : AdvSIMD_SVE_CADD_Intrinsic; 1987def int_aarch64_sve_fcmla : AdvSIMD_SVE_CMLA_Intrinsic; 1988def int_aarch64_sve_fcmla_lane : AdvSIMD_SVE_CMLA_LANE_Intrinsic; 1989def int_aarch64_sve_fdiv : AdvSIMD_Pred2VectorArg_Intrinsic; 1990def int_aarch64_sve_fdiv_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1991def int_aarch64_sve_fdivr : AdvSIMD_Pred2VectorArg_Intrinsic; 1992def int_aarch64_sve_fexpa_x : AdvSIMD_SVE_EXPA_Intrinsic; 1993def int_aarch64_sve_fmad : AdvSIMD_Pred3VectorArg_Intrinsic; 1994def int_aarch64_sve_fmax : AdvSIMD_Pred2VectorArg_Intrinsic; 1995def int_aarch64_sve_fmax_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1996def int_aarch64_sve_fmaxnm : AdvSIMD_Pred2VectorArg_Intrinsic; 1997def int_aarch64_sve_fmaxnm_u : AdvSIMD_Pred2VectorArg_Intrinsic; 1998def int_aarch64_sve_fmin : AdvSIMD_Pred2VectorArg_Intrinsic; 1999def int_aarch64_sve_fmin_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2000def int_aarch64_sve_fminnm : AdvSIMD_Pred2VectorArg_Intrinsic; 2001def int_aarch64_sve_fminnm_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2002def int_aarch64_sve_fmla : AdvSIMD_Pred3VectorArg_Intrinsic; 2003def int_aarch64_sve_fmla_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 2004def int_aarch64_sve_fmla_u : AdvSIMD_Pred3VectorArg_Intrinsic; 2005def int_aarch64_sve_fmls : AdvSIMD_Pred3VectorArg_Intrinsic; 2006def int_aarch64_sve_fmls_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 2007def int_aarch64_sve_fmls_u : AdvSIMD_Pred3VectorArg_Intrinsic; 2008def int_aarch64_sve_fmsb : AdvSIMD_Pred3VectorArg_Intrinsic; 2009def int_aarch64_sve_fmul : AdvSIMD_Pred2VectorArg_Intrinsic; 2010def int_aarch64_sve_fmul_lane : AdvSIMD_2VectorArgIndexed_Intrinsic; 2011def int_aarch64_sve_fmul_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2012def int_aarch64_sve_fmulx : AdvSIMD_Pred2VectorArg_Intrinsic; 2013def int_aarch64_sve_fmulx_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2014def int_aarch64_sve_fneg : AdvSIMD_Merged1VectorArg_Intrinsic; 2015def int_aarch64_sve_fnmad : AdvSIMD_Pred3VectorArg_Intrinsic; 2016def int_aarch64_sve_fnmla : AdvSIMD_Pred3VectorArg_Intrinsic; 2017def int_aarch64_sve_fnmla_u : AdvSIMD_Pred3VectorArg_Intrinsic; 2018def int_aarch64_sve_fnmls : AdvSIMD_Pred3VectorArg_Intrinsic; 2019def int_aarch64_sve_fnmls_u : AdvSIMD_Pred3VectorArg_Intrinsic; 2020def int_aarch64_sve_fnmsb : AdvSIMD_Pred3VectorArg_Intrinsic; 2021def int_aarch64_sve_frecpe_x : AdvSIMD_1VectorArg_Intrinsic; 2022def int_aarch64_sve_frecps_x : AdvSIMD_2VectorArg_Intrinsic; 2023def int_aarch64_sve_frecpx : AdvSIMD_Merged1VectorArg_Intrinsic; 2024def int_aarch64_sve_frinta : AdvSIMD_Merged1VectorArg_Intrinsic; 2025def int_aarch64_sve_frinti : AdvSIMD_Merged1VectorArg_Intrinsic; 2026def int_aarch64_sve_frintm : AdvSIMD_Merged1VectorArg_Intrinsic; 2027def int_aarch64_sve_frintn : AdvSIMD_Merged1VectorArg_Intrinsic; 2028def int_aarch64_sve_frintp : AdvSIMD_Merged1VectorArg_Intrinsic; 2029def int_aarch64_sve_frintx : AdvSIMD_Merged1VectorArg_Intrinsic; 2030def int_aarch64_sve_frintz : AdvSIMD_Merged1VectorArg_Intrinsic; 2031def int_aarch64_sve_frsqrte_x : AdvSIMD_1VectorArg_Intrinsic; 2032def int_aarch64_sve_frsqrts_x : AdvSIMD_2VectorArg_Intrinsic; 2033def int_aarch64_sve_fscale : AdvSIMD_SVE_SCALE_Intrinsic; 2034def int_aarch64_sve_fsqrt : AdvSIMD_Merged1VectorArg_Intrinsic; 2035def int_aarch64_sve_fsub : AdvSIMD_Pred2VectorArg_Intrinsic; 2036def int_aarch64_sve_fsub_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2037def int_aarch64_sve_fsubr : AdvSIMD_Pred2VectorArg_Intrinsic; 2038def int_aarch64_sve_ftmad_x : AdvSIMD_2VectorArgIndexed_Intrinsic; 2039def int_aarch64_sve_ftsmul_x : AdvSIMD_SVE_TSMUL_Intrinsic; 2040def int_aarch64_sve_ftssel_x : AdvSIMD_SVE_TSMUL_Intrinsic; 2041 2042// 2043// Floating-point reductions 2044// 2045 2046def int_aarch64_sve_fadda : AdvSIMD_SVE_ReduceWithInit_Intrinsic; 2047def int_aarch64_sve_faddv : AdvSIMD_SVE_Reduce_Intrinsic; 2048def int_aarch64_sve_fmaxv : AdvSIMD_SVE_Reduce_Intrinsic; 2049def int_aarch64_sve_fmaxnmv : AdvSIMD_SVE_Reduce_Intrinsic; 2050def int_aarch64_sve_fminv : AdvSIMD_SVE_Reduce_Intrinsic; 2051def int_aarch64_sve_fminnmv : AdvSIMD_SVE_Reduce_Intrinsic; 2052def int_aarch64_sve_addqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 2053def int_aarch64_sve_fmaxnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 2054def int_aarch64_sve_fminnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 2055def int_aarch64_sve_fmaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 2056def int_aarch64_sve_fminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; 2057 2058// 2059// Floating-point conversions 2060// 2061 2062def int_aarch64_sve_fcvt : AdvSIMD_SVE_FCVT_Intrinsic; 2063def int_aarch64_sve_fcvtzs : AdvSIMD_SVE_FCVTZS_Intrinsic; 2064def int_aarch64_sve_fcvtzu : AdvSIMD_SVE_FCVTZS_Intrinsic; 2065def int_aarch64_sve_scvtf : AdvSIMD_SVE_SCVTF_Intrinsic; 2066def int_aarch64_sve_ucvtf : AdvSIMD_SVE_SCVTF_Intrinsic; 2067 2068// 2069// Floating-point comparisons 2070// 2071 2072def int_aarch64_sve_facge : AdvSIMD_SVE_Compare_Intrinsic; 2073def int_aarch64_sve_facgt : AdvSIMD_SVE_Compare_Intrinsic; 2074 2075def int_aarch64_sve_fcmpeq : AdvSIMD_SVE_Compare_Intrinsic; 2076def int_aarch64_sve_fcmpge : AdvSIMD_SVE_Compare_Intrinsic; 2077def int_aarch64_sve_fcmpgt : AdvSIMD_SVE_Compare_Intrinsic; 2078def int_aarch64_sve_fcmpne : AdvSIMD_SVE_Compare_Intrinsic; 2079def int_aarch64_sve_fcmpuo : AdvSIMD_SVE_Compare_Intrinsic; 2080 2081def int_aarch64_sve_fcvtzs_i32f16 : Builtin_SVCVT<llvm_nxv4i32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>; 2082def int_aarch64_sve_fcvtzs_i32f64 : Builtin_SVCVT<llvm_nxv4i32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2083def int_aarch64_sve_fcvtzs_i64f16 : Builtin_SVCVT<llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>; 2084def int_aarch64_sve_fcvtzs_i64f32 : Builtin_SVCVT<llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>; 2085 2086def int_aarch64_sve_fcvt_bf16f32 : Builtin_SVCVT<llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>; 2087def int_aarch64_sve_fcvtnt_bf16f32 : Builtin_SVCVT<llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>; 2088 2089def int_aarch64_sve_fcvtzu_i32f16 : Builtin_SVCVT<llvm_nxv4i32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>; 2090def int_aarch64_sve_fcvtzu_i32f64 : Builtin_SVCVT<llvm_nxv4i32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2091def int_aarch64_sve_fcvtzu_i64f16 : Builtin_SVCVT<llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>; 2092def int_aarch64_sve_fcvtzu_i64f32 : Builtin_SVCVT<llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>; 2093 2094def int_aarch64_sve_fcvt_f16f32 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4f32_ty>; 2095def int_aarch64_sve_fcvt_f16f64 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2096def int_aarch64_sve_fcvt_f32f64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2097 2098def int_aarch64_sve_fcvt_f32f16 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>; 2099def int_aarch64_sve_fcvt_f64f16 : Builtin_SVCVT<llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>; 2100def int_aarch64_sve_fcvt_f64f32 : Builtin_SVCVT<llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>; 2101 2102def int_aarch64_sve_fcvtlt_f32f16 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>; 2103def int_aarch64_sve_fcvtlt_f64f32 : Builtin_SVCVT<llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>; 2104def int_aarch64_sve_fcvtnt_f16f32 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4f32_ty>; 2105def int_aarch64_sve_fcvtnt_f32f64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2106 2107def int_aarch64_sve_fcvtx_f32f64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2108def int_aarch64_sve_fcvtxnt_f32f64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>; 2109 2110def int_aarch64_sve_scvtf_f16i32 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4i32_ty>; 2111def int_aarch64_sve_scvtf_f16i64 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>; 2112def int_aarch64_sve_scvtf_f32i64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>; 2113def int_aarch64_sve_scvtf_f64i32 : Builtin_SVCVT<llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4i32_ty>; 2114 2115def int_aarch64_sve_ucvtf_f16i32 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4i32_ty>; 2116def int_aarch64_sve_ucvtf_f16i64 : Builtin_SVCVT<llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>; 2117def int_aarch64_sve_ucvtf_f32i64 : Builtin_SVCVT<llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>; 2118def int_aarch64_sve_ucvtf_f64i32 : Builtin_SVCVT<llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4i32_ty>; 2119 2120// 2121// Predicate creation 2122// 2123 2124def int_aarch64_sve_ptrue : AdvSIMD_SVE_PTRUE_Intrinsic; 2125 2126// 2127// Predicate operations 2128// 2129 2130def int_aarch64_sve_and_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2131def int_aarch64_sve_bic_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2132def int_aarch64_sve_brka : AdvSIMD_Merged1VectorArg_Intrinsic; 2133def int_aarch64_sve_brka_z : AdvSIMD_Pred1VectorArg_Intrinsic; 2134def int_aarch64_sve_brkb : AdvSIMD_Merged1VectorArg_Intrinsic; 2135def int_aarch64_sve_brkb_z : AdvSIMD_Pred1VectorArg_Intrinsic; 2136def int_aarch64_sve_brkn_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2137def int_aarch64_sve_brkpa_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2138def int_aarch64_sve_brkpb_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2139def int_aarch64_sve_eor_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2140def int_aarch64_sve_nand_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2141def int_aarch64_sve_nor_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2142def int_aarch64_sve_orn_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2143def int_aarch64_sve_orr_z : AdvSIMD_Pred2VectorArg_Intrinsic; 2144def int_aarch64_sve_pfirst : AdvSIMD_Pred1VectorArg_Intrinsic; 2145def int_aarch64_sve_pnext : AdvSIMD_Pred1VectorArg_Intrinsic; 2146def int_aarch64_sve_punpkhi : AdvSIMD_SVE_PUNPKHI_Intrinsic; 2147def int_aarch64_sve_punpklo : AdvSIMD_SVE_PUNPKHI_Intrinsic; 2148 2149// 2150// Testing predicates 2151// 2152 2153def int_aarch64_sve_ptest_any : AdvSIMD_SVE_PTEST_Intrinsic; 2154def int_aarch64_sve_ptest_first : AdvSIMD_SVE_PTEST_Intrinsic; 2155def int_aarch64_sve_ptest_last : AdvSIMD_SVE_PTEST_Intrinsic; 2156 2157// 2158// Reinterpreting data 2159// 2160 2161def int_aarch64_sve_convert_from_svbool : DefaultAttrsIntrinsic<[llvm_any_ty], 2162 [llvm_nxv16i1_ty], 2163 [IntrNoMem]>; 2164 2165def int_aarch64_sve_convert_to_svbool : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], 2166 [llvm_any_ty], 2167 [IntrNoMem]>; 2168 2169// 2170// Gather loads: scalar base + vector offsets 2171// 2172 2173// 64 bit unscaled offsets 2174def int_aarch64_sve_ld1_gather : AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic; 2175 2176// 64 bit scaled offsets 2177def int_aarch64_sve_ld1_gather_index : AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic; 2178 2179// 32 bit unscaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits 2180def int_aarch64_sve_ld1_gather_sxtw : AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic; 2181def int_aarch64_sve_ld1_gather_uxtw : AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic; 2182 2183// 32 bit scaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits 2184def int_aarch64_sve_ld1_gather_sxtw_index : AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic; 2185def int_aarch64_sve_ld1_gather_uxtw_index : AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic; 2186 2187// 128-bit loads, scaled offsets (indices) 2188def int_aarch64_sve_ld1q_gather_index : AdvSIMD_GatherLoadQ_SV_Intrinsic; 2189 2190// 128-bit loads, unscaled offsets 2191def int_aarch64_sve_ld1q_gather_vector_offset : AdvSIMD_GatherLoadQ_SV_Intrinsic; 2192 2193// 2194// Gather loads: vector base + scalar offset 2195// 2196 2197def int_aarch64_sve_ld1_gather_scalar_offset : AdvSIMD_GatherLoad_VS_Intrinsic; 2198 2199// 128-bit loads, unscaled offsets 2200def int_aarch64_sve_ld1q_gather_scalar_offset : AdvSIMD_GatherLoadQ_VS_Intrinsic; 2201 2202// 2203// First-faulting gather loads: scalar base + vector offsets 2204// 2205 2206// 64 bit unscaled offsets 2207def int_aarch64_sve_ldff1_gather : AdvSIMD_GatherLoad_SV_64b_Offsets_WriteFFR_Intrinsic; 2208 2209// 64 bit scaled offsets 2210def int_aarch64_sve_ldff1_gather_index : AdvSIMD_GatherLoad_SV_64b_Offsets_WriteFFR_Intrinsic; 2211 2212// 32 bit unscaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits 2213def int_aarch64_sve_ldff1_gather_sxtw : AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic; 2214def int_aarch64_sve_ldff1_gather_uxtw : AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic; 2215 2216// 32 bit scaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits 2217def int_aarch64_sve_ldff1_gather_sxtw_index : AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic; 2218def int_aarch64_sve_ldff1_gather_uxtw_index : AdvSIMD_GatherLoad_SV_32b_Offsets_WriteFFR_Intrinsic; 2219 2220// 2221// First-faulting gather loads: vector base + scalar offset 2222// 2223 2224def int_aarch64_sve_ldff1_gather_scalar_offset : AdvSIMD_GatherLoad_VS_WriteFFR_Intrinsic; 2225 2226 2227// 2228// Non-temporal gather loads: scalar base + vector offsets 2229// 2230 2231// 64 bit unscaled offsets 2232def int_aarch64_sve_ldnt1_gather : AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic; 2233 2234// 64 bit indices 2235def int_aarch64_sve_ldnt1_gather_index : AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic; 2236 2237// 32 bit unscaled offsets, zero (zxtw) extended to 64 bits 2238def int_aarch64_sve_ldnt1_gather_uxtw : AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic; 2239 2240// 2241// Non-temporal gather loads: vector base + scalar offset 2242// 2243 2244def int_aarch64_sve_ldnt1_gather_scalar_offset : AdvSIMD_GatherLoad_VS_Intrinsic; 2245 2246// 2247// Scatter stores: scalar base + vector offsets 2248// 2249 2250// 64 bit unscaled offsets 2251def int_aarch64_sve_st1_scatter : AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic; 2252 2253// 64 bit scaled offsets 2254def int_aarch64_sve_st1_scatter_index 2255 : AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic; 2256 2257// 32 bit unscaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits 2258def int_aarch64_sve_st1_scatter_sxtw 2259 : AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic; 2260 2261def int_aarch64_sve_st1_scatter_uxtw 2262 : AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic; 2263 2264// 32 bit scaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits 2265def int_aarch64_sve_st1_scatter_sxtw_index 2266 : AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic; 2267 2268def int_aarch64_sve_st1_scatter_uxtw_index 2269 : AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic; 2270 2271// 128-bit stores, scaled offsets (indices) 2272def int_aarch64_sve_st1q_scatter_index : AdvSIMD_ScatterStoreQ_SV_Intrinsic; 2273 2274// 128-bit stores, unscaled offsets 2275def int_aarch64_sve_st1q_scatter_vector_offset : AdvSIMD_ScatterStoreQ_SV_Intrinsic; 2276 2277// 2278// Scatter stores: vector base + scalar offset 2279// 2280 2281def int_aarch64_sve_st1_scatter_scalar_offset : AdvSIMD_ScatterStore_VS_Intrinsic; 2282 2283// 128-bit stores, unscaled offsets 2284def int_aarch64_sve_st1q_scatter_scalar_offset : AdvSIMD_ScatterStoreQ_VS_Intrinsic; 2285 2286// 2287// Non-temporal scatter stores: scalar base + vector offsets 2288// 2289 2290// 64 bit unscaled offsets 2291def int_aarch64_sve_stnt1_scatter : AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic; 2292 2293// 64 bit indices 2294def int_aarch64_sve_stnt1_scatter_index 2295 : AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic; 2296 2297// 32 bit unscaled offsets, zero (zxtw) extended to 64 bits 2298def int_aarch64_sve_stnt1_scatter_uxtw : AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic; 2299 2300// 2301// Non-temporal scatter stores: vector base + scalar offset 2302// 2303 2304def int_aarch64_sve_stnt1_scatter_scalar_offset : AdvSIMD_ScatterStore_VS_Intrinsic; 2305 2306// 2307// SVE2 - Uniform DSP operations 2308// 2309 2310def int_aarch64_sve_saba : AdvSIMD_3VectorArg_Intrinsic; 2311def int_aarch64_sve_shadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2312def int_aarch64_sve_shsub : AdvSIMD_Pred2VectorArg_Intrinsic; 2313def int_aarch64_sve_shsubr : AdvSIMD_Pred2VectorArg_Intrinsic; 2314def int_aarch64_sve_sli : AdvSIMD_2VectorArgIndexed_Intrinsic; 2315def int_aarch64_sve_sqabs : AdvSIMD_Merged1VectorArg_Intrinsic; 2316def int_aarch64_sve_sqadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2317def int_aarch64_sve_sqdmulh : AdvSIMD_2VectorArg_Intrinsic; 2318def int_aarch64_sve_sqdmulh_lane : AdvSIMD_2VectorArgIndexed_Intrinsic; 2319def int_aarch64_sve_sqneg : AdvSIMD_Merged1VectorArg_Intrinsic; 2320def int_aarch64_sve_sqrdmlah : AdvSIMD_3VectorArg_Intrinsic; 2321def int_aarch64_sve_sqrdmlah_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 2322def int_aarch64_sve_sqrdmlsh : AdvSIMD_3VectorArg_Intrinsic; 2323def int_aarch64_sve_sqrdmlsh_lane : AdvSIMD_3VectorArgIndexed_Intrinsic; 2324def int_aarch64_sve_sqrdmulh : AdvSIMD_2VectorArg_Intrinsic; 2325def int_aarch64_sve_sqrdmulh_lane : AdvSIMD_2VectorArgIndexed_Intrinsic; 2326def int_aarch64_sve_sqrshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2327def int_aarch64_sve_sqshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2328def int_aarch64_sve_sqshlu : AdvSIMD_SVE_ShiftByImm_Intrinsic; 2329def int_aarch64_sve_sqsub : AdvSIMD_Pred2VectorArg_Intrinsic; 2330def int_aarch64_sve_sqsub_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2331def int_aarch64_sve_sqsubr : AdvSIMD_Pred2VectorArg_Intrinsic; 2332def int_aarch64_sve_srhadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2333def int_aarch64_sve_sri : AdvSIMD_2VectorArgIndexed_Intrinsic; 2334def int_aarch64_sve_srshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2335def int_aarch64_sve_srshr : AdvSIMD_SVE_ShiftByImm_Intrinsic; 2336def int_aarch64_sve_srsra : AdvSIMD_2VectorArgIndexed_Intrinsic; 2337def int_aarch64_sve_ssra : AdvSIMD_2VectorArgIndexed_Intrinsic; 2338def int_aarch64_sve_suqadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2339def int_aarch64_sve_uaba : AdvSIMD_3VectorArg_Intrinsic; 2340def int_aarch64_sve_uhadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2341def int_aarch64_sve_uhsub : AdvSIMD_Pred2VectorArg_Intrinsic; 2342def int_aarch64_sve_uhsubr : AdvSIMD_Pred2VectorArg_Intrinsic; 2343def int_aarch64_sve_uqadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2344def int_aarch64_sve_uqrshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2345def int_aarch64_sve_uqshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2346def int_aarch64_sve_uqsub : AdvSIMD_Pred2VectorArg_Intrinsic; 2347def int_aarch64_sve_uqsub_u : AdvSIMD_Pred2VectorArg_Intrinsic; 2348def int_aarch64_sve_uqsubr : AdvSIMD_Pred2VectorArg_Intrinsic; 2349def int_aarch64_sve_urecpe : AdvSIMD_Merged1VectorArg_Intrinsic; 2350def int_aarch64_sve_urhadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2351def int_aarch64_sve_urshl : AdvSIMD_Pred2VectorArg_Intrinsic; 2352def int_aarch64_sve_urshr : AdvSIMD_SVE_ShiftByImm_Intrinsic; 2353def int_aarch64_sve_ursqrte : AdvSIMD_Merged1VectorArg_Intrinsic; 2354def int_aarch64_sve_ursra : AdvSIMD_2VectorArgIndexed_Intrinsic; 2355def int_aarch64_sve_usqadd : AdvSIMD_Pred2VectorArg_Intrinsic; 2356def int_aarch64_sve_usra : AdvSIMD_2VectorArgIndexed_Intrinsic; 2357 2358// 2359// SVE2 - Widening DSP operations 2360// 2361 2362def int_aarch64_sve_sabalb : SVE2_3VectorArg_Long_Intrinsic; 2363def int_aarch64_sve_sabalt : SVE2_3VectorArg_Long_Intrinsic; 2364def int_aarch64_sve_sabdlb : SVE2_2VectorArg_Long_Intrinsic; 2365def int_aarch64_sve_sabdlt : SVE2_2VectorArg_Long_Intrinsic; 2366def int_aarch64_sve_saddlb : SVE2_2VectorArg_Long_Intrinsic; 2367def int_aarch64_sve_saddlt : SVE2_2VectorArg_Long_Intrinsic; 2368def int_aarch64_sve_saddwb : SVE2_2VectorArg_Wide_Intrinsic; 2369def int_aarch64_sve_saddwt : SVE2_2VectorArg_Wide_Intrinsic; 2370def int_aarch64_sve_sshllb : SVE2_1VectorArg_Long_Intrinsic; 2371def int_aarch64_sve_sshllt : SVE2_1VectorArg_Long_Intrinsic; 2372def int_aarch64_sve_ssublb : SVE2_2VectorArg_Long_Intrinsic; 2373def int_aarch64_sve_ssublt : SVE2_2VectorArg_Long_Intrinsic; 2374def int_aarch64_sve_ssubwb : SVE2_2VectorArg_Wide_Intrinsic; 2375def int_aarch64_sve_ssubwt : SVE2_2VectorArg_Wide_Intrinsic; 2376def int_aarch64_sve_uabalb : SVE2_3VectorArg_Long_Intrinsic; 2377def int_aarch64_sve_uabalt : SVE2_3VectorArg_Long_Intrinsic; 2378def int_aarch64_sve_uabdlb : SVE2_2VectorArg_Long_Intrinsic; 2379def int_aarch64_sve_uabdlt : SVE2_2VectorArg_Long_Intrinsic; 2380def int_aarch64_sve_uaddlb : SVE2_2VectorArg_Long_Intrinsic; 2381def int_aarch64_sve_uaddlt : SVE2_2VectorArg_Long_Intrinsic; 2382def int_aarch64_sve_uaddwb : SVE2_2VectorArg_Wide_Intrinsic; 2383def int_aarch64_sve_uaddwt : SVE2_2VectorArg_Wide_Intrinsic; 2384def int_aarch64_sve_ushllb : SVE2_1VectorArg_Long_Intrinsic; 2385def int_aarch64_sve_ushllt : SVE2_1VectorArg_Long_Intrinsic; 2386def int_aarch64_sve_usublb : SVE2_2VectorArg_Long_Intrinsic; 2387def int_aarch64_sve_usublt : SVE2_2VectorArg_Long_Intrinsic; 2388def int_aarch64_sve_usubwb : SVE2_2VectorArg_Wide_Intrinsic; 2389def int_aarch64_sve_usubwt : SVE2_2VectorArg_Wide_Intrinsic; 2390 2391// 2392// SVE2 - Non-widening pairwise arithmetic 2393// 2394 2395def int_aarch64_sve_addp : AdvSIMD_Pred2VectorArg_Intrinsic; 2396def int_aarch64_sve_faddp : AdvSIMD_Pred2VectorArg_Intrinsic; 2397def int_aarch64_sve_fmaxp : AdvSIMD_Pred2VectorArg_Intrinsic; 2398def int_aarch64_sve_fmaxnmp : AdvSIMD_Pred2VectorArg_Intrinsic; 2399def int_aarch64_sve_fminp : AdvSIMD_Pred2VectorArg_Intrinsic; 2400def int_aarch64_sve_fminnmp : AdvSIMD_Pred2VectorArg_Intrinsic; 2401def int_aarch64_sve_smaxp : AdvSIMD_Pred2VectorArg_Intrinsic; 2402def int_aarch64_sve_sminp : AdvSIMD_Pred2VectorArg_Intrinsic; 2403def int_aarch64_sve_umaxp : AdvSIMD_Pred2VectorArg_Intrinsic; 2404def int_aarch64_sve_uminp : AdvSIMD_Pred2VectorArg_Intrinsic; 2405 2406// 2407// SVE2 - Widening pairwise arithmetic 2408// 2409 2410def int_aarch64_sve_sadalp : SVE2_2VectorArg_Pred_Long_Intrinsic; 2411def int_aarch64_sve_uadalp : SVE2_2VectorArg_Pred_Long_Intrinsic; 2412 2413// 2414// SVE2 - Uniform complex integer arithmetic 2415// 2416 2417def int_aarch64_sve_cadd_x : AdvSIMD_SVE2_CADD_Intrinsic; 2418def int_aarch64_sve_sqcadd_x : AdvSIMD_SVE2_CADD_Intrinsic; 2419def int_aarch64_sve_cmla_x : AdvSIMD_SVE2_CMLA_Intrinsic; 2420def int_aarch64_sve_cmla_lane_x : AdvSIMD_SVE_CMLA_LANE_Intrinsic; 2421def int_aarch64_sve_sqrdcmlah_x : AdvSIMD_SVE2_CMLA_Intrinsic; 2422def int_aarch64_sve_sqrdcmlah_lane_x : AdvSIMD_SVE_CMLA_LANE_Intrinsic; 2423 2424// 2425// SVE2 - Widening complex integer arithmetic 2426// 2427 2428def int_aarch64_sve_saddlbt : SVE2_2VectorArg_Long_Intrinsic; 2429def int_aarch64_sve_ssublbt : SVE2_2VectorArg_Long_Intrinsic; 2430def int_aarch64_sve_ssubltb : SVE2_2VectorArg_Long_Intrinsic; 2431 2432// 2433// SVE2 - Widening complex integer dot product 2434// 2435 2436def int_aarch64_sve_cdot : AdvSIMD_SVE_DOT_Indexed_Intrinsic; 2437def int_aarch64_sve_cdot_lane : AdvSIMD_SVE_CDOT_LANE_Intrinsic; 2438 2439// 2440// SVE2 - Floating-point widening multiply-accumulate 2441// 2442 2443def int_aarch64_sve_fmlalb : SVE2_3VectorArg_Long_Intrinsic; 2444def int_aarch64_sve_fmlalb_lane : SVE2_3VectorArgIndexed_Long_Intrinsic; 2445def int_aarch64_sve_fmlalt : SVE2_3VectorArg_Long_Intrinsic; 2446def int_aarch64_sve_fmlalt_lane : SVE2_3VectorArgIndexed_Long_Intrinsic; 2447def int_aarch64_sve_fmlslb : SVE2_3VectorArg_Long_Intrinsic; 2448def int_aarch64_sve_fmlslb_lane : SVE2_3VectorArgIndexed_Long_Intrinsic; 2449def int_aarch64_sve_fmlslt : SVE2_3VectorArg_Long_Intrinsic; 2450def int_aarch64_sve_fmlslt_lane : SVE2_3VectorArgIndexed_Long_Intrinsic; 2451 2452// 2453// SVE2 - Floating-point integer binary logarithm 2454// 2455 2456def int_aarch64_sve_flogb : AdvSIMD_SVE_LOGB_Intrinsic; 2457 2458// 2459// SVE2 - Vector histogram count 2460// 2461 2462def int_aarch64_sve_histcnt : AdvSIMD_Pred2VectorArg_Intrinsic; 2463def int_aarch64_sve_histseg : AdvSIMD_2VectorArg_Intrinsic; 2464 2465// 2466// SVE2 - Character match 2467// 2468 2469def int_aarch64_sve_match : AdvSIMD_SVE_Compare_Intrinsic; 2470def int_aarch64_sve_nmatch : AdvSIMD_SVE_Compare_Intrinsic; 2471 2472// 2473// SVE2 - Unary narrowing operations 2474// 2475 2476def int_aarch64_sve_sqxtnb : SVE2_1VectorArg_Narrowing_Intrinsic; 2477def int_aarch64_sve_sqxtnt : SVE2_Merged1VectorArg_Narrowing_Intrinsic; 2478def int_aarch64_sve_sqxtunb : SVE2_1VectorArg_Narrowing_Intrinsic; 2479def int_aarch64_sve_sqxtunt : SVE2_Merged1VectorArg_Narrowing_Intrinsic; 2480def int_aarch64_sve_uqxtnb : SVE2_1VectorArg_Narrowing_Intrinsic; 2481def int_aarch64_sve_uqxtnt : SVE2_Merged1VectorArg_Narrowing_Intrinsic; 2482 2483// 2484// SVE2 - Binary narrowing DSP operations 2485// 2486def int_aarch64_sve_addhnb : SVE2_2VectorArg_Narrowing_Intrinsic; 2487def int_aarch64_sve_addhnt : SVE2_Merged2VectorArg_Narrowing_Intrinsic; 2488 2489def int_aarch64_sve_raddhnb : SVE2_2VectorArg_Narrowing_Intrinsic; 2490def int_aarch64_sve_raddhnt : SVE2_Merged2VectorArg_Narrowing_Intrinsic; 2491 2492def int_aarch64_sve_subhnb : SVE2_2VectorArg_Narrowing_Intrinsic; 2493def int_aarch64_sve_subhnt : SVE2_Merged2VectorArg_Narrowing_Intrinsic; 2494 2495def int_aarch64_sve_rsubhnb : SVE2_2VectorArg_Narrowing_Intrinsic; 2496def int_aarch64_sve_rsubhnt : SVE2_Merged2VectorArg_Narrowing_Intrinsic; 2497 2498// Narrowing shift right 2499def int_aarch64_sve_shrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2500def int_aarch64_sve_shrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2501 2502def int_aarch64_sve_rshrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2503def int_aarch64_sve_rshrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2504 2505// Saturating shift right - signed input/output 2506def int_aarch64_sve_sqshrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2507def int_aarch64_sve_sqshrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2508 2509def int_aarch64_sve_sqrshrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2510def int_aarch64_sve_sqrshrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2511 2512// Saturating shift right - unsigned input/output 2513def int_aarch64_sve_uqshrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2514def int_aarch64_sve_uqshrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2515 2516def int_aarch64_sve_uqrshrnb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2517def int_aarch64_sve_uqrshrnt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2518 2519// Saturating shift right - signed input, unsigned output 2520def int_aarch64_sve_sqshrunb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2521def int_aarch64_sve_sqshrunt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2522 2523def int_aarch64_sve_sqrshrunb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic; 2524def int_aarch64_sve_sqrshrunt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic; 2525 2526// SVE2 MLA LANE. 2527def int_aarch64_sve_smlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2528def int_aarch64_sve_smlalt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2529def int_aarch64_sve_umlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2530def int_aarch64_sve_umlalt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2531def int_aarch64_sve_smlslb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2532def int_aarch64_sve_smlslt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2533def int_aarch64_sve_umlslb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2534def int_aarch64_sve_umlslt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2535def int_aarch64_sve_smullb_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2536def int_aarch64_sve_smullt_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2537def int_aarch64_sve_umullb_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2538def int_aarch64_sve_umullt_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2539def int_aarch64_sve_sqdmlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2540def int_aarch64_sve_sqdmlalt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2541def int_aarch64_sve_sqdmlslb_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2542def int_aarch64_sve_sqdmlslt_lane : SVE2_3VectorArg_Indexed_Intrinsic; 2543def int_aarch64_sve_sqdmullb_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2544def int_aarch64_sve_sqdmullt_lane : SVE2_2VectorArgIndexed_Long_Intrinsic; 2545 2546// SVE2 MLA Unpredicated. 2547def int_aarch64_sve_smlalb : SVE2_3VectorArg_Long_Intrinsic; 2548def int_aarch64_sve_smlalt : SVE2_3VectorArg_Long_Intrinsic; 2549def int_aarch64_sve_umlalb : SVE2_3VectorArg_Long_Intrinsic; 2550def int_aarch64_sve_umlalt : SVE2_3VectorArg_Long_Intrinsic; 2551def int_aarch64_sve_smlslb : SVE2_3VectorArg_Long_Intrinsic; 2552def int_aarch64_sve_smlslt : SVE2_3VectorArg_Long_Intrinsic; 2553def int_aarch64_sve_umlslb : SVE2_3VectorArg_Long_Intrinsic; 2554def int_aarch64_sve_umlslt : SVE2_3VectorArg_Long_Intrinsic; 2555def int_aarch64_sve_smullb : SVE2_2VectorArg_Long_Intrinsic; 2556def int_aarch64_sve_smullt : SVE2_2VectorArg_Long_Intrinsic; 2557def int_aarch64_sve_umullb : SVE2_2VectorArg_Long_Intrinsic; 2558def int_aarch64_sve_umullt : SVE2_2VectorArg_Long_Intrinsic; 2559 2560def int_aarch64_sve_sqdmlalb : SVE2_3VectorArg_Long_Intrinsic; 2561def int_aarch64_sve_sqdmlalt : SVE2_3VectorArg_Long_Intrinsic; 2562def int_aarch64_sve_sqdmlslb : SVE2_3VectorArg_Long_Intrinsic; 2563def int_aarch64_sve_sqdmlslt : SVE2_3VectorArg_Long_Intrinsic; 2564def int_aarch64_sve_sqdmullb : SVE2_2VectorArg_Long_Intrinsic; 2565def int_aarch64_sve_sqdmullt : SVE2_2VectorArg_Long_Intrinsic; 2566def int_aarch64_sve_sqdmlalbt : SVE2_3VectorArg_Long_Intrinsic; 2567def int_aarch64_sve_sqdmlslbt : SVE2_3VectorArg_Long_Intrinsic; 2568 2569// SVE2 ADDSUB Long Unpredicated. 2570def int_aarch64_sve_adclb : AdvSIMD_3VectorArg_Intrinsic; 2571def int_aarch64_sve_adclt : AdvSIMD_3VectorArg_Intrinsic; 2572def int_aarch64_sve_sbclb : AdvSIMD_3VectorArg_Intrinsic; 2573def int_aarch64_sve_sbclt : AdvSIMD_3VectorArg_Intrinsic; 2574 2575// 2576// SVE2 - Polynomial arithmetic 2577// 2578def int_aarch64_sve_eorbt : AdvSIMD_3VectorArg_Intrinsic; 2579def int_aarch64_sve_eortb : AdvSIMD_3VectorArg_Intrinsic; 2580def int_aarch64_sve_pmullb_pair : AdvSIMD_2VectorArg_Intrinsic; 2581def int_aarch64_sve_pmullt_pair : AdvSIMD_2VectorArg_Intrinsic; 2582 2583// 2584// SVE2 bitwise ternary operations. 2585// 2586def int_aarch64_sve_eor3 : AdvSIMD_3VectorArg_Intrinsic; 2587def int_aarch64_sve_bcax : AdvSIMD_3VectorArg_Intrinsic; 2588def int_aarch64_sve_bsl : AdvSIMD_3VectorArg_Intrinsic; 2589def int_aarch64_sve_bsl1n : AdvSIMD_3VectorArg_Intrinsic; 2590def int_aarch64_sve_bsl2n : AdvSIMD_3VectorArg_Intrinsic; 2591def int_aarch64_sve_nbsl : AdvSIMD_3VectorArg_Intrinsic; 2592def int_aarch64_sve_xar : AdvSIMD_2VectorArgIndexed_Intrinsic; 2593 2594// 2595// SVE2 - Optional AES, SHA-3 and SM4 2596// 2597 2598def int_aarch64_sve_aesd : ClangBuiltin<"__builtin_sve_svaesd_u8">, 2599 DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], 2600 [llvm_nxv16i8_ty, llvm_nxv16i8_ty], 2601 [IntrNoMem]>; 2602def int_aarch64_sve_aesimc : ClangBuiltin<"__builtin_sve_svaesimc_u8">, 2603 DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], 2604 [llvm_nxv16i8_ty], 2605 [IntrNoMem]>; 2606def int_aarch64_sve_aese : ClangBuiltin<"__builtin_sve_svaese_u8">, 2607 DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], 2608 [llvm_nxv16i8_ty, llvm_nxv16i8_ty], 2609 [IntrNoMem]>; 2610def int_aarch64_sve_aesmc : ClangBuiltin<"__builtin_sve_svaesmc_u8">, 2611 DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], 2612 [llvm_nxv16i8_ty], 2613 [IntrNoMem]>; 2614def int_aarch64_sve_rax1 : ClangBuiltin<"__builtin_sve_svrax1_u64">, 2615 DefaultAttrsIntrinsic<[llvm_nxv2i64_ty], 2616 [llvm_nxv2i64_ty, llvm_nxv2i64_ty], 2617 [IntrNoMem]>; 2618def int_aarch64_sve_sm4e : ClangBuiltin<"__builtin_sve_svsm4e_u32">, 2619 DefaultAttrsIntrinsic<[llvm_nxv4i32_ty], 2620 [llvm_nxv4i32_ty, llvm_nxv4i32_ty], 2621 [IntrNoMem]>; 2622def int_aarch64_sve_sm4ekey : ClangBuiltin<"__builtin_sve_svsm4ekey_u32">, 2623 DefaultAttrsIntrinsic<[llvm_nxv4i32_ty], 2624 [llvm_nxv4i32_ty, llvm_nxv4i32_ty], 2625 [IntrNoMem]>; 2626// 2627// SVE2 - Extended table lookup/permute 2628// 2629 2630def int_aarch64_sve_tbl2 : AdvSIMD_SVE2_TBX_Intrinsic; 2631def int_aarch64_sve_tbx : AdvSIMD_SVE2_TBX_Intrinsic; 2632 2633// 2634// SVE2 - Optional bit permutation 2635// 2636 2637def int_aarch64_sve_bdep_x : AdvSIMD_2VectorArg_Intrinsic; 2638def int_aarch64_sve_bext_x : AdvSIMD_2VectorArg_Intrinsic; 2639def int_aarch64_sve_bgrp_x : AdvSIMD_2VectorArg_Intrinsic; 2640 2641 2642// 2643// SVE ACLE: 7.3. INT8 matrix multiply extensions 2644// 2645def int_aarch64_sve_ummla : SVE_MatMul_Intrinsic; 2646def int_aarch64_sve_smmla : SVE_MatMul_Intrinsic; 2647def int_aarch64_sve_usmmla : SVE_MatMul_Intrinsic; 2648 2649def int_aarch64_sve_usdot : AdvSIMD_SVE_DOT_Intrinsic; 2650def int_aarch64_sve_usdot_lane : AdvSIMD_SVE_DOT_Indexed_Intrinsic; 2651def int_aarch64_sve_sudot_lane : AdvSIMD_SVE_DOT_Indexed_Intrinsic; 2652 2653// 2654// SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions 2655// 2656def int_aarch64_sve_fmmla : AdvSIMD_3VectorArg_Intrinsic; 2657 2658// 2659// SVE ACLE: 7.2. BFloat16 extensions 2660// 2661 2662def int_aarch64_sve_bfdot : SVE_4Vec_BF16; 2663def int_aarch64_sve_bfmlalb : SVE_4Vec_BF16; 2664def int_aarch64_sve_bfmlalt : SVE_4Vec_BF16; 2665 2666def int_aarch64_sve_bfmmla : SVE_4Vec_BF16; 2667 2668def int_aarch64_sve_bfdot_lane_v2 : SVE_4Vec_BF16_Indexed; 2669def int_aarch64_sve_bfmlalb_lane_v2 : SVE_4Vec_BF16_Indexed; 2670def int_aarch64_sve_bfmlalt_lane_v2 : SVE_4Vec_BF16_Indexed; 2671 2672// 2673// SVE2.1 - Contiguous loads to multiple consecutive vectors 2674// 2675 2676 class SVE2p1_Load_PN_X2_Intrinsic 2677 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 2678 [llvm_aarch64_svcount_ty, llvm_ptr_ty], 2679 [IntrReadMem, IntrArgMemOnly]>; 2680 2681 class SVE2p1_Load_PN_X4_Intrinsic 2682 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 2683 LLVMMatchType<0>, LLVMMatchType<0>], 2684 [llvm_aarch64_svcount_ty, llvm_ptr_ty], 2685 [IntrReadMem, IntrArgMemOnly]>; 2686 2687def int_aarch64_sve_ld1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic; 2688def int_aarch64_sve_ld1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic; 2689def int_aarch64_sve_ldnt1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic; 2690def int_aarch64_sve_ldnt1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic; 2691 2692// 2693// SVE2.1 - Contiguous loads to quadword (single vector) 2694// 2695 2696class SVE2p1_Single_Load_Quadword 2697 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 2698 [llvm_nxv1i1_ty, llvm_ptr_ty], 2699 [IntrReadMem, IntrArgMemOnly]>; 2700def int_aarch64_sve_ld1uwq : SVE2p1_Single_Load_Quadword; 2701def int_aarch64_sve_ld1udq : SVE2p1_Single_Load_Quadword; 2702 2703// 2704// SVE2.1 - Contiguous store from quadword (single vector) 2705// 2706 2707class SVE2p1_Single_Store_Quadword 2708 : DefaultAttrsIntrinsic<[], 2709 [llvm_anyvector_ty, llvm_nxv1i1_ty, llvm_ptr_ty], 2710 [IntrWriteMem, IntrArgMemOnly]>; 2711def int_aarch64_sve_st1wq : SVE2p1_Single_Store_Quadword; 2712def int_aarch64_sve_st1dq : SVE2p1_Single_Store_Quadword; 2713 2714 2715def int_aarch64_sve_ld2q_sret : AdvSIMD_2Vec_PredLoad_Intrinsic; 2716def int_aarch64_sve_ld3q_sret : AdvSIMD_3Vec_PredLoad_Intrinsic; 2717def int_aarch64_sve_ld4q_sret : AdvSIMD_4Vec_PredLoad_Intrinsic; 2718 2719def int_aarch64_sve_st2q : AdvSIMD_2Vec_PredStore_Intrinsic; 2720def int_aarch64_sve_st3q : AdvSIMD_3Vec_PredStore_Intrinsic; 2721def int_aarch64_sve_st4q : AdvSIMD_4Vec_PredStore_Intrinsic; 2722 2723// 2724// SVE2.1 - Contiguous stores to multiple consecutive vectors 2725// 2726 2727 class SVE2p1_Store_PN_X2_Intrinsic 2728 : DefaultAttrsIntrinsic<[], [ llvm_anyvector_ty, LLVMMatchType<0>, 2729 llvm_aarch64_svcount_ty, llvm_ptr_ty ], 2730 [IntrWriteMem, IntrArgMemOnly]>; 2731 2732 class SVE2p1_Store_PN_X4_Intrinsic 2733 : DefaultAttrsIntrinsic<[], [ llvm_anyvector_ty, LLVMMatchType<0>, 2734 LLVMMatchType<0>, LLVMMatchType<0>, 2735 llvm_aarch64_svcount_ty, llvm_ptr_ty], 2736 [IntrWriteMem, IntrArgMemOnly]>; 2737 2738def int_aarch64_sve_st1_pn_x2 : SVE2p1_Store_PN_X2_Intrinsic; 2739def int_aarch64_sve_st1_pn_x4 : SVE2p1_Store_PN_X4_Intrinsic; 2740def int_aarch64_sve_stnt1_pn_x2 : SVE2p1_Store_PN_X2_Intrinsic; 2741def int_aarch64_sve_stnt1_pn_x4 : SVE2p1_Store_PN_X4_Intrinsic; 2742} 2743 2744// 2745// SVE2 - Contiguous conflict detection 2746// 2747 2748def int_aarch64_sve_whilerw_b : SVE2_CONFLICT_DETECT_Intrinsic; 2749def int_aarch64_sve_whilerw_h : SVE2_CONFLICT_DETECT_Intrinsic; 2750def int_aarch64_sve_whilerw_s : SVE2_CONFLICT_DETECT_Intrinsic; 2751def int_aarch64_sve_whilerw_d : SVE2_CONFLICT_DETECT_Intrinsic; 2752def int_aarch64_sve_whilewr_b : SVE2_CONFLICT_DETECT_Intrinsic; 2753def int_aarch64_sve_whilewr_h : SVE2_CONFLICT_DETECT_Intrinsic; 2754def int_aarch64_sve_whilewr_s : SVE2_CONFLICT_DETECT_Intrinsic; 2755def int_aarch64_sve_whilewr_d : SVE2_CONFLICT_DETECT_Intrinsic; 2756 2757// Scalable Matrix Extension (SME) Intrinsics 2758let TargetPrefix = "aarch64" in { 2759 class SME_Load_Store_Intrinsic<LLVMType pred_ty> 2760 : DefaultAttrsIntrinsic<[], 2761 [pred_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>; 2762 2763 // Loads 2764 def int_aarch64_sme_ld1b_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>; 2765 def int_aarch64_sme_ld1h_horiz : SME_Load_Store_Intrinsic<llvm_nxv8i1_ty>; 2766 def int_aarch64_sme_ld1w_horiz : SME_Load_Store_Intrinsic<llvm_nxv4i1_ty>; 2767 def int_aarch64_sme_ld1d_horiz : SME_Load_Store_Intrinsic<llvm_nxv2i1_ty>; 2768 def int_aarch64_sme_ld1q_horiz : SME_Load_Store_Intrinsic<llvm_nxv1i1_ty>; 2769 def int_aarch64_sme_ld1b_vert : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>; 2770 def int_aarch64_sme_ld1h_vert : SME_Load_Store_Intrinsic<llvm_nxv8i1_ty>; 2771 def int_aarch64_sme_ld1w_vert : SME_Load_Store_Intrinsic<llvm_nxv4i1_ty>; 2772 def int_aarch64_sme_ld1d_vert : SME_Load_Store_Intrinsic<llvm_nxv2i1_ty>; 2773 def int_aarch64_sme_ld1q_vert : SME_Load_Store_Intrinsic<llvm_nxv1i1_ty>; 2774 2775 // Stores 2776 def int_aarch64_sme_st1b_horiz : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>; 2777 def int_aarch64_sme_st1h_horiz : SME_Load_Store_Intrinsic<llvm_nxv8i1_ty>; 2778 def int_aarch64_sme_st1w_horiz : SME_Load_Store_Intrinsic<llvm_nxv4i1_ty>; 2779 def int_aarch64_sme_st1d_horiz : SME_Load_Store_Intrinsic<llvm_nxv2i1_ty>; 2780 def int_aarch64_sme_st1q_horiz : SME_Load_Store_Intrinsic<llvm_nxv1i1_ty>; 2781 def int_aarch64_sme_st1b_vert : SME_Load_Store_Intrinsic<llvm_nxv16i1_ty>; 2782 def int_aarch64_sme_st1h_vert : SME_Load_Store_Intrinsic<llvm_nxv8i1_ty>; 2783 def int_aarch64_sme_st1w_vert : SME_Load_Store_Intrinsic<llvm_nxv4i1_ty>; 2784 def int_aarch64_sme_st1d_vert : SME_Load_Store_Intrinsic<llvm_nxv2i1_ty>; 2785 def int_aarch64_sme_st1q_vert : SME_Load_Store_Intrinsic<llvm_nxv1i1_ty>; 2786 2787 // Spill + fill 2788 class SME_LDR_STR_ZA_Intrinsic 2789 : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty]>; 2790 def int_aarch64_sme_ldr : SME_LDR_STR_ZA_Intrinsic; 2791 def int_aarch64_sme_str : SME_LDR_STR_ZA_Intrinsic; 2792 2793 class SME_TileToVector_Intrinsic 2794 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 2795 [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2796 llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>; 2797 class SME_VectorToTile_Intrinsic 2798 : DefaultAttrsIntrinsic<[], 2799 [llvm_i32_ty, llvm_i32_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2800 llvm_anyvector_ty], [ImmArg<ArgIndex<0>>]>; 2801 2802 def int_aarch64_sme_read_horiz : SME_TileToVector_Intrinsic; 2803 def int_aarch64_sme_read_vert : SME_TileToVector_Intrinsic; 2804 def int_aarch64_sme_write_horiz : SME_VectorToTile_Intrinsic; 2805 def int_aarch64_sme_write_vert : SME_VectorToTile_Intrinsic; 2806 2807 def int_aarch64_sme_readq_horiz : SME_TileToVector_Intrinsic; 2808 def int_aarch64_sme_readq_vert : SME_TileToVector_Intrinsic; 2809 def int_aarch64_sme_writeq_horiz : SME_VectorToTile_Intrinsic; 2810 def int_aarch64_sme_writeq_vert : SME_VectorToTile_Intrinsic; 2811 2812 def int_aarch64_sme_zero : DefaultAttrsIntrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 2813 2814 class SME_OuterProduct_Intrinsic 2815 : DefaultAttrsIntrinsic<[], 2816 [llvm_i32_ty, 2817 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2818 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2819 LLVMMatchType<0>, 2820 llvm_anyvector_ty], [ImmArg<ArgIndex<0>>]>; 2821 2822 def int_aarch64_sme_mopa : SME_OuterProduct_Intrinsic; 2823 def int_aarch64_sme_mops : SME_OuterProduct_Intrinsic; 2824 2825 def int_aarch64_sme_mopa_wide : SME_OuterProduct_Intrinsic; 2826 def int_aarch64_sme_mops_wide : SME_OuterProduct_Intrinsic; 2827 2828 def int_aarch64_sme_smopa_wide : SME_OuterProduct_Intrinsic; 2829 def int_aarch64_sme_smops_wide : SME_OuterProduct_Intrinsic; 2830 def int_aarch64_sme_umopa_wide : SME_OuterProduct_Intrinsic; 2831 def int_aarch64_sme_umops_wide : SME_OuterProduct_Intrinsic; 2832 def int_aarch64_sme_sumopa_wide : SME_OuterProduct_Intrinsic; 2833 def int_aarch64_sme_sumops_wide : SME_OuterProduct_Intrinsic; 2834 def int_aarch64_sme_usmopa_wide : SME_OuterProduct_Intrinsic; 2835 def int_aarch64_sme_usmops_wide : SME_OuterProduct_Intrinsic; 2836 2837 class SME_AddVectorToTile_Intrinsic 2838 : DefaultAttrsIntrinsic<[], 2839 [llvm_i32_ty, 2840 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2841 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 2842 llvm_anyvector_ty], [ImmArg<ArgIndex<0>>]>; 2843 2844 def int_aarch64_sme_addha : SME_AddVectorToTile_Intrinsic; 2845 def int_aarch64_sme_addva : SME_AddVectorToTile_Intrinsic; 2846 2847 // 2848 // Counting elements 2849 // 2850 2851 class AdvSIMD_SME_CNTSB_Intrinsic 2852 : DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem]>; 2853 2854 def int_aarch64_sme_cntsb : AdvSIMD_SME_CNTSB_Intrinsic; 2855 def int_aarch64_sme_cntsh : AdvSIMD_SME_CNTSB_Intrinsic; 2856 def int_aarch64_sme_cntsw : AdvSIMD_SME_CNTSB_Intrinsic; 2857 def int_aarch64_sme_cntsd : AdvSIMD_SME_CNTSB_Intrinsic; 2858 2859 // 2860 // PSTATE Functions 2861 // 2862 2863 def int_aarch64_sme_get_tpidr2 2864 : DefaultAttrsIntrinsic<[llvm_i64_ty], [], 2865 [IntrNoMem, IntrHasSideEffects]>; 2866 def int_aarch64_sme_set_tpidr2 2867 : DefaultAttrsIntrinsic<[], [llvm_i64_ty], 2868 [IntrNoMem, IntrHasSideEffects]>; 2869 2870 def int_aarch64_sme_za_enable 2871 : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; 2872 def int_aarch64_sme_za_disable 2873 : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; 2874 2875 // Clamp 2876 // 2877 2878 def int_aarch64_sve_sclamp : AdvSIMD_3VectorArg_Intrinsic; 2879 def int_aarch64_sve_uclamp : AdvSIMD_3VectorArg_Intrinsic; 2880 def int_aarch64_sve_fclamp : AdvSIMD_3VectorArg_Intrinsic; 2881 2882 2883 // 2884 // Reversal 2885 // 2886 2887 def int_aarch64_sve_revd : AdvSIMD_Merged1VectorArg_Intrinsic; 2888 2889 // 2890 // Predicate selection 2891 // 2892 2893 def int_aarch64_sve_psel 2894 : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], 2895 [llvm_nxv16i1_ty, 2896 llvm_anyvector_ty, llvm_i32_ty], 2897 [IntrNoMem]>; 2898 2899 // 2900 // Predicate-pair intrinsics 2901 // 2902 foreach cmp = ["ge", "gt", "hi", "hs", "le", "lo", "ls", "lt"] in { 2903 def int_aarch64_sve_while # cmp # _x2 2904 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 2905 [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; 2906 } 2907 2908 // 2909 // Predicate-as-counter intrinsics 2910 // 2911 2912 def int_aarch64_sve_pext 2913 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], 2914 [llvm_aarch64_svcount_ty, llvm_i32_ty], 2915 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2916 2917 def int_aarch64_sve_pext_x2 2918 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 2919 [llvm_aarch64_svcount_ty, llvm_i32_ty], 2920 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2921 2922 def int_aarch64_sve_ptrue_c8 2923 : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty], [], [IntrNoMem]>; 2924 def int_aarch64_sve_ptrue_c16 2925 : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty], [], [IntrNoMem]>; 2926 def int_aarch64_sve_ptrue_c32 2927 : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty], [], [IntrNoMem]>; 2928 def int_aarch64_sve_ptrue_c64 2929 : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty], [], [IntrNoMem]>; 2930 2931 def int_aarch64_sve_cntp_c8 2932 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_aarch64_svcount_ty, llvm_i32_ty], 2933 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2934 def int_aarch64_sve_cntp_c16 2935 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_aarch64_svcount_ty, llvm_i32_ty], 2936 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2937 def int_aarch64_sve_cntp_c32 2938 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_aarch64_svcount_ty, llvm_i32_ty], 2939 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2940 def int_aarch64_sve_cntp_c64 2941 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_aarch64_svcount_ty, llvm_i32_ty], 2942 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2943 2944 // While (predicate-as-counter) intrinsics 2945 foreach cmp = ["ge", "gt", "hi", "hs", "le", "lo", "ls", "lt"] in { 2946 foreach ty = ["c8", "c16", "c32", "c64"] in { 2947 def int_aarch64_sve_while # cmp # _ # ty 2948 : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty], 2949 [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], 2950 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2951 } 2952 } 2953 2954 // 2955 // SME2 Intrinsics 2956 // 2957 2958 class SME2_Matrix_ArrayVector_Single_Single_Intrinsic 2959 : DefaultAttrsIntrinsic<[], 2960 [llvm_i32_ty, 2961 llvm_anyvector_ty, LLVMMatchType<0>], 2962 []>; 2963 2964 class SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic 2965 : DefaultAttrsIntrinsic<[], 2966 [llvm_i32_ty, 2967 llvm_anyvector_ty, LLVMMatchType<0>, 2968 LLVMMatchType<0>], 2969 []>; 2970 2971 class SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic 2972 : DefaultAttrsIntrinsic<[], 2973 [llvm_i32_ty, 2974 llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, 2975 LLVMMatchType<0>], 2976 []>; 2977 2978 class SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic 2979 : DefaultAttrsIntrinsic<[], 2980 [llvm_i32_ty, 2981 llvm_anyvector_ty, LLVMMatchType<0>, 2982 LLVMMatchType<0>, LLVMMatchType<0>], 2983 []>; 2984 2985 class SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic 2986 : DefaultAttrsIntrinsic<[], 2987 [llvm_i32_ty, 2988 llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, 2989 LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 2990 []>; 2991 2992 class SME2_Matrix_ArrayVector_Single_Index_Intrinsic 2993 : DefaultAttrsIntrinsic<[], 2994 [llvm_i32_ty, 2995 llvm_anyvector_ty, 2996 LLVMMatchType<0>, llvm_i32_ty], 2997 [ImmArg<ArgIndex<3>>]>; 2998 2999 class SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic 3000 : DefaultAttrsIntrinsic<[], 3001 [llvm_i32_ty, 3002 llvm_anyvector_ty, LLVMMatchType<0>, 3003 LLVMMatchType<0>, llvm_i32_ty], 3004 [ImmArg<ArgIndex<4>>]>; 3005 3006 class SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic 3007 : DefaultAttrsIntrinsic<[], 3008 [llvm_i32_ty, 3009 llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, 3010 LLVMMatchType<0>, llvm_i32_ty], 3011 [ImmArg<ArgIndex<6>>]>; 3012 3013 class SME2_VG2_Multi_Imm_Intrinsic 3014 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 3015 [llvm_anyvector_ty, LLVMMatchType<0>, 3016 llvm_i32_ty], 3017 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3018 3019 class SME2_VG4_Multi_Imm_Intrinsic 3020 : DefaultAttrsIntrinsic<[LLVMSubdivide4VectorType<0>], 3021 [llvm_anyvector_ty, LLVMMatchType<0>, 3022 LLVMMatchType<0>, LLVMMatchType<0>, 3023 llvm_i32_ty], 3024 [IntrNoMem, ImmArg<ArgIndex<4>>]>; 3025 3026 class SME2_ZA_Write_VG2_Intrinsic 3027 : DefaultAttrsIntrinsic<[], 3028 [llvm_i32_ty, 3029 llvm_anyvector_ty, LLVMMatchType<0>], 3030 []>; 3031 3032 class SME2_ZA_Write_VG4_Intrinsic 3033 : DefaultAttrsIntrinsic<[], 3034 [llvm_i32_ty, 3035 llvm_anyvector_ty, LLVMMatchType<0>, 3036 LLVMMatchType<0>, LLVMMatchType<0>], 3037 []>; 3038 3039 class SME2_VG2_Multi_Single_Intrinsic 3040 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3041 [LLVMMatchType<0>, LLVMMatchType<0>, 3042 LLVMMatchType<0>], 3043 [IntrNoMem]>; 3044 3045 class SME2_VG4_Multi_Single_Intrinsic 3046 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3047 LLVMMatchType<0>, LLVMMatchType<0>], 3048 [LLVMMatchType<0>, LLVMMatchType<0>, 3049 LLVMMatchType<0>, LLVMMatchType<0>, 3050 LLVMMatchType<0>], 3051 [IntrNoMem]>; 3052 3053 class SME2_VG2_Multi_Multi_Intrinsic 3054 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3055 [LLVMMatchType<0>, LLVMMatchType<0>, 3056 LLVMMatchType<0>, LLVMMatchType<0>], 3057 [IntrNoMem]>; 3058 3059 class SME2_VG4_Multi_Multi_Intrinsic 3060 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3061 LLVMMatchType<0>, LLVMMatchType<0>], 3062 [LLVMMatchType<0>, LLVMMatchType<0>, 3063 LLVMMatchType<0>, LLVMMatchType<0>, 3064 LLVMMatchType<0>, LLVMMatchType<0>, 3065 LLVMMatchType<0>, LLVMMatchType<0>], 3066 [IntrNoMem]>; 3067 3068 class SVE2_VG2_Sel_Intrinsic 3069 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3070 [llvm_aarch64_svcount_ty, LLVMMatchType<0>, 3071 LLVMMatchType<0>, LLVMMatchType<0>, 3072 LLVMMatchType<0>], [IntrNoMem]>; 3073 3074 class SVE2_VG4_Sel_Intrinsic 3075 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3076 LLVMMatchType<0>, LLVMMatchType<0>], 3077 [llvm_aarch64_svcount_ty, LLVMMatchType<0>, 3078 LLVMMatchType<0>, LLVMMatchType<0>, 3079 LLVMMatchType<0>, LLVMMatchType<0>, 3080 LLVMMatchType<0>, LLVMMatchType<0>, 3081 LLVMMatchType<0>], [IntrNoMem]>; 3082 3083 class SME2_CVT_VG2_SINGLE_Intrinsic 3084 : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], 3085 [llvm_anyvector_ty, LLVMMatchType<0>], 3086 [IntrNoMem]>; 3087 3088 class SME2_CVT_VG2_SINGLE_BF16_Intrinsic 3089 : DefaultAttrsIntrinsic<[llvm_nxv8bf16_ty], 3090 [llvm_nxv4f32_ty, llvm_nxv4f32_ty], 3091 [IntrNoMem]>; 3092 3093 class SME2_CVT_VG4_SINGLE_Intrinsic 3094 : DefaultAttrsIntrinsic<[LLVMSubdivide4VectorType<0>], 3095 [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 3096 [IntrNoMem]>; 3097 3098 class SME2_CVT_X2_Intrinsic 3099 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3100 [llvm_anyvector_ty, LLVMMatchType<1>], 3101 [IntrNoMem]>; 3102 3103 class SME2_CVT_X4_Intrinsic 3104 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 3105 [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>], 3106 [IntrNoMem]>; 3107 3108 class SME2_BFMLS_Intrinsic 3109 : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], 3110 [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty], 3111 [IntrNoMem]>; 3112 3113 class SME2_BFMLS_Lane_Intrinsic 3114 : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], 3115 [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty, llvm_i32_ty], 3116 [IntrNoMem, ImmArg<ArgIndex<3>>]>; 3117 3118 class SME2_ZA_ArrayVector_Read_VG2_Intrinsic 3119 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3120 [llvm_i32_ty], 3121 []>; 3122 3123 class SME2_ZA_ArrayVector_Read_VG4_Intrinsic 3124 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3125 LLVMMatchType<0>, LLVMMatchType<0>], 3126 [llvm_i32_ty], 3127 []>; 3128 3129 class SME2_Matrix_TileVector_Read_VG2_Intrinsic 3130 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3131 [llvm_i32_ty, llvm_i32_ty], 3132 []>; 3133 3134 class SME2_Matrix_TileVector_Read_VG4_Intrinsic 3135 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3136 LLVMMatchType<0>, LLVMMatchType<0>], 3137 [llvm_i32_ty, llvm_i32_ty], 3138 []>; 3139 3140 class SME2_ZA_ArrayVector_Write_VG2_Intrinsic 3141 : DefaultAttrsIntrinsic<[], 3142 [llvm_i32_ty, 3143 llvm_anyvector_ty, LLVMMatchType<0>], 3144 []>; 3145 3146 class SME2_ZA_ArrayVector_Write_VG4_Intrinsic 3147 : DefaultAttrsIntrinsic<[], 3148 [llvm_i32_ty, 3149 llvm_anyvector_ty, LLVMMatchType<0>, 3150 LLVMMatchType<0>, LLVMMatchType<0>], 3151 []>; 3152 3153 class SME2_Matrix_TileVector_Write_VG2_Intrinsic 3154 : DefaultAttrsIntrinsic<[], 3155 [llvm_i32_ty, llvm_i32_ty, 3156 llvm_anyvector_ty, LLVMMatchType<0>], 3157 [ImmArg<ArgIndex<0>>]>; 3158 3159 class SME2_Matrix_TileVector_Write_VG4_Intrinsic 3160 : DefaultAttrsIntrinsic<[], 3161 [llvm_i32_ty, llvm_i32_ty, 3162 llvm_anyvector_ty, LLVMMatchType<0>, 3163 LLVMMatchType<0>, LLVMMatchType<0>], 3164 [ImmArg<ArgIndex<0>>]>; 3165 3166 class SME2_VG2_Multi_Single_Single_Intrinsic 3167 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3168 [LLVMMatchType<0>, LLVMMatchType<0>, 3169 LLVMMatchType<0>, LLVMMatchType<0>], 3170 [IntrNoMem]>; 3171 3172 class SME2_VG4_Multi_Single_Single_Intrinsic 3173 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3174 LLVMMatchType<0>, LLVMMatchType<0>], 3175 [LLVMMatchType<0>, LLVMMatchType<0>, 3176 LLVMMatchType<0>, LLVMMatchType<0>, 3177 LLVMMatchType<0>, LLVMMatchType<0>], 3178 [IntrNoMem]>; 3179 3180 class SVE2_VG2_ZipUzp_Intrinsic 3181 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3182 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; 3183 3184 class SVE2_VG4_ZipUzp_Intrinsic 3185 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3186 LLVMMatchType<0>, LLVMMatchType<0>], 3187 [LLVMMatchType<0>, LLVMMatchType<0>, 3188 LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; 3189 3190 class SME2_VG2_Unpk_Intrinsic 3191 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 3192 [LLVMSubdivide2VectorType<0>], [IntrNoMem]>; 3193 3194 class SME2_VG4_Unpk_Intrinsic 3195 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 3196 LLVMMatchType<0>, LLVMMatchType<0>], 3197 [LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>], 3198 [IntrNoMem]>; 3199 3200 // 3201 // Multi-vector fused multiply-add/subtract 3202 // 3203 3204 def int_aarch64_sme_fmla_single_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3205 def int_aarch64_sme_fmls_single_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3206 def int_aarch64_sme_fmla_single_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3207 def int_aarch64_sme_fmls_single_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3208 3209 def int_aarch64_sme_fmla_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3210 def int_aarch64_sme_fmls_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3211 def int_aarch64_sme_fmla_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3212 def int_aarch64_sme_fmls_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3213 3214 def int_aarch64_sme_fmla_lane_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3215 def int_aarch64_sme_fmls_lane_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3216 def int_aarch64_sme_fmla_lane_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3217 def int_aarch64_sme_fmls_lane_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3218 3219 // 3220 // Outer product and accumulate/subtract intrinsics 3221 // 3222 3223 def int_aarch64_sme_smopa_za32 : SME_OuterProduct_Intrinsic; 3224 def int_aarch64_sme_umopa_za32 : SME_OuterProduct_Intrinsic; 3225 def int_aarch64_sme_smops_za32 : SME_OuterProduct_Intrinsic; 3226 def int_aarch64_sme_umops_za32 : SME_OuterProduct_Intrinsic; 3227 3228 def int_aarch64_sme_bmopa_za32 : SME_OuterProduct_Intrinsic; 3229 def int_aarch64_sme_bmops_za32 : SME_OuterProduct_Intrinsic; 3230 3231 // 3232 // Multi-vector rounding shift left intrinsics 3233 // 3234 3235 def int_aarch64_sve_srshl_single_x2 : SME2_VG2_Multi_Single_Intrinsic; 3236 def int_aarch64_sve_urshl_single_x2 : SME2_VG2_Multi_Single_Intrinsic; 3237 def int_aarch64_sve_srshl_single_x4 : SME2_VG4_Multi_Single_Intrinsic; 3238 def int_aarch64_sve_urshl_single_x4 : SME2_VG4_Multi_Single_Intrinsic; 3239 3240 def int_aarch64_sve_srshl_x2 : SME2_VG2_Multi_Multi_Intrinsic; 3241 def int_aarch64_sve_urshl_x2 : SME2_VG2_Multi_Multi_Intrinsic; 3242 def int_aarch64_sve_srshl_x4 : SME2_VG4_Multi_Multi_Intrinsic; 3243 def int_aarch64_sve_urshl_x4 : SME2_VG4_Multi_Multi_Intrinsic; 3244 3245 // Multi-vector saturating rounding shift right intrinsics 3246 3247 def int_aarch64_sve_sqrshr_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3248 def int_aarch64_sve_uqrshr_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3249 def int_aarch64_sve_sqrshr_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3250 def int_aarch64_sve_uqrshr_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3251 3252 def int_aarch64_sve_sqrshrn_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3253 def int_aarch64_sve_uqrshrn_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3254 def int_aarch64_sve_sqrshrn_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3255 def int_aarch64_sve_uqrshrn_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3256 3257 def int_aarch64_sve_sqrshru_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3258 def int_aarch64_sve_sqrshru_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3259 3260 def int_aarch64_sve_sqrshrun_x2 : SME2_VG2_Multi_Imm_Intrinsic; 3261 def int_aarch64_sve_sqrshrun_x4 : SME2_VG4_Multi_Imm_Intrinsic; 3262 3263 // 3264 // Multi-vector multiply-add/subtract long 3265 // 3266 3267 foreach ty = ["f", "s", "u"] in { 3268 foreach instr = ["mlal", "mlsl"] in { 3269 def int_aarch64_sme_ # ty # instr # _single_vg2x1 : SME2_Matrix_ArrayVector_Single_Single_Intrinsic; 3270 def int_aarch64_sme_ # ty # instr # _single_vg2x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3271 def int_aarch64_sme_ # ty # instr # _single_vg2x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3272 3273 def int_aarch64_sme_ # ty # instr # _vg2x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3274 def int_aarch64_sme_ # ty # instr # _vg2x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3275 3276 def int_aarch64_sme_ # ty # instr # _lane_vg2x1 : SME2_Matrix_ArrayVector_Single_Index_Intrinsic; 3277 def int_aarch64_sme_ # ty # instr # _lane_vg2x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3278 def int_aarch64_sme_ # ty # instr # _lane_vg2x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3279 } 3280 } 3281 3282 // 3283 // Multi-vector multiply-add long long 3284 // 3285 3286 foreach ty = ["s", "u"] in { 3287 foreach instr = ["mla", "mls"] in { 3288 foreach za = ["za32", "za64"] in { 3289 def int_aarch64_sme_ # ty # instr # _ # za # _single_vg4x1 : SME2_Matrix_ArrayVector_Single_Single_Intrinsic; 3290 def int_aarch64_sme_ # ty # instr # _ # za # _single_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3291 def int_aarch64_sme_ # ty # instr # _ # za # _single_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3292 3293 def int_aarch64_sme_ # ty # instr # _ # za # _vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3294 def int_aarch64_sme_ # ty # instr # _ # za # _vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3295 3296 def int_aarch64_sme_ # ty # instr # _ # za # _lane_vg4x1 : SME2_Matrix_ArrayVector_Single_Index_Intrinsic; 3297 def int_aarch64_sme_ # ty # instr # _ # za # _lane_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3298 def int_aarch64_sme_ # ty # instr # _ # za # _lane_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3299 } 3300 } 3301 } 3302 3303 def int_aarch64_sme_sumla_za32_single_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3304 def int_aarch64_sme_sumla_za32_single_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3305 3306 def int_aarch64_sme_sumla_za32_lane_vg4x1 : SME2_Matrix_ArrayVector_Single_Index_Intrinsic; 3307 def int_aarch64_sme_sumla_za32_lane_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3308 def int_aarch64_sme_sumla_za32_lane_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3309 3310 def int_aarch64_sme_usmla_za32_single_vg4x1 : SME2_Matrix_ArrayVector_Single_Single_Intrinsic; 3311 def int_aarch64_sme_usmla_za32_single_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3312 def int_aarch64_sme_usmla_za32_single_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3313 3314 def int_aarch64_sme_usmla_za32_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3315 def int_aarch64_sme_usmla_za32_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3316 3317 def int_aarch64_sme_usmla_za32_lane_vg4x1 : SME2_Matrix_ArrayVector_Single_Index_Intrinsic; 3318 def int_aarch64_sme_usmla_za32_lane_vg4x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3319 def int_aarch64_sme_usmla_za32_lane_vg4x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3320 3321 def int_aarch64_sve_bfmlslb : SME2_BFMLS_Intrinsic; 3322 def int_aarch64_sve_bfmlslb_lane : SME2_BFMLS_Lane_Intrinsic; 3323 3324 def int_aarch64_sve_bfmlslt : SME2_BFMLS_Intrinsic; 3325 def int_aarch64_sve_bfmlslt_lane : SME2_BFMLS_Lane_Intrinsic; 3326 3327 // Multi-vector signed saturating doubling multiply high 3328 3329 def int_aarch64_sve_sqdmulh_single_vgx2 : SME2_VG2_Multi_Single_Intrinsic; 3330 def int_aarch64_sve_sqdmulh_single_vgx4 : SME2_VG4_Multi_Single_Intrinsic; 3331 3332 def int_aarch64_sve_sqdmulh_vgx2 : SME2_VG2_Multi_Multi_Intrinsic; 3333 def int_aarch64_sve_sqdmulh_vgx4 : SME2_VG4_Multi_Multi_Intrinsic; 3334 3335 // Multi-vector floating-point round to integral value 3336 3337 foreach inst = ["a", "m", "n", "p"] in { 3338 def int_aarch64_sve_frint # inst # _x2 : SVE2_VG2_ZipUzp_Intrinsic; 3339 def int_aarch64_sve_frint # inst # _x4 : SVE2_VG4_ZipUzp_Intrinsic; 3340 } 3341 3342 // 3343 // Multi-vector min/max 3344 // 3345 3346 foreach ty = ["f", "s", "u"] in { 3347 foreach instr = ["max", "min"] in { 3348 def int_aarch64_sve_ # ty # instr # _single_x2 : SME2_VG2_Multi_Single_Intrinsic; 3349 def int_aarch64_sve_ # ty # instr # _single_x4 : SME2_VG4_Multi_Single_Intrinsic; 3350 3351 def int_aarch64_sve_ # ty # instr # _x2 : SME2_VG2_Multi_Multi_Intrinsic; 3352 def int_aarch64_sve_ # ty # instr # _x4 : SME2_VG4_Multi_Multi_Intrinsic; 3353 } 3354 } 3355 3356 // 3357 // Multi-vector floating point min/max number 3358 // 3359 3360 foreach instr = ["fmaxnm", "fminnm"] in { 3361 def int_aarch64_sve_ # instr # _single_x2 : SME2_VG2_Multi_Single_Intrinsic; 3362 def int_aarch64_sve_ # instr # _single_x4 : SME2_VG4_Multi_Single_Intrinsic; 3363 3364 def int_aarch64_sve_ # instr # _x2 : SME2_VG2_Multi_Multi_Intrinsic; 3365 def int_aarch64_sve_ # instr # _x4 : SME2_VG4_Multi_Multi_Intrinsic; 3366 } 3367 3368 // 3369 // Multi-vector vertical dot-products 3370 // 3371 3372 def int_aarch64_sme_fvdot_lane_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3373 3374 foreach ty = ["s", "u"] in { 3375 def int_aarch64_sme_ #ty # vdot_lane_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3376 def int_aarch64_sme_ #ty # vdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3377 def int_aarch64_sme_ #ty # vdot_lane_za64_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3378 } 3379 3380 def int_aarch64_sme_suvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3381 def int_aarch64_sme_usvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3382 3383 // 3384 // Multi-vector floating-point CVT from single-precision to interleaved half-precision/BFloat16 3385 // 3386 def int_aarch64_sve_fcvtn_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3387 def int_aarch64_sve_bfcvtn_x2 : SME2_CVT_VG2_SINGLE_BF16_Intrinsic; 3388 3389 // 3390 // Multi-vector convert to/from floating-point. 3391 // 3392 def int_aarch64_sve_fcvt_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3393 def int_aarch64_sve_bfcvt_x2 : SME2_CVT_VG2_SINGLE_BF16_Intrinsic; 3394 def int_aarch64_sve_fcvtzs_x2 : SME2_CVT_X2_Intrinsic; 3395 def int_aarch64_sve_fcvtzu_x2 : SME2_CVT_X2_Intrinsic; 3396 def int_aarch64_sve_scvtf_x2 : SME2_CVT_X2_Intrinsic; 3397 def int_aarch64_sve_ucvtf_x2 : SME2_CVT_X2_Intrinsic; 3398 def int_aarch64_sve_fcvtzs_x4 : SME2_CVT_X4_Intrinsic; 3399 def int_aarch64_sve_fcvtzu_x4 : SME2_CVT_X4_Intrinsic; 3400 def int_aarch64_sve_scvtf_x4 : SME2_CVT_X4_Intrinsic; 3401 def int_aarch64_sve_ucvtf_x4 : SME2_CVT_X4_Intrinsic; 3402 3403 // 3404 // Multi-vector saturating extract narrow 3405 // 3406 def int_aarch64_sve_sqcvt_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3407 def int_aarch64_sve_uqcvt_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3408 def int_aarch64_sve_sqcvtu_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3409 def int_aarch64_sve_sqcvt_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3410 def int_aarch64_sve_uqcvt_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3411 def int_aarch64_sve_sqcvtu_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3412 3413 // 3414 // Multi-vector saturating extract narrow and interleave 3415 // 3416 def int_aarch64_sve_sqcvtn_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3417 def int_aarch64_sve_uqcvtn_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3418 def int_aarch64_sve_sqcvtun_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; 3419 def int_aarch64_sve_sqcvtn_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3420 def int_aarch64_sve_uqcvtn_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3421 def int_aarch64_sve_sqcvtun_x4 : SME2_CVT_VG4_SINGLE_Intrinsic; 3422 3423 // 3424 // Multi-Single add/sub 3425 // 3426 def int_aarch64_sme_add_write_single_za_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3427 def int_aarch64_sme_sub_write_single_za_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3428 def int_aarch64_sme_add_write_single_za_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3429 def int_aarch64_sme_sub_write_single_za_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3430 3431 // 3432 // Multi-Multi add/sub 3433 // 3434 def int_aarch64_sme_add_write_za_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3435 def int_aarch64_sme_sub_write_za_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3436 def int_aarch64_sme_add_write_za_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3437 def int_aarch64_sme_sub_write_za_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3438 3439 // Multi-vector clamps 3440 def int_aarch64_sve_sclamp_single_x2 : SME2_VG2_Multi_Single_Single_Intrinsic; 3441 def int_aarch64_sve_uclamp_single_x2 : SME2_VG2_Multi_Single_Single_Intrinsic; 3442 def int_aarch64_sve_fclamp_single_x2 : SME2_VG2_Multi_Single_Single_Intrinsic; 3443 3444 def int_aarch64_sve_sclamp_single_x4 : SME2_VG4_Multi_Single_Single_Intrinsic; 3445 def int_aarch64_sve_uclamp_single_x4 : SME2_VG4_Multi_Single_Single_Intrinsic; 3446 def int_aarch64_sve_fclamp_single_x4 : SME2_VG4_Multi_Single_Single_Intrinsic; 3447 3448 // 3449 // Multi-vector add/sub and accumulate into ZA 3450 // 3451 foreach intr = ["add", "sub"] in { 3452 foreach za = ["za32", "za64"] in { 3453 def int_aarch64_sme_ # intr # _ # za # _vg1x2 : SME2_ZA_Write_VG2_Intrinsic; 3454 def int_aarch64_sme_ # intr # _ # za # _vg1x4 : SME2_ZA_Write_VG4_Intrinsic; 3455 } 3456 } 3457 3458 // 3459 // Move multi-vectors to/from ZA 3460 // 3461 3462 def int_aarch64_sme_read_hor_vg2 : SME2_Matrix_TileVector_Read_VG2_Intrinsic; 3463 def int_aarch64_sme_read_hor_vg4 : SME2_Matrix_TileVector_Read_VG4_Intrinsic; 3464 3465 def int_aarch64_sme_read_ver_vg2 : SME2_Matrix_TileVector_Read_VG2_Intrinsic; 3466 def int_aarch64_sme_read_ver_vg4 : SME2_Matrix_TileVector_Read_VG4_Intrinsic; 3467 3468 def int_aarch64_sme_read_vg1x2 : SME2_ZA_ArrayVector_Read_VG2_Intrinsic; 3469 def int_aarch64_sme_read_vg1x4 : SME2_ZA_ArrayVector_Read_VG4_Intrinsic; 3470 3471 def int_aarch64_sme_write_hor_vg2 : SME2_Matrix_TileVector_Write_VG2_Intrinsic; 3472 def int_aarch64_sme_write_hor_vg4 : SME2_Matrix_TileVector_Write_VG4_Intrinsic; 3473 3474 def int_aarch64_sme_write_ver_vg2 : SME2_Matrix_TileVector_Write_VG2_Intrinsic; 3475 def int_aarch64_sme_write_ver_vg4 : SME2_Matrix_TileVector_Write_VG4_Intrinsic; 3476 3477 def int_aarch64_sme_write_vg1x2 : SME2_ZA_ArrayVector_Write_VG2_Intrinsic; 3478 def int_aarch64_sme_write_vg1x4 : SME2_ZA_ArrayVector_Write_VG4_Intrinsic; 3479 3480 // 3481 // Multi-Single Vector add 3482 // 3483 def int_aarch64_sve_add_single_x2 : SME2_VG2_Multi_Single_Intrinsic; 3484 def int_aarch64_sve_add_single_x4 : SME2_VG4_Multi_Single_Intrinsic; 3485 3486 // 2-way and 4-way multi-vector signed/unsigned integer dot-product 3487 foreach ty = ["s", "u"] in { 3488 foreach sz = ["za32", "za64"] in { 3489 def int_aarch64_sme_ # ty # dot_single_ # sz # _vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3490 def int_aarch64_sme_ # ty # dot_single_ # sz # _vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3491 3492 def int_aarch64_sme_ # ty # dot_ # sz # _vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3493 def int_aarch64_sme_ # ty # dot_ # sz # _vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3494 3495 def int_aarch64_sme_ # ty # dot_lane_ # sz # _vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3496 def int_aarch64_sme_ # ty # dot_lane_ # sz # _vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3497 } 3498 } 3499 3500 foreach ty = ["su", "us"] in { 3501 def int_aarch64_sme_ # ty # dot_single_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3502 def int_aarch64_sme_ # ty # dot_single_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3503 3504 def int_aarch64_sme_ # ty # dot_lane_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3505 def int_aarch64_sme_ # ty # dot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3506 } 3507 3508 def int_aarch64_sme_usdot_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3509 def int_aarch64_sme_usdot_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3510 3511 // Multi-vector half-precision or bfloat floating-point dot-product 3512 def int_aarch64_sme_fdot_single_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Single_Intrinsic; 3513 def int_aarch64_sme_fdot_single_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Single_Intrinsic; 3514 3515 def int_aarch64_sme_fdot_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Multi_Intrinsic; 3516 def int_aarch64_sme_fdot_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Multi_Intrinsic; 3517 3518 def int_aarch64_sme_fdot_lane_za32_vg1x2 : SME2_Matrix_ArrayVector_VG2_Multi_Index_Intrinsic; 3519 def int_aarch64_sme_fdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic; 3520 3521 // Multi-vector zip and unzips 3522 def int_aarch64_sve_zip_x2 : SVE2_VG2_ZipUzp_Intrinsic; 3523 def int_aarch64_sve_zipq_x2 : SVE2_VG2_ZipUzp_Intrinsic; 3524 def int_aarch64_sve_zip_x4 : SVE2_VG4_ZipUzp_Intrinsic; 3525 def int_aarch64_sve_zipq_x4 : SVE2_VG4_ZipUzp_Intrinsic; 3526 def int_aarch64_sve_uzp_x2 : SVE2_VG2_ZipUzp_Intrinsic; 3527 def int_aarch64_sve_uzpq_x2 : SVE2_VG2_ZipUzp_Intrinsic; 3528 def int_aarch64_sve_uzp_x4 : SVE2_VG4_ZipUzp_Intrinsic; 3529 def int_aarch64_sve_uzpq_x4 : SVE2_VG4_ZipUzp_Intrinsic; 3530 3531 // Vector dot-products (2-way) 3532 def int_aarch64_sve_sdot_x2 : SVE2_3VectorArg_Long_Intrinsic; 3533 def int_aarch64_sve_udot_x2 : SVE2_3VectorArg_Long_Intrinsic; 3534 def int_aarch64_sve_fdot_x2 : SVE2_3VectorArg_Long_Intrinsic; 3535 def int_aarch64_sve_sdot_lane_x2 : SVE2_3VectorArgIndexed_Long_Intrinsic; 3536 def int_aarch64_sve_udot_lane_x2 : SVE2_3VectorArgIndexed_Long_Intrinsic; 3537 def int_aarch64_sve_fdot_lane_x2 : SVE2_3VectorArgIndexed_Long_Intrinsic; 3538 3539 // 3540 // Signed/unsigned multi-vector unpacks 3541 // 3542 def int_aarch64_sve_sunpk_x2 : SME2_VG2_Unpk_Intrinsic; 3543 def int_aarch64_sve_uunpk_x2 : SME2_VG2_Unpk_Intrinsic; 3544 def int_aarch64_sve_sunpk_x4 : SME2_VG4_Unpk_Intrinsic; 3545 def int_aarch64_sve_uunpk_x4 : SME2_VG4_Unpk_Intrinsic; 3546 3547 // 2-way and 4-way vector selects 3548 def int_aarch64_sve_sel_x2 : SVE2_VG2_Sel_Intrinsic; 3549 def int_aarch64_sve_sel_x4 : SVE2_VG4_Sel_Intrinsic; 3550 3551 class SME_LDR_STR_ZT_Intrinsic 3552 : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>; 3553 def int_aarch64_sme_ldr_zt : SME_LDR_STR_ZT_Intrinsic; 3554 def int_aarch64_sme_str_zt : SME_LDR_STR_ZT_Intrinsic; 3555 3556 // 3557 // Zero ZT0 3558 // 3559 def int_aarch64_sme_zero_zt : DefaultAttrsIntrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrWriteMem]>; 3560 3561 // 3562 // Lookup table expand one register 3563 // 3564 def int_aarch64_sme_luti2_lane_zt 3565 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3566 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3567 def int_aarch64_sme_luti4_lane_zt 3568 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3569 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3570 3571 // Lookup table expand two registers 3572 // 3573 def int_aarch64_sme_luti2_lane_zt_x2 3574 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3575 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3576 def int_aarch64_sme_luti4_lane_zt_x2 3577 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3578 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3579 3580 // 3581 // Lookup table expand four registers 3582 // 3583 def int_aarch64_sme_luti2_lane_zt_x4 3584 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 3585 [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3586 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3587 def int_aarch64_sme_luti4_lane_zt_x4 3588 : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 3589 [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], 3590 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>; 3591} 3592 3593// SVE2.1 - ZIPQ1, ZIPQ2, UZPQ1, UZPQ2 3594// 3595def int_aarch64_sve_zipq1 : AdvSIMD_2VectorArg_Intrinsic; 3596def int_aarch64_sve_zipq2 : AdvSIMD_2VectorArg_Intrinsic; 3597def int_aarch64_sve_uzpq1 : AdvSIMD_2VectorArg_Intrinsic; 3598def int_aarch64_sve_uzpq2 : AdvSIMD_2VectorArg_Intrinsic; 3599 3600// SVE2.1 - Programmable table lookup within each quadword vector segment 3601// (zeroing)/(merging) 3602// 3603def int_aarch64_sve_tblq : AdvSIMD_SVE_TBL_Intrinsic; 3604def int_aarch64_sve_tbxq : AdvSIMD_SVE2_TBX_Intrinsic; 3605 3606// SVE2.1 - Extract vector segment from each pair of quadword segments. 3607// 3608def int_aarch64_sve_extq : AdvSIMD_2VectorArgIndexed_Intrinsic; 3609 3610// 3611// SVE2.1 - Move predicate to/from vector 3612// 3613def int_aarch64_sve_pmov_to_pred_lane : 3614 DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 3615 [llvm_anyvector_ty, llvm_i32_ty], 3616 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3617 3618def int_aarch64_sve_pmov_to_pred_lane_zero : 3619 DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 3620 [llvm_anyvector_ty], 3621 [IntrNoMem]>; 3622 3623def int_aarch64_sve_pmov_to_vector_lane_merging : 3624 DefaultAttrsIntrinsic<[llvm_anyvector_ty], 3625 [LLVMMatchType<0>, 3626 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_i32_ty], 3627 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3628 3629def int_aarch64_sve_pmov_to_vector_lane_zeroing : 3630 DefaultAttrsIntrinsic<[llvm_anyvector_ty], 3631 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], 3632 [IntrNoMem]>; 3633