1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// Target-Independent Code Generator Pass Configuration Options pass. 10 /// 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H 14 #define LLVM_CODEGEN_TARGETPASSCONFIG_H 15 16 #include "llvm/Pass.h" 17 #include "llvm/Support/CodeGen.h" 18 #include <cassert> 19 #include <string> 20 21 namespace llvm { 22 23 class LLVMTargetMachine; 24 struct MachineSchedContext; 25 class PassConfigImpl; 26 class ScheduleDAGInstrs; 27 class CSEConfigBase; 28 class PassInstrumentationCallbacks; 29 30 // The old pass manager infrastructure is hidden in a legacy namespace now. 31 namespace legacy { 32 33 class PassManagerBase; 34 35 } // end namespace legacy 36 37 using legacy::PassManagerBase; 38 39 /// Discriminated union of Pass ID types. 40 /// 41 /// The PassConfig API prefers dealing with IDs because they are safer and more 42 /// efficient. IDs decouple configuration from instantiation. This way, when a 43 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to 44 /// refer to a Pass pointer after adding it to a pass manager, which deletes 45 /// redundant pass instances. 46 /// 47 /// However, it is convient to directly instantiate target passes with 48 /// non-default ctors. These often don't have a registered PassInfo. Rather than 49 /// force all target passes to implement the pass registry boilerplate, allow 50 /// the PassConfig API to handle either type. 51 /// 52 /// AnalysisID is sadly char*, so PointerIntPair won't work. 53 class IdentifyingPassPtr { 54 union { 55 AnalysisID ID; 56 Pass *P; 57 }; 58 bool IsInstance = false; 59 60 public: 61 IdentifyingPassPtr() : P(nullptr) {} 62 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {} 63 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} 64 65 bool isValid() const { return P; } 66 bool isInstance() const { return IsInstance; } 67 68 AnalysisID getID() const { 69 assert(!IsInstance && "Not a Pass ID"); 70 return ID; 71 } 72 73 Pass *getInstance() const { 74 assert(IsInstance && "Not a Pass Instance"); 75 return P; 76 } 77 }; 78 79 80 /// Target-Independent Code Generator Pass Configuration Options. 81 /// 82 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options 83 /// to the internals of other CodeGen passes. 84 class TargetPassConfig : public ImmutablePass { 85 private: 86 PassManagerBase *PM = nullptr; 87 AnalysisID StartBefore = nullptr; 88 AnalysisID StartAfter = nullptr; 89 AnalysisID StopBefore = nullptr; 90 AnalysisID StopAfter = nullptr; 91 92 unsigned StartBeforeInstanceNum = 0; 93 unsigned StartBeforeCount = 0; 94 95 unsigned StartAfterInstanceNum = 0; 96 unsigned StartAfterCount = 0; 97 98 unsigned StopBeforeInstanceNum = 0; 99 unsigned StopBeforeCount = 0; 100 101 unsigned StopAfterInstanceNum = 0; 102 unsigned StopAfterCount = 0; 103 104 bool Started = true; 105 bool Stopped = false; 106 bool AddingMachinePasses = false; 107 bool DebugifyIsSafe = true; 108 109 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only 110 /// a portion of the normal code-gen pass sequence. 111 /// 112 /// If the StartAfter and StartBefore pass ID is zero, then compilation will 113 /// begin at the normal point; otherwise, clear the Started flag to indicate 114 /// that passes should not be added until the starting pass is seen. If the 115 /// Stop pass ID is zero, then compilation will continue to the end. 116 /// 117 /// This function expects that at least one of the StartAfter or the 118 /// StartBefore pass IDs is null. 119 void setStartStopPasses(); 120 121 protected: 122 LLVMTargetMachine *TM; 123 PassConfigImpl *Impl = nullptr; // Internal data structures 124 bool Initialized = false; // Flagged after all passes are configured. 125 126 // Target Pass Options 127 // Targets provide a default setting, user flags override. 128 bool DisableVerify = false; 129 130 /// Default setting for -enable-tail-merge on this target. 131 bool EnableTailMerge = true; 132 133 /// Require processing of functions such that callees are generated before 134 /// callers. 135 bool RequireCodeGenSCCOrder = false; 136 137 /// Add the actual instruction selection passes. This does not include 138 /// preparation passes on IR. 139 bool addCoreISelPasses(); 140 141 public: 142 TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm); 143 // Dummy constructor. 144 TargetPassConfig(); 145 146 ~TargetPassConfig() override; 147 148 static char ID; 149 150 /// Get the right type of TargetMachine for this target. 151 template<typename TMC> TMC &getTM() const { 152 return *static_cast<TMC*>(TM); 153 } 154 155 // 156 void setInitialized() { Initialized = true; } 157 158 CodeGenOpt::Level getOptLevel() const; 159 160 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after` 161 /// or `-stop-before` options is set. 162 static bool hasLimitedCodeGenPipeline(); 163 164 /// Returns true if none of the `-stop-before` and `-stop-after` options is 165 /// set. 166 static bool willCompleteCodeGenPipeline(); 167 168 /// If hasLimitedCodeGenPipeline is true, this method 169 /// returns a string with the name of the options, separated 170 /// by \p Separator that caused this pipeline to be limited. 171 static std::string 172 getLimitedCodeGenPipelineReason(const char *Separator = "/"); 173 174 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 175 176 bool getEnableTailMerge() const { return EnableTailMerge; } 177 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 178 179 bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; } 180 void setRequiresCodeGenSCCOrder(bool Enable = true) { 181 setOpt(RequireCodeGenSCCOrder, Enable); 182 } 183 184 /// Allow the target to override a specific pass without overriding the pass 185 /// pipeline. When passes are added to the standard pipeline at the 186 /// point where StandardID is expected, add TargetID in its place. 187 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); 188 189 /// Insert InsertedPassID pass after TargetPassID pass. 190 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); 191 192 /// Allow the target to enable a specific standard pass by default. 193 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 194 195 /// Allow the target to disable a specific standard pass by default. 196 void disablePass(AnalysisID PassID) { 197 substitutePass(PassID, IdentifyingPassPtr()); 198 } 199 200 /// Return the pass substituted for StandardID by the target. 201 /// If no substitution exists, return StandardID. 202 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; 203 204 /// Return true if the pass has been substituted by the target or 205 /// overridden on the command line. 206 bool isPassSubstitutedOrOverridden(AnalysisID ID) const; 207 208 /// Return true if the optimized regalloc pipeline is enabled. 209 bool getOptimizeRegAlloc() const; 210 211 /// Return true if the default global register allocator is in use and 212 /// has not be overriden on the command line with '-regalloc=...' 213 bool usingDefaultRegAlloc() const; 214 215 /// High level function that adds all passes necessary to go from llvm IR 216 /// representation to the MI representation. 217 /// Adds IR based lowering and target specific optimization passes and finally 218 /// the core instruction selection passes. 219 /// \returns true if an error occurred, false otherwise. 220 bool addISelPasses(); 221 222 /// Add common target configurable passes that perform LLVM IR to IR 223 /// transforms following machine independent optimization. 224 virtual void addIRPasses(); 225 226 /// Add passes to lower exception handling for the code generator. 227 void addPassesToHandleExceptions(); 228 229 /// Add pass to prepare the LLVM IR for code generation. This should be done 230 /// before exception handling preparation passes. 231 virtual void addCodeGenPrepare(); 232 233 /// Add common passes that perform LLVM IR to IR transforms in preparation for 234 /// instruction selection. 235 virtual void addISelPrepare(); 236 237 /// addInstSelector - This method should install an instruction selector pass, 238 /// which converts from LLVM code to machine instructions. 239 virtual bool addInstSelector() { 240 return true; 241 } 242 243 /// This method should install an IR translator pass, which converts from 244 /// LLVM code to machine instructions with possibly generic opcodes. 245 virtual bool addIRTranslator() { return true; } 246 247 /// This method may be implemented by targets that want to run passes 248 /// immediately before legalization. 249 virtual void addPreLegalizeMachineIR() {} 250 251 /// This method should install a legalize pass, which converts the instruction 252 /// sequence into one that can be selected by the target. 253 virtual bool addLegalizeMachineIR() { return true; } 254 255 /// This method may be implemented by targets that want to run passes 256 /// immediately before the register bank selection. 257 virtual void addPreRegBankSelect() {} 258 259 /// This method should install a register bank selector pass, which 260 /// assigns register banks to virtual registers without a register 261 /// class or register banks. 262 virtual bool addRegBankSelect() { return true; } 263 264 /// This method may be implemented by targets that want to run passes 265 /// immediately before the (global) instruction selection. 266 virtual void addPreGlobalInstructionSelect() {} 267 268 /// This method should install a (global) instruction selector pass, which 269 /// converts possibly generic instructions to fully target-specific 270 /// instructions, thereby constraining all generic virtual registers to 271 /// register classes. 272 virtual bool addGlobalInstructionSelect() { return true; } 273 274 /// Add the complete, standard set of LLVM CodeGen passes. 275 /// Fully developed targets will not generally override this. 276 virtual void addMachinePasses(); 277 278 /// Create an instance of ScheduleDAGInstrs to be run within the standard 279 /// MachineScheduler pass for this function and target at the current 280 /// optimization level. 281 /// 282 /// This can also be used to plug a new MachineSchedStrategy into an instance 283 /// of the standard ScheduleDAGMI: 284 /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false) 285 /// 286 /// Return NULL to select the default (generic) machine scheduler. 287 virtual ScheduleDAGInstrs * 288 createMachineScheduler(MachineSchedContext *C) const { 289 return nullptr; 290 } 291 292 /// Similar to createMachineScheduler but used when postRA machine scheduling 293 /// is enabled. 294 virtual ScheduleDAGInstrs * 295 createPostMachineScheduler(MachineSchedContext *C) const { 296 return nullptr; 297 } 298 299 /// printAndVerify - Add a pass to dump then verify the machine function, if 300 /// those steps are enabled. 301 void printAndVerify(const std::string &Banner); 302 303 /// Add a pass to print the machine function if printing is enabled. 304 void addPrintPass(const std::string &Banner); 305 306 /// Add a pass to perform basic verification of the machine function if 307 /// verification is enabled. 308 void addVerifyPass(const std::string &Banner); 309 310 /// Add a pass to add synthesized debug info to the MIR. 311 void addDebugifyPass(); 312 313 /// Add a pass to remove debug info from the MIR. 314 void addStripDebugPass(); 315 316 /// Add a pass to check synthesized debug info for MIR. 317 void addCheckDebugPass(); 318 319 /// Add standard passes before a pass that's about to be added. For example, 320 /// the DebugifyMachineModulePass if it is enabled. 321 void addMachinePrePasses(bool AllowDebugify = true); 322 323 /// Add standard passes after a pass that has just been added. For example, 324 /// the MachineVerifier if it is enabled. 325 void addMachinePostPasses(const std::string &Banner); 326 327 /// Check whether or not GlobalISel should abort on error. 328 /// When this is disabled, GlobalISel will fall back on SDISel instead of 329 /// erroring out. 330 bool isGlobalISelAbortEnabled() const; 331 332 /// Check whether or not a diagnostic should be emitted when GlobalISel 333 /// uses the fallback path. In other words, it will emit a diagnostic 334 /// when GlobalISel failed and isGlobalISelAbortEnabled is false. 335 virtual bool reportDiagnosticWhenGlobalISelFallback() const; 336 337 /// Check whether continuous CSE should be enabled in GISel passes. 338 /// By default, it's enabled for non O0 levels. 339 virtual bool isGISelCSEEnabled() const; 340 341 /// Returns the CSEConfig object to use for the current optimization level. 342 virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const; 343 344 protected: 345 // Helper to verify the analysis is really immutable. 346 void setOpt(bool &Opt, bool Val); 347 348 /// Methods with trivial inline returns are convenient points in the common 349 /// codegen pass pipeline where targets may insert passes. Methods with 350 /// out-of-line standard implementations are major CodeGen stages called by 351 /// addMachinePasses. Some targets may override major stages when inserting 352 /// passes is insufficient, but maintaining overriden stages is more work. 353 /// 354 355 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 356 /// passes (which are run just before instruction selector). 357 virtual bool addPreISel() { 358 return true; 359 } 360 361 /// addMachineSSAOptimization - Add standard passes that optimize machine 362 /// instructions in SSA form. 363 virtual void addMachineSSAOptimization(); 364 365 /// Add passes that optimize instruction level parallelism for out-of-order 366 /// targets. These passes are run while the machine code is still in SSA 367 /// form, so they can use MachineTraceMetrics to control their heuristics. 368 /// 369 /// All passes added here should preserve the MachineDominatorTree, 370 /// MachineLoopInfo, and MachineTraceMetrics analyses. 371 virtual bool addILPOpts() { 372 return false; 373 } 374 375 /// This method may be implemented by targets that want to run passes 376 /// immediately before register allocation. 377 virtual void addPreRegAlloc() { } 378 379 /// createTargetRegisterAllocator - Create the register allocator pass for 380 /// this target at the current optimization level. 381 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 382 383 /// addFastRegAlloc - Add the minimum set of target-independent passes that 384 /// are required for fast register allocation. 385 virtual void addFastRegAlloc(); 386 387 /// addOptimizedRegAlloc - Add passes related to register allocation. 388 /// LLVMTargetMachine provides standard regalloc passes for most targets. 389 virtual void addOptimizedRegAlloc(); 390 391 /// addPreRewrite - Add passes to the optimized register allocation pipeline 392 /// after register allocation is complete, but before virtual registers are 393 /// rewritten to physical registers. 394 /// 395 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 396 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 397 /// When these passes run, VirtRegMap contains legal physreg assignments for 398 /// all virtual registers. 399 /// 400 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not 401 /// be honored. This is also not generally used for the the fast variant, 402 /// where the allocation and rewriting are done in one pass. 403 virtual bool addPreRewrite() { 404 return false; 405 } 406 407 /// addPostFastRegAllocRewrite - Add passes to the optimized register 408 /// allocation pipeline after fast register allocation is complete. 409 virtual bool addPostFastRegAllocRewrite() { return false; } 410 411 /// Add passes to be run immediately after virtual registers are rewritten 412 /// to physical registers. 413 virtual void addPostRewrite() { } 414 415 /// This method may be implemented by targets that want to run passes after 416 /// register allocation pass pipeline but before prolog-epilog insertion. 417 virtual void addPostRegAlloc() { } 418 419 /// Add passes that optimize machine instructions after register allocation. 420 virtual void addMachineLateOptimization(); 421 422 /// This method may be implemented by targets that want to run passes after 423 /// prolog-epilog insertion and before the second instruction scheduling pass. 424 virtual void addPreSched2() { } 425 426 /// addGCPasses - Add late codegen passes that analyze code for garbage 427 /// collection. This should return true if GC info should be printed after 428 /// these passes. 429 virtual bool addGCPasses(); 430 431 /// Add standard basic block placement passes. 432 virtual void addBlockPlacement(); 433 434 /// This pass may be implemented by targets that want to run passes 435 /// immediately before machine code is emitted. 436 virtual void addPreEmitPass() { } 437 438 /// Targets may add passes immediately before machine code is emitted in this 439 /// callback. This is called even later than `addPreEmitPass`. 440 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual 441 // position and remove the `2` suffix here as this callback is what 442 // `addPreEmitPass` *should* be but in reality isn't. 443 virtual void addPreEmitPass2() {} 444 445 /// Utilities for targets to add passes to the pass manager. 446 /// 447 448 /// Add a CodeGen pass at this point in the pipeline after checking overrides. 449 /// Return the pass that was added, or zero if no pass was added. 450 AnalysisID addPass(AnalysisID PassID); 451 452 /// Add a pass to the PassManager if that pass is supposed to be run, as 453 /// determined by the StartAfter and StopAfter options. Takes ownership of the 454 /// pass. 455 void addPass(Pass *P); 456 457 /// addMachinePasses helper to create the target-selected or overriden 458 /// regalloc pass. 459 virtual FunctionPass *createRegAllocPass(bool Optimized); 460 461 /// Add core register allocator passes which do the actual register assignment 462 /// and rewriting. \returns true if any passes were added. 463 virtual bool addRegAssignAndRewriteFast(); 464 virtual bool addRegAssignAndRewriteOptimized(); 465 }; 466 467 void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, 468 LLVMTargetMachine &); 469 470 } // end namespace llvm 471 472 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H 473