1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 9 #include <cassert> 10 #include <stddef.h> 11 #include <vector> 12 13 #include "lldb/lldb-defines.h" 14 #include "llvm/Support/Compiler.h" 15 16 #include "RegisterInfoPOSIX_arm64.h" 17 18 // Based on RegisterContextDarwin_arm64.cpp 19 #define GPR_OFFSET(idx) ((idx)*8) 20 #define GPR_OFFSET_NAME(reg) \ 21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg)) 22 23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR)) 24 #define FPU_OFFSET_NAME(reg) \ 25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \ 26 sizeof(RegisterInfoPOSIX_arm64::GPR)) 27 28 #define EXC_OFFSET_NAME(reg) \ 29 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \ 30 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 31 sizeof(RegisterInfoPOSIX_arm64::FPU)) 32 #define DBG_OFFSET_NAME(reg) \ 33 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \ 34 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 35 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 36 sizeof(RegisterInfoPOSIX_arm64::EXC)) 37 38 #define DEFINE_DBG(reg, i) \ 39 #reg, NULL, \ 40 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \ 41 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ 42 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 43 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 44 dbg_##reg##i }, \ 45 NULL, NULL, NULL, 0 46 #define REG_CONTEXT_SIZE \ 47 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 48 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 49 sizeof(RegisterInfoPOSIX_arm64::EXC)) 50 51 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 52 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 53 #include "RegisterInfos_arm64.h" 54 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 55 56 static const lldb_private::RegisterInfo * 57 GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) { 58 switch (target_arch.GetMachine()) { 59 case llvm::Triple::aarch64: 60 case llvm::Triple::aarch64_32: 61 return g_register_infos_arm64_le; 62 default: 63 assert(false && "Unhandled target architecture."); 64 return nullptr; 65 } 66 } 67 68 // Number of register sets provided by this context. 69 enum { 70 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1, 71 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1, 72 k_num_register_sets = 2 73 }; 74 75 // ARM64 general purpose registers. 76 static const uint32_t g_gpr_regnums_arm64[] = { 77 gpr_x0, gpr_x1, gpr_x2, gpr_x3, 78 gpr_x4, gpr_x5, gpr_x6, gpr_x7, 79 gpr_x8, gpr_x9, gpr_x10, gpr_x11, 80 gpr_x12, gpr_x13, gpr_x14, gpr_x15, 81 gpr_x16, gpr_x17, gpr_x18, gpr_x19, 82 gpr_x20, gpr_x21, gpr_x22, gpr_x23, 83 gpr_x24, gpr_x25, gpr_x26, gpr_x27, 84 gpr_x28, gpr_fp, gpr_lr, gpr_sp, 85 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1, 86 gpr_w2, gpr_w3, gpr_w4, gpr_w5, 87 gpr_w6, gpr_w7, gpr_w8, gpr_w9, 88 gpr_w10, gpr_w11, gpr_w12, gpr_w13, 89 gpr_w14, gpr_w15, gpr_w16, gpr_w17, 90 gpr_w18, gpr_w19, gpr_w20, gpr_w21, 91 gpr_w22, gpr_w23, gpr_w24, gpr_w25, 92 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM}; 93 94 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 95 1) == k_num_gpr_registers, 96 "g_gpr_regnums_arm64 has wrong number of register infos"); 97 98 // ARM64 floating point registers. 99 static const uint32_t g_fpu_regnums_arm64[] = { 100 fpu_v0, fpu_v1, fpu_v2, 101 fpu_v3, fpu_v4, fpu_v5, 102 fpu_v6, fpu_v7, fpu_v8, 103 fpu_v9, fpu_v10, fpu_v11, 104 fpu_v12, fpu_v13, fpu_v14, 105 fpu_v15, fpu_v16, fpu_v17, 106 fpu_v18, fpu_v19, fpu_v20, 107 fpu_v21, fpu_v22, fpu_v23, 108 fpu_v24, fpu_v25, fpu_v26, 109 fpu_v27, fpu_v28, fpu_v29, 110 fpu_v30, fpu_v31, fpu_s0, 111 fpu_s1, fpu_s2, fpu_s3, 112 fpu_s4, fpu_s5, fpu_s6, 113 fpu_s7, fpu_s8, fpu_s9, 114 fpu_s10, fpu_s11, fpu_s12, 115 fpu_s13, fpu_s14, fpu_s15, 116 fpu_s16, fpu_s17, fpu_s18, 117 fpu_s19, fpu_s20, fpu_s21, 118 fpu_s22, fpu_s23, fpu_s24, 119 fpu_s25, fpu_s26, fpu_s27, 120 fpu_s28, fpu_s29, fpu_s30, 121 fpu_s31, fpu_d0, fpu_d1, 122 fpu_d2, fpu_d3, fpu_d4, 123 fpu_d5, fpu_d6, fpu_d7, 124 fpu_d8, fpu_d9, fpu_d10, 125 fpu_d11, fpu_d12, fpu_d13, 126 fpu_d14, fpu_d15, fpu_d16, 127 fpu_d17, fpu_d18, fpu_d19, 128 fpu_d20, fpu_d21, fpu_d22, 129 fpu_d23, fpu_d24, fpu_d25, 130 fpu_d26, fpu_d27, fpu_d28, 131 fpu_d29, fpu_d30, fpu_d31, 132 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM}; 133 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 134 1) == k_num_fpr_registers, 135 "g_fpu_regnums_arm64 has wrong number of register infos"); 136 // clang-format on 137 // Register sets for ARM64. 138 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 139 {"General Purpose Registers", "gpr", k_num_gpr_registers, 140 g_gpr_regnums_arm64}, 141 {"Floating Point Registers", "fpu", k_num_fpr_registers, 142 g_fpu_regnums_arm64}}; 143 144 static uint32_t 145 GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) { 146 switch (target_arch.GetMachine()) { 147 case llvm::Triple::aarch64: 148 case llvm::Triple::aarch64_32: 149 return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) / 150 sizeof(g_register_infos_arm64_le[0])); 151 default: 152 assert(false && "Unhandled target architecture."); 153 return 0; 154 } 155 } 156 157 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64( 158 const lldb_private::ArchSpec &target_arch) 159 : lldb_private::RegisterInfoAndSetInterface(target_arch), 160 m_register_info_p(GetRegisterInfoPtr(target_arch)), 161 m_register_info_count(GetRegisterInfoCount(target_arch)) { 162 163 switch (target_arch.GetMachine()) { 164 case llvm::Triple::aarch64: 165 case llvm::Triple::aarch64_32: 166 num_registers = k_num_gpr_registers + k_num_fpr_registers; 167 num_gpr_registers = k_num_gpr_registers; 168 num_fpr_registers = k_num_fpr_registers; 169 last_gpr = gpr_w28; 170 first_fpr = fpu_v0; 171 last_fpr = fpu_fpcr; 172 break; 173 default: 174 assert(false && "Unhandled target architecture."); 175 break; 176 } 177 } 178 179 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const { 180 return num_gpr_registers + num_fpr_registers; 181 } 182 183 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const { 184 return sizeof(struct RegisterInfoPOSIX_arm64::GPR); 185 } 186 187 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const { 188 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); 189 } 190 191 const lldb_private::RegisterInfo * 192 RegisterInfoPOSIX_arm64::GetRegisterInfo() const { 193 return m_register_info_p; 194 } 195 196 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const { 197 return k_num_register_sets; 198 } 199 200 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex( 201 uint32_t reg_index) const { 202 if (reg_index <= last_gpr) 203 return GPRegSet; 204 else if (reg_index <= last_fpr) 205 return FPRegSet; 206 return LLDB_INVALID_REGNUM; 207 } 208 209 const lldb_private::RegisterSet * 210 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const { 211 if (set_index < k_num_register_sets) 212 return &g_reg_sets_arm64[set_index]; 213 214 return nullptr; 215 } 216