1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include <cstddef> 20 #include <cstdint> 21 #include <string> 22 23 namespace lldb_private { 24 25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 26 /// specification class. 27 /// 28 /// A class designed to be created from a cpu type and subtype, a 29 /// string representation, or an llvm::Triple. Keeping all of the conversions 30 /// of strings to architecture enumeration values confined to this class 31 /// allows new architecture support to be added easily. 32 class ArchSpec { 33 public: 34 enum MIPSSubType { 35 eMIPSSubType_unknown, 36 eMIPSSubType_mips32, 37 eMIPSSubType_mips32r2, 38 eMIPSSubType_mips32r6, 39 eMIPSSubType_mips32el, 40 eMIPSSubType_mips32r2el, 41 eMIPSSubType_mips32r6el, 42 eMIPSSubType_mips64, 43 eMIPSSubType_mips64r2, 44 eMIPSSubType_mips64r6, 45 eMIPSSubType_mips64el, 46 eMIPSSubType_mips64r2el, 47 eMIPSSubType_mips64r6el, 48 }; 49 50 // Masks for the ases word of an ABI flags structure. 51 enum MIPSASE { 52 eMIPSAse_dsp = 0x00000001, // DSP ASE 53 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 54 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 55 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 56 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 57 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 58 eMIPSAse_mt = 0x00000040, // MT ASE 59 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 60 eMIPSAse_virt = 0x00000100, // VZ ASE 61 eMIPSAse_msa = 0x00000200, // MSA ASE 62 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 63 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 64 eMIPSAse_xpa = 0x00001000, // XPA ASE 65 eMIPSAse_mask = 0x00001fff, 66 eMIPSABI_O32 = 0x00002000, 67 eMIPSABI_N32 = 0x00004000, 68 eMIPSABI_N64 = 0x00008000, 69 eMIPSABI_O64 = 0x00020000, 70 eMIPSABI_EABI32 = 0x00040000, 71 eMIPSABI_EABI64 = 0x00080000, 72 eMIPSABI_mask = 0x000ff000 73 }; 74 75 // MIPS Floating point ABI Values 76 enum MIPS_ABI_FP { 77 eMIPS_ABI_FP_ANY = 0x00000000, 78 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 79 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 80 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 81 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 82 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 83 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 84 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 85 eMIPS_ABI_FP_mask = 0x00700000 86 }; 87 88 // ARM specific e_flags 89 enum ARMeflags { 90 eARM_abi_soft_float = 0x00000200, 91 eARM_abi_hard_float = 0x00000400 92 }; 93 94 enum RISCVeflags { 95 eRISCV_rvc = 0x00000001, /// RVC, +c 96 eRISCV_float_abi_soft = 0x00000000, /// soft float 97 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f 98 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d 99 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q 100 eRISCV_float_abi_mask = 0x00000006, 101 eRISCV_rve = 0x00000008, /// RVE, +e 102 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering) 103 }; 104 105 enum RISCVSubType { 106 eRISCVSubType_unknown, 107 eRISCVSubType_riscv32, 108 eRISCVSubType_riscv64, 109 }; 110 111 enum LoongArchSubType { 112 eLoongArchSubType_unknown, 113 eLoongArchSubType_loongarch32, 114 eLoongArchSubType_loongarch64, 115 }; 116 117 enum Core { 118 eCore_arm_generic, 119 eCore_arm_armv4, 120 eCore_arm_armv4t, 121 eCore_arm_armv5, 122 eCore_arm_armv5e, 123 eCore_arm_armv5t, 124 eCore_arm_armv6, 125 eCore_arm_armv6m, 126 eCore_arm_armv7, 127 eCore_arm_armv7l, 128 eCore_arm_armv7f, 129 eCore_arm_armv7s, 130 eCore_arm_armv7k, 131 eCore_arm_armv7m, 132 eCore_arm_armv7em, 133 eCore_arm_xscale, 134 135 eCore_thumb, 136 eCore_thumbv4t, 137 eCore_thumbv5, 138 eCore_thumbv5e, 139 eCore_thumbv6, 140 eCore_thumbv6m, 141 eCore_thumbv7, 142 eCore_thumbv7s, 143 eCore_thumbv7k, 144 eCore_thumbv7f, 145 eCore_thumbv7m, 146 eCore_thumbv7em, 147 eCore_arm_arm64, 148 eCore_arm_armv8, 149 eCore_arm_armv8l, 150 eCore_arm_arm64e, 151 eCore_arm_arm64_32, 152 eCore_arm_aarch64, 153 154 eCore_mips32, 155 eCore_mips32r2, 156 eCore_mips32r3, 157 eCore_mips32r5, 158 eCore_mips32r6, 159 eCore_mips32el, 160 eCore_mips32r2el, 161 eCore_mips32r3el, 162 eCore_mips32r5el, 163 eCore_mips32r6el, 164 eCore_mips64, 165 eCore_mips64r2, 166 eCore_mips64r3, 167 eCore_mips64r5, 168 eCore_mips64r6, 169 eCore_mips64el, 170 eCore_mips64r2el, 171 eCore_mips64r3el, 172 eCore_mips64r5el, 173 eCore_mips64r6el, 174 175 eCore_ppc_generic, 176 eCore_ppc_ppc601, 177 eCore_ppc_ppc602, 178 eCore_ppc_ppc603, 179 eCore_ppc_ppc603e, 180 eCore_ppc_ppc603ev, 181 eCore_ppc_ppc604, 182 eCore_ppc_ppc604e, 183 eCore_ppc_ppc620, 184 eCore_ppc_ppc750, 185 eCore_ppc_ppc7400, 186 eCore_ppc_ppc7450, 187 eCore_ppc_ppc970, 188 189 eCore_ppc64le_generic, 190 eCore_ppc64_generic, 191 eCore_ppc64_ppc970_64, 192 193 eCore_s390x_generic, 194 195 eCore_sparc_generic, 196 197 eCore_sparc9_generic, 198 199 eCore_x86_32_i386, 200 eCore_x86_32_i486, 201 eCore_x86_32_i486sx, 202 eCore_x86_32_i686, 203 204 eCore_x86_64_x86_64, 205 eCore_x86_64_x86_64h, // Haswell enabled x86_64 206 eCore_hexagon_generic, 207 eCore_hexagon_hexagonv4, 208 eCore_hexagon_hexagonv5, 209 210 eCore_riscv32, 211 eCore_riscv64, 212 213 eCore_loongarch32, 214 eCore_loongarch64, 215 216 eCore_uknownMach32, 217 eCore_uknownMach64, 218 219 eCore_arc, // little endian ARC 220 221 eCore_avr, 222 223 eCore_wasm32, 224 225 kNumCores, 226 227 kCore_invalid, 228 // The following constants are used for wildcard matching only 229 kCore_any, 230 kCore_arm_any, 231 kCore_ppc_any, 232 kCore_ppc64_any, 233 kCore_x86_32_any, 234 kCore_x86_64_any, 235 kCore_hexagon_any, 236 237 kCore_arm_first = eCore_arm_generic, 238 kCore_arm_last = eCore_arm_xscale, 239 240 kCore_thumb_first = eCore_thumb, 241 kCore_thumb_last = eCore_thumbv7em, 242 243 kCore_ppc_first = eCore_ppc_generic, 244 kCore_ppc_last = eCore_ppc_ppc970, 245 246 kCore_ppc64_first = eCore_ppc64_generic, 247 kCore_ppc64_last = eCore_ppc64_ppc970_64, 248 249 kCore_x86_32_first = eCore_x86_32_i386, 250 kCore_x86_32_last = eCore_x86_32_i686, 251 252 kCore_x86_64_first = eCore_x86_64_x86_64, 253 kCore_x86_64_last = eCore_x86_64_x86_64h, 254 255 kCore_hexagon_first = eCore_hexagon_generic, 256 kCore_hexagon_last = eCore_hexagon_hexagonv5, 257 258 kCore_mips32_first = eCore_mips32, 259 kCore_mips32_last = eCore_mips32r6, 260 261 kCore_mips32el_first = eCore_mips32el, 262 kCore_mips32el_last = eCore_mips32r6el, 263 264 kCore_mips64_first = eCore_mips64, 265 kCore_mips64_last = eCore_mips64r6, 266 267 kCore_mips64el_first = eCore_mips64el, 268 kCore_mips64el_last = eCore_mips64r6el, 269 270 kCore_mips_first = eCore_mips32, 271 kCore_mips_last = eCore_mips64r6el 272 273 }; 274 275 /// Default constructor. 276 /// 277 /// Default constructor that initializes the object with invalid cpu type 278 /// and subtype values. 279 ArchSpec(); 280 281 /// Constructor over triple. 282 /// 283 /// Constructs an ArchSpec with properties consistent with the given Triple. 284 explicit ArchSpec(const llvm::Triple &triple); 285 explicit ArchSpec(const char *triple_cstr); 286 explicit ArchSpec(llvm::StringRef triple_str); 287 /// Constructor over architecture name. 288 /// 289 /// Constructs an ArchSpec with properties consistent with the given object 290 /// type and architecture name. 291 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 292 uint32_t cpu_subtype); 293 294 /// Destructor. 295 ~ArchSpec(); 296 297 /// Returns true if the OS, vendor and environment fields of the triple are 298 /// unset. The triple is expected to be normalized 299 /// (llvm::Triple::normalize). 300 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 301 302 static void ListSupportedArchNames(StringList &list); 303 static void AutoComplete(CompletionRequest &request); 304 305 /// Returns a static string representing the current architecture. 306 /// 307 /// \return A static string corresponding to the current 308 /// architecture. 309 const char *GetArchitectureName() const; 310 311 /// if MIPS architecture return true. 312 /// 313 /// \return a boolean value. 314 bool IsMIPS() const; 315 316 /// Returns a string representing current architecture as a target CPU for 317 /// tools like compiler, disassembler etc. 318 /// 319 /// \return A string representing target CPU for the current 320 /// architecture. 321 std::string GetClangTargetCPU() const; 322 323 /// Return a string representing target application ABI. 324 /// 325 /// \return A string representing target application ABI. 326 std::string GetTargetABI() const; 327 328 /// Clears the object state. 329 /// 330 /// Clears the object state back to a default invalid state. 331 void Clear(); 332 333 /// Returns the size in bytes of an address of the current architecture. 334 /// 335 /// \return The byte size of an address of the current architecture. 336 uint32_t GetAddressByteSize() const; 337 338 /// Returns a machine family for the current architecture. 339 /// 340 /// \return An LLVM arch type. 341 llvm::Triple::ArchType GetMachine() const; 342 343 /// Returns the distribution id of the architecture. 344 /// 345 /// This will be something like "ubuntu", "fedora", etc. on Linux. 346 /// 347 /// \return A ConstString ref containing the distribution id, 348 /// potentially empty. 349 ConstString GetDistributionId() const; 350 351 /// Set the distribution id of the architecture. 352 /// 353 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 354 /// should be the same value returned by HostInfo::GetDistributionId (). 355 void SetDistributionId(const char *distribution_id); 356 357 /// Tests if this ArchSpec is valid. 358 /// 359 /// \return True if the current architecture is valid, false 360 /// otherwise. 361 bool IsValid() const { 362 return m_core >= eCore_arm_generic && m_core < kNumCores; 363 } 364 explicit operator bool() const { return IsValid(); } 365 366 bool TripleVendorWasSpecified() const { 367 return !m_triple.getVendorName().empty(); 368 } 369 370 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 371 372 bool TripleEnvironmentWasSpecified() const { 373 return m_triple.hasEnvironment(); 374 } 375 376 /// Merges fields from another ArchSpec into this ArchSpec. 377 /// 378 /// This will use the supplied ArchSpec to fill in any fields of the triple 379 /// in this ArchSpec which were unspecified. This can be used to refine a 380 /// generic ArchSpec with a more specific one. For example, if this 381 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 382 /// have a triple which is x64-pc-windows-msvc, then merging that triple 383 /// into this one will result in the triple i386-pc-windows-msvc. 384 /// 385 void MergeFrom(const ArchSpec &other); 386 387 /// Change the architecture object type, CPU type and OS type. 388 /// 389 /// \param[in] arch_type The object type of this ArchSpec. 390 /// 391 /// \param[in] cpu The required CPU type. 392 /// 393 /// \param[in] os The optional OS type 394 /// The default value of 0 was chosen to from the ELF spec value 395 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 396 /// format uses this parameter and 0 does not work, use a value over 397 /// 255 because in the ELF header this is value is only a byte. 398 /// 399 /// \return True if the object, and CPU were successfully set. 400 /// 401 /// As a side effect, the vendor value is usually set to unknown. The 402 /// exceptions are 403 /// aarch64-apple-ios 404 /// arm-apple-ios 405 /// thumb-apple-ios 406 /// x86-apple- 407 /// x86_64-apple- 408 /// 409 /// As a side effect, the os value is usually set to unknown The exceptions 410 /// are 411 /// *-*-aix 412 /// aarch64-apple-ios 413 /// arm-apple-ios 414 /// thumb-apple-ios 415 /// powerpc-apple-darwin 416 /// *-*-freebsd 417 /// *-*-linux 418 /// *-*-netbsd 419 /// *-*-openbsd 420 /// *-*-solaris 421 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 422 uint32_t os = 0); 423 424 /// Returns the byte order for the architecture specification. 425 /// 426 /// \return The endian enumeration for the current endianness of 427 /// the architecture specification 428 lldb::ByteOrder GetByteOrder() const; 429 430 /// Sets this ArchSpec's byte order. 431 /// 432 /// In the common case there is no need to call this method as the byte 433 /// order can almost always be determined by the architecture. However, many 434 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 435 /// byte order may be incorrect. 436 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 437 438 uint32_t GetMinimumOpcodeByteSize() const; 439 440 uint32_t GetMaximumOpcodeByteSize() const; 441 442 Core GetCore() const { return m_core; } 443 444 uint32_t GetMachOCPUType() const; 445 446 uint32_t GetMachOCPUSubType() const; 447 448 /// Architecture data byte width accessor 449 /// 450 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 451 /// from the Architecture's data bus 452 uint32_t GetDataByteSize() const; 453 454 /// Architecture code byte width accessor 455 /// 456 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 457 /// from the Architecture's code bus 458 uint32_t GetCodeByteSize() const; 459 460 /// Architecture triple accessor. 461 /// 462 /// \return A triple describing this ArchSpec. 463 llvm::Triple &GetTriple() { return m_triple; } 464 465 /// Architecture triple accessor. 466 /// 467 /// \return A triple describing this ArchSpec. 468 const llvm::Triple &GetTriple() const { return m_triple; } 469 470 void DumpTriple(llvm::raw_ostream &s) const; 471 472 /// Architecture triple setter. 473 /// 474 /// Configures this ArchSpec according to the given triple. If the triple 475 /// has unknown components in all of the vendor, OS, and the optional 476 /// environment field (i.e. "i386-unknown-unknown") then default values are 477 /// taken from the host. Architecture and environment components are used 478 /// to further resolve the CPU type and subtype, endian characteristics, 479 /// etc. 480 /// 481 /// \return A triple describing this ArchSpec. 482 bool SetTriple(const llvm::Triple &triple); 483 484 bool SetTriple(llvm::StringRef triple_str); 485 486 /// Returns the default endianness of the architecture. 487 /// 488 /// \return The endian enumeration for the default endianness of 489 /// the architecture. 490 lldb::ByteOrder GetDefaultEndian() const; 491 492 /// Returns true if 'char' is a signed type by default in the architecture 493 /// false otherwise 494 /// 495 /// \return True if 'char' is a signed type by default on the 496 /// architecture and false otherwise. 497 bool CharIsSignedByDefault() const; 498 499 enum MatchType : bool { CompatibleMatch, ExactMatch }; 500 501 /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of 502 /// matching that is to be done. CompatibleMatch requires only a compatible 503 /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an 504 /// exact match (armv7s is not an exact match with armv7). 505 /// 506 /// \return true if the two ArchSpecs match. 507 bool IsMatch(const ArchSpec &rhs, MatchType match) const; 508 509 /// Shorthand for IsMatch(rhs, ExactMatch). 510 bool IsExactMatch(const ArchSpec &rhs) const { 511 return IsMatch(rhs, ExactMatch); 512 } 513 514 /// Shorthand for IsMatch(rhs, CompatibleMatch). 515 bool IsCompatibleMatch(const ArchSpec &rhs) const { 516 return IsMatch(rhs, CompatibleMatch); 517 } 518 519 bool IsFullySpecifiedTriple() const; 520 521 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 522 bool &vendor_different, bool &os_different, 523 bool &os_version_different, 524 bool &env_different) const; 525 526 /// Detect whether this architecture uses thumb code exclusively 527 /// 528 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 529 /// the Thumb instructions, never Arm. We should normally pick up 530 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 531 /// on each function - but when doing bare-boards low level debugging 532 /// (especially common with these embedded processors), we may not have 533 /// those things easily accessible. 534 /// 535 /// \return true if this is an arm ArchSpec which can only execute Thumb 536 /// instructions 537 bool IsAlwaysThumbInstructions() const; 538 539 uint32_t GetFlags() const { return m_flags; } 540 541 void SetFlags(uint32_t flags) { m_flags = flags; } 542 543 void SetFlags(const std::string &elf_abi); 544 545 protected: 546 void UpdateCore(); 547 548 llvm::Triple m_triple; 549 Core m_core = kCore_invalid; 550 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 551 552 // Additional arch flags which we cannot get from triple and core For MIPS 553 // these are application specific extensions like micromips, mips16 etc. 554 uint32_t m_flags = 0; 555 556 ConstString m_distribution_id; 557 558 // Called when m_def or m_entry are changed. Fills in all remaining members 559 // with default values. 560 void CoreUpdated(bool update_triple); 561 }; 562 563 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 564 /// operator. 565 /// 566 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 567 /// 568 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 569 /// rhs The Left Hand Side ArchSpec object to compare. 570 /// 571 /// \return true if \a lhs is less than \a rhs 572 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 573 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 574 575 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 576 577 } // namespace lldb_private 578 579 #endif // LLDB_UTILITY_ARCHSPEC_H 580