1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include <cstddef> 20 #include <cstdint> 21 #include <string> 22 23 namespace lldb_private { 24 25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 26 /// specification class. 27 /// 28 /// A class designed to be created from a cpu type and subtype, a 29 /// string representation, or an llvm::Triple. Keeping all of the conversions 30 /// of strings to architecture enumeration values confined to this class 31 /// allows new architecture support to be added easily. 32 class ArchSpec { 33 public: 34 enum MIPSSubType { 35 eMIPSSubType_unknown, 36 eMIPSSubType_mips32, 37 eMIPSSubType_mips32r2, 38 eMIPSSubType_mips32r6, 39 eMIPSSubType_mips32el, 40 eMIPSSubType_mips32r2el, 41 eMIPSSubType_mips32r6el, 42 eMIPSSubType_mips64, 43 eMIPSSubType_mips64r2, 44 eMIPSSubType_mips64r6, 45 eMIPSSubType_mips64el, 46 eMIPSSubType_mips64r2el, 47 eMIPSSubType_mips64r6el, 48 }; 49 50 // Masks for the ases word of an ABI flags structure. 51 enum MIPSASE { 52 eMIPSAse_dsp = 0x00000001, // DSP ASE 53 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 54 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 55 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 56 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 57 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 58 eMIPSAse_mt = 0x00000040, // MT ASE 59 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 60 eMIPSAse_virt = 0x00000100, // VZ ASE 61 eMIPSAse_msa = 0x00000200, // MSA ASE 62 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 63 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 64 eMIPSAse_xpa = 0x00001000, // XPA ASE 65 eMIPSAse_mask = 0x00001fff, 66 eMIPSABI_O32 = 0x00002000, 67 eMIPSABI_N32 = 0x00004000, 68 eMIPSABI_N64 = 0x00008000, 69 eMIPSABI_O64 = 0x00020000, 70 eMIPSABI_EABI32 = 0x00040000, 71 eMIPSABI_EABI64 = 0x00080000, 72 eMIPSABI_mask = 0x000ff000 73 }; 74 75 // MIPS Floating point ABI Values 76 enum MIPS_ABI_FP { 77 eMIPS_ABI_FP_ANY = 0x00000000, 78 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 79 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 80 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 81 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 82 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 83 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 84 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 85 eMIPS_ABI_FP_mask = 0x00700000 86 }; 87 88 // ARM specific e_flags 89 enum ARMeflags { 90 eARM_abi_soft_float = 0x00000200, 91 eARM_abi_hard_float = 0x00000400 92 }; 93 94 enum Core { 95 eCore_arm_generic, 96 eCore_arm_armv4, 97 eCore_arm_armv4t, 98 eCore_arm_armv5, 99 eCore_arm_armv5e, 100 eCore_arm_armv5t, 101 eCore_arm_armv6, 102 eCore_arm_armv6m, 103 eCore_arm_armv7, 104 eCore_arm_armv7l, 105 eCore_arm_armv7f, 106 eCore_arm_armv7s, 107 eCore_arm_armv7k, 108 eCore_arm_armv7m, 109 eCore_arm_armv7em, 110 eCore_arm_xscale, 111 112 eCore_thumb, 113 eCore_thumbv4t, 114 eCore_thumbv5, 115 eCore_thumbv5e, 116 eCore_thumbv6, 117 eCore_thumbv6m, 118 eCore_thumbv7, 119 eCore_thumbv7s, 120 eCore_thumbv7k, 121 eCore_thumbv7f, 122 eCore_thumbv7m, 123 eCore_thumbv7em, 124 eCore_arm_arm64, 125 eCore_arm_armv8, 126 eCore_arm_armv8l, 127 eCore_arm_arm64_32, 128 eCore_arm_aarch64, 129 130 eCore_mips32, 131 eCore_mips32r2, 132 eCore_mips32r3, 133 eCore_mips32r5, 134 eCore_mips32r6, 135 eCore_mips32el, 136 eCore_mips32r2el, 137 eCore_mips32r3el, 138 eCore_mips32r5el, 139 eCore_mips32r6el, 140 eCore_mips64, 141 eCore_mips64r2, 142 eCore_mips64r3, 143 eCore_mips64r5, 144 eCore_mips64r6, 145 eCore_mips64el, 146 eCore_mips64r2el, 147 eCore_mips64r3el, 148 eCore_mips64r5el, 149 eCore_mips64r6el, 150 151 eCore_ppc_generic, 152 eCore_ppc_ppc601, 153 eCore_ppc_ppc602, 154 eCore_ppc_ppc603, 155 eCore_ppc_ppc603e, 156 eCore_ppc_ppc603ev, 157 eCore_ppc_ppc604, 158 eCore_ppc_ppc604e, 159 eCore_ppc_ppc620, 160 eCore_ppc_ppc750, 161 eCore_ppc_ppc7400, 162 eCore_ppc_ppc7450, 163 eCore_ppc_ppc970, 164 165 eCore_ppc64le_generic, 166 eCore_ppc64_generic, 167 eCore_ppc64_ppc970_64, 168 169 eCore_s390x_generic, 170 171 eCore_sparc_generic, 172 173 eCore_sparc9_generic, 174 175 eCore_x86_32_i386, 176 eCore_x86_32_i486, 177 eCore_x86_32_i486sx, 178 eCore_x86_32_i686, 179 180 eCore_x86_64_x86_64, 181 eCore_x86_64_x86_64h, // Haswell enabled x86_64 182 eCore_hexagon_generic, 183 eCore_hexagon_hexagonv4, 184 eCore_hexagon_hexagonv5, 185 186 eCore_uknownMach32, 187 eCore_uknownMach64, 188 189 eCore_arc, // little endian ARC 190 191 kNumCores, 192 193 kCore_invalid, 194 // The following constants are used for wildcard matching only 195 kCore_any, 196 kCore_arm_any, 197 kCore_ppc_any, 198 kCore_ppc64_any, 199 kCore_x86_32_any, 200 kCore_x86_64_any, 201 kCore_hexagon_any, 202 203 kCore_arm_first = eCore_arm_generic, 204 kCore_arm_last = eCore_arm_xscale, 205 206 kCore_thumb_first = eCore_thumb, 207 kCore_thumb_last = eCore_thumbv7em, 208 209 kCore_ppc_first = eCore_ppc_generic, 210 kCore_ppc_last = eCore_ppc_ppc970, 211 212 kCore_ppc64_first = eCore_ppc64_generic, 213 kCore_ppc64_last = eCore_ppc64_ppc970_64, 214 215 kCore_x86_32_first = eCore_x86_32_i386, 216 kCore_x86_32_last = eCore_x86_32_i686, 217 218 kCore_x86_64_first = eCore_x86_64_x86_64, 219 kCore_x86_64_last = eCore_x86_64_x86_64h, 220 221 kCore_hexagon_first = eCore_hexagon_generic, 222 kCore_hexagon_last = eCore_hexagon_hexagonv5, 223 224 kCore_mips32_first = eCore_mips32, 225 kCore_mips32_last = eCore_mips32r6, 226 227 kCore_mips32el_first = eCore_mips32el, 228 kCore_mips32el_last = eCore_mips32r6el, 229 230 kCore_mips64_first = eCore_mips64, 231 kCore_mips64_last = eCore_mips64r6, 232 233 kCore_mips64el_first = eCore_mips64el, 234 kCore_mips64el_last = eCore_mips64r6el, 235 236 kCore_mips_first = eCore_mips32, 237 kCore_mips_last = eCore_mips64r6el 238 239 }; 240 241 /// Default constructor. 242 /// 243 /// Default constructor that initializes the object with invalid cpu type 244 /// and subtype values. 245 ArchSpec(); 246 247 /// Constructor over triple. 248 /// 249 /// Constructs an ArchSpec with properties consistent with the given Triple. 250 explicit ArchSpec(const llvm::Triple &triple); 251 explicit ArchSpec(const char *triple_cstr); 252 explicit ArchSpec(llvm::StringRef triple_str); 253 /// Constructor over architecture name. 254 /// 255 /// Constructs an ArchSpec with properties consistent with the given object 256 /// type and architecture name. 257 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 258 uint32_t cpu_subtype); 259 260 /// Destructor. 261 ~ArchSpec(); 262 263 /// Returns true if the OS, vendor and environment fields of the triple are 264 /// unset. The triple is expected to be normalized 265 /// (llvm::Triple::normalize). 266 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 267 268 static void ListSupportedArchNames(StringList &list); 269 static void AutoComplete(CompletionRequest &request); 270 271 /// Returns a static string representing the current architecture. 272 /// 273 /// \return A static string corresponding to the current 274 /// architecture. 275 const char *GetArchitectureName() const; 276 277 /// if MIPS architecture return true. 278 /// 279 /// \return a boolean value. 280 bool IsMIPS() const; 281 282 /// Returns a string representing current architecture as a target CPU for 283 /// tools like compiler, disassembler etc. 284 /// 285 /// \return A string representing target CPU for the current 286 /// architecture. 287 std::string GetClangTargetCPU() const; 288 289 /// Return a string representing target application ABI. 290 /// 291 /// \return A string representing target application ABI. 292 std::string GetTargetABI() const; 293 294 /// Clears the object state. 295 /// 296 /// Clears the object state back to a default invalid state. 297 void Clear(); 298 299 /// Returns the size in bytes of an address of the current architecture. 300 /// 301 /// \return The byte size of an address of the current architecture. 302 uint32_t GetAddressByteSize() const; 303 304 /// Returns a machine family for the current architecture. 305 /// 306 /// \return An LLVM arch type. 307 llvm::Triple::ArchType GetMachine() const; 308 309 /// Returns the distribution id of the architecture. 310 /// 311 /// This will be something like "ubuntu", "fedora", etc. on Linux. 312 /// 313 /// \return A ConstString ref containing the distribution id, 314 /// potentially empty. 315 ConstString GetDistributionId() const; 316 317 /// Set the distribution id of the architecture. 318 /// 319 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 320 /// should be the same value returned by HostInfo::GetDistributionId (). 321 void SetDistributionId(const char *distribution_id); 322 323 /// Tests if this ArchSpec is valid. 324 /// 325 /// \return True if the current architecture is valid, false 326 /// otherwise. 327 bool IsValid() const { 328 return m_core >= eCore_arm_generic && m_core < kNumCores; 329 } 330 explicit operator bool() const { return IsValid(); } 331 332 bool TripleVendorWasSpecified() const { 333 return !m_triple.getVendorName().empty(); 334 } 335 336 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 337 338 bool TripleEnvironmentWasSpecified() const { 339 return m_triple.hasEnvironment(); 340 } 341 342 /// Merges fields from another ArchSpec into this ArchSpec. 343 /// 344 /// This will use the supplied ArchSpec to fill in any fields of the triple 345 /// in this ArchSpec which were unspecified. This can be used to refine a 346 /// generic ArchSpec with a more specific one. For example, if this 347 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 348 /// have a triple which is x64-pc-windows-msvc, then merging that triple 349 /// into this one will result in the triple i386-pc-windows-msvc. 350 /// 351 void MergeFrom(const ArchSpec &other); 352 353 /// Change the architecture object type, CPU type and OS type. 354 /// 355 /// \param[in] arch_type The object type of this ArchSpec. 356 /// 357 /// \param[in] cpu The required CPU type. 358 /// 359 /// \param[in] os The optional OS type 360 /// The default value of 0 was chosen to from the ELF spec value 361 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 362 /// format uses this parameter and 0 does not work, use a value over 363 /// 255 because in the ELF header this is value is only a byte. 364 /// 365 /// \return True if the object, and CPU were successfully set. 366 /// 367 /// As a side effect, the vendor value is usually set to unknown. The 368 /// exceptions are 369 /// aarch64-apple-ios 370 /// arm-apple-ios 371 /// thumb-apple-ios 372 /// x86-apple- 373 /// x86_64-apple- 374 /// 375 /// As a side effect, the os value is usually set to unknown The exceptions 376 /// are 377 /// *-*-aix 378 /// aarch64-apple-ios 379 /// arm-apple-ios 380 /// thumb-apple-ios 381 /// powerpc-apple-darwin 382 /// *-*-freebsd 383 /// *-*-linux 384 /// *-*-netbsd 385 /// *-*-openbsd 386 /// *-*-solaris 387 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 388 uint32_t os = 0); 389 390 /// Returns the byte order for the architecture specification. 391 /// 392 /// \return The endian enumeration for the current endianness of 393 /// the architecture specification 394 lldb::ByteOrder GetByteOrder() const; 395 396 /// Sets this ArchSpec's byte order. 397 /// 398 /// In the common case there is no need to call this method as the byte 399 /// order can almost always be determined by the architecture. However, many 400 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 401 /// byte order may be incorrect. 402 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 403 404 uint32_t GetMinimumOpcodeByteSize() const; 405 406 uint32_t GetMaximumOpcodeByteSize() const; 407 408 Core GetCore() const { return m_core; } 409 410 uint32_t GetMachOCPUType() const; 411 412 uint32_t GetMachOCPUSubType() const; 413 414 /// Architecture data byte width accessor 415 /// 416 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 417 /// from the Architecture's data bus 418 uint32_t GetDataByteSize() const; 419 420 /// Architecture code byte width accessor 421 /// 422 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 423 /// from the Architecture's code bus 424 uint32_t GetCodeByteSize() const; 425 426 /// Architecture triple accessor. 427 /// 428 /// \return A triple describing this ArchSpec. 429 llvm::Triple &GetTriple() { return m_triple; } 430 431 /// Architecture triple accessor. 432 /// 433 /// \return A triple describing this ArchSpec. 434 const llvm::Triple &GetTriple() const { return m_triple; } 435 436 void DumpTriple(llvm::raw_ostream &s) const; 437 438 /// Architecture triple setter. 439 /// 440 /// Configures this ArchSpec according to the given triple. If the triple 441 /// has unknown components in all of the vendor, OS, and the optional 442 /// environment field (i.e. "i386-unknown-unknown") then default values are 443 /// taken from the host. Architecture and environment components are used 444 /// to further resolve the CPU type and subtype, endian characteristics, 445 /// etc. 446 /// 447 /// \return A triple describing this ArchSpec. 448 bool SetTriple(const llvm::Triple &triple); 449 450 bool SetTriple(llvm::StringRef triple_str); 451 452 /// Returns the default endianness of the architecture. 453 /// 454 /// \return The endian enumeration for the default endianness of 455 /// the architecture. 456 lldb::ByteOrder GetDefaultEndian() const; 457 458 /// Returns true if 'char' is a signed type by default in the architecture 459 /// false otherwise 460 /// 461 /// \return True if 'char' is a signed type by default on the 462 /// architecture and false otherwise. 463 bool CharIsSignedByDefault() const; 464 465 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 466 /// match between them. e.g. armv7s is not an exact match with armv7 - this 467 /// would return false 468 /// 469 /// \return true if the two ArchSpecs match. 470 bool IsExactMatch(const ArchSpec &rhs) const; 471 472 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 473 /// match between them. e.g. armv7s is compatible with armv7 - this method 474 /// would return true 475 /// 476 /// \return true if the two ArchSpecs are compatible 477 bool IsCompatibleMatch(const ArchSpec &rhs) const; 478 479 bool IsFullySpecifiedTriple() const; 480 481 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 482 bool &vendor_different, bool &os_different, 483 bool &os_version_different, 484 bool &env_different) const; 485 486 /// Detect whether this architecture uses thumb code exclusively 487 /// 488 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 489 /// the Thumb instructions, never Arm. We should normally pick up 490 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 491 /// on each function - but when doing bare-boards low level debugging 492 /// (especially common with these embedded processors), we may not have 493 /// those things easily accessible. 494 /// 495 /// \return true if this is an arm ArchSpec which can only execute Thumb 496 /// instructions 497 bool IsAlwaysThumbInstructions() const; 498 499 uint32_t GetFlags() const { return m_flags; } 500 501 void SetFlags(uint32_t flags) { m_flags = flags; } 502 503 void SetFlags(std::string elf_abi); 504 505 protected: 506 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 507 void UpdateCore(); 508 509 llvm::Triple m_triple; 510 Core m_core = kCore_invalid; 511 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 512 513 // Additional arch flags which we cannot get from triple and core For MIPS 514 // these are application specific extensions like micromips, mips16 etc. 515 uint32_t m_flags = 0; 516 517 ConstString m_distribution_id; 518 519 // Called when m_def or m_entry are changed. Fills in all remaining members 520 // with default values. 521 void CoreUpdated(bool update_triple); 522 }; 523 524 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 525 /// operator. 526 /// 527 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 528 /// 529 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 530 /// rhs The Left Hand Side ArchSpec object to compare. 531 /// 532 /// \return true if \a lhs is less than \a rhs 533 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 534 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 535 536 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 537 538 } // namespace lldb_private 539 540 #endif // #ifndef LLDB_UTILITY_ARCHSPEC_H 541