1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include <cstddef> 20 #include <cstdint> 21 #include <string> 22 23 namespace lldb_private { 24 25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 26 /// specification class. 27 /// 28 /// A class designed to be created from a cpu type and subtype, a 29 /// string representation, or an llvm::Triple. Keeping all of the conversions 30 /// of strings to architecture enumeration values confined to this class 31 /// allows new architecture support to be added easily. 32 class ArchSpec { 33 public: 34 enum MIPSSubType { 35 eMIPSSubType_unknown, 36 eMIPSSubType_mips32, 37 eMIPSSubType_mips32r2, 38 eMIPSSubType_mips32r6, 39 eMIPSSubType_mips32el, 40 eMIPSSubType_mips32r2el, 41 eMIPSSubType_mips32r6el, 42 eMIPSSubType_mips64, 43 eMIPSSubType_mips64r2, 44 eMIPSSubType_mips64r6, 45 eMIPSSubType_mips64el, 46 eMIPSSubType_mips64r2el, 47 eMIPSSubType_mips64r6el, 48 }; 49 50 // Masks for the ases word of an ABI flags structure. 51 enum MIPSASE { 52 eMIPSAse_dsp = 0x00000001, // DSP ASE 53 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 54 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 55 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 56 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 57 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 58 eMIPSAse_mt = 0x00000040, // MT ASE 59 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 60 eMIPSAse_virt = 0x00000100, // VZ ASE 61 eMIPSAse_msa = 0x00000200, // MSA ASE 62 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 63 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 64 eMIPSAse_xpa = 0x00001000, // XPA ASE 65 eMIPSAse_mask = 0x00001fff, 66 eMIPSABI_O32 = 0x00002000, 67 eMIPSABI_N32 = 0x00004000, 68 eMIPSABI_N64 = 0x00008000, 69 eMIPSABI_O64 = 0x00020000, 70 eMIPSABI_EABI32 = 0x00040000, 71 eMIPSABI_EABI64 = 0x00080000, 72 eMIPSABI_mask = 0x000ff000 73 }; 74 75 // MIPS Floating point ABI Values 76 enum MIPS_ABI_FP { 77 eMIPS_ABI_FP_ANY = 0x00000000, 78 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 79 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 80 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 81 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 82 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 83 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 84 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 85 eMIPS_ABI_FP_mask = 0x00700000 86 }; 87 88 // ARM specific e_flags 89 enum ARMeflags { 90 eARM_abi_soft_float = 0x00000200, 91 eARM_abi_hard_float = 0x00000400 92 }; 93 94 enum Core { 95 eCore_arm_generic, 96 eCore_arm_armv4, 97 eCore_arm_armv4t, 98 eCore_arm_armv5, 99 eCore_arm_armv5e, 100 eCore_arm_armv5t, 101 eCore_arm_armv6, 102 eCore_arm_armv6m, 103 eCore_arm_armv7, 104 eCore_arm_armv7f, 105 eCore_arm_armv7s, 106 eCore_arm_armv7k, 107 eCore_arm_armv7m, 108 eCore_arm_armv7em, 109 eCore_arm_xscale, 110 111 eCore_thumb, 112 eCore_thumbv4t, 113 eCore_thumbv5, 114 eCore_thumbv5e, 115 eCore_thumbv6, 116 eCore_thumbv6m, 117 eCore_thumbv7, 118 eCore_thumbv7s, 119 eCore_thumbv7k, 120 eCore_thumbv7f, 121 eCore_thumbv7m, 122 eCore_thumbv7em, 123 eCore_arm_arm64, 124 eCore_arm_armv8, 125 eCore_arm_aarch64, 126 127 eCore_mips32, 128 eCore_mips32r2, 129 eCore_mips32r3, 130 eCore_mips32r5, 131 eCore_mips32r6, 132 eCore_mips32el, 133 eCore_mips32r2el, 134 eCore_mips32r3el, 135 eCore_mips32r5el, 136 eCore_mips32r6el, 137 eCore_mips64, 138 eCore_mips64r2, 139 eCore_mips64r3, 140 eCore_mips64r5, 141 eCore_mips64r6, 142 eCore_mips64el, 143 eCore_mips64r2el, 144 eCore_mips64r3el, 145 eCore_mips64r5el, 146 eCore_mips64r6el, 147 148 eCore_ppc_generic, 149 eCore_ppc_ppc601, 150 eCore_ppc_ppc602, 151 eCore_ppc_ppc603, 152 eCore_ppc_ppc603e, 153 eCore_ppc_ppc603ev, 154 eCore_ppc_ppc604, 155 eCore_ppc_ppc604e, 156 eCore_ppc_ppc620, 157 eCore_ppc_ppc750, 158 eCore_ppc_ppc7400, 159 eCore_ppc_ppc7450, 160 eCore_ppc_ppc970, 161 162 eCore_ppc64le_generic, 163 eCore_ppc64_generic, 164 eCore_ppc64_ppc970_64, 165 166 eCore_s390x_generic, 167 168 eCore_sparc_generic, 169 170 eCore_sparc9_generic, 171 172 eCore_x86_32_i386, 173 eCore_x86_32_i486, 174 eCore_x86_32_i486sx, 175 eCore_x86_32_i686, 176 177 eCore_x86_64_x86_64, 178 eCore_x86_64_x86_64h, // Haswell enabled x86_64 179 eCore_hexagon_generic, 180 eCore_hexagon_hexagonv4, 181 eCore_hexagon_hexagonv5, 182 183 eCore_uknownMach32, 184 eCore_uknownMach64, 185 186 kNumCores, 187 188 kCore_invalid, 189 // The following constants are used for wildcard matching only 190 kCore_any, 191 kCore_arm_any, 192 kCore_ppc_any, 193 kCore_ppc64_any, 194 kCore_x86_32_any, 195 kCore_x86_64_any, 196 kCore_hexagon_any, 197 198 kCore_arm_first = eCore_arm_generic, 199 kCore_arm_last = eCore_arm_xscale, 200 201 kCore_thumb_first = eCore_thumb, 202 kCore_thumb_last = eCore_thumbv7em, 203 204 kCore_ppc_first = eCore_ppc_generic, 205 kCore_ppc_last = eCore_ppc_ppc970, 206 207 kCore_ppc64_first = eCore_ppc64_generic, 208 kCore_ppc64_last = eCore_ppc64_ppc970_64, 209 210 kCore_x86_32_first = eCore_x86_32_i386, 211 kCore_x86_32_last = eCore_x86_32_i686, 212 213 kCore_x86_64_first = eCore_x86_64_x86_64, 214 kCore_x86_64_last = eCore_x86_64_x86_64h, 215 216 kCore_hexagon_first = eCore_hexagon_generic, 217 kCore_hexagon_last = eCore_hexagon_hexagonv5, 218 219 kCore_mips32_first = eCore_mips32, 220 kCore_mips32_last = eCore_mips32r6, 221 222 kCore_mips32el_first = eCore_mips32el, 223 kCore_mips32el_last = eCore_mips32r6el, 224 225 kCore_mips64_first = eCore_mips64, 226 kCore_mips64_last = eCore_mips64r6, 227 228 kCore_mips64el_first = eCore_mips64el, 229 kCore_mips64el_last = eCore_mips64r6el, 230 231 kCore_mips_first = eCore_mips32, 232 kCore_mips_last = eCore_mips64r6el 233 234 }; 235 236 /// Default constructor. 237 /// 238 /// Default constructor that initializes the object with invalid cpu type 239 /// and subtype values. 240 ArchSpec(); 241 242 /// Constructor over triple. 243 /// 244 /// Constructs an ArchSpec with properties consistent with the given Triple. 245 explicit ArchSpec(const llvm::Triple &triple); 246 explicit ArchSpec(const char *triple_cstr); 247 explicit ArchSpec(llvm::StringRef triple_str); 248 /// Constructor over architecture name. 249 /// 250 /// Constructs an ArchSpec with properties consistent with the given object 251 /// type and architecture name. 252 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 253 uint32_t cpu_subtype); 254 255 /// Destructor. 256 ~ArchSpec(); 257 258 /// Assignment operator. 259 /// 260 /// \param[in] rhs another ArchSpec object to copy. 261 /// 262 /// \return A const reference to this object. 263 const ArchSpec &operator=(const ArchSpec &rhs); 264 265 /// Returns true if the OS, vendor and environment fields of the triple are 266 /// unset. The triple is expected to be normalized 267 /// (llvm::Triple::normalize). 268 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 269 270 static void ListSupportedArchNames(StringList &list); 271 static size_t AutoComplete(CompletionRequest &request); 272 273 /// Returns a static string representing the current architecture. 274 /// 275 /// \return A static string corresponding to the current 276 /// architecture. 277 const char *GetArchitectureName() const; 278 279 /// if MIPS architecture return true. 280 /// 281 /// \return a boolean value. 282 bool IsMIPS() const; 283 284 /// Returns a string representing current architecture as a target CPU for 285 /// tools like compiler, disassembler etc. 286 /// 287 /// \return A string representing target CPU for the current 288 /// architecture. 289 std::string GetClangTargetCPU() const; 290 291 /// Return a string representing target application ABI. 292 /// 293 /// \return A string representing target application ABI. 294 std::string GetTargetABI() const; 295 296 /// Clears the object state. 297 /// 298 /// Clears the object state back to a default invalid state. 299 void Clear(); 300 301 /// Returns the size in bytes of an address of the current architecture. 302 /// 303 /// \return The byte size of an address of the current architecture. 304 uint32_t GetAddressByteSize() const; 305 306 /// Returns a machine family for the current architecture. 307 /// 308 /// \return An LLVM arch type. 309 llvm::Triple::ArchType GetMachine() const; 310 311 /// Returns the distribution id of the architecture. 312 /// 313 /// This will be something like "ubuntu", "fedora", etc. on Linux. 314 /// 315 /// \return A ConstString ref containing the distribution id, 316 /// potentially empty. 317 ConstString GetDistributionId() const; 318 319 /// Set the distribution id of the architecture. 320 /// 321 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 322 /// should be the same value returned by HostInfo::GetDistributionId (). 323 void SetDistributionId(const char *distribution_id); 324 325 /// Tests if this ArchSpec is valid. 326 /// 327 /// \return True if the current architecture is valid, false 328 /// otherwise. 329 bool IsValid() const { 330 return m_core >= eCore_arm_generic && m_core < kNumCores; 331 } 332 explicit operator bool() const { return IsValid(); } 333 334 bool TripleVendorWasSpecified() const { 335 return !m_triple.getVendorName().empty(); 336 } 337 338 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 339 340 bool TripleEnvironmentWasSpecified() const { 341 return m_triple.hasEnvironment(); 342 } 343 344 /// Merges fields from another ArchSpec into this ArchSpec. 345 /// 346 /// This will use the supplied ArchSpec to fill in any fields of the triple 347 /// in this ArchSpec which were unspecified. This can be used to refine a 348 /// generic ArchSpec with a more specific one. For example, if this 349 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 350 /// have a triple which is x64-pc-windows-msvc, then merging that triple 351 /// into this one will result in the triple i386-pc-windows-msvc. 352 /// 353 void MergeFrom(const ArchSpec &other); 354 355 /// Change the architecture object type, CPU type and OS type. 356 /// 357 /// \param[in] arch_type The object type of this ArchSpec. 358 /// 359 /// \param[in] cpu The required CPU type. 360 /// 361 /// \param[in] os The optional OS type 362 /// The default value of 0 was chosen to from the ELF spec value 363 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 364 /// format uses this parameter and 0 does not work, use a value over 365 /// 255 because in the ELF header this is value is only a byte. 366 /// 367 /// \return True if the object, and CPU were successfully set. 368 /// 369 /// As a side effect, the vendor value is usually set to unknown. The 370 /// exceptions are 371 /// aarch64-apple-ios 372 /// arm-apple-ios 373 /// thumb-apple-ios 374 /// x86-apple- 375 /// x86_64-apple- 376 /// 377 /// As a side effect, the os value is usually set to unknown The exceptions 378 /// are 379 /// *-*-aix 380 /// aarch64-apple-ios 381 /// arm-apple-ios 382 /// thumb-apple-ios 383 /// powerpc-apple-darwin 384 /// *-*-freebsd 385 /// *-*-linux 386 /// *-*-netbsd 387 /// *-*-openbsd 388 /// *-*-solaris 389 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 390 uint32_t os = 0); 391 392 /// Returns the byte order for the architecture specification. 393 /// 394 /// \return The endian enumeration for the current endianness of 395 /// the architecture specification 396 lldb::ByteOrder GetByteOrder() const; 397 398 /// Sets this ArchSpec's byte order. 399 /// 400 /// In the common case there is no need to call this method as the byte 401 /// order can almost always be determined by the architecture. However, many 402 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 403 /// byte order may be incorrect. 404 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 405 406 uint32_t GetMinimumOpcodeByteSize() const; 407 408 uint32_t GetMaximumOpcodeByteSize() const; 409 410 Core GetCore() const { return m_core; } 411 412 uint32_t GetMachOCPUType() const; 413 414 uint32_t GetMachOCPUSubType() const; 415 416 /// Architecture data byte width accessor 417 /// 418 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 419 /// from the Architecture's data bus 420 uint32_t GetDataByteSize() const; 421 422 /// Architecture code byte width accessor 423 /// 424 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 425 /// from the Architecture's code bus 426 uint32_t GetCodeByteSize() const; 427 428 /// Architecture triple accessor. 429 /// 430 /// \return A triple describing this ArchSpec. 431 llvm::Triple &GetTriple() { return m_triple; } 432 433 /// Architecture triple accessor. 434 /// 435 /// \return A triple describing this ArchSpec. 436 const llvm::Triple &GetTriple() const { return m_triple; } 437 438 void DumpTriple(Stream &s) const; 439 440 /// Architecture triple setter. 441 /// 442 /// Configures this ArchSpec according to the given triple. If the triple 443 /// has unknown components in all of the vendor, OS, and the optional 444 /// environment field (i.e. "i386-unknown-unknown") then default values are 445 /// taken from the host. Architecture and environment components are used 446 /// to further resolve the CPU type and subtype, endian characteristics, 447 /// etc. 448 /// 449 /// \return A triple describing this ArchSpec. 450 bool SetTriple(const llvm::Triple &triple); 451 452 bool SetTriple(llvm::StringRef triple_str); 453 454 /// Returns the default endianness of the architecture. 455 /// 456 /// \return The endian enumeration for the default endianness of 457 /// the architecture. 458 lldb::ByteOrder GetDefaultEndian() const; 459 460 /// Returns true if 'char' is a signed type by default in the architecture 461 /// false otherwise 462 /// 463 /// \return True if 'char' is a signed type by default on the 464 /// architecture and false otherwise. 465 bool CharIsSignedByDefault() const; 466 467 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 468 /// match between them. e.g. armv7s is not an exact match with armv7 - this 469 /// would return false 470 /// 471 /// \return true if the two ArchSpecs match. 472 bool IsExactMatch(const ArchSpec &rhs) const; 473 474 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 475 /// match between them. e.g. armv7s is compatible with armv7 - this method 476 /// would return true 477 /// 478 /// \return true if the two ArchSpecs are compatible 479 bool IsCompatibleMatch(const ArchSpec &rhs) const; 480 481 bool IsFullySpecifiedTriple() const; 482 483 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 484 bool &vendor_different, bool &os_different, 485 bool &os_version_different, 486 bool &env_different) const; 487 488 /// Detect whether this architecture uses thumb code exclusively 489 /// 490 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 491 /// the Thumb instructions, never Arm. We should normally pick up 492 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 493 /// on each function - but when doing bare-boards low level debugging 494 /// (especially common with these embedded processors), we may not have 495 /// those things easily accessible. 496 /// 497 /// \return true if this is an arm ArchSpec which can only execute Thumb 498 /// instructions 499 bool IsAlwaysThumbInstructions() const; 500 501 uint32_t GetFlags() const { return m_flags; } 502 503 void SetFlags(uint32_t flags) { m_flags = flags; } 504 505 void SetFlags(std::string elf_abi); 506 507 protected: 508 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 509 void UpdateCore(); 510 511 llvm::Triple m_triple; 512 Core m_core = kCore_invalid; 513 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 514 515 // Additional arch flags which we cannot get from triple and core For MIPS 516 // these are application specific extensions like micromips, mips16 etc. 517 uint32_t m_flags = 0; 518 519 ConstString m_distribution_id; 520 521 // Called when m_def or m_entry are changed. Fills in all remaining members 522 // with default values. 523 void CoreUpdated(bool update_triple); 524 }; 525 526 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 527 /// operator. 528 /// 529 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 530 /// 531 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 532 /// rhs The Left Hand Side ArchSpec object to compare. 533 /// 534 /// \return true if \a lhs is less than \a rhs 535 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 536 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 537 538 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 539 540 } // namespace lldb_private 541 542 #endif // #ifndef LLDB_UTILITY_ARCHSPEC_H 543