1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Support/YAMLTraits.h" 20 #include <cstddef> 21 #include <cstdint> 22 #include <string> 23 24 namespace lldb_private { 25 26 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 27 /// specification class. 28 /// 29 /// A class designed to be created from a cpu type and subtype, a 30 /// string representation, or an llvm::Triple. Keeping all of the conversions 31 /// of strings to architecture enumeration values confined to this class 32 /// allows new architecture support to be added easily. 33 class ArchSpec { 34 public: 35 enum MIPSSubType { 36 eMIPSSubType_unknown, 37 eMIPSSubType_mips32, 38 eMIPSSubType_mips32r2, 39 eMIPSSubType_mips32r6, 40 eMIPSSubType_mips32el, 41 eMIPSSubType_mips32r2el, 42 eMIPSSubType_mips32r6el, 43 eMIPSSubType_mips64, 44 eMIPSSubType_mips64r2, 45 eMIPSSubType_mips64r6, 46 eMIPSSubType_mips64el, 47 eMIPSSubType_mips64r2el, 48 eMIPSSubType_mips64r6el, 49 }; 50 51 // Masks for the ases word of an ABI flags structure. 52 enum MIPSASE { 53 eMIPSAse_dsp = 0x00000001, // DSP ASE 54 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 55 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 56 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 57 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 58 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 59 eMIPSAse_mt = 0x00000040, // MT ASE 60 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 61 eMIPSAse_virt = 0x00000100, // VZ ASE 62 eMIPSAse_msa = 0x00000200, // MSA ASE 63 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 64 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 65 eMIPSAse_xpa = 0x00001000, // XPA ASE 66 eMIPSAse_mask = 0x00001fff, 67 eMIPSABI_O32 = 0x00002000, 68 eMIPSABI_N32 = 0x00004000, 69 eMIPSABI_N64 = 0x00008000, 70 eMIPSABI_O64 = 0x00020000, 71 eMIPSABI_EABI32 = 0x00040000, 72 eMIPSABI_EABI64 = 0x00080000, 73 eMIPSABI_mask = 0x000ff000 74 }; 75 76 // MIPS Floating point ABI Values 77 enum MIPS_ABI_FP { 78 eMIPS_ABI_FP_ANY = 0x00000000, 79 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 80 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 81 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 82 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 83 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 84 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 85 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 86 eMIPS_ABI_FP_mask = 0x00700000 87 }; 88 89 // ARM specific e_flags 90 enum ARMeflags { 91 eARM_abi_soft_float = 0x00000200, 92 eARM_abi_hard_float = 0x00000400 93 }; 94 95 enum RISCVeflags { 96 eRISCV_rvc = 0x00000001, /// RVC, +c 97 eRISCV_float_abi_soft = 0x00000000, /// soft float 98 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f 99 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d 100 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q 101 eRISCV_float_abi_mask = 0x00000006, 102 eRISCV_rve = 0x00000008, /// RVE, +e 103 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering) 104 }; 105 106 enum RISCVSubType { 107 eRISCVSubType_unknown, 108 eRISCVSubType_riscv32, 109 eRISCVSubType_riscv64, 110 }; 111 112 enum Core { 113 eCore_arm_generic, 114 eCore_arm_armv4, 115 eCore_arm_armv4t, 116 eCore_arm_armv5, 117 eCore_arm_armv5e, 118 eCore_arm_armv5t, 119 eCore_arm_armv6, 120 eCore_arm_armv6m, 121 eCore_arm_armv7, 122 eCore_arm_armv7l, 123 eCore_arm_armv7f, 124 eCore_arm_armv7s, 125 eCore_arm_armv7k, 126 eCore_arm_armv7m, 127 eCore_arm_armv7em, 128 eCore_arm_xscale, 129 130 eCore_thumb, 131 eCore_thumbv4t, 132 eCore_thumbv5, 133 eCore_thumbv5e, 134 eCore_thumbv6, 135 eCore_thumbv6m, 136 eCore_thumbv7, 137 eCore_thumbv7s, 138 eCore_thumbv7k, 139 eCore_thumbv7f, 140 eCore_thumbv7m, 141 eCore_thumbv7em, 142 eCore_arm_arm64, 143 eCore_arm_armv8, 144 eCore_arm_armv8l, 145 eCore_arm_arm64e, 146 eCore_arm_arm64_32, 147 eCore_arm_aarch64, 148 149 eCore_mips32, 150 eCore_mips32r2, 151 eCore_mips32r3, 152 eCore_mips32r5, 153 eCore_mips32r6, 154 eCore_mips32el, 155 eCore_mips32r2el, 156 eCore_mips32r3el, 157 eCore_mips32r5el, 158 eCore_mips32r6el, 159 eCore_mips64, 160 eCore_mips64r2, 161 eCore_mips64r3, 162 eCore_mips64r5, 163 eCore_mips64r6, 164 eCore_mips64el, 165 eCore_mips64r2el, 166 eCore_mips64r3el, 167 eCore_mips64r5el, 168 eCore_mips64r6el, 169 170 eCore_ppc_generic, 171 eCore_ppc_ppc601, 172 eCore_ppc_ppc602, 173 eCore_ppc_ppc603, 174 eCore_ppc_ppc603e, 175 eCore_ppc_ppc603ev, 176 eCore_ppc_ppc604, 177 eCore_ppc_ppc604e, 178 eCore_ppc_ppc620, 179 eCore_ppc_ppc750, 180 eCore_ppc_ppc7400, 181 eCore_ppc_ppc7450, 182 eCore_ppc_ppc970, 183 184 eCore_ppc64le_generic, 185 eCore_ppc64_generic, 186 eCore_ppc64_ppc970_64, 187 188 eCore_s390x_generic, 189 190 eCore_sparc_generic, 191 192 eCore_sparc9_generic, 193 194 eCore_x86_32_i386, 195 eCore_x86_32_i486, 196 eCore_x86_32_i486sx, 197 eCore_x86_32_i686, 198 199 eCore_x86_64_x86_64, 200 eCore_x86_64_x86_64h, // Haswell enabled x86_64 201 eCore_hexagon_generic, 202 eCore_hexagon_hexagonv4, 203 eCore_hexagon_hexagonv5, 204 205 eCore_riscv32, 206 eCore_riscv64, 207 208 eCore_uknownMach32, 209 eCore_uknownMach64, 210 211 eCore_arc, // little endian ARC 212 213 eCore_avr, 214 215 eCore_wasm32, 216 217 kNumCores, 218 219 kCore_invalid, 220 // The following constants are used for wildcard matching only 221 kCore_any, 222 kCore_arm_any, 223 kCore_ppc_any, 224 kCore_ppc64_any, 225 kCore_x86_32_any, 226 kCore_x86_64_any, 227 kCore_hexagon_any, 228 229 kCore_arm_first = eCore_arm_generic, 230 kCore_arm_last = eCore_arm_xscale, 231 232 kCore_thumb_first = eCore_thumb, 233 kCore_thumb_last = eCore_thumbv7em, 234 235 kCore_ppc_first = eCore_ppc_generic, 236 kCore_ppc_last = eCore_ppc_ppc970, 237 238 kCore_ppc64_first = eCore_ppc64_generic, 239 kCore_ppc64_last = eCore_ppc64_ppc970_64, 240 241 kCore_x86_32_first = eCore_x86_32_i386, 242 kCore_x86_32_last = eCore_x86_32_i686, 243 244 kCore_x86_64_first = eCore_x86_64_x86_64, 245 kCore_x86_64_last = eCore_x86_64_x86_64h, 246 247 kCore_hexagon_first = eCore_hexagon_generic, 248 kCore_hexagon_last = eCore_hexagon_hexagonv5, 249 250 kCore_mips32_first = eCore_mips32, 251 kCore_mips32_last = eCore_mips32r6, 252 253 kCore_mips32el_first = eCore_mips32el, 254 kCore_mips32el_last = eCore_mips32r6el, 255 256 kCore_mips64_first = eCore_mips64, 257 kCore_mips64_last = eCore_mips64r6, 258 259 kCore_mips64el_first = eCore_mips64el, 260 kCore_mips64el_last = eCore_mips64r6el, 261 262 kCore_mips_first = eCore_mips32, 263 kCore_mips_last = eCore_mips64r6el 264 265 }; 266 267 /// Default constructor. 268 /// 269 /// Default constructor that initializes the object with invalid cpu type 270 /// and subtype values. 271 ArchSpec(); 272 273 /// Constructor over triple. 274 /// 275 /// Constructs an ArchSpec with properties consistent with the given Triple. 276 explicit ArchSpec(const llvm::Triple &triple); 277 explicit ArchSpec(const char *triple_cstr); 278 explicit ArchSpec(llvm::StringRef triple_str); 279 /// Constructor over architecture name. 280 /// 281 /// Constructs an ArchSpec with properties consistent with the given object 282 /// type and architecture name. 283 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 284 uint32_t cpu_subtype); 285 286 /// Destructor. 287 ~ArchSpec(); 288 289 /// Returns true if the OS, vendor and environment fields of the triple are 290 /// unset. The triple is expected to be normalized 291 /// (llvm::Triple::normalize). 292 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 293 294 static void ListSupportedArchNames(StringList &list); 295 static void AutoComplete(CompletionRequest &request); 296 297 /// Returns a static string representing the current architecture. 298 /// 299 /// \return A static string corresponding to the current 300 /// architecture. 301 const char *GetArchitectureName() const; 302 303 /// if MIPS architecture return true. 304 /// 305 /// \return a boolean value. 306 bool IsMIPS() const; 307 308 /// Returns a string representing current architecture as a target CPU for 309 /// tools like compiler, disassembler etc. 310 /// 311 /// \return A string representing target CPU for the current 312 /// architecture. 313 std::string GetClangTargetCPU() const; 314 315 /// Return a string representing target application ABI. 316 /// 317 /// \return A string representing target application ABI. 318 std::string GetTargetABI() const; 319 320 /// Clears the object state. 321 /// 322 /// Clears the object state back to a default invalid state. 323 void Clear(); 324 325 /// Returns the size in bytes of an address of the current architecture. 326 /// 327 /// \return The byte size of an address of the current architecture. 328 uint32_t GetAddressByteSize() const; 329 330 /// Returns a machine family for the current architecture. 331 /// 332 /// \return An LLVM arch type. 333 llvm::Triple::ArchType GetMachine() const; 334 335 /// Returns the distribution id of the architecture. 336 /// 337 /// This will be something like "ubuntu", "fedora", etc. on Linux. 338 /// 339 /// \return A ConstString ref containing the distribution id, 340 /// potentially empty. 341 ConstString GetDistributionId() const; 342 343 /// Set the distribution id of the architecture. 344 /// 345 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 346 /// should be the same value returned by HostInfo::GetDistributionId (). 347 void SetDistributionId(const char *distribution_id); 348 349 /// Tests if this ArchSpec is valid. 350 /// 351 /// \return True if the current architecture is valid, false 352 /// otherwise. 353 bool IsValid() const { 354 return m_core >= eCore_arm_generic && m_core < kNumCores; 355 } 356 explicit operator bool() const { return IsValid(); } 357 358 bool TripleVendorWasSpecified() const { 359 return !m_triple.getVendorName().empty(); 360 } 361 362 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 363 364 bool TripleEnvironmentWasSpecified() const { 365 return m_triple.hasEnvironment(); 366 } 367 368 /// Merges fields from another ArchSpec into this ArchSpec. 369 /// 370 /// This will use the supplied ArchSpec to fill in any fields of the triple 371 /// in this ArchSpec which were unspecified. This can be used to refine a 372 /// generic ArchSpec with a more specific one. For example, if this 373 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 374 /// have a triple which is x64-pc-windows-msvc, then merging that triple 375 /// into this one will result in the triple i386-pc-windows-msvc. 376 /// 377 void MergeFrom(const ArchSpec &other); 378 379 /// Change the architecture object type, CPU type and OS type. 380 /// 381 /// \param[in] arch_type The object type of this ArchSpec. 382 /// 383 /// \param[in] cpu The required CPU type. 384 /// 385 /// \param[in] os The optional OS type 386 /// The default value of 0 was chosen to from the ELF spec value 387 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 388 /// format uses this parameter and 0 does not work, use a value over 389 /// 255 because in the ELF header this is value is only a byte. 390 /// 391 /// \return True if the object, and CPU were successfully set. 392 /// 393 /// As a side effect, the vendor value is usually set to unknown. The 394 /// exceptions are 395 /// aarch64-apple-ios 396 /// arm-apple-ios 397 /// thumb-apple-ios 398 /// x86-apple- 399 /// x86_64-apple- 400 /// 401 /// As a side effect, the os value is usually set to unknown The exceptions 402 /// are 403 /// *-*-aix 404 /// aarch64-apple-ios 405 /// arm-apple-ios 406 /// thumb-apple-ios 407 /// powerpc-apple-darwin 408 /// *-*-freebsd 409 /// *-*-linux 410 /// *-*-netbsd 411 /// *-*-openbsd 412 /// *-*-solaris 413 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 414 uint32_t os = 0); 415 416 /// Returns the byte order for the architecture specification. 417 /// 418 /// \return The endian enumeration for the current endianness of 419 /// the architecture specification 420 lldb::ByteOrder GetByteOrder() const; 421 422 /// Sets this ArchSpec's byte order. 423 /// 424 /// In the common case there is no need to call this method as the byte 425 /// order can almost always be determined by the architecture. However, many 426 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 427 /// byte order may be incorrect. 428 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 429 430 uint32_t GetMinimumOpcodeByteSize() const; 431 432 uint32_t GetMaximumOpcodeByteSize() const; 433 434 Core GetCore() const { return m_core; } 435 436 uint32_t GetMachOCPUType() const; 437 438 uint32_t GetMachOCPUSubType() const; 439 440 /// Architecture data byte width accessor 441 /// 442 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 443 /// from the Architecture's data bus 444 uint32_t GetDataByteSize() const; 445 446 /// Architecture code byte width accessor 447 /// 448 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 449 /// from the Architecture's code bus 450 uint32_t GetCodeByteSize() const; 451 452 /// Architecture triple accessor. 453 /// 454 /// \return A triple describing this ArchSpec. 455 llvm::Triple &GetTriple() { return m_triple; } 456 457 /// Architecture triple accessor. 458 /// 459 /// \return A triple describing this ArchSpec. 460 const llvm::Triple &GetTriple() const { return m_triple; } 461 462 void DumpTriple(llvm::raw_ostream &s) const; 463 464 /// Architecture triple setter. 465 /// 466 /// Configures this ArchSpec according to the given triple. If the triple 467 /// has unknown components in all of the vendor, OS, and the optional 468 /// environment field (i.e. "i386-unknown-unknown") then default values are 469 /// taken from the host. Architecture and environment components are used 470 /// to further resolve the CPU type and subtype, endian characteristics, 471 /// etc. 472 /// 473 /// \return A triple describing this ArchSpec. 474 bool SetTriple(const llvm::Triple &triple); 475 476 bool SetTriple(llvm::StringRef triple_str); 477 478 /// Returns the default endianness of the architecture. 479 /// 480 /// \return The endian enumeration for the default endianness of 481 /// the architecture. 482 lldb::ByteOrder GetDefaultEndian() const; 483 484 /// Returns true if 'char' is a signed type by default in the architecture 485 /// false otherwise 486 /// 487 /// \return True if 'char' is a signed type by default on the 488 /// architecture and false otherwise. 489 bool CharIsSignedByDefault() const; 490 491 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 492 /// match between them. e.g. armv7s is not an exact match with armv7 - this 493 /// would return false 494 /// 495 /// \return true if the two ArchSpecs match. 496 bool IsExactMatch(const ArchSpec &rhs) const; 497 498 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 499 /// match between them. e.g. armv7s is compatible with armv7 - this method 500 /// would return true 501 /// 502 /// \return true if the two ArchSpecs are compatible 503 bool IsCompatibleMatch(const ArchSpec &rhs) const; 504 505 bool IsFullySpecifiedTriple() const; 506 507 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 508 bool &vendor_different, bool &os_different, 509 bool &os_version_different, 510 bool &env_different) const; 511 512 /// Detect whether this architecture uses thumb code exclusively 513 /// 514 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 515 /// the Thumb instructions, never Arm. We should normally pick up 516 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 517 /// on each function - but when doing bare-boards low level debugging 518 /// (especially common with these embedded processors), we may not have 519 /// those things easily accessible. 520 /// 521 /// \return true if this is an arm ArchSpec which can only execute Thumb 522 /// instructions 523 bool IsAlwaysThumbInstructions() const; 524 525 uint32_t GetFlags() const { return m_flags; } 526 527 void SetFlags(uint32_t flags) { m_flags = flags; } 528 529 void SetFlags(const std::string &elf_abi); 530 531 protected: 532 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 533 void UpdateCore(); 534 535 llvm::Triple m_triple; 536 Core m_core = kCore_invalid; 537 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 538 539 // Additional arch flags which we cannot get from triple and core For MIPS 540 // these are application specific extensions like micromips, mips16 etc. 541 uint32_t m_flags = 0; 542 543 ConstString m_distribution_id; 544 545 // Called when m_def or m_entry are changed. Fills in all remaining members 546 // with default values. 547 void CoreUpdated(bool update_triple); 548 }; 549 550 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 551 /// operator. 552 /// 553 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 554 /// 555 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 556 /// rhs The Left Hand Side ArchSpec object to compare. 557 /// 558 /// \return true if \a lhs is less than \a rhs 559 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 560 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 561 562 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 563 564 } // namespace lldb_private 565 566 namespace llvm { 567 namespace yaml { 568 template <> struct ScalarTraits<lldb_private::ArchSpec> { 569 static void output(const lldb_private::ArchSpec &, void *, raw_ostream &); 570 static StringRef input(StringRef, void *, lldb_private::ArchSpec &); 571 static QuotingType mustQuote(StringRef S) { return QuotingType::Double; } 572 }; 573 } // namespace yaml 574 } // namespace llvm 575 576 LLVM_YAML_IS_SEQUENCE_VECTOR(lldb_private::ArchSpec) 577 578 #endif // LLDB_UTILITY_ARCHSPEC_H 579