1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Support/YAMLTraits.h" 20 #include <cstddef> 21 #include <cstdint> 22 #include <string> 23 24 namespace lldb_private { 25 26 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 27 /// specification class. 28 /// 29 /// A class designed to be created from a cpu type and subtype, a 30 /// string representation, or an llvm::Triple. Keeping all of the conversions 31 /// of strings to architecture enumeration values confined to this class 32 /// allows new architecture support to be added easily. 33 class ArchSpec { 34 public: 35 enum MIPSSubType { 36 eMIPSSubType_unknown, 37 eMIPSSubType_mips32, 38 eMIPSSubType_mips32r2, 39 eMIPSSubType_mips32r6, 40 eMIPSSubType_mips32el, 41 eMIPSSubType_mips32r2el, 42 eMIPSSubType_mips32r6el, 43 eMIPSSubType_mips64, 44 eMIPSSubType_mips64r2, 45 eMIPSSubType_mips64r6, 46 eMIPSSubType_mips64el, 47 eMIPSSubType_mips64r2el, 48 eMIPSSubType_mips64r6el, 49 }; 50 51 // Masks for the ases word of an ABI flags structure. 52 enum MIPSASE { 53 eMIPSAse_dsp = 0x00000001, // DSP ASE 54 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 55 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 56 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 57 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 58 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 59 eMIPSAse_mt = 0x00000040, // MT ASE 60 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 61 eMIPSAse_virt = 0x00000100, // VZ ASE 62 eMIPSAse_msa = 0x00000200, // MSA ASE 63 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 64 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 65 eMIPSAse_xpa = 0x00001000, // XPA ASE 66 eMIPSAse_mask = 0x00001fff, 67 eMIPSABI_O32 = 0x00002000, 68 eMIPSABI_N32 = 0x00004000, 69 eMIPSABI_N64 = 0x00008000, 70 eMIPSABI_O64 = 0x00020000, 71 eMIPSABI_EABI32 = 0x00040000, 72 eMIPSABI_EABI64 = 0x00080000, 73 eMIPSABI_mask = 0x000ff000 74 }; 75 76 // MIPS Floating point ABI Values 77 enum MIPS_ABI_FP { 78 eMIPS_ABI_FP_ANY = 0x00000000, 79 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 80 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 81 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 82 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 83 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 84 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 85 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 86 eMIPS_ABI_FP_mask = 0x00700000 87 }; 88 89 // ARM specific e_flags 90 enum ARMeflags { 91 eARM_abi_soft_float = 0x00000200, 92 eARM_abi_hard_float = 0x00000400 93 }; 94 95 enum RISCVSubType { 96 eRISCVSubType_unknown, 97 eRISCVSubType_riscv32, 98 eRISCVSubType_riscv64, 99 }; 100 101 enum Core { 102 eCore_arm_generic, 103 eCore_arm_armv4, 104 eCore_arm_armv4t, 105 eCore_arm_armv5, 106 eCore_arm_armv5e, 107 eCore_arm_armv5t, 108 eCore_arm_armv6, 109 eCore_arm_armv6m, 110 eCore_arm_armv7, 111 eCore_arm_armv7l, 112 eCore_arm_armv7f, 113 eCore_arm_armv7s, 114 eCore_arm_armv7k, 115 eCore_arm_armv7m, 116 eCore_arm_armv7em, 117 eCore_arm_xscale, 118 119 eCore_thumb, 120 eCore_thumbv4t, 121 eCore_thumbv5, 122 eCore_thumbv5e, 123 eCore_thumbv6, 124 eCore_thumbv6m, 125 eCore_thumbv7, 126 eCore_thumbv7s, 127 eCore_thumbv7k, 128 eCore_thumbv7f, 129 eCore_thumbv7m, 130 eCore_thumbv7em, 131 eCore_arm_arm64, 132 eCore_arm_armv8, 133 eCore_arm_armv8l, 134 eCore_arm_arm64e, 135 eCore_arm_arm64_32, 136 eCore_arm_aarch64, 137 138 eCore_mips32, 139 eCore_mips32r2, 140 eCore_mips32r3, 141 eCore_mips32r5, 142 eCore_mips32r6, 143 eCore_mips32el, 144 eCore_mips32r2el, 145 eCore_mips32r3el, 146 eCore_mips32r5el, 147 eCore_mips32r6el, 148 eCore_mips64, 149 eCore_mips64r2, 150 eCore_mips64r3, 151 eCore_mips64r5, 152 eCore_mips64r6, 153 eCore_mips64el, 154 eCore_mips64r2el, 155 eCore_mips64r3el, 156 eCore_mips64r5el, 157 eCore_mips64r6el, 158 159 eCore_ppc_generic, 160 eCore_ppc_ppc601, 161 eCore_ppc_ppc602, 162 eCore_ppc_ppc603, 163 eCore_ppc_ppc603e, 164 eCore_ppc_ppc603ev, 165 eCore_ppc_ppc604, 166 eCore_ppc_ppc604e, 167 eCore_ppc_ppc620, 168 eCore_ppc_ppc750, 169 eCore_ppc_ppc7400, 170 eCore_ppc_ppc7450, 171 eCore_ppc_ppc970, 172 173 eCore_ppc64le_generic, 174 eCore_ppc64_generic, 175 eCore_ppc64_ppc970_64, 176 177 eCore_s390x_generic, 178 179 eCore_sparc_generic, 180 181 eCore_sparc9_generic, 182 183 eCore_x86_32_i386, 184 eCore_x86_32_i486, 185 eCore_x86_32_i486sx, 186 eCore_x86_32_i686, 187 188 eCore_x86_64_x86_64, 189 eCore_x86_64_x86_64h, // Haswell enabled x86_64 190 eCore_hexagon_generic, 191 eCore_hexagon_hexagonv4, 192 eCore_hexagon_hexagonv5, 193 194 eCore_riscv32, 195 eCore_riscv64, 196 197 eCore_uknownMach32, 198 eCore_uknownMach64, 199 200 eCore_arc, // little endian ARC 201 202 eCore_avr, 203 204 eCore_wasm32, 205 206 kNumCores, 207 208 kCore_invalid, 209 // The following constants are used for wildcard matching only 210 kCore_any, 211 kCore_arm_any, 212 kCore_ppc_any, 213 kCore_ppc64_any, 214 kCore_x86_32_any, 215 kCore_x86_64_any, 216 kCore_hexagon_any, 217 218 kCore_arm_first = eCore_arm_generic, 219 kCore_arm_last = eCore_arm_xscale, 220 221 kCore_thumb_first = eCore_thumb, 222 kCore_thumb_last = eCore_thumbv7em, 223 224 kCore_ppc_first = eCore_ppc_generic, 225 kCore_ppc_last = eCore_ppc_ppc970, 226 227 kCore_ppc64_first = eCore_ppc64_generic, 228 kCore_ppc64_last = eCore_ppc64_ppc970_64, 229 230 kCore_x86_32_first = eCore_x86_32_i386, 231 kCore_x86_32_last = eCore_x86_32_i686, 232 233 kCore_x86_64_first = eCore_x86_64_x86_64, 234 kCore_x86_64_last = eCore_x86_64_x86_64h, 235 236 kCore_hexagon_first = eCore_hexagon_generic, 237 kCore_hexagon_last = eCore_hexagon_hexagonv5, 238 239 kCore_mips32_first = eCore_mips32, 240 kCore_mips32_last = eCore_mips32r6, 241 242 kCore_mips32el_first = eCore_mips32el, 243 kCore_mips32el_last = eCore_mips32r6el, 244 245 kCore_mips64_first = eCore_mips64, 246 kCore_mips64_last = eCore_mips64r6, 247 248 kCore_mips64el_first = eCore_mips64el, 249 kCore_mips64el_last = eCore_mips64r6el, 250 251 kCore_mips_first = eCore_mips32, 252 kCore_mips_last = eCore_mips64r6el 253 254 }; 255 256 /// Default constructor. 257 /// 258 /// Default constructor that initializes the object with invalid cpu type 259 /// and subtype values. 260 ArchSpec(); 261 262 /// Constructor over triple. 263 /// 264 /// Constructs an ArchSpec with properties consistent with the given Triple. 265 explicit ArchSpec(const llvm::Triple &triple); 266 explicit ArchSpec(const char *triple_cstr); 267 explicit ArchSpec(llvm::StringRef triple_str); 268 /// Constructor over architecture name. 269 /// 270 /// Constructs an ArchSpec with properties consistent with the given object 271 /// type and architecture name. 272 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 273 uint32_t cpu_subtype); 274 275 /// Destructor. 276 ~ArchSpec(); 277 278 /// Returns true if the OS, vendor and environment fields of the triple are 279 /// unset. The triple is expected to be normalized 280 /// (llvm::Triple::normalize). 281 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 282 283 static void ListSupportedArchNames(StringList &list); 284 static void AutoComplete(CompletionRequest &request); 285 286 /// Returns a static string representing the current architecture. 287 /// 288 /// \return A static string corresponding to the current 289 /// architecture. 290 const char *GetArchitectureName() const; 291 292 /// if MIPS architecture return true. 293 /// 294 /// \return a boolean value. 295 bool IsMIPS() const; 296 297 /// Returns a string representing current architecture as a target CPU for 298 /// tools like compiler, disassembler etc. 299 /// 300 /// \return A string representing target CPU for the current 301 /// architecture. 302 std::string GetClangTargetCPU() const; 303 304 /// Return a string representing target application ABI. 305 /// 306 /// \return A string representing target application ABI. 307 std::string GetTargetABI() const; 308 309 /// Clears the object state. 310 /// 311 /// Clears the object state back to a default invalid state. 312 void Clear(); 313 314 /// Returns the size in bytes of an address of the current architecture. 315 /// 316 /// \return The byte size of an address of the current architecture. 317 uint32_t GetAddressByteSize() const; 318 319 /// Returns a machine family for the current architecture. 320 /// 321 /// \return An LLVM arch type. 322 llvm::Triple::ArchType GetMachine() const; 323 324 /// Returns the distribution id of the architecture. 325 /// 326 /// This will be something like "ubuntu", "fedora", etc. on Linux. 327 /// 328 /// \return A ConstString ref containing the distribution id, 329 /// potentially empty. 330 ConstString GetDistributionId() const; 331 332 /// Set the distribution id of the architecture. 333 /// 334 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 335 /// should be the same value returned by HostInfo::GetDistributionId (). 336 void SetDistributionId(const char *distribution_id); 337 338 /// Tests if this ArchSpec is valid. 339 /// 340 /// \return True if the current architecture is valid, false 341 /// otherwise. 342 bool IsValid() const { 343 return m_core >= eCore_arm_generic && m_core < kNumCores; 344 } 345 explicit operator bool() const { return IsValid(); } 346 347 bool TripleVendorWasSpecified() const { 348 return !m_triple.getVendorName().empty(); 349 } 350 351 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 352 353 bool TripleEnvironmentWasSpecified() const { 354 return m_triple.hasEnvironment(); 355 } 356 357 /// Merges fields from another ArchSpec into this ArchSpec. 358 /// 359 /// This will use the supplied ArchSpec to fill in any fields of the triple 360 /// in this ArchSpec which were unspecified. This can be used to refine a 361 /// generic ArchSpec with a more specific one. For example, if this 362 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 363 /// have a triple which is x64-pc-windows-msvc, then merging that triple 364 /// into this one will result in the triple i386-pc-windows-msvc. 365 /// 366 void MergeFrom(const ArchSpec &other); 367 368 /// Change the architecture object type, CPU type and OS type. 369 /// 370 /// \param[in] arch_type The object type of this ArchSpec. 371 /// 372 /// \param[in] cpu The required CPU type. 373 /// 374 /// \param[in] os The optional OS type 375 /// The default value of 0 was chosen to from the ELF spec value 376 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 377 /// format uses this parameter and 0 does not work, use a value over 378 /// 255 because in the ELF header this is value is only a byte. 379 /// 380 /// \return True if the object, and CPU were successfully set. 381 /// 382 /// As a side effect, the vendor value is usually set to unknown. The 383 /// exceptions are 384 /// aarch64-apple-ios 385 /// arm-apple-ios 386 /// thumb-apple-ios 387 /// x86-apple- 388 /// x86_64-apple- 389 /// 390 /// As a side effect, the os value is usually set to unknown The exceptions 391 /// are 392 /// *-*-aix 393 /// aarch64-apple-ios 394 /// arm-apple-ios 395 /// thumb-apple-ios 396 /// powerpc-apple-darwin 397 /// *-*-freebsd 398 /// *-*-linux 399 /// *-*-netbsd 400 /// *-*-openbsd 401 /// *-*-solaris 402 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 403 uint32_t os = 0); 404 405 /// Returns the byte order for the architecture specification. 406 /// 407 /// \return The endian enumeration for the current endianness of 408 /// the architecture specification 409 lldb::ByteOrder GetByteOrder() const; 410 411 /// Sets this ArchSpec's byte order. 412 /// 413 /// In the common case there is no need to call this method as the byte 414 /// order can almost always be determined by the architecture. However, many 415 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 416 /// byte order may be incorrect. 417 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 418 419 uint32_t GetMinimumOpcodeByteSize() const; 420 421 uint32_t GetMaximumOpcodeByteSize() const; 422 423 Core GetCore() const { return m_core; } 424 425 uint32_t GetMachOCPUType() const; 426 427 uint32_t GetMachOCPUSubType() const; 428 429 /// Architecture data byte width accessor 430 /// 431 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 432 /// from the Architecture's data bus 433 uint32_t GetDataByteSize() const; 434 435 /// Architecture code byte width accessor 436 /// 437 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 438 /// from the Architecture's code bus 439 uint32_t GetCodeByteSize() const; 440 441 /// Architecture triple accessor. 442 /// 443 /// \return A triple describing this ArchSpec. 444 llvm::Triple &GetTriple() { return m_triple; } 445 446 /// Architecture triple accessor. 447 /// 448 /// \return A triple describing this ArchSpec. 449 const llvm::Triple &GetTriple() const { return m_triple; } 450 451 void DumpTriple(llvm::raw_ostream &s) const; 452 453 /// Architecture triple setter. 454 /// 455 /// Configures this ArchSpec according to the given triple. If the triple 456 /// has unknown components in all of the vendor, OS, and the optional 457 /// environment field (i.e. "i386-unknown-unknown") then default values are 458 /// taken from the host. Architecture and environment components are used 459 /// to further resolve the CPU type and subtype, endian characteristics, 460 /// etc. 461 /// 462 /// \return A triple describing this ArchSpec. 463 bool SetTriple(const llvm::Triple &triple); 464 465 bool SetTriple(llvm::StringRef triple_str); 466 467 /// Returns the default endianness of the architecture. 468 /// 469 /// \return The endian enumeration for the default endianness of 470 /// the architecture. 471 lldb::ByteOrder GetDefaultEndian() const; 472 473 /// Returns true if 'char' is a signed type by default in the architecture 474 /// false otherwise 475 /// 476 /// \return True if 'char' is a signed type by default on the 477 /// architecture and false otherwise. 478 bool CharIsSignedByDefault() const; 479 480 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 481 /// match between them. e.g. armv7s is not an exact match with armv7 - this 482 /// would return false 483 /// 484 /// \return true if the two ArchSpecs match. 485 bool IsExactMatch(const ArchSpec &rhs) const; 486 487 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 488 /// match between them. e.g. armv7s is compatible with armv7 - this method 489 /// would return true 490 /// 491 /// \return true if the two ArchSpecs are compatible 492 bool IsCompatibleMatch(const ArchSpec &rhs) const; 493 494 bool IsFullySpecifiedTriple() const; 495 496 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 497 bool &vendor_different, bool &os_different, 498 bool &os_version_different, 499 bool &env_different) const; 500 501 /// Detect whether this architecture uses thumb code exclusively 502 /// 503 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 504 /// the Thumb instructions, never Arm. We should normally pick up 505 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 506 /// on each function - but when doing bare-boards low level debugging 507 /// (especially common with these embedded processors), we may not have 508 /// those things easily accessible. 509 /// 510 /// \return true if this is an arm ArchSpec which can only execute Thumb 511 /// instructions 512 bool IsAlwaysThumbInstructions() const; 513 514 uint32_t GetFlags() const { return m_flags; } 515 516 void SetFlags(uint32_t flags) { m_flags = flags; } 517 518 void SetFlags(const std::string &elf_abi); 519 520 protected: 521 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 522 void UpdateCore(); 523 524 llvm::Triple m_triple; 525 Core m_core = kCore_invalid; 526 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 527 528 // Additional arch flags which we cannot get from triple and core For MIPS 529 // these are application specific extensions like micromips, mips16 etc. 530 uint32_t m_flags = 0; 531 532 ConstString m_distribution_id; 533 534 // Called when m_def or m_entry are changed. Fills in all remaining members 535 // with default values. 536 void CoreUpdated(bool update_triple); 537 }; 538 539 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 540 /// operator. 541 /// 542 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 543 /// 544 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 545 /// rhs The Left Hand Side ArchSpec object to compare. 546 /// 547 /// \return true if \a lhs is less than \a rhs 548 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 549 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 550 551 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 552 553 } // namespace lldb_private 554 555 namespace llvm { 556 namespace yaml { 557 template <> struct ScalarTraits<lldb_private::ArchSpec> { 558 static void output(const lldb_private::ArchSpec &, void *, raw_ostream &); 559 static StringRef input(StringRef, void *, lldb_private::ArchSpec &); 560 static QuotingType mustQuote(StringRef S) { return QuotingType::Double; } 561 }; 562 } // namespace yaml 563 } // namespace llvm 564 565 LLVM_YAML_IS_SEQUENCE_VECTOR(lldb_private::ArchSpec) 566 567 #endif // LLDB_UTILITY_ARCHSPEC_H 568