1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Machine-specific things, such as applying relocations, creation of 10 // GOT or PLT entries, etc., are handled in this file. 11 // 12 // Refer the ELF spec for the single letter variables, S, A or P, used 13 // in this file. 14 // 15 // Some functions defined in this file has "relaxTls" as part of their names. 16 // They do peephole optimization for TLS variables by rewriting instructions. 17 // They are not part of the ABI but optional optimization, so you can skip 18 // them if you are not interested in how TLS variables are optimized. 19 // See the following paper for the details. 20 // 21 // Ulrich Drepper, ELF Handling For Thread-Local Storage 22 // http://www.akkadia.org/drepper/tls.pdf 23 // 24 //===----------------------------------------------------------------------===// 25 26 #include "Target.h" 27 #include "InputFiles.h" 28 #include "OutputSections.h" 29 #include "SymbolTable.h" 30 #include "Symbols.h" 31 #include "lld/Common/ErrorHandler.h" 32 #include "llvm/Object/ELF.h" 33 34 using namespace llvm; 35 using namespace llvm::object; 36 using namespace llvm::ELF; 37 using namespace lld; 38 using namespace lld::elf; 39 40 std::string elf::toStr(Ctx &ctx, RelType type) { 41 StringRef s = getELFRelocationTypeName(ctx.arg.emachine, type); 42 if (s == "Unknown") 43 return ("Unknown (" + Twine(type) + ")").str(); 44 return std::string(s); 45 } 46 47 const ELFSyncStream &elf::operator<<(const ELFSyncStream &s, RelType type) { 48 s << toStr(s.ctx, type); 49 return s; 50 } 51 52 void elf::setTarget(Ctx &ctx) { 53 switch (ctx.arg.emachine) { 54 case EM_386: 55 case EM_IAMCU: 56 return setX86TargetInfo(ctx); 57 case EM_AARCH64: 58 return setAArch64TargetInfo(ctx); 59 case EM_AMDGPU: 60 return setAMDGPUTargetInfo(ctx); 61 case EM_ARM: 62 return setARMTargetInfo(ctx); 63 case EM_AVR: 64 return setAVRTargetInfo(ctx); 65 case EM_HEXAGON: 66 return setHexagonTargetInfo(ctx); 67 case EM_LOONGARCH: 68 return setLoongArchTargetInfo(ctx); 69 case EM_MIPS: 70 return setMipsTargetInfo(ctx); 71 case EM_MSP430: 72 return setMSP430TargetInfo(ctx); 73 case EM_PPC: 74 return setPPCTargetInfo(ctx); 75 case EM_PPC64: 76 return setPPC64TargetInfo(ctx); 77 case EM_RISCV: 78 return setRISCVTargetInfo(ctx); 79 case EM_SPARCV9: 80 return setSPARCV9TargetInfo(ctx); 81 case EM_S390: 82 return setSystemZTargetInfo(ctx); 83 case EM_X86_64: 84 return setX86_64TargetInfo(ctx); 85 default: 86 Fatal(ctx) << "unsupported e_machine value: " << ctx.arg.emachine; 87 } 88 } 89 90 ErrorPlace elf::getErrorPlace(Ctx &ctx, const uint8_t *loc) { 91 assert(loc != nullptr); 92 for (InputSectionBase *d : ctx.inputSections) { 93 auto *isec = dyn_cast<InputSection>(d); 94 if (!isec || !isec->getParent() || (isec->type & SHT_NOBITS)) 95 continue; 96 97 const uint8_t *isecLoc = 98 ctx.bufferStart 99 ? (ctx.bufferStart + isec->getParent()->offset + isec->outSecOff) 100 : isec->contentMaybeDecompress().data(); 101 if (isecLoc == nullptr) { 102 assert(isa<SyntheticSection>(isec) && "No data but not synthetic?"); 103 continue; 104 } 105 if (isecLoc <= loc && loc < isecLoc + isec->getSize()) { 106 std::string objLoc = isec->getLocation(loc - isecLoc); 107 // Return object file location and source file location. 108 Undefined dummy(ctx.internalFile, "", STB_LOCAL, 0, 0); 109 ELFSyncStream msg(ctx, DiagLevel::None); 110 if (isec->file) 111 msg << isec->getSrcMsg(dummy, loc - isecLoc); 112 return {isec, objLoc + ": ", std::string(msg.str())}; 113 } 114 } 115 return {}; 116 } 117 118 TargetInfo::~TargetInfo() {} 119 120 int64_t TargetInfo::getImplicitAddend(const uint8_t *buf, RelType type) const { 121 InternalErr(ctx, buf) << "cannot read addend for relocation " << type; 122 return 0; 123 } 124 125 bool TargetInfo::usesOnlyLowPageBits(RelType type) const { return false; } 126 127 bool TargetInfo::needsThunk(RelExpr expr, RelType type, const InputFile *file, 128 uint64_t branchAddr, const Symbol &s, 129 int64_t a) const { 130 return false; 131 } 132 133 bool TargetInfo::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end, 134 uint8_t stOther) const { 135 Err(ctx) << "target doesn't support split stacks"; 136 return false; 137 } 138 139 bool TargetInfo::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { 140 return true; 141 } 142 143 RelExpr TargetInfo::adjustTlsExpr(RelType type, RelExpr expr) const { 144 return expr; 145 } 146 147 RelExpr TargetInfo::adjustGotPcExpr(RelType type, int64_t addend, 148 const uint8_t *data) const { 149 return R_GOT_PC; 150 } 151 152 void TargetInfo::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { 153 const unsigned bits = ctx.arg.is64 ? 64 : 32; 154 uint64_t secAddr = sec.getOutputSection()->addr; 155 if (auto *s = dyn_cast<InputSection>(&sec)) 156 secAddr += s->outSecOff; 157 else if (auto *ehIn = dyn_cast<EhInputSection>(&sec)) 158 secAddr += ehIn->getParent()->outSecOff; 159 for (const Relocation &rel : sec.relocs()) { 160 uint8_t *loc = buf + rel.offset; 161 const uint64_t val = SignExtend64( 162 sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset), bits); 163 if (rel.expr != R_RELAX_HINT) 164 relocate(loc, rel, val); 165 } 166 } 167 168 uint64_t TargetInfo::getImageBase() const { 169 // Use --image-base if set. Fall back to the target default if not. 170 if (ctx.arg.imageBase) 171 return *ctx.arg.imageBase; 172 return ctx.arg.isPic ? 0 : defaultImageBase; 173 } 174