1 //===- RISCV.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 14 using namespace llvm; 15 using namespace llvm::object; 16 using namespace llvm::support::endian; 17 using namespace llvm::ELF; 18 using namespace lld; 19 using namespace lld::elf; 20 21 namespace { 22 23 class RISCV final : public TargetInfo { 24 public: 25 RISCV(); 26 uint32_t calcEFlags() const override; 27 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 28 void writeGotHeader(uint8_t *buf) const override; 29 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 30 void writeIgotPlt(uint8_t *buf, const Symbol &s) const override; 31 void writePltHeader(uint8_t *buf) const override; 32 void writePlt(uint8_t *buf, const Symbol &sym, 33 uint64_t pltEntryAddr) const override; 34 RelType getDynRel(RelType type) const override; 35 RelExpr getRelExpr(RelType type, const Symbol &s, 36 const uint8_t *loc) const override; 37 void relocate(uint8_t *loc, const Relocation &rel, 38 uint64_t val) const override; 39 }; 40 41 } // end anonymous namespace 42 43 const uint64_t dtpOffset = 0x800; 44 45 enum Op { 46 ADDI = 0x13, 47 AUIPC = 0x17, 48 JALR = 0x67, 49 LD = 0x3003, 50 LW = 0x2003, 51 SRLI = 0x5013, 52 SUB = 0x40000033, 53 }; 54 55 enum Reg { 56 X_RA = 1, 57 X_T0 = 5, 58 X_T1 = 6, 59 X_T2 = 7, 60 X_T3 = 28, 61 }; 62 63 static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; } 64 static uint32_t lo12(uint32_t val) { return val & 4095; } 65 66 static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) { 67 return op | (rd << 7) | (rs1 << 15) | (imm << 20); 68 } 69 static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) { 70 return op | (rd << 7) | (rs1 << 15) | (rs2 << 20); 71 } 72 static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) { 73 return op | (rd << 7) | (imm << 12); 74 } 75 76 RISCV::RISCV() { 77 copyRel = R_RISCV_COPY; 78 pltRel = R_RISCV_JUMP_SLOT; 79 relativeRel = R_RISCV_RELATIVE; 80 iRelativeRel = R_RISCV_IRELATIVE; 81 if (config->is64) { 82 symbolicRel = R_RISCV_64; 83 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64; 84 tlsOffsetRel = R_RISCV_TLS_DTPREL64; 85 tlsGotRel = R_RISCV_TLS_TPREL64; 86 } else { 87 symbolicRel = R_RISCV_32; 88 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32; 89 tlsOffsetRel = R_RISCV_TLS_DTPREL32; 90 tlsGotRel = R_RISCV_TLS_TPREL32; 91 } 92 gotRel = symbolicRel; 93 94 // .got[0] = _DYNAMIC 95 gotHeaderEntriesNum = 1; 96 97 // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map 98 gotPltHeaderEntriesNum = 2; 99 100 pltHeaderSize = 32; 101 pltEntrySize = 16; 102 ipltEntrySize = 16; 103 } 104 105 static uint32_t getEFlags(InputFile *f) { 106 if (config->is64) 107 return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader().e_flags; 108 return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags; 109 } 110 111 uint32_t RISCV::calcEFlags() const { 112 // If there are only binary input files (from -b binary), use a 113 // value of 0 for the ELF header flags. 114 if (objectFiles.empty()) 115 return 0; 116 117 uint32_t target = getEFlags(objectFiles.front()); 118 119 for (InputFile *f : objectFiles) { 120 uint32_t eflags = getEFlags(f); 121 if (eflags & EF_RISCV_RVC) 122 target |= EF_RISCV_RVC; 123 124 if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI)) 125 error(toString(f) + 126 ": cannot link object files with different floating-point ABI"); 127 128 if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE)) 129 error(toString(f) + 130 ": cannot link object files with different EF_RISCV_RVE"); 131 } 132 133 return target; 134 } 135 136 int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const { 137 switch (type) { 138 default: 139 internalLinkerError(getErrorLocation(buf), 140 "cannot read addend for relocation " + toString(type)); 141 return 0; 142 case R_RISCV_32: 143 case R_RISCV_TLS_DTPMOD32: 144 case R_RISCV_TLS_DTPREL32: 145 return SignExtend64<32>(read32le(buf)); 146 case R_RISCV_64: 147 return read64le(buf); 148 case R_RISCV_RELATIVE: 149 case R_RISCV_IRELATIVE: 150 return config->is64 ? read64le(buf) : read32le(buf); 151 case R_RISCV_NONE: 152 case R_RISCV_JUMP_SLOT: 153 // These relocations are defined as not having an implicit addend. 154 return 0; 155 } 156 } 157 158 void RISCV::writeGotHeader(uint8_t *buf) const { 159 if (config->is64) 160 write64le(buf, mainPart->dynamic->getVA()); 161 else 162 write32le(buf, mainPart->dynamic->getVA()); 163 } 164 165 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const { 166 if (config->is64) 167 write64le(buf, in.plt->getVA()); 168 else 169 write32le(buf, in.plt->getVA()); 170 } 171 172 void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const { 173 if (config->writeAddends) { 174 if (config->is64) 175 write64le(buf, s.getVA()); 176 else 177 write32le(buf, s.getVA()); 178 } 179 } 180 181 void RISCV::writePltHeader(uint8_t *buf) const { 182 // 1: auipc t2, %pcrel_hi(.got.plt) 183 // sub t1, t1, t3 184 // l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve 185 // addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0] 186 // addi t0, t2, %pcrel_lo(1b) 187 // srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0] 188 // l[wd] t0, Wordsize(t0); t0 = link_map 189 // jr t3 190 uint32_t offset = in.gotPlt->getVA() - in.plt->getVA(); 191 uint32_t load = config->is64 ? LD : LW; 192 write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset))); 193 write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3)); 194 write32le(buf + 8, itype(load, X_T3, X_T2, lo12(offset))); 195 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12)); 196 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); 197 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2)); 198 write32le(buf + 24, itype(load, X_T0, X_T0, config->wordsize)); 199 write32le(buf + 28, itype(JALR, 0, X_T3, 0)); 200 } 201 202 void RISCV::writePlt(uint8_t *buf, const Symbol &sym, 203 uint64_t pltEntryAddr) const { 204 // 1: auipc t3, %pcrel_hi(f@.got.plt) 205 // l[wd] t3, %pcrel_lo(1b)(t3) 206 // jalr t1, t3 207 // nop 208 uint32_t offset = sym.getGotPltVA() - pltEntryAddr; 209 write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset))); 210 write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset))); 211 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0)); 212 write32le(buf + 12, itype(ADDI, 0, 0, 0)); 213 } 214 215 RelType RISCV::getDynRel(RelType type) const { 216 return type == target->symbolicRel ? type 217 : static_cast<RelType>(R_RISCV_NONE); 218 } 219 220 RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s, 221 const uint8_t *loc) const { 222 switch (type) { 223 case R_RISCV_NONE: 224 return R_NONE; 225 case R_RISCV_32: 226 case R_RISCV_64: 227 case R_RISCV_HI20: 228 case R_RISCV_LO12_I: 229 case R_RISCV_LO12_S: 230 case R_RISCV_RVC_LUI: 231 return R_ABS; 232 case R_RISCV_ADD8: 233 case R_RISCV_ADD16: 234 case R_RISCV_ADD32: 235 case R_RISCV_ADD64: 236 case R_RISCV_SET6: 237 case R_RISCV_SET8: 238 case R_RISCV_SET16: 239 case R_RISCV_SET32: 240 case R_RISCV_SUB6: 241 case R_RISCV_SUB8: 242 case R_RISCV_SUB16: 243 case R_RISCV_SUB32: 244 case R_RISCV_SUB64: 245 return R_RISCV_ADD; 246 case R_RISCV_JAL: 247 case R_RISCV_BRANCH: 248 case R_RISCV_PCREL_HI20: 249 case R_RISCV_RVC_BRANCH: 250 case R_RISCV_RVC_JUMP: 251 case R_RISCV_32_PCREL: 252 return R_PC; 253 case R_RISCV_CALL: 254 case R_RISCV_CALL_PLT: 255 return R_PLT_PC; 256 case R_RISCV_GOT_HI20: 257 return R_GOT_PC; 258 case R_RISCV_PCREL_LO12_I: 259 case R_RISCV_PCREL_LO12_S: 260 return R_RISCV_PC_INDIRECT; 261 case R_RISCV_TLS_GD_HI20: 262 return R_TLSGD_PC; 263 case R_RISCV_TLS_GOT_HI20: 264 config->hasTlsIe = true; 265 return R_GOT_PC; 266 case R_RISCV_TPREL_HI20: 267 case R_RISCV_TPREL_LO12_I: 268 case R_RISCV_TPREL_LO12_S: 269 return R_TPREL; 270 case R_RISCV_RELAX: 271 case R_RISCV_TPREL_ADD: 272 return R_NONE; 273 case R_RISCV_ALIGN: 274 // Not just a hint; always padded to the worst-case number of NOPs, so may 275 // not currently be aligned, and without linker relaxation support we can't 276 // delete NOPs to realign. 277 errorOrWarn(getErrorLocation(loc) + "relocation R_RISCV_ALIGN requires " 278 "unimplemented linker relaxation; recompile with -mno-relax"); 279 return R_NONE; 280 default: 281 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 282 ") against symbol " + toString(s)); 283 return R_NONE; 284 } 285 } 286 287 // Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63. 288 static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) { 289 return (v & ((1ULL << (begin + 1)) - 1)) >> end; 290 } 291 292 void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { 293 const unsigned bits = config->wordsize * 8; 294 295 switch (rel.type) { 296 case R_RISCV_32: 297 write32le(loc, val); 298 return; 299 case R_RISCV_64: 300 write64le(loc, val); 301 return; 302 303 case R_RISCV_RVC_BRANCH: { 304 checkInt(loc, static_cast<int64_t>(val) >> 1, 8, rel); 305 checkAlignment(loc, val, 2, rel); 306 uint16_t insn = read16le(loc) & 0xE383; 307 uint16_t imm8 = extractBits(val, 8, 8) << 12; 308 uint16_t imm4_3 = extractBits(val, 4, 3) << 10; 309 uint16_t imm7_6 = extractBits(val, 7, 6) << 5; 310 uint16_t imm2_1 = extractBits(val, 2, 1) << 3; 311 uint16_t imm5 = extractBits(val, 5, 5) << 2; 312 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; 313 314 write16le(loc, insn); 315 return; 316 } 317 318 case R_RISCV_RVC_JUMP: { 319 checkInt(loc, static_cast<int64_t>(val) >> 1, 11, rel); 320 checkAlignment(loc, val, 2, rel); 321 uint16_t insn = read16le(loc) & 0xE003; 322 uint16_t imm11 = extractBits(val, 11, 11) << 12; 323 uint16_t imm4 = extractBits(val, 4, 4) << 11; 324 uint16_t imm9_8 = extractBits(val, 9, 8) << 9; 325 uint16_t imm10 = extractBits(val, 10, 10) << 8; 326 uint16_t imm6 = extractBits(val, 6, 6) << 7; 327 uint16_t imm7 = extractBits(val, 7, 7) << 6; 328 uint16_t imm3_1 = extractBits(val, 3, 1) << 3; 329 uint16_t imm5 = extractBits(val, 5, 5) << 2; 330 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; 331 332 write16le(loc, insn); 333 return; 334 } 335 336 case R_RISCV_RVC_LUI: { 337 int64_t imm = SignExtend64(val + 0x800, bits) >> 12; 338 checkInt(loc, imm, 6, rel); 339 if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0` 340 write16le(loc, (read16le(loc) & 0x0F83) | 0x4000); 341 } else { 342 uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12; 343 uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2; 344 write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12); 345 } 346 return; 347 } 348 349 case R_RISCV_JAL: { 350 checkInt(loc, static_cast<int64_t>(val) >> 1, 20, rel); 351 checkAlignment(loc, val, 2, rel); 352 353 uint32_t insn = read32le(loc) & 0xFFF; 354 uint32_t imm20 = extractBits(val, 20, 20) << 31; 355 uint32_t imm10_1 = extractBits(val, 10, 1) << 21; 356 uint32_t imm11 = extractBits(val, 11, 11) << 20; 357 uint32_t imm19_12 = extractBits(val, 19, 12) << 12; 358 insn |= imm20 | imm10_1 | imm11 | imm19_12; 359 360 write32le(loc, insn); 361 return; 362 } 363 364 case R_RISCV_BRANCH: { 365 checkInt(loc, static_cast<int64_t>(val) >> 1, 12, rel); 366 checkAlignment(loc, val, 2, rel); 367 368 uint32_t insn = read32le(loc) & 0x1FFF07F; 369 uint32_t imm12 = extractBits(val, 12, 12) << 31; 370 uint32_t imm10_5 = extractBits(val, 10, 5) << 25; 371 uint32_t imm4_1 = extractBits(val, 4, 1) << 8; 372 uint32_t imm11 = extractBits(val, 11, 11) << 7; 373 insn |= imm12 | imm10_5 | imm4_1 | imm11; 374 375 write32le(loc, insn); 376 return; 377 } 378 379 // auipc + jalr pair 380 case R_RISCV_CALL: 381 case R_RISCV_CALL_PLT: { 382 int64_t hi = SignExtend64(val + 0x800, bits) >> 12; 383 checkInt(loc, hi, 20, rel); 384 if (isInt<20>(hi)) { 385 relocateNoSym(loc, R_RISCV_PCREL_HI20, val); 386 relocateNoSym(loc + 4, R_RISCV_PCREL_LO12_I, val); 387 } 388 return; 389 } 390 391 case R_RISCV_GOT_HI20: 392 case R_RISCV_PCREL_HI20: 393 case R_RISCV_TLS_GD_HI20: 394 case R_RISCV_TLS_GOT_HI20: 395 case R_RISCV_TPREL_HI20: 396 case R_RISCV_HI20: { 397 uint64_t hi = val + 0x800; 398 checkInt(loc, SignExtend64(hi, bits) >> 12, 20, rel); 399 write32le(loc, (read32le(loc) & 0xFFF) | (hi & 0xFFFFF000)); 400 return; 401 } 402 403 case R_RISCV_PCREL_LO12_I: 404 case R_RISCV_TPREL_LO12_I: 405 case R_RISCV_LO12_I: { 406 uint64_t hi = (val + 0x800) >> 12; 407 uint64_t lo = val - (hi << 12); 408 write32le(loc, (read32le(loc) & 0xFFFFF) | ((lo & 0xFFF) << 20)); 409 return; 410 } 411 412 case R_RISCV_PCREL_LO12_S: 413 case R_RISCV_TPREL_LO12_S: 414 case R_RISCV_LO12_S: { 415 uint64_t hi = (val + 0x800) >> 12; 416 uint64_t lo = val - (hi << 12); 417 uint32_t imm11_5 = extractBits(lo, 11, 5) << 25; 418 uint32_t imm4_0 = extractBits(lo, 4, 0) << 7; 419 write32le(loc, (read32le(loc) & 0x1FFF07F) | imm11_5 | imm4_0); 420 return; 421 } 422 423 case R_RISCV_ADD8: 424 *loc += val; 425 return; 426 case R_RISCV_ADD16: 427 write16le(loc, read16le(loc) + val); 428 return; 429 case R_RISCV_ADD32: 430 write32le(loc, read32le(loc) + val); 431 return; 432 case R_RISCV_ADD64: 433 write64le(loc, read64le(loc) + val); 434 return; 435 case R_RISCV_SUB6: 436 *loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f); 437 return; 438 case R_RISCV_SUB8: 439 *loc -= val; 440 return; 441 case R_RISCV_SUB16: 442 write16le(loc, read16le(loc) - val); 443 return; 444 case R_RISCV_SUB32: 445 write32le(loc, read32le(loc) - val); 446 return; 447 case R_RISCV_SUB64: 448 write64le(loc, read64le(loc) - val); 449 return; 450 case R_RISCV_SET6: 451 *loc = (*loc & 0xc0) | (val & 0x3f); 452 return; 453 case R_RISCV_SET8: 454 *loc = val; 455 return; 456 case R_RISCV_SET16: 457 write16le(loc, val); 458 return; 459 case R_RISCV_SET32: 460 case R_RISCV_32_PCREL: 461 write32le(loc, val); 462 return; 463 464 case R_RISCV_TLS_DTPREL32: 465 write32le(loc, val - dtpOffset); 466 break; 467 case R_RISCV_TLS_DTPREL64: 468 write64le(loc, val - dtpOffset); 469 break; 470 471 case R_RISCV_RELAX: 472 return; // Ignored (for now) 473 474 default: 475 llvm_unreachable("unknown relocation"); 476 } 477 } 478 479 TargetInfo *elf::getRISCVTargetInfo() { 480 static RISCV target; 481 return ⌖ 482 } 483