1 //===- PPC64.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "Symbols.h" 10 #include "SyntheticSections.h" 11 #include "Target.h" 12 #include "lld/Common/ErrorHandler.h" 13 #include "llvm/Support/Endian.h" 14 15 using namespace llvm; 16 using namespace llvm::object; 17 using namespace llvm::support::endian; 18 using namespace llvm::ELF; 19 using namespace lld; 20 using namespace lld::elf; 21 22 static uint64_t ppc64TocOffset = 0x8000; 23 static uint64_t dynamicThreadPointerOffset = 0x8000; 24 25 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform 26 // instructions that can be used as part of the initial exec TLS sequence. 27 enum XFormOpcd { 28 LBZX = 87, 29 LHZX = 279, 30 LWZX = 23, 31 LDX = 21, 32 STBX = 215, 33 STHX = 407, 34 STWX = 151, 35 STDX = 149, 36 ADD = 266, 37 }; 38 39 enum DFormOpcd { 40 LBZ = 34, 41 LBZU = 35, 42 LHZ = 40, 43 LHZU = 41, 44 LHAU = 43, 45 LWZ = 32, 46 LWZU = 33, 47 LFSU = 49, 48 LD = 58, 49 LFDU = 51, 50 STB = 38, 51 STBU = 39, 52 STH = 44, 53 STHU = 45, 54 STW = 36, 55 STWU = 37, 56 STFSU = 53, 57 STFDU = 55, 58 STD = 62, 59 ADDI = 14 60 }; 61 62 uint64_t elf::getPPC64TocBase() { 63 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 64 // TOC starts where the first of these sections starts. We always create a 65 // .got when we see a relocation that uses it, so for us the start is always 66 // the .got. 67 uint64_t tocVA = in.got->getVA(); 68 69 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 70 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 71 // code (crt1.o) assumes that you can get from the TOC base to the 72 // start of the .toc section with only a single (signed) 16-bit relocation. 73 return tocVA + ppc64TocOffset; 74 } 75 76 unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) { 77 // The offset is encoded into the 3 most significant bits of the st_other 78 // field, with some special values described in section 3.4.1 of the ABI: 79 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use 80 // the TOC pointer (r2). r2 will hold the same value on returning from 81 // the function as it did on entering the function. 82 // 1 --> Zero offset between the GEP and LEP, and r2 should be treated as a 83 // caller-saved register for all callers. 84 // 2-6 --> The binary logarithm of the offset eg: 85 // 2 --> 2^2 = 4 bytes --> 1 instruction. 86 // 6 --> 2^6 = 64 bytes --> 16 instructions. 87 // 7 --> Reserved. 88 uint8_t gepToLep = (stOther >> 5) & 7; 89 if (gepToLep < 2) 90 return 0; 91 92 // The value encoded in the st_other bits is the 93 // log-base-2(offset). 94 if (gepToLep < 7) 95 return 1 << gepToLep; 96 97 error("reserved value of 7 in the 3 most-significant-bits of st_other"); 98 return 0; 99 } 100 101 bool elf::isPPC64SmallCodeModelTocReloc(RelType type) { 102 // The only small code model relocations that access the .toc section. 103 return type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS; 104 } 105 106 // Find the R_PPC64_ADDR64 in .rela.toc with matching offset. 107 template <typename ELFT> 108 static std::pair<Defined *, int64_t> 109 getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) { 110 if (tocSec->numRelocations == 0) 111 return {}; 112 113 // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by 114 // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the 115 // relocation index in most cases. 116 // 117 // In rare cases a TOC entry may store a constant that doesn't need an 118 // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8 119 // points to a relocation with larger r_offset. Do a linear probe then. 120 // Constants are extremely uncommon in .toc and the extra number of array 121 // accesses can be seen as a small constant. 122 ArrayRef<typename ELFT::Rela> relas = tocSec->template relas<ELFT>(); 123 uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1); 124 for (;;) { 125 if (relas[index].r_offset == offset) { 126 Symbol &sym = tocSec->getFile<ELFT>()->getRelocTargetSym(relas[index]); 127 return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])}; 128 } 129 if (relas[index].r_offset < offset || index == 0) 130 break; 131 --index; 132 } 133 return {}; 134 } 135 136 // When accessing a symbol defined in another translation unit, compilers 137 // reserve a .toc entry, allocate a local label and generate toc-indirect 138 // instuctions: 139 // 140 // addis 3, 2, .LC0@toc@ha # R_PPC64_TOC16_HA 141 // ld 3, .LC0@toc@l(3) # R_PPC64_TOC16_LO_DS, load the address from a .toc entry 142 // ld/lwa 3, 0(3) # load the value from the address 143 // 144 // .section .toc,"aw",@progbits 145 // .LC0: .tc var[TC],var 146 // 147 // If var is defined, non-preemptable and addressable with a 32-bit signed 148 // offset from the toc base, the address of var can be computed by adding an 149 // offset to the toc base, saving a load. 150 // 151 // addis 3,2,var@toc@ha # this may be relaxed to a nop, 152 // addi 3,3,var@toc@l # then this becomes addi 3,2,var@toc 153 // ld/lwa 3, 0(3) # load the value from the address 154 // 155 // Returns true if the relaxation is performed. 156 bool elf::tryRelaxPPC64TocIndirection(RelType type, const Relocation &rel, 157 uint8_t *bufLoc) { 158 assert(config->tocOptimize); 159 if (rel.addend < 0) 160 return false; 161 162 // If the symbol is not the .toc section, this isn't a toc-indirection. 163 Defined *defSym = dyn_cast<Defined>(rel.sym); 164 if (!defSym || !defSym->isSection() || defSym->section->name != ".toc") 165 return false; 166 167 Defined *d; 168 int64_t addend; 169 auto *tocISB = cast<InputSectionBase>(defSym->section); 170 std::tie(d, addend) = 171 config->isLE ? getRelaTocSymAndAddend<ELF64LE>(tocISB, rel.addend) 172 : getRelaTocSymAndAddend<ELF64BE>(tocISB, rel.addend); 173 174 // Only non-preemptable defined symbols can be relaxed. 175 if (!d || d->isPreemptible) 176 return false; 177 178 // Two instructions can materialize a 32-bit signed offset from the toc base. 179 uint64_t tocRelative = d->getVA(addend) - getPPC64TocBase(); 180 if (!isInt<32>(tocRelative)) 181 return false; 182 183 // Add PPC64TocOffset that will be subtracted by relocateOne(). 184 target->relaxGot(bufLoc, type, tocRelative + ppc64TocOffset); 185 return true; 186 } 187 188 namespace { 189 class PPC64 final : public TargetInfo { 190 public: 191 PPC64(); 192 int getTlsGdRelaxSkip(RelType type) const override; 193 uint32_t calcEFlags() const override; 194 RelExpr getRelExpr(RelType type, const Symbol &s, 195 const uint8_t *loc) const override; 196 RelType getDynRel(RelType type) const override; 197 void writePltHeader(uint8_t *buf) const override; 198 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 199 int32_t index, unsigned relOff) const override; 200 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 201 void writeGotHeader(uint8_t *buf) const override; 202 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 203 uint64_t branchAddr, const Symbol &s) const override; 204 uint32_t getThunkSectionSpacing() const override; 205 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override; 206 RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, 207 RelExpr expr) const override; 208 void relaxGot(uint8_t *loc, RelType type, uint64_t val) const override; 209 void relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const override; 210 void relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const override; 211 void relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const override; 212 void relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const override; 213 214 bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end, 215 uint8_t stOther) const override; 216 }; 217 } // namespace 218 219 // Relocation masks following the #lo(value), #hi(value), #ha(value), 220 // #higher(value), #highera(value), #highest(value), and #highesta(value) 221 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 222 // document. 223 static uint16_t lo(uint64_t v) { return v; } 224 static uint16_t hi(uint64_t v) { return v >> 16; } 225 static uint16_t ha(uint64_t v) { return (v + 0x8000) >> 16; } 226 static uint16_t higher(uint64_t v) { return v >> 32; } 227 static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; } 228 static uint16_t highest(uint64_t v) { return v >> 48; } 229 static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; } 230 231 // Extracts the 'PO' field of an instruction encoding. 232 static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); } 233 234 static bool isDQFormInstruction(uint32_t encoding) { 235 switch (getPrimaryOpCode(encoding)) { 236 default: 237 return false; 238 case 56: 239 // The only instruction with a primary opcode of 56 is `lq`. 240 return true; 241 case 61: 242 // There are both DS and DQ instruction forms with this primary opcode. 243 // Namely `lxv` and `stxv` are the DQ-forms that use it. 244 // The DS 'XO' bits being set to 01 is restricted to DQ form. 245 return (encoding & 3) == 0x1; 246 } 247 } 248 249 static bool isInstructionUpdateForm(uint32_t encoding) { 250 switch (getPrimaryOpCode(encoding)) { 251 default: 252 return false; 253 case LBZU: 254 case LHAU: 255 case LHZU: 256 case LWZU: 257 case LFSU: 258 case LFDU: 259 case STBU: 260 case STHU: 261 case STWU: 262 case STFSU: 263 case STFDU: 264 return true; 265 // LWA has the same opcode as LD, and the DS bits is what differentiates 266 // between LD/LDU/LWA 267 case LD: 268 case STD: 269 return (encoding & 3) == 1; 270 } 271 } 272 273 // There are a number of places when we either want to read or write an 274 // instruction when handling a half16 relocation type. On big-endian the buffer 275 // pointer is pointing into the middle of the word we want to extract, and on 276 // little-endian it is pointing to the start of the word. These 2 helpers are to 277 // simplify reading and writing in that context. 278 static void writeFromHalf16(uint8_t *loc, uint32_t insn) { 279 write32(config->isLE ? loc : loc - 2, insn); 280 } 281 282 static uint32_t readFromHalf16(const uint8_t *loc) { 283 return read32(config->isLE ? loc : loc - 2); 284 } 285 286 PPC64::PPC64() { 287 gotRel = R_PPC64_GLOB_DAT; 288 noneRel = R_PPC64_NONE; 289 pltRel = R_PPC64_JMP_SLOT; 290 relativeRel = R_PPC64_RELATIVE; 291 iRelativeRel = R_PPC64_IRELATIVE; 292 symbolicRel = R_PPC64_ADDR64; 293 pltEntrySize = 4; 294 gotBaseSymInGotPlt = false; 295 gotHeaderEntriesNum = 1; 296 gotPltHeaderEntriesNum = 2; 297 pltHeaderSize = 60; 298 needsThunks = true; 299 300 tlsModuleIndexRel = R_PPC64_DTPMOD64; 301 tlsOffsetRel = R_PPC64_DTPREL64; 302 303 tlsGotRel = R_PPC64_TPREL64; 304 305 needsMoreStackNonSplit = false; 306 307 // We need 64K pages (at least under glibc/Linux, the loader won't 308 // set different permissions on a finer granularity than that). 309 defaultMaxPageSize = 65536; 310 311 // The PPC64 ELF ABI v1 spec, says: 312 // 313 // It is normally desirable to put segments with different characteristics 314 // in separate 256 Mbyte portions of the address space, to give the 315 // operating system full paging flexibility in the 64-bit address space. 316 // 317 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 318 // use 0x10000000 as the starting address. 319 defaultImageBase = 0x10000000; 320 321 write32(trapInstr.data(), 0x7fe00008); 322 } 323 324 int PPC64::getTlsGdRelaxSkip(RelType type) const { 325 // A __tls_get_addr call instruction is marked with 2 relocations: 326 // 327 // R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation 328 // R_PPC64_REL24: __tls_get_addr 329 // 330 // After the relaxation we no longer call __tls_get_addr and should skip both 331 // relocations to not create a false dependence on __tls_get_addr being 332 // defined. 333 if (type == R_PPC64_TLSGD || type == R_PPC64_TLSLD) 334 return 2; 335 return 1; 336 } 337 338 static uint32_t getEFlags(InputFile *file) { 339 if (config->ekind == ELF64BEKind) 340 return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader()->e_flags; 341 return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader()->e_flags; 342 } 343 344 // This file implements v2 ABI. This function makes sure that all 345 // object files have v2 or an unspecified version as an ABI version. 346 uint32_t PPC64::calcEFlags() const { 347 for (InputFile *f : objectFiles) { 348 uint32_t flag = getEFlags(f); 349 if (flag == 1) 350 error(toString(f) + ": ABI version 1 is not supported"); 351 else if (flag > 2) 352 error(toString(f) + ": unrecognized e_flags: " + Twine(flag)); 353 } 354 return 2; 355 } 356 357 void PPC64::relaxGot(uint8_t *loc, RelType type, uint64_t val) const { 358 switch (type) { 359 case R_PPC64_TOC16_HA: 360 // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop". 361 relocateOne(loc, type, val); 362 break; 363 case R_PPC64_TOC16_LO_DS: { 364 // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or 365 // "addi reg, 2, var@toc". 366 uint32_t insn = readFromHalf16(loc); 367 if (getPrimaryOpCode(insn) != LD) 368 error("expected a 'ld' for got-indirect to toc-relative relaxing"); 369 writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000); 370 relocateOne(loc, R_PPC64_TOC16_LO, val); 371 break; 372 } 373 default: 374 llvm_unreachable("unexpected relocation type"); 375 } 376 } 377 378 void PPC64::relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const { 379 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement. 380 // The general dynamic code sequence for a global `x` will look like: 381 // Instruction Relocation Symbol 382 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 383 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 384 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 385 // R_PPC64_REL24 __tls_get_addr 386 // nop None None 387 388 // Relaxing to local exec entails converting: 389 // addis r3, r2, x@got@tlsgd@ha into nop 390 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha 391 // bl __tls_get_addr(x@tlsgd) into nop 392 // nop into addi r3, r3, x@tprel@l 393 394 switch (type) { 395 case R_PPC64_GOT_TLSGD16_HA: 396 writeFromHalf16(loc, 0x60000000); // nop 397 break; 398 case R_PPC64_GOT_TLSGD16: 399 case R_PPC64_GOT_TLSGD16_LO: 400 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13 401 relocateOne(loc, R_PPC64_TPREL16_HA, val); 402 break; 403 case R_PPC64_TLSGD: 404 write32(loc, 0x60000000); // nop 405 write32(loc + 4, 0x38630000); // addi r3, r3 406 // Since we are relocating a half16 type relocation and Loc + 4 points to 407 // the start of an instruction we need to advance the buffer by an extra 408 // 2 bytes on BE. 409 relocateOne(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0), 410 R_PPC64_TPREL16_LO, val); 411 break; 412 default: 413 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 414 } 415 } 416 417 void PPC64::relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const { 418 // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement. 419 // The local dynamic code sequence for a global `x` will look like: 420 // Instruction Relocation Symbol 421 // addis r3, r2, x@got@tlsld@ha R_PPC64_GOT_TLSLD16_HA x 422 // addi r3, r3, x@got@tlsld@l R_PPC64_GOT_TLSLD16_LO x 423 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSLD x 424 // R_PPC64_REL24 __tls_get_addr 425 // nop None None 426 427 // Relaxing to local exec entails converting: 428 // addis r3, r2, x@got@tlsld@ha into nop 429 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0 430 // bl __tls_get_addr(x@tlsgd) into nop 431 // nop into addi r3, r3, 4096 432 433 switch (type) { 434 case R_PPC64_GOT_TLSLD16_HA: 435 writeFromHalf16(loc, 0x60000000); // nop 436 break; 437 case R_PPC64_GOT_TLSLD16_LO: 438 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0 439 break; 440 case R_PPC64_TLSLD: 441 write32(loc, 0x60000000); // nop 442 write32(loc + 4, 0x38631000); // addi r3, r3, 4096 443 break; 444 case R_PPC64_DTPREL16: 445 case R_PPC64_DTPREL16_HA: 446 case R_PPC64_DTPREL16_HI: 447 case R_PPC64_DTPREL16_DS: 448 case R_PPC64_DTPREL16_LO: 449 case R_PPC64_DTPREL16_LO_DS: 450 relocateOne(loc, type, val); 451 break; 452 default: 453 llvm_unreachable("unsupported relocation for TLS LD to LE relaxation"); 454 } 455 } 456 457 unsigned elf::getPPCDFormOp(unsigned secondaryOp) { 458 switch (secondaryOp) { 459 case LBZX: 460 return LBZ; 461 case LHZX: 462 return LHZ; 463 case LWZX: 464 return LWZ; 465 case LDX: 466 return LD; 467 case STBX: 468 return STB; 469 case STHX: 470 return STH; 471 case STWX: 472 return STW; 473 case STDX: 474 return STD; 475 case ADD: 476 return ADDI; 477 default: 478 return 0; 479 } 480 } 481 482 void PPC64::relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const { 483 // The initial exec code sequence for a global `x` will look like: 484 // Instruction Relocation Symbol 485 // addis r9, r2, x@got@tprel@ha R_PPC64_GOT_TPREL16_HA x 486 // ld r9, x@got@tprel@l(r9) R_PPC64_GOT_TPREL16_LO_DS x 487 // add r9, r9, x@tls R_PPC64_TLS x 488 489 // Relaxing to local exec entails converting: 490 // addis r9, r2, x@got@tprel@ha into nop 491 // ld r9, x@got@tprel@l(r9) into addis r9, r13, x@tprel@ha 492 // add r9, r9, x@tls into addi r9, r9, x@tprel@l 493 494 // x@tls R_PPC64_TLS is a relocation which does not compute anything, 495 // it is replaced with r13 (thread pointer). 496 497 // The add instruction in the initial exec sequence has multiple variations 498 // that need to be handled. If we are building an address it will use an add 499 // instruction, if we are accessing memory it will use any of the X-form 500 // indexed load or store instructions. 501 502 unsigned offset = (config->ekind == ELF64BEKind) ? 2 : 0; 503 switch (type) { 504 case R_PPC64_GOT_TPREL16_HA: 505 write32(loc - offset, 0x60000000); // nop 506 break; 507 case R_PPC64_GOT_TPREL16_LO_DS: 508 case R_PPC64_GOT_TPREL16_DS: { 509 uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10 510 write32(loc - offset, 0x3C0D0000 | regNo); // addis RegNo, r13 511 relocateOne(loc, R_PPC64_TPREL16_HA, val); 512 break; 513 } 514 case R_PPC64_TLS: { 515 uint32_t primaryOp = getPrimaryOpCode(read32(loc)); 516 if (primaryOp != 31) 517 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 518 uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30 519 uint32_t dFormOp = getPPCDFormOp(secondaryOp); 520 if (dFormOp == 0) 521 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 522 write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF))); 523 relocateOne(loc + offset, R_PPC64_TPREL16_LO, val); 524 break; 525 } 526 default: 527 llvm_unreachable("unknown relocation for IE to LE"); 528 break; 529 } 530 } 531 532 RelExpr PPC64::getRelExpr(RelType type, const Symbol &s, 533 const uint8_t *loc) const { 534 switch (type) { 535 case R_PPC64_NONE: 536 return R_NONE; 537 case R_PPC64_ADDR16: 538 case R_PPC64_ADDR16_DS: 539 case R_PPC64_ADDR16_HA: 540 case R_PPC64_ADDR16_HI: 541 case R_PPC64_ADDR16_HIGHER: 542 case R_PPC64_ADDR16_HIGHERA: 543 case R_PPC64_ADDR16_HIGHEST: 544 case R_PPC64_ADDR16_HIGHESTA: 545 case R_PPC64_ADDR16_LO: 546 case R_PPC64_ADDR16_LO_DS: 547 case R_PPC64_ADDR32: 548 case R_PPC64_ADDR64: 549 return R_ABS; 550 case R_PPC64_GOT16: 551 case R_PPC64_GOT16_DS: 552 case R_PPC64_GOT16_HA: 553 case R_PPC64_GOT16_HI: 554 case R_PPC64_GOT16_LO: 555 case R_PPC64_GOT16_LO_DS: 556 return R_GOT_OFF; 557 case R_PPC64_TOC16: 558 case R_PPC64_TOC16_DS: 559 case R_PPC64_TOC16_HI: 560 case R_PPC64_TOC16_LO: 561 return R_GOTREL; 562 case R_PPC64_TOC16_HA: 563 case R_PPC64_TOC16_LO_DS: 564 return config->tocOptimize ? R_PPC64_RELAX_TOC : R_GOTREL; 565 case R_PPC64_TOC: 566 return R_PPC64_TOCBASE; 567 case R_PPC64_REL14: 568 case R_PPC64_REL24: 569 return R_PPC64_CALL_PLT; 570 case R_PPC64_REL16_LO: 571 case R_PPC64_REL16_HA: 572 case R_PPC64_REL16_HI: 573 case R_PPC64_REL32: 574 case R_PPC64_REL64: 575 return R_PC; 576 case R_PPC64_GOT_TLSGD16: 577 case R_PPC64_GOT_TLSGD16_HA: 578 case R_PPC64_GOT_TLSGD16_HI: 579 case R_PPC64_GOT_TLSGD16_LO: 580 return R_TLSGD_GOT; 581 case R_PPC64_GOT_TLSLD16: 582 case R_PPC64_GOT_TLSLD16_HA: 583 case R_PPC64_GOT_TLSLD16_HI: 584 case R_PPC64_GOT_TLSLD16_LO: 585 return R_TLSLD_GOT; 586 case R_PPC64_GOT_TPREL16_HA: 587 case R_PPC64_GOT_TPREL16_LO_DS: 588 case R_PPC64_GOT_TPREL16_DS: 589 case R_PPC64_GOT_TPREL16_HI: 590 return R_GOT_OFF; 591 case R_PPC64_GOT_DTPREL16_HA: 592 case R_PPC64_GOT_DTPREL16_LO_DS: 593 case R_PPC64_GOT_DTPREL16_DS: 594 case R_PPC64_GOT_DTPREL16_HI: 595 return R_TLSLD_GOT_OFF; 596 case R_PPC64_TPREL16: 597 case R_PPC64_TPREL16_HA: 598 case R_PPC64_TPREL16_LO: 599 case R_PPC64_TPREL16_HI: 600 case R_PPC64_TPREL16_DS: 601 case R_PPC64_TPREL16_LO_DS: 602 case R_PPC64_TPREL16_HIGHER: 603 case R_PPC64_TPREL16_HIGHERA: 604 case R_PPC64_TPREL16_HIGHEST: 605 case R_PPC64_TPREL16_HIGHESTA: 606 return R_TLS; 607 case R_PPC64_DTPREL16: 608 case R_PPC64_DTPREL16_DS: 609 case R_PPC64_DTPREL16_HA: 610 case R_PPC64_DTPREL16_HI: 611 case R_PPC64_DTPREL16_HIGHER: 612 case R_PPC64_DTPREL16_HIGHERA: 613 case R_PPC64_DTPREL16_HIGHEST: 614 case R_PPC64_DTPREL16_HIGHESTA: 615 case R_PPC64_DTPREL16_LO: 616 case R_PPC64_DTPREL16_LO_DS: 617 case R_PPC64_DTPREL64: 618 return R_DTPREL; 619 case R_PPC64_TLSGD: 620 return R_TLSDESC_CALL; 621 case R_PPC64_TLSLD: 622 return R_TLSLD_HINT; 623 case R_PPC64_TLS: 624 return R_TLSIE_HINT; 625 default: 626 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 627 ") against symbol " + toString(s)); 628 return R_NONE; 629 } 630 } 631 632 RelType PPC64::getDynRel(RelType type) const { 633 if (type == R_PPC64_ADDR64 || type == R_PPC64_TOC) 634 return R_PPC64_ADDR64; 635 return R_PPC64_NONE; 636 } 637 638 void PPC64::writeGotHeader(uint8_t *buf) const { 639 write64(buf, getPPC64TocBase()); 640 } 641 642 void PPC64::writePltHeader(uint8_t *buf) const { 643 // The generic resolver stub goes first. 644 write32(buf + 0, 0x7c0802a6); // mflr r0 645 write32(buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8> 646 write32(buf + 8, 0x7d6802a6); // mflr r11 647 write32(buf + 12, 0x7c0803a6); // mtlr r0 648 write32(buf + 16, 0x7d8b6050); // subf r12, r11, r12 649 write32(buf + 20, 0x380cffcc); // subi r0,r12,52 650 write32(buf + 24, 0x7800f082); // srdi r0,r0,62,2 651 write32(buf + 28, 0xe98b002c); // ld r12,44(r11) 652 write32(buf + 32, 0x7d6c5a14); // add r11,r12,r11 653 write32(buf + 36, 0xe98b0000); // ld r12,0(r11) 654 write32(buf + 40, 0xe96b0008); // ld r11,8(r11) 655 write32(buf + 44, 0x7d8903a6); // mtctr r12 656 write32(buf + 48, 0x4e800420); // bctr 657 658 // The 'bcl' instruction will set the link register to the address of the 659 // following instruction ('mflr r11'). Here we store the offset from that 660 // instruction to the first entry in the GotPlt section. 661 int64_t gotPltOffset = in.gotPlt->getVA() - (in.plt->getVA() + 8); 662 write64(buf + 52, gotPltOffset); 663 } 664 665 void PPC64::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 666 uint64_t pltEntryAddr, int32_t index, 667 unsigned relOff) const { 668 int32_t offset = pltHeaderSize + index * pltEntrySize; 669 // bl __glink_PLTresolve 670 write32(buf, 0x48000000 | ((-offset) & 0x03FFFFFc)); 671 } 672 673 static std::pair<RelType, uint64_t> toAddr16Rel(RelType type, uint64_t val) { 674 // Relocations relative to the toc-base need to be adjusted by the Toc offset. 675 uint64_t tocBiasedVal = val - ppc64TocOffset; 676 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset. 677 uint64_t dtpBiasedVal = val - dynamicThreadPointerOffset; 678 679 switch (type) { 680 // TOC biased relocation. 681 case R_PPC64_GOT16: 682 case R_PPC64_GOT_TLSGD16: 683 case R_PPC64_GOT_TLSLD16: 684 case R_PPC64_TOC16: 685 return {R_PPC64_ADDR16, tocBiasedVal}; 686 case R_PPC64_GOT16_DS: 687 case R_PPC64_TOC16_DS: 688 case R_PPC64_GOT_TPREL16_DS: 689 case R_PPC64_GOT_DTPREL16_DS: 690 return {R_PPC64_ADDR16_DS, tocBiasedVal}; 691 case R_PPC64_GOT16_HA: 692 case R_PPC64_GOT_TLSGD16_HA: 693 case R_PPC64_GOT_TLSLD16_HA: 694 case R_PPC64_GOT_TPREL16_HA: 695 case R_PPC64_GOT_DTPREL16_HA: 696 case R_PPC64_TOC16_HA: 697 return {R_PPC64_ADDR16_HA, tocBiasedVal}; 698 case R_PPC64_GOT16_HI: 699 case R_PPC64_GOT_TLSGD16_HI: 700 case R_PPC64_GOT_TLSLD16_HI: 701 case R_PPC64_GOT_TPREL16_HI: 702 case R_PPC64_GOT_DTPREL16_HI: 703 case R_PPC64_TOC16_HI: 704 return {R_PPC64_ADDR16_HI, tocBiasedVal}; 705 case R_PPC64_GOT16_LO: 706 case R_PPC64_GOT_TLSGD16_LO: 707 case R_PPC64_GOT_TLSLD16_LO: 708 case R_PPC64_TOC16_LO: 709 return {R_PPC64_ADDR16_LO, tocBiasedVal}; 710 case R_PPC64_GOT16_LO_DS: 711 case R_PPC64_TOC16_LO_DS: 712 case R_PPC64_GOT_TPREL16_LO_DS: 713 case R_PPC64_GOT_DTPREL16_LO_DS: 714 return {R_PPC64_ADDR16_LO_DS, tocBiasedVal}; 715 716 // Dynamic Thread pointer biased relocation types. 717 case R_PPC64_DTPREL16: 718 return {R_PPC64_ADDR16, dtpBiasedVal}; 719 case R_PPC64_DTPREL16_DS: 720 return {R_PPC64_ADDR16_DS, dtpBiasedVal}; 721 case R_PPC64_DTPREL16_HA: 722 return {R_PPC64_ADDR16_HA, dtpBiasedVal}; 723 case R_PPC64_DTPREL16_HI: 724 return {R_PPC64_ADDR16_HI, dtpBiasedVal}; 725 case R_PPC64_DTPREL16_HIGHER: 726 return {R_PPC64_ADDR16_HIGHER, dtpBiasedVal}; 727 case R_PPC64_DTPREL16_HIGHERA: 728 return {R_PPC64_ADDR16_HIGHERA, dtpBiasedVal}; 729 case R_PPC64_DTPREL16_HIGHEST: 730 return {R_PPC64_ADDR16_HIGHEST, dtpBiasedVal}; 731 case R_PPC64_DTPREL16_HIGHESTA: 732 return {R_PPC64_ADDR16_HIGHESTA, dtpBiasedVal}; 733 case R_PPC64_DTPREL16_LO: 734 return {R_PPC64_ADDR16_LO, dtpBiasedVal}; 735 case R_PPC64_DTPREL16_LO_DS: 736 return {R_PPC64_ADDR16_LO_DS, dtpBiasedVal}; 737 case R_PPC64_DTPREL64: 738 return {R_PPC64_ADDR64, dtpBiasedVal}; 739 740 default: 741 return {type, val}; 742 } 743 } 744 745 static bool isTocOptType(RelType type) { 746 switch (type) { 747 case R_PPC64_GOT16_HA: 748 case R_PPC64_GOT16_LO_DS: 749 case R_PPC64_TOC16_HA: 750 case R_PPC64_TOC16_LO_DS: 751 case R_PPC64_TOC16_LO: 752 return true; 753 default: 754 return false; 755 } 756 } 757 758 void PPC64::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 759 // We need to save the original relocation type to use in diagnostics, and 760 // use the original type to determine if we should toc-optimize the 761 // instructions being relocated. 762 RelType originalType = type; 763 bool shouldTocOptimize = isTocOptType(type); 764 // For dynamic thread pointer relative, toc-relative, and got-indirect 765 // relocations, proceed in terms of the corresponding ADDR16 relocation type. 766 std::tie(type, val) = toAddr16Rel(type, val); 767 768 switch (type) { 769 case R_PPC64_ADDR14: { 770 checkAlignment(loc, val, 4, type); 771 // Preserve the AA/LK bits in the branch instruction 772 uint8_t aalk = loc[3]; 773 write16(loc + 2, (aalk & 3) | (val & 0xfffc)); 774 break; 775 } 776 case R_PPC64_ADDR16: 777 checkIntUInt(loc, val, 16, originalType); 778 write16(loc, val); 779 break; 780 case R_PPC64_ADDR32: 781 checkIntUInt(loc, val, 32, originalType); 782 write32(loc, val); 783 break; 784 case R_PPC64_ADDR16_DS: 785 case R_PPC64_TPREL16_DS: { 786 checkInt(loc, val, 16, originalType); 787 // DQ-form instructions use bits 28-31 as part of the instruction encoding 788 // DS-form instructions only use bits 30-31. 789 uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 0xf : 0x3; 790 checkAlignment(loc, lo(val), mask + 1, originalType); 791 write16(loc, (read16(loc) & mask) | lo(val)); 792 } break; 793 case R_PPC64_ADDR16_HA: 794 case R_PPC64_REL16_HA: 795 case R_PPC64_TPREL16_HA: 796 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) 797 writeFromHalf16(loc, 0x60000000); 798 else 799 write16(loc, ha(val)); 800 break; 801 case R_PPC64_ADDR16_HI: 802 case R_PPC64_REL16_HI: 803 case R_PPC64_TPREL16_HI: 804 write16(loc, hi(val)); 805 break; 806 case R_PPC64_ADDR16_HIGHER: 807 case R_PPC64_TPREL16_HIGHER: 808 write16(loc, higher(val)); 809 break; 810 case R_PPC64_ADDR16_HIGHERA: 811 case R_PPC64_TPREL16_HIGHERA: 812 write16(loc, highera(val)); 813 break; 814 case R_PPC64_ADDR16_HIGHEST: 815 case R_PPC64_TPREL16_HIGHEST: 816 write16(loc, highest(val)); 817 break; 818 case R_PPC64_ADDR16_HIGHESTA: 819 case R_PPC64_TPREL16_HIGHESTA: 820 write16(loc, highesta(val)); 821 break; 822 case R_PPC64_ADDR16_LO: 823 case R_PPC64_REL16_LO: 824 case R_PPC64_TPREL16_LO: 825 // When the high-adjusted part of a toc relocation evalutes to 0, it is 826 // changed into a nop. The lo part then needs to be updated to use the 827 // toc-pointer register r2, as the base register. 828 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) { 829 uint32_t insn = readFromHalf16(loc); 830 if (isInstructionUpdateForm(insn)) 831 error(getErrorLocation(loc) + 832 "can't toc-optimize an update instruction: 0x" + 833 utohexstr(insn)); 834 writeFromHalf16(loc, (insn & 0xffe00000) | 0x00020000 | lo(val)); 835 } else { 836 write16(loc, lo(val)); 837 } 838 break; 839 case R_PPC64_ADDR16_LO_DS: 840 case R_PPC64_TPREL16_LO_DS: { 841 // DQ-form instructions use bits 28-31 as part of the instruction encoding 842 // DS-form instructions only use bits 30-31. 843 uint32_t insn = readFromHalf16(loc); 844 uint16_t mask = isDQFormInstruction(insn) ? 0xf : 0x3; 845 checkAlignment(loc, lo(val), mask + 1, originalType); 846 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) { 847 // When the high-adjusted part of a toc relocation evalutes to 0, it is 848 // changed into a nop. The lo part then needs to be updated to use the toc 849 // pointer register r2, as the base register. 850 if (isInstructionUpdateForm(insn)) 851 error(getErrorLocation(loc) + 852 "Can't toc-optimize an update instruction: 0x" + 853 Twine::utohexstr(insn)); 854 insn &= 0xffe00000 | mask; 855 writeFromHalf16(loc, insn | 0x00020000 | lo(val)); 856 } else { 857 write16(loc, (read16(loc) & mask) | lo(val)); 858 } 859 } break; 860 case R_PPC64_TPREL16: 861 checkInt(loc, val, 16, originalType); 862 write16(loc, val); 863 break; 864 case R_PPC64_REL32: 865 checkInt(loc, val, 32, type); 866 write32(loc, val); 867 break; 868 case R_PPC64_ADDR64: 869 case R_PPC64_REL64: 870 case R_PPC64_TOC: 871 write64(loc, val); 872 break; 873 case R_PPC64_REL14: { 874 uint32_t mask = 0x0000FFFC; 875 checkInt(loc, val, 16, type); 876 checkAlignment(loc, val, 4, type); 877 write32(loc, (read32(loc) & ~mask) | (val & mask)); 878 break; 879 } 880 case R_PPC64_REL24: { 881 uint32_t mask = 0x03FFFFFC; 882 checkInt(loc, val, 26, type); 883 checkAlignment(loc, val, 4, type); 884 write32(loc, (read32(loc) & ~mask) | (val & mask)); 885 break; 886 } 887 case R_PPC64_DTPREL64: 888 write64(loc, val - dynamicThreadPointerOffset); 889 break; 890 default: 891 llvm_unreachable("unknown relocation"); 892 } 893 } 894 895 bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file, 896 uint64_t branchAddr, const Symbol &s) const { 897 if (type != R_PPC64_REL14 && type != R_PPC64_REL24) 898 return false; 899 900 // If a function is in the Plt it needs to be called with a call-stub. 901 if (s.isInPlt()) 902 return true; 903 904 // If a symbol is a weak undefined and we are compiling an executable 905 // it doesn't need a range-extending thunk since it can't be called. 906 if (s.isUndefWeak() && !config->shared) 907 return false; 908 909 // If the offset exceeds the range of the branch type then it will need 910 // a range-extending thunk. 911 // See the comment in getRelocTargetVA() about R_PPC64_CALL. 912 return !inBranchRange(type, branchAddr, 913 s.getVA() + 914 getPPC64GlobalEntryToLocalEntryOffset(s.stOther)); 915 } 916 917 uint32_t PPC64::getThunkSectionSpacing() const { 918 // See comment in Arch/ARM.cpp for a more detailed explanation of 919 // getThunkSectionSpacing(). For PPC64 we pick the constant here based on 920 // R_PPC64_REL24, which is used by unconditional branch instructions. 921 // 0x2000000 = (1 << 24-1) * 4 922 return 0x2000000; 923 } 924 925 bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { 926 int64_t offset = dst - src; 927 if (type == R_PPC64_REL14) 928 return isInt<16>(offset); 929 if (type == R_PPC64_REL24) 930 return isInt<26>(offset); 931 llvm_unreachable("unsupported relocation type used in branch"); 932 } 933 934 RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data, 935 RelExpr expr) const { 936 if (expr == R_RELAX_TLS_GD_TO_IE) 937 return R_RELAX_TLS_GD_TO_IE_GOT_OFF; 938 if (expr == R_RELAX_TLS_LD_TO_LE) 939 return R_RELAX_TLS_LD_TO_LE_ABS; 940 return expr; 941 } 942 943 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement. 944 // The general dynamic code sequence for a global `x` uses 4 instructions. 945 // Instruction Relocation Symbol 946 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 947 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 948 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 949 // R_PPC64_REL24 __tls_get_addr 950 // nop None None 951 // 952 // Relaxing to initial-exec entails: 953 // 1) Convert the addis/addi pair that builds the address of the tls_index 954 // struct for 'x' to an addis/ld pair that loads an offset from a got-entry. 955 // 2) Convert the call to __tls_get_addr to a nop. 956 // 3) Convert the nop following the call to an add of the loaded offset to the 957 // thread pointer. 958 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is 959 // used as the relaxation hint for both steps 2 and 3. 960 void PPC64::relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const { 961 switch (type) { 962 case R_PPC64_GOT_TLSGD16_HA: 963 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to 964 // addis rT, r2, sym@got@tprel@ha. 965 relocateOne(loc, R_PPC64_GOT_TPREL16_HA, val); 966 return; 967 case R_PPC64_GOT_TLSGD16: 968 case R_PPC64_GOT_TLSGD16_LO: { 969 // Relax from addi r3, rA, sym@got@tlsgd@l to 970 // ld r3, sym@got@tprel@l(rA) 971 uint32_t ra = (readFromHalf16(loc) & (0x1f << 16)); 972 writeFromHalf16(loc, 0xe8600000 | ra); 973 relocateOne(loc, R_PPC64_GOT_TPREL16_LO_DS, val); 974 return; 975 } 976 case R_PPC64_TLSGD: 977 write32(loc, 0x60000000); // bl __tls_get_addr(sym@tlsgd) --> nop 978 write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13 979 return; 980 default: 981 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation"); 982 } 983 } 984 985 // The prologue for a split-stack function is expected to look roughly 986 // like this: 987 // .Lglobal_entry_point: 988 // # TOC pointer initalization. 989 // ... 990 // .Llocal_entry_point: 991 // # load the __private_ss member of the threads tcbhead. 992 // ld r0,-0x7000-64(r13) 993 // # subtract the functions stack size from the stack pointer. 994 // addis r12, r1, ha(-stack-frame size) 995 // addi r12, r12, l(-stack-frame size) 996 // # compare needed to actual and branch to allocate_more_stack if more 997 // # space is needed, otherwise fallthrough to 'normal' function body. 998 // cmpld cr7,r12,r0 999 // blt- cr7, .Lallocate_more_stack 1000 // 1001 // -) The allocate_more_stack block might be placed after the split-stack 1002 // prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body` 1003 // instead. 1004 // -) If either the addis or addi is not needed due to the stack size being 1005 // smaller then 32K or a multiple of 64K they will be replaced with a nop, 1006 // but there will always be 2 instructions the linker can overwrite for the 1007 // adjusted stack size. 1008 // 1009 // The linkers job here is to increase the stack size used in the addis/addi 1010 // pair by split-stack-size-adjust. 1011 // addis r12, r1, ha(-stack-frame size - split-stack-adjust-size) 1012 // addi r12, r12, l(-stack-frame size - split-stack-adjust-size) 1013 bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end, 1014 uint8_t stOther) const { 1015 // If the caller has a global entry point adjust the buffer past it. The start 1016 // of the split-stack prologue will be at the local entry point. 1017 loc += getPPC64GlobalEntryToLocalEntryOffset(stOther); 1018 1019 // At the very least we expect to see a load of some split-stack data from the 1020 // tcb, and 2 instructions that calculate the ending stack address this 1021 // function will require. If there is not enough room for at least 3 1022 // instructions it can't be a split-stack prologue. 1023 if (loc + 12 >= end) 1024 return false; 1025 1026 // First instruction must be `ld r0, -0x7000-64(r13)` 1027 if (read32(loc) != 0xe80d8fc0) 1028 return false; 1029 1030 int16_t hiImm = 0; 1031 int16_t loImm = 0; 1032 // First instruction can be either an addis if the frame size is larger then 1033 // 32K, or an addi if the size is less then 32K. 1034 int32_t firstInstr = read32(loc + 4); 1035 if (getPrimaryOpCode(firstInstr) == 15) { 1036 hiImm = firstInstr & 0xFFFF; 1037 } else if (getPrimaryOpCode(firstInstr) == 14) { 1038 loImm = firstInstr & 0xFFFF; 1039 } else { 1040 return false; 1041 } 1042 1043 // Second instruction is either an addi or a nop. If the first instruction was 1044 // an addi then LoImm is set and the second instruction must be a nop. 1045 uint32_t secondInstr = read32(loc + 8); 1046 if (!loImm && getPrimaryOpCode(secondInstr) == 14) { 1047 loImm = secondInstr & 0xFFFF; 1048 } else if (secondInstr != 0x60000000) { 1049 return false; 1050 } 1051 1052 // The register operands of the first instruction should be the stack-pointer 1053 // (r1) as the input (RA) and r12 as the output (RT). If the second 1054 // instruction is not a nop, then it should use r12 as both input and output. 1055 auto checkRegOperands = [](uint32_t instr, uint8_t expectedRT, 1056 uint8_t expectedRA) { 1057 return ((instr & 0x3E00000) >> 21 == expectedRT) && 1058 ((instr & 0x1F0000) >> 16 == expectedRA); 1059 }; 1060 if (!checkRegOperands(firstInstr, 12, 1)) 1061 return false; 1062 if (secondInstr != 0x60000000 && !checkRegOperands(secondInstr, 12, 12)) 1063 return false; 1064 1065 int32_t stackFrameSize = (hiImm * 65536) + loImm; 1066 // Check that the adjusted size doesn't overflow what we can represent with 2 1067 // instructions. 1068 if (stackFrameSize < config->splitStackAdjustSize + INT32_MIN) { 1069 error(getErrorLocation(loc) + "split-stack prologue adjustment overflows"); 1070 return false; 1071 } 1072 1073 int32_t adjustedStackFrameSize = 1074 stackFrameSize - config->splitStackAdjustSize; 1075 1076 loImm = adjustedStackFrameSize & 0xFFFF; 1077 hiImm = (adjustedStackFrameSize + 0x8000) >> 16; 1078 if (hiImm) { 1079 write32(loc + 4, 0x3D810000 | (uint16_t)hiImm); 1080 // If the low immediate is zero the second instruction will be a nop. 1081 secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : 0x60000000; 1082 write32(loc + 8, secondInstr); 1083 } else { 1084 // addi r12, r1, imm 1085 write32(loc + 4, (0x39810000) | (uint16_t)loImm); 1086 write32(loc + 8, 0x60000000); 1087 } 1088 1089 return true; 1090 } 1091 1092 TargetInfo *elf::getPPC64TargetInfo() { 1093 static PPC64 target; 1094 return ⌖ 1095 } 1096