1 //===- PPC64.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "SymbolTable.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/CommonLinkerContext.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 using namespace llvm::object; 20 using namespace llvm::support::endian; 21 using namespace llvm::ELF; 22 using namespace lld; 23 using namespace lld::elf; 24 25 constexpr uint64_t ppc64TocOffset = 0x8000; 26 constexpr uint64_t dynamicThreadPointerOffset = 0x8000; 27 28 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform 29 // instructions that can be used as part of the initial exec TLS sequence. 30 enum XFormOpcd { 31 LBZX = 87, 32 LHZX = 279, 33 LWZX = 23, 34 LDX = 21, 35 STBX = 215, 36 STHX = 407, 37 STWX = 151, 38 STDX = 149, 39 ADD = 266, 40 }; 41 42 enum DFormOpcd { 43 LBZ = 34, 44 LBZU = 35, 45 LHZ = 40, 46 LHZU = 41, 47 LHAU = 43, 48 LWZ = 32, 49 LWZU = 33, 50 LFSU = 49, 51 LD = 58, 52 LFDU = 51, 53 STB = 38, 54 STBU = 39, 55 STH = 44, 56 STHU = 45, 57 STW = 36, 58 STWU = 37, 59 STFSU = 53, 60 STFDU = 55, 61 STD = 62, 62 ADDI = 14 63 }; 64 65 constexpr uint32_t NOP = 0x60000000; 66 67 enum class PPCLegacyInsn : uint32_t { 68 NOINSN = 0, 69 // Loads. 70 LBZ = 0x88000000, 71 LHZ = 0xa0000000, 72 LWZ = 0x80000000, 73 LHA = 0xa8000000, 74 LWA = 0xe8000002, 75 LD = 0xe8000000, 76 LFS = 0xC0000000, 77 LXSSP = 0xe4000003, 78 LFD = 0xc8000000, 79 LXSD = 0xe4000002, 80 LXV = 0xf4000001, 81 LXVP = 0x18000000, 82 83 // Stores. 84 STB = 0x98000000, 85 STH = 0xb0000000, 86 STW = 0x90000000, 87 STD = 0xf8000000, 88 STFS = 0xd0000000, 89 STXSSP = 0xf4000003, 90 STFD = 0xd8000000, 91 STXSD = 0xf4000002, 92 STXV = 0xf4000005, 93 STXVP = 0x18000001 94 }; 95 enum class PPCPrefixedInsn : uint64_t { 96 NOINSN = 0, 97 PREFIX_MLS = 0x0610000000000000, 98 PREFIX_8LS = 0x0410000000000000, 99 100 // Loads. 101 PLBZ = PREFIX_MLS, 102 PLHZ = PREFIX_MLS, 103 PLWZ = PREFIX_MLS, 104 PLHA = PREFIX_MLS, 105 PLWA = PREFIX_8LS | 0xa4000000, 106 PLD = PREFIX_8LS | 0xe4000000, 107 PLFS = PREFIX_MLS, 108 PLXSSP = PREFIX_8LS | 0xac000000, 109 PLFD = PREFIX_MLS, 110 PLXSD = PREFIX_8LS | 0xa8000000, 111 PLXV = PREFIX_8LS | 0xc8000000, 112 PLXVP = PREFIX_8LS | 0xe8000000, 113 114 // Stores. 115 PSTB = PREFIX_MLS, 116 PSTH = PREFIX_MLS, 117 PSTW = PREFIX_MLS, 118 PSTD = PREFIX_8LS | 0xf4000000, 119 PSTFS = PREFIX_MLS, 120 PSTXSSP = PREFIX_8LS | 0xbc000000, 121 PSTFD = PREFIX_MLS, 122 PSTXSD = PREFIX_8LS | 0xb8000000, 123 PSTXV = PREFIX_8LS | 0xd8000000, 124 PSTXVP = PREFIX_8LS | 0xf8000000 125 }; 126 static bool checkPPCLegacyInsn(uint32_t encoding) { 127 PPCLegacyInsn insn = static_cast<PPCLegacyInsn>(encoding); 128 if (insn == PPCLegacyInsn::NOINSN) 129 return false; 130 #define PCREL_OPT(Legacy, PCRel, InsnMask) \ 131 if (insn == PPCLegacyInsn::Legacy) \ 132 return true; 133 #include "PPCInsns.def" 134 #undef PCREL_OPT 135 return false; 136 } 137 138 // Masks to apply to legacy instructions when converting them to prefixed, 139 // pc-relative versions. For the most part, the primary opcode is shared 140 // between the legacy instruction and the suffix of its prefixed version. 141 // However, there are some instances where that isn't the case (DS-Form and 142 // DQ-form instructions). 143 enum class LegacyToPrefixMask : uint64_t { 144 NOMASK = 0x0, 145 OPC_AND_RST = 0xffe00000, // Primary opc (0-5) and R[ST] (6-10). 146 ONLY_RST = 0x3e00000, // [RS]T (6-10). 147 ST_STX28_TO5 = 148 0x8000000003e00000, // S/T (6-10) - The [S/T]X bit moves from 28 to 5. 149 }; 150 151 uint64_t elf::getPPC64TocBase() { 152 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 153 // TOC starts where the first of these sections starts. We always create a 154 // .got when we see a relocation that uses it, so for us the start is always 155 // the .got. 156 uint64_t tocVA = in.got->getVA(); 157 158 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 159 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 160 // code (crt1.o) assumes that you can get from the TOC base to the 161 // start of the .toc section with only a single (signed) 16-bit relocation. 162 return tocVA + ppc64TocOffset; 163 } 164 165 unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) { 166 // The offset is encoded into the 3 most significant bits of the st_other 167 // field, with some special values described in section 3.4.1 of the ABI: 168 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use 169 // the TOC pointer (r2). r2 will hold the same value on returning from 170 // the function as it did on entering the function. 171 // 1 --> Zero offset between the GEP and LEP, and r2 should be treated as a 172 // caller-saved register for all callers. 173 // 2-6 --> The binary logarithm of the offset eg: 174 // 2 --> 2^2 = 4 bytes --> 1 instruction. 175 // 6 --> 2^6 = 64 bytes --> 16 instructions. 176 // 7 --> Reserved. 177 uint8_t gepToLep = (stOther >> 5) & 7; 178 if (gepToLep < 2) 179 return 0; 180 181 // The value encoded in the st_other bits is the 182 // log-base-2(offset). 183 if (gepToLep < 7) 184 return 1 << gepToLep; 185 186 error("reserved value of 7 in the 3 most-significant-bits of st_other"); 187 return 0; 188 } 189 190 void elf::writePrefixedInstruction(uint8_t *loc, uint64_t insn) { 191 insn = config->isLE ? insn << 32 | insn >> 32 : insn; 192 write64(loc, insn); 193 } 194 195 static bool addOptional(StringRef name, uint64_t value, 196 std::vector<Defined *> &defined) { 197 Symbol *sym = symtab->find(name); 198 if (!sym || sym->isDefined()) 199 return false; 200 sym->resolve(Defined{/*file=*/nullptr, StringRef(), STB_GLOBAL, STV_HIDDEN, 201 STT_FUNC, value, 202 /*size=*/0, /*section=*/nullptr}); 203 defined.push_back(cast<Defined>(sym)); 204 return true; 205 } 206 207 // If from is 14, write ${prefix}14: firstInsn; ${prefix}15: 208 // firstInsn+0x200008; ...; ${prefix}31: firstInsn+(31-14)*0x200008; $tail 209 // The labels are defined only if they exist in the symbol table. 210 static void writeSequence(MutableArrayRef<uint32_t> buf, const char *prefix, 211 int from, uint32_t firstInsn, 212 ArrayRef<uint32_t> tail) { 213 std::vector<Defined *> defined; 214 char name[16]; 215 int first; 216 uint32_t *ptr = buf.data(); 217 for (int r = from; r < 32; ++r) { 218 format("%s%d", prefix, r).snprint(name, sizeof(name)); 219 if (addOptional(name, 4 * (r - from), defined) && defined.size() == 1) 220 first = r - from; 221 write32(ptr++, firstInsn + 0x200008 * (r - from)); 222 } 223 for (uint32_t insn : tail) 224 write32(ptr++, insn); 225 assert(ptr == &*buf.end()); 226 227 if (defined.empty()) 228 return; 229 // The full section content has the extent of [begin, end). We drop unused 230 // instructions and write [first,end). 231 auto *sec = make<InputSection>( 232 nullptr, SHF_ALLOC, SHT_PROGBITS, 4, 233 makeArrayRef(reinterpret_cast<uint8_t *>(buf.data() + first), 234 4 * (buf.size() - first)), 235 ".text"); 236 inputSections.push_back(sec); 237 for (Defined *sym : defined) { 238 sym->section = sec; 239 sym->value -= 4 * first; 240 } 241 } 242 243 // Implements some save and restore functions as described by ELF V2 ABI to be 244 // compatible with GCC. With GCC -Os, when the number of call-saved registers 245 // exceeds a certain threshold, GCC generates _savegpr0_* _restgpr0_* calls and 246 // expects the linker to define them. See 247 // https://sourceware.org/pipermail/binutils/2002-February/017444.html and 248 // https://sourceware.org/pipermail/binutils/2004-August/036765.html . This is 249 // weird because libgcc.a would be the natural place. The linker generation 250 // approach has the advantage that the linker can generate multiple copies to 251 // avoid long branch thunks. However, we don't consider the advantage 252 // significant enough to complicate our trunk implementation, so we take the 253 // simple approach and synthesize .text sections providing the implementation. 254 void elf::addPPC64SaveRestore() { 255 static uint32_t savegpr0[20], restgpr0[21], savegpr1[19], restgpr1[19]; 256 constexpr uint32_t blr = 0x4e800020, mtlr_0 = 0x7c0803a6; 257 258 // _restgpr0_14: ld 14, -144(1); _restgpr0_15: ld 15, -136(1); ... 259 // Tail: ld 0, 16(1); mtlr 0; blr 260 writeSequence(restgpr0, "_restgpr0_", 14, 0xe9c1ff70, 261 {0xe8010010, mtlr_0, blr}); 262 // _restgpr1_14: ld 14, -144(12); _restgpr1_15: ld 15, -136(12); ... 263 // Tail: blr 264 writeSequence(restgpr1, "_restgpr1_", 14, 0xe9ccff70, {blr}); 265 // _savegpr0_14: std 14, -144(1); _savegpr0_15: std 15, -136(1); ... 266 // Tail: std 0, 16(1); blr 267 writeSequence(savegpr0, "_savegpr0_", 14, 0xf9c1ff70, {0xf8010010, blr}); 268 // _savegpr1_14: std 14, -144(12); _savegpr1_15: std 15, -136(12); ... 269 // Tail: blr 270 writeSequence(savegpr1, "_savegpr1_", 14, 0xf9ccff70, {blr}); 271 } 272 273 // Find the R_PPC64_ADDR64 in .rela.toc with matching offset. 274 template <typename ELFT> 275 static std::pair<Defined *, int64_t> 276 getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) { 277 // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by 278 // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the 279 // relocation index in most cases. 280 // 281 // In rare cases a TOC entry may store a constant that doesn't need an 282 // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8 283 // points to a relocation with larger r_offset. Do a linear probe then. 284 // Constants are extremely uncommon in .toc and the extra number of array 285 // accesses can be seen as a small constant. 286 ArrayRef<typename ELFT::Rela> relas = 287 tocSec->template relsOrRelas<ELFT>().relas; 288 if (relas.empty()) 289 return {}; 290 uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1); 291 for (;;) { 292 if (relas[index].r_offset == offset) { 293 Symbol &sym = tocSec->getFile<ELFT>()->getRelocTargetSym(relas[index]); 294 return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])}; 295 } 296 if (relas[index].r_offset < offset || index == 0) 297 break; 298 --index; 299 } 300 return {}; 301 } 302 303 // When accessing a symbol defined in another translation unit, compilers 304 // reserve a .toc entry, allocate a local label and generate toc-indirect 305 // instructions: 306 // 307 // addis 3, 2, .LC0@toc@ha # R_PPC64_TOC16_HA 308 // ld 3, .LC0@toc@l(3) # R_PPC64_TOC16_LO_DS, load the address from a .toc entry 309 // ld/lwa 3, 0(3) # load the value from the address 310 // 311 // .section .toc,"aw",@progbits 312 // .LC0: .tc var[TC],var 313 // 314 // If var is defined, non-preemptable and addressable with a 32-bit signed 315 // offset from the toc base, the address of var can be computed by adding an 316 // offset to the toc base, saving a load. 317 // 318 // addis 3,2,var@toc@ha # this may be relaxed to a nop, 319 // addi 3,3,var@toc@l # then this becomes addi 3,2,var@toc 320 // ld/lwa 3, 0(3) # load the value from the address 321 // 322 // Returns true if the relaxation is performed. 323 bool elf::tryRelaxPPC64TocIndirection(const Relocation &rel, uint8_t *bufLoc) { 324 assert(config->tocOptimize); 325 if (rel.addend < 0) 326 return false; 327 328 // If the symbol is not the .toc section, this isn't a toc-indirection. 329 Defined *defSym = dyn_cast<Defined>(rel.sym); 330 if (!defSym || !defSym->isSection() || defSym->section->name != ".toc") 331 return false; 332 333 Defined *d; 334 int64_t addend; 335 auto *tocISB = cast<InputSectionBase>(defSym->section); 336 std::tie(d, addend) = 337 config->isLE ? getRelaTocSymAndAddend<ELF64LE>(tocISB, rel.addend) 338 : getRelaTocSymAndAddend<ELF64BE>(tocISB, rel.addend); 339 340 // Only non-preemptable defined symbols can be relaxed. 341 if (!d || d->isPreemptible) 342 return false; 343 344 // R_PPC64_ADDR64 should have created a canonical PLT for the non-preemptable 345 // ifunc and changed its type to STT_FUNC. 346 assert(!d->isGnuIFunc()); 347 348 // Two instructions can materialize a 32-bit signed offset from the toc base. 349 uint64_t tocRelative = d->getVA(addend) - getPPC64TocBase(); 350 if (!isInt<32>(tocRelative)) 351 return false; 352 353 // Add PPC64TocOffset that will be subtracted by PPC64::relocate(). 354 target->relaxGot(bufLoc, rel, tocRelative + ppc64TocOffset); 355 return true; 356 } 357 358 namespace { 359 class PPC64 final : public TargetInfo { 360 public: 361 PPC64(); 362 int getTlsGdRelaxSkip(RelType type) const override; 363 uint32_t calcEFlags() const override; 364 RelExpr getRelExpr(RelType type, const Symbol &s, 365 const uint8_t *loc) const override; 366 RelType getDynRel(RelType type) const override; 367 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 368 void writePltHeader(uint8_t *buf) const override; 369 void writePlt(uint8_t *buf, const Symbol &sym, 370 uint64_t pltEntryAddr) const override; 371 void writeIplt(uint8_t *buf, const Symbol &sym, 372 uint64_t pltEntryAddr) const override; 373 void relocate(uint8_t *loc, const Relocation &rel, 374 uint64_t val) const override; 375 void writeGotHeader(uint8_t *buf) const override; 376 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 377 uint64_t branchAddr, const Symbol &s, 378 int64_t a) const override; 379 uint32_t getThunkSectionSpacing() const override; 380 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override; 381 RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; 382 RelExpr adjustGotPcExpr(RelType type, int64_t addend, 383 const uint8_t *loc) const override; 384 void relaxGot(uint8_t *loc, const Relocation &rel, 385 uint64_t val) const override; 386 void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, 387 uint64_t val) const override; 388 void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, 389 uint64_t val) const override; 390 void relaxTlsLdToLe(uint8_t *loc, const Relocation &rel, 391 uint64_t val) const override; 392 void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, 393 uint64_t val) const override; 394 395 bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end, 396 uint8_t stOther) const override; 397 }; 398 } // namespace 399 400 // Relocation masks following the #lo(value), #hi(value), #ha(value), 401 // #higher(value), #highera(value), #highest(value), and #highesta(value) 402 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 403 // document. 404 static uint16_t lo(uint64_t v) { return v; } 405 static uint16_t hi(uint64_t v) { return v >> 16; } 406 static uint64_t ha(uint64_t v) { return (v + 0x8000) >> 16; } 407 static uint16_t higher(uint64_t v) { return v >> 32; } 408 static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; } 409 static uint16_t highest(uint64_t v) { return v >> 48; } 410 static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; } 411 412 // Extracts the 'PO' field of an instruction encoding. 413 static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); } 414 415 static bool isDQFormInstruction(uint32_t encoding) { 416 switch (getPrimaryOpCode(encoding)) { 417 default: 418 return false; 419 case 6: // Power10 paired loads/stores (lxvp, stxvp). 420 case 56: 421 // The only instruction with a primary opcode of 56 is `lq`. 422 return true; 423 case 61: 424 // There are both DS and DQ instruction forms with this primary opcode. 425 // Namely `lxv` and `stxv` are the DQ-forms that use it. 426 // The DS 'XO' bits being set to 01 is restricted to DQ form. 427 return (encoding & 3) == 0x1; 428 } 429 } 430 431 static bool isDSFormInstruction(PPCLegacyInsn insn) { 432 switch (insn) { 433 default: 434 return false; 435 case PPCLegacyInsn::LWA: 436 case PPCLegacyInsn::LD: 437 case PPCLegacyInsn::LXSD: 438 case PPCLegacyInsn::LXSSP: 439 case PPCLegacyInsn::STD: 440 case PPCLegacyInsn::STXSD: 441 case PPCLegacyInsn::STXSSP: 442 return true; 443 } 444 } 445 446 static PPCLegacyInsn getPPCLegacyInsn(uint32_t encoding) { 447 uint32_t opc = encoding & 0xfc000000; 448 449 // If the primary opcode is shared between multiple instructions, we need to 450 // fix it up to match the actual instruction we are after. 451 if ((opc == 0xe4000000 || opc == 0xe8000000 || opc == 0xf4000000 || 452 opc == 0xf8000000) && 453 !isDQFormInstruction(encoding)) 454 opc = encoding & 0xfc000003; 455 else if (opc == 0xf4000000) 456 opc = encoding & 0xfc000007; 457 else if (opc == 0x18000000) 458 opc = encoding & 0xfc00000f; 459 460 // If the value is not one of the enumerators in PPCLegacyInsn, we want to 461 // return PPCLegacyInsn::NOINSN. 462 if (!checkPPCLegacyInsn(opc)) 463 return PPCLegacyInsn::NOINSN; 464 return static_cast<PPCLegacyInsn>(opc); 465 } 466 467 static PPCPrefixedInsn getPCRelativeForm(PPCLegacyInsn insn) { 468 switch (insn) { 469 #define PCREL_OPT(Legacy, PCRel, InsnMask) \ 470 case PPCLegacyInsn::Legacy: \ 471 return PPCPrefixedInsn::PCRel 472 #include "PPCInsns.def" 473 #undef PCREL_OPT 474 } 475 return PPCPrefixedInsn::NOINSN; 476 } 477 478 static LegacyToPrefixMask getInsnMask(PPCLegacyInsn insn) { 479 switch (insn) { 480 #define PCREL_OPT(Legacy, PCRel, InsnMask) \ 481 case PPCLegacyInsn::Legacy: \ 482 return LegacyToPrefixMask::InsnMask 483 #include "PPCInsns.def" 484 #undef PCREL_OPT 485 } 486 return LegacyToPrefixMask::NOMASK; 487 } 488 static uint64_t getPCRelativeForm(uint32_t encoding) { 489 PPCLegacyInsn origInsn = getPPCLegacyInsn(encoding); 490 PPCPrefixedInsn pcrelInsn = getPCRelativeForm(origInsn); 491 if (pcrelInsn == PPCPrefixedInsn::NOINSN) 492 return UINT64_C(-1); 493 LegacyToPrefixMask origInsnMask = getInsnMask(origInsn); 494 uint64_t pcrelEncoding = 495 (uint64_t)pcrelInsn | (encoding & (uint64_t)origInsnMask); 496 497 // If the mask requires moving bit 28 to bit 5, do that now. 498 if (origInsnMask == LegacyToPrefixMask::ST_STX28_TO5) 499 pcrelEncoding |= (encoding & 0x8) << 23; 500 return pcrelEncoding; 501 } 502 503 static bool isInstructionUpdateForm(uint32_t encoding) { 504 switch (getPrimaryOpCode(encoding)) { 505 default: 506 return false; 507 case LBZU: 508 case LHAU: 509 case LHZU: 510 case LWZU: 511 case LFSU: 512 case LFDU: 513 case STBU: 514 case STHU: 515 case STWU: 516 case STFSU: 517 case STFDU: 518 return true; 519 // LWA has the same opcode as LD, and the DS bits is what differentiates 520 // between LD/LDU/LWA 521 case LD: 522 case STD: 523 return (encoding & 3) == 1; 524 } 525 } 526 527 // Compute the total displacement between the prefixed instruction that gets 528 // to the start of the data and the load/store instruction that has the offset 529 // into the data structure. 530 // For example: 531 // paddi 3, 0, 1000, 1 532 // lwz 3, 20(3) 533 // Should add up to 1020 for total displacement. 534 static int64_t getTotalDisp(uint64_t prefixedInsn, uint32_t accessInsn) { 535 int64_t disp34 = llvm::SignExtend64( 536 ((prefixedInsn & 0x3ffff00000000) >> 16) | (prefixedInsn & 0xffff), 34); 537 int32_t disp16 = llvm::SignExtend32(accessInsn & 0xffff, 16); 538 // For DS and DQ form instructions, we need to mask out the XO bits. 539 if (isDQFormInstruction(accessInsn)) 540 disp16 &= ~0xf; 541 else if (isDSFormInstruction(getPPCLegacyInsn(accessInsn))) 542 disp16 &= ~0x3; 543 return disp34 + disp16; 544 } 545 546 // There are a number of places when we either want to read or write an 547 // instruction when handling a half16 relocation type. On big-endian the buffer 548 // pointer is pointing into the middle of the word we want to extract, and on 549 // little-endian it is pointing to the start of the word. These 2 helpers are to 550 // simplify reading and writing in that context. 551 static void writeFromHalf16(uint8_t *loc, uint32_t insn) { 552 write32(config->isLE ? loc : loc - 2, insn); 553 } 554 555 static uint32_t readFromHalf16(const uint8_t *loc) { 556 return read32(config->isLE ? loc : loc - 2); 557 } 558 559 static uint64_t readPrefixedInstruction(const uint8_t *loc) { 560 uint64_t fullInstr = read64(loc); 561 return config->isLE ? (fullInstr << 32 | fullInstr >> 32) : fullInstr; 562 } 563 564 PPC64::PPC64() { 565 copyRel = R_PPC64_COPY; 566 gotRel = R_PPC64_GLOB_DAT; 567 pltRel = R_PPC64_JMP_SLOT; 568 relativeRel = R_PPC64_RELATIVE; 569 iRelativeRel = R_PPC64_IRELATIVE; 570 symbolicRel = R_PPC64_ADDR64; 571 pltHeaderSize = 60; 572 pltEntrySize = 4; 573 ipltEntrySize = 16; // PPC64PltCallStub::size 574 gotHeaderEntriesNum = 1; 575 gotPltHeaderEntriesNum = 2; 576 needsThunks = true; 577 578 tlsModuleIndexRel = R_PPC64_DTPMOD64; 579 tlsOffsetRel = R_PPC64_DTPREL64; 580 581 tlsGotRel = R_PPC64_TPREL64; 582 583 needsMoreStackNonSplit = false; 584 585 // We need 64K pages (at least under glibc/Linux, the loader won't 586 // set different permissions on a finer granularity than that). 587 defaultMaxPageSize = 65536; 588 589 // The PPC64 ELF ABI v1 spec, says: 590 // 591 // It is normally desirable to put segments with different characteristics 592 // in separate 256 Mbyte portions of the address space, to give the 593 // operating system full paging flexibility in the 64-bit address space. 594 // 595 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 596 // use 0x10000000 as the starting address. 597 defaultImageBase = 0x10000000; 598 599 write32(trapInstr.data(), 0x7fe00008); 600 } 601 602 int PPC64::getTlsGdRelaxSkip(RelType type) const { 603 // A __tls_get_addr call instruction is marked with 2 relocations: 604 // 605 // R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation 606 // R_PPC64_REL24: __tls_get_addr 607 // 608 // After the relaxation we no longer call __tls_get_addr and should skip both 609 // relocations to not create a false dependence on __tls_get_addr being 610 // defined. 611 if (type == R_PPC64_TLSGD || type == R_PPC64_TLSLD) 612 return 2; 613 return 1; 614 } 615 616 static uint32_t getEFlags(InputFile *file) { 617 if (config->ekind == ELF64BEKind) 618 return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader().e_flags; 619 return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader().e_flags; 620 } 621 622 // This file implements v2 ABI. This function makes sure that all 623 // object files have v2 or an unspecified version as an ABI version. 624 uint32_t PPC64::calcEFlags() const { 625 for (InputFile *f : ctx->objectFiles) { 626 uint32_t flag = getEFlags(f); 627 if (flag == 1) 628 error(toString(f) + ": ABI version 1 is not supported"); 629 else if (flag > 2) 630 error(toString(f) + ": unrecognized e_flags: " + Twine(flag)); 631 } 632 return 2; 633 } 634 635 void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const { 636 switch (rel.type) { 637 case R_PPC64_TOC16_HA: 638 // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop". 639 relocate(loc, rel, val); 640 break; 641 case R_PPC64_TOC16_LO_DS: { 642 // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or 643 // "addi reg, 2, var@toc". 644 uint32_t insn = readFromHalf16(loc); 645 if (getPrimaryOpCode(insn) != LD) 646 error("expected a 'ld' for got-indirect to toc-relative relaxing"); 647 writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000); 648 relocateNoSym(loc, R_PPC64_TOC16_LO, val); 649 break; 650 } 651 case R_PPC64_GOT_PCREL34: { 652 // Clear the first 8 bits of the prefix and the first 6 bits of the 653 // instruction (the primary opcode). 654 uint64_t insn = readPrefixedInstruction(loc); 655 if ((insn & 0xfc000000) != 0xe4000000) 656 error("expected a 'pld' for got-indirect to pc-relative relaxing"); 657 insn &= ~0xff000000fc000000; 658 659 // Replace the cleared bits with the values for PADDI (0x600000038000000); 660 insn |= 0x600000038000000; 661 writePrefixedInstruction(loc, insn); 662 relocate(loc, rel, val); 663 break; 664 } 665 case R_PPC64_PCREL_OPT: { 666 // We can only relax this if the R_PPC64_GOT_PCREL34 at this offset can 667 // be relaxed. The eligibility for the relaxation needs to be determined 668 // on that relocation since this one does not relocate a symbol. 669 uint64_t insn = readPrefixedInstruction(loc); 670 uint32_t accessInsn = read32(loc + rel.addend); 671 uint64_t pcRelInsn = getPCRelativeForm(accessInsn); 672 673 // This error is not necessary for correctness but is emitted for now 674 // to ensure we don't miss these opportunities in real code. It can be 675 // removed at a later date. 676 if (pcRelInsn == UINT64_C(-1)) { 677 errorOrWarn( 678 "unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x" + 679 Twine::utohexstr(accessInsn)); 680 break; 681 } 682 683 int64_t totalDisp = getTotalDisp(insn, accessInsn); 684 if (!isInt<34>(totalDisp)) 685 break; // Displacement doesn't fit. 686 // Convert the PADDI to the prefixed version of accessInsn and convert 687 // accessInsn to a nop. 688 writePrefixedInstruction(loc, pcRelInsn | 689 ((totalDisp & 0x3ffff0000) << 16) | 690 (totalDisp & 0xffff)); 691 write32(loc + rel.addend, NOP); // nop accessInsn. 692 break; 693 } 694 default: 695 llvm_unreachable("unexpected relocation type"); 696 } 697 } 698 699 void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, 700 uint64_t val) const { 701 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement. 702 // The general dynamic code sequence for a global `x` will look like: 703 // Instruction Relocation Symbol 704 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 705 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 706 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 707 // R_PPC64_REL24 __tls_get_addr 708 // nop None None 709 710 // Relaxing to local exec entails converting: 711 // addis r3, r2, x@got@tlsgd@ha into nop 712 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha 713 // bl __tls_get_addr(x@tlsgd) into nop 714 // nop into addi r3, r3, x@tprel@l 715 716 switch (rel.type) { 717 case R_PPC64_GOT_TLSGD16_HA: 718 writeFromHalf16(loc, NOP); 719 break; 720 case R_PPC64_GOT_TLSGD16: 721 case R_PPC64_GOT_TLSGD16_LO: 722 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13 723 relocateNoSym(loc, R_PPC64_TPREL16_HA, val); 724 break; 725 case R_PPC64_GOT_TLSGD_PCREL34: 726 // Relax from paddi r3, 0, x@got@tlsgd@pcrel, 1 to 727 // paddi r3, r13, x@tprel, 0 728 writePrefixedInstruction(loc, 0x06000000386d0000); 729 relocateNoSym(loc, R_PPC64_TPREL34, val); 730 break; 731 case R_PPC64_TLSGD: { 732 // PC Relative Relaxation: 733 // Relax from bl __tls_get_addr@notoc(x@tlsgd) to 734 // nop 735 // TOC Relaxation: 736 // Relax from bl __tls_get_addr(x@tlsgd) 737 // nop 738 // to 739 // nop 740 // addi r3, r3, x@tprel@l 741 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc); 742 if (locAsInt % 4 == 0) { 743 write32(loc, NOP); // nop 744 write32(loc + 4, 0x38630000); // addi r3, r3 745 // Since we are relocating a half16 type relocation and Loc + 4 points to 746 // the start of an instruction we need to advance the buffer by an extra 747 // 2 bytes on BE. 748 relocateNoSym(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0), 749 R_PPC64_TPREL16_LO, val); 750 } else if (locAsInt % 4 == 1) { 751 write32(loc - 1, NOP); 752 } else { 753 errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment"); 754 } 755 break; 756 } 757 default: 758 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 759 } 760 } 761 762 void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel, 763 uint64_t val) const { 764 // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement. 765 // The local dynamic code sequence for a global `x` will look like: 766 // Instruction Relocation Symbol 767 // addis r3, r2, x@got@tlsld@ha R_PPC64_GOT_TLSLD16_HA x 768 // addi r3, r3, x@got@tlsld@l R_PPC64_GOT_TLSLD16_LO x 769 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSLD x 770 // R_PPC64_REL24 __tls_get_addr 771 // nop None None 772 773 // Relaxing to local exec entails converting: 774 // addis r3, r2, x@got@tlsld@ha into nop 775 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0 776 // bl __tls_get_addr(x@tlsgd) into nop 777 // nop into addi r3, r3, 4096 778 779 switch (rel.type) { 780 case R_PPC64_GOT_TLSLD16_HA: 781 writeFromHalf16(loc, NOP); 782 break; 783 case R_PPC64_GOT_TLSLD16_LO: 784 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0 785 break; 786 case R_PPC64_GOT_TLSLD_PCREL34: 787 // Relax from paddi r3, 0, x1@got@tlsld@pcrel, 1 to 788 // paddi r3, r13, 0x1000, 0 789 writePrefixedInstruction(loc, 0x06000000386d1000); 790 break; 791 case R_PPC64_TLSLD: { 792 // PC Relative Relaxation: 793 // Relax from bl __tls_get_addr@notoc(x@tlsld) 794 // to 795 // nop 796 // TOC Relaxation: 797 // Relax from bl __tls_get_addr(x@tlsld) 798 // nop 799 // to 800 // nop 801 // addi r3, r3, 4096 802 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc); 803 if (locAsInt % 4 == 0) { 804 write32(loc, NOP); 805 write32(loc + 4, 0x38631000); // addi r3, r3, 4096 806 } else if (locAsInt % 4 == 1) { 807 write32(loc - 1, NOP); 808 } else { 809 errorOrWarn("R_PPC64_TLSLD has unexpected byte alignment"); 810 } 811 break; 812 } 813 case R_PPC64_DTPREL16: 814 case R_PPC64_DTPREL16_HA: 815 case R_PPC64_DTPREL16_HI: 816 case R_PPC64_DTPREL16_DS: 817 case R_PPC64_DTPREL16_LO: 818 case R_PPC64_DTPREL16_LO_DS: 819 case R_PPC64_DTPREL34: 820 relocate(loc, rel, val); 821 break; 822 default: 823 llvm_unreachable("unsupported relocation for TLS LD to LE relaxation"); 824 } 825 } 826 827 unsigned elf::getPPCDFormOp(unsigned secondaryOp) { 828 switch (secondaryOp) { 829 case LBZX: 830 return LBZ; 831 case LHZX: 832 return LHZ; 833 case LWZX: 834 return LWZ; 835 case LDX: 836 return LD; 837 case STBX: 838 return STB; 839 case STHX: 840 return STH; 841 case STWX: 842 return STW; 843 case STDX: 844 return STD; 845 case ADD: 846 return ADDI; 847 default: 848 return 0; 849 } 850 } 851 852 void PPC64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, 853 uint64_t val) const { 854 // The initial exec code sequence for a global `x` will look like: 855 // Instruction Relocation Symbol 856 // addis r9, r2, x@got@tprel@ha R_PPC64_GOT_TPREL16_HA x 857 // ld r9, x@got@tprel@l(r9) R_PPC64_GOT_TPREL16_LO_DS x 858 // add r9, r9, x@tls R_PPC64_TLS x 859 860 // Relaxing to local exec entails converting: 861 // addis r9, r2, x@got@tprel@ha into nop 862 // ld r9, x@got@tprel@l(r9) into addis r9, r13, x@tprel@ha 863 // add r9, r9, x@tls into addi r9, r9, x@tprel@l 864 865 // x@tls R_PPC64_TLS is a relocation which does not compute anything, 866 // it is replaced with r13 (thread pointer). 867 868 // The add instruction in the initial exec sequence has multiple variations 869 // that need to be handled. If we are building an address it will use an add 870 // instruction, if we are accessing memory it will use any of the X-form 871 // indexed load or store instructions. 872 873 unsigned offset = (config->ekind == ELF64BEKind) ? 2 : 0; 874 switch (rel.type) { 875 case R_PPC64_GOT_TPREL16_HA: 876 write32(loc - offset, NOP); 877 break; 878 case R_PPC64_GOT_TPREL16_LO_DS: 879 case R_PPC64_GOT_TPREL16_DS: { 880 uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10 881 write32(loc - offset, 0x3C0D0000 | regNo); // addis RegNo, r13 882 relocateNoSym(loc, R_PPC64_TPREL16_HA, val); 883 break; 884 } 885 case R_PPC64_GOT_TPREL_PCREL34: { 886 const uint64_t pldRT = readPrefixedInstruction(loc) & 0x0000000003e00000; 887 // paddi RT(from pld), r13, symbol@tprel, 0 888 writePrefixedInstruction(loc, 0x06000000380d0000 | pldRT); 889 relocateNoSym(loc, R_PPC64_TPREL34, val); 890 break; 891 } 892 case R_PPC64_TLS: { 893 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc); 894 if (locAsInt % 4 == 0) { 895 uint32_t primaryOp = getPrimaryOpCode(read32(loc)); 896 if (primaryOp != 31) 897 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 898 uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30 899 uint32_t dFormOp = getPPCDFormOp(secondaryOp); 900 if (dFormOp == 0) 901 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 902 write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF))); 903 relocateNoSym(loc + offset, R_PPC64_TPREL16_LO, val); 904 } else if (locAsInt % 4 == 1) { 905 // If the offset is not 4 byte aligned then we have a PCRel type reloc. 906 // This version of the relocation is offset by one byte from the 907 // instruction it references. 908 uint32_t tlsInstr = read32(loc - 1); 909 uint32_t primaryOp = getPrimaryOpCode(tlsInstr); 910 if (primaryOp != 31) 911 errorOrWarn("unrecognized instruction for IE to LE R_PPC64_TLS"); 912 uint32_t secondaryOp = (tlsInstr & 0x000007FE) >> 1; // bits 21-30 913 // The add is a special case and should be turned into a nop. The paddi 914 // that comes before it will already have computed the address of the 915 // symbol. 916 if (secondaryOp == 266) { 917 // Check if the add uses the same result register as the input register. 918 uint32_t rt = (tlsInstr & 0x03E00000) >> 21; // bits 6-10 919 uint32_t ra = (tlsInstr & 0x001F0000) >> 16; // bits 11-15 920 if (ra == rt) { 921 write32(loc - 1, NOP); 922 } else { 923 // mr rt, ra 924 write32(loc - 1, 0x7C000378 | (rt << 16) | (ra << 21) | (ra << 11)); 925 } 926 } else { 927 uint32_t dFormOp = getPPCDFormOp(secondaryOp); 928 if (dFormOp == 0) 929 errorOrWarn("unrecognized instruction for IE to LE R_PPC64_TLS"); 930 write32(loc - 1, ((dFormOp << 26) | (tlsInstr & 0x03FF0000))); 931 } 932 } else { 933 errorOrWarn("R_PPC64_TLS must be either 4 byte aligned or one byte " 934 "offset from 4 byte aligned"); 935 } 936 break; 937 } 938 default: 939 llvm_unreachable("unknown relocation for IE to LE"); 940 break; 941 } 942 } 943 944 RelExpr PPC64::getRelExpr(RelType type, const Symbol &s, 945 const uint8_t *loc) const { 946 switch (type) { 947 case R_PPC64_NONE: 948 return R_NONE; 949 case R_PPC64_ADDR16: 950 case R_PPC64_ADDR16_DS: 951 case R_PPC64_ADDR16_HA: 952 case R_PPC64_ADDR16_HI: 953 case R_PPC64_ADDR16_HIGH: 954 case R_PPC64_ADDR16_HIGHER: 955 case R_PPC64_ADDR16_HIGHERA: 956 case R_PPC64_ADDR16_HIGHEST: 957 case R_PPC64_ADDR16_HIGHESTA: 958 case R_PPC64_ADDR16_LO: 959 case R_PPC64_ADDR16_LO_DS: 960 case R_PPC64_ADDR32: 961 case R_PPC64_ADDR64: 962 return R_ABS; 963 case R_PPC64_GOT16: 964 case R_PPC64_GOT16_DS: 965 case R_PPC64_GOT16_HA: 966 case R_PPC64_GOT16_HI: 967 case R_PPC64_GOT16_LO: 968 case R_PPC64_GOT16_LO_DS: 969 return R_GOT_OFF; 970 case R_PPC64_TOC16: 971 case R_PPC64_TOC16_DS: 972 case R_PPC64_TOC16_HI: 973 case R_PPC64_TOC16_LO: 974 return R_GOTREL; 975 case R_PPC64_GOT_PCREL34: 976 case R_PPC64_GOT_TPREL_PCREL34: 977 case R_PPC64_PCREL_OPT: 978 return R_GOT_PC; 979 case R_PPC64_TOC16_HA: 980 case R_PPC64_TOC16_LO_DS: 981 return config->tocOptimize ? R_PPC64_RELAX_TOC : R_GOTREL; 982 case R_PPC64_TOC: 983 return R_PPC64_TOCBASE; 984 case R_PPC64_REL14: 985 case R_PPC64_REL24: 986 return R_PPC64_CALL_PLT; 987 case R_PPC64_REL24_NOTOC: 988 return R_PLT_PC; 989 case R_PPC64_REL16_LO: 990 case R_PPC64_REL16_HA: 991 case R_PPC64_REL16_HI: 992 case R_PPC64_REL32: 993 case R_PPC64_REL64: 994 case R_PPC64_PCREL34: 995 return R_PC; 996 case R_PPC64_GOT_TLSGD16: 997 case R_PPC64_GOT_TLSGD16_HA: 998 case R_PPC64_GOT_TLSGD16_HI: 999 case R_PPC64_GOT_TLSGD16_LO: 1000 return R_TLSGD_GOT; 1001 case R_PPC64_GOT_TLSGD_PCREL34: 1002 return R_TLSGD_PC; 1003 case R_PPC64_GOT_TLSLD16: 1004 case R_PPC64_GOT_TLSLD16_HA: 1005 case R_PPC64_GOT_TLSLD16_HI: 1006 case R_PPC64_GOT_TLSLD16_LO: 1007 return R_TLSLD_GOT; 1008 case R_PPC64_GOT_TLSLD_PCREL34: 1009 return R_TLSLD_PC; 1010 case R_PPC64_GOT_TPREL16_HA: 1011 case R_PPC64_GOT_TPREL16_LO_DS: 1012 case R_PPC64_GOT_TPREL16_DS: 1013 case R_PPC64_GOT_TPREL16_HI: 1014 return R_GOT_OFF; 1015 case R_PPC64_GOT_DTPREL16_HA: 1016 case R_PPC64_GOT_DTPREL16_LO_DS: 1017 case R_PPC64_GOT_DTPREL16_DS: 1018 case R_PPC64_GOT_DTPREL16_HI: 1019 return R_TLSLD_GOT_OFF; 1020 case R_PPC64_TPREL16: 1021 case R_PPC64_TPREL16_HA: 1022 case R_PPC64_TPREL16_LO: 1023 case R_PPC64_TPREL16_HI: 1024 case R_PPC64_TPREL16_DS: 1025 case R_PPC64_TPREL16_LO_DS: 1026 case R_PPC64_TPREL16_HIGHER: 1027 case R_PPC64_TPREL16_HIGHERA: 1028 case R_PPC64_TPREL16_HIGHEST: 1029 case R_PPC64_TPREL16_HIGHESTA: 1030 case R_PPC64_TPREL34: 1031 return R_TPREL; 1032 case R_PPC64_DTPREL16: 1033 case R_PPC64_DTPREL16_DS: 1034 case R_PPC64_DTPREL16_HA: 1035 case R_PPC64_DTPREL16_HI: 1036 case R_PPC64_DTPREL16_HIGHER: 1037 case R_PPC64_DTPREL16_HIGHERA: 1038 case R_PPC64_DTPREL16_HIGHEST: 1039 case R_PPC64_DTPREL16_HIGHESTA: 1040 case R_PPC64_DTPREL16_LO: 1041 case R_PPC64_DTPREL16_LO_DS: 1042 case R_PPC64_DTPREL64: 1043 case R_PPC64_DTPREL34: 1044 return R_DTPREL; 1045 case R_PPC64_TLSGD: 1046 return R_TLSDESC_CALL; 1047 case R_PPC64_TLSLD: 1048 return R_TLSLD_HINT; 1049 case R_PPC64_TLS: 1050 return R_TLSIE_HINT; 1051 default: 1052 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 1053 ") against symbol " + toString(s)); 1054 return R_NONE; 1055 } 1056 } 1057 1058 RelType PPC64::getDynRel(RelType type) const { 1059 if (type == R_PPC64_ADDR64 || type == R_PPC64_TOC) 1060 return R_PPC64_ADDR64; 1061 return R_PPC64_NONE; 1062 } 1063 1064 int64_t PPC64::getImplicitAddend(const uint8_t *buf, RelType type) const { 1065 switch (type) { 1066 case R_PPC64_NONE: 1067 return 0; 1068 case R_PPC64_REL32: 1069 return SignExtend64<32>(read32(buf)); 1070 case R_PPC64_ADDR64: 1071 case R_PPC64_REL64: 1072 return read64(buf); 1073 default: 1074 internalLinkerError(getErrorLocation(buf), 1075 "cannot read addend for relocation " + toString(type)); 1076 return 0; 1077 } 1078 } 1079 1080 void PPC64::writeGotHeader(uint8_t *buf) const { 1081 write64(buf, getPPC64TocBase()); 1082 } 1083 1084 void PPC64::writePltHeader(uint8_t *buf) const { 1085 // The generic resolver stub goes first. 1086 write32(buf + 0, 0x7c0802a6); // mflr r0 1087 write32(buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8> 1088 write32(buf + 8, 0x7d6802a6); // mflr r11 1089 write32(buf + 12, 0x7c0803a6); // mtlr r0 1090 write32(buf + 16, 0x7d8b6050); // subf r12, r11, r12 1091 write32(buf + 20, 0x380cffcc); // subi r0,r12,52 1092 write32(buf + 24, 0x7800f082); // srdi r0,r0,62,2 1093 write32(buf + 28, 0xe98b002c); // ld r12,44(r11) 1094 write32(buf + 32, 0x7d6c5a14); // add r11,r12,r11 1095 write32(buf + 36, 0xe98b0000); // ld r12,0(r11) 1096 write32(buf + 40, 0xe96b0008); // ld r11,8(r11) 1097 write32(buf + 44, 0x7d8903a6); // mtctr r12 1098 write32(buf + 48, 0x4e800420); // bctr 1099 1100 // The 'bcl' instruction will set the link register to the address of the 1101 // following instruction ('mflr r11'). Here we store the offset from that 1102 // instruction to the first entry in the GotPlt section. 1103 int64_t gotPltOffset = in.gotPlt->getVA() - (in.plt->getVA() + 8); 1104 write64(buf + 52, gotPltOffset); 1105 } 1106 1107 void PPC64::writePlt(uint8_t *buf, const Symbol &sym, 1108 uint64_t /*pltEntryAddr*/) const { 1109 int32_t offset = pltHeaderSize + sym.getPltIdx() * pltEntrySize; 1110 // bl __glink_PLTresolve 1111 write32(buf, 0x48000000 | ((-offset) & 0x03FFFFFc)); 1112 } 1113 1114 void PPC64::writeIplt(uint8_t *buf, const Symbol &sym, 1115 uint64_t /*pltEntryAddr*/) const { 1116 writePPC64LoadAndBranch(buf, sym.getGotPltVA() - getPPC64TocBase()); 1117 } 1118 1119 static std::pair<RelType, uint64_t> toAddr16Rel(RelType type, uint64_t val) { 1120 // Relocations relative to the toc-base need to be adjusted by the Toc offset. 1121 uint64_t tocBiasedVal = val - ppc64TocOffset; 1122 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset. 1123 uint64_t dtpBiasedVal = val - dynamicThreadPointerOffset; 1124 1125 switch (type) { 1126 // TOC biased relocation. 1127 case R_PPC64_GOT16: 1128 case R_PPC64_GOT_TLSGD16: 1129 case R_PPC64_GOT_TLSLD16: 1130 case R_PPC64_TOC16: 1131 return {R_PPC64_ADDR16, tocBiasedVal}; 1132 case R_PPC64_GOT16_DS: 1133 case R_PPC64_TOC16_DS: 1134 case R_PPC64_GOT_TPREL16_DS: 1135 case R_PPC64_GOT_DTPREL16_DS: 1136 return {R_PPC64_ADDR16_DS, tocBiasedVal}; 1137 case R_PPC64_GOT16_HA: 1138 case R_PPC64_GOT_TLSGD16_HA: 1139 case R_PPC64_GOT_TLSLD16_HA: 1140 case R_PPC64_GOT_TPREL16_HA: 1141 case R_PPC64_GOT_DTPREL16_HA: 1142 case R_PPC64_TOC16_HA: 1143 return {R_PPC64_ADDR16_HA, tocBiasedVal}; 1144 case R_PPC64_GOT16_HI: 1145 case R_PPC64_GOT_TLSGD16_HI: 1146 case R_PPC64_GOT_TLSLD16_HI: 1147 case R_PPC64_GOT_TPREL16_HI: 1148 case R_PPC64_GOT_DTPREL16_HI: 1149 case R_PPC64_TOC16_HI: 1150 return {R_PPC64_ADDR16_HI, tocBiasedVal}; 1151 case R_PPC64_GOT16_LO: 1152 case R_PPC64_GOT_TLSGD16_LO: 1153 case R_PPC64_GOT_TLSLD16_LO: 1154 case R_PPC64_TOC16_LO: 1155 return {R_PPC64_ADDR16_LO, tocBiasedVal}; 1156 case R_PPC64_GOT16_LO_DS: 1157 case R_PPC64_TOC16_LO_DS: 1158 case R_PPC64_GOT_TPREL16_LO_DS: 1159 case R_PPC64_GOT_DTPREL16_LO_DS: 1160 return {R_PPC64_ADDR16_LO_DS, tocBiasedVal}; 1161 1162 // Dynamic Thread pointer biased relocation types. 1163 case R_PPC64_DTPREL16: 1164 return {R_PPC64_ADDR16, dtpBiasedVal}; 1165 case R_PPC64_DTPREL16_DS: 1166 return {R_PPC64_ADDR16_DS, dtpBiasedVal}; 1167 case R_PPC64_DTPREL16_HA: 1168 return {R_PPC64_ADDR16_HA, dtpBiasedVal}; 1169 case R_PPC64_DTPREL16_HI: 1170 return {R_PPC64_ADDR16_HI, dtpBiasedVal}; 1171 case R_PPC64_DTPREL16_HIGHER: 1172 return {R_PPC64_ADDR16_HIGHER, dtpBiasedVal}; 1173 case R_PPC64_DTPREL16_HIGHERA: 1174 return {R_PPC64_ADDR16_HIGHERA, dtpBiasedVal}; 1175 case R_PPC64_DTPREL16_HIGHEST: 1176 return {R_PPC64_ADDR16_HIGHEST, dtpBiasedVal}; 1177 case R_PPC64_DTPREL16_HIGHESTA: 1178 return {R_PPC64_ADDR16_HIGHESTA, dtpBiasedVal}; 1179 case R_PPC64_DTPREL16_LO: 1180 return {R_PPC64_ADDR16_LO, dtpBiasedVal}; 1181 case R_PPC64_DTPREL16_LO_DS: 1182 return {R_PPC64_ADDR16_LO_DS, dtpBiasedVal}; 1183 case R_PPC64_DTPREL64: 1184 return {R_PPC64_ADDR64, dtpBiasedVal}; 1185 1186 default: 1187 return {type, val}; 1188 } 1189 } 1190 1191 static bool isTocOptType(RelType type) { 1192 switch (type) { 1193 case R_PPC64_GOT16_HA: 1194 case R_PPC64_GOT16_LO_DS: 1195 case R_PPC64_TOC16_HA: 1196 case R_PPC64_TOC16_LO_DS: 1197 case R_PPC64_TOC16_LO: 1198 return true; 1199 default: 1200 return false; 1201 } 1202 } 1203 1204 void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { 1205 RelType type = rel.type; 1206 bool shouldTocOptimize = isTocOptType(type); 1207 // For dynamic thread pointer relative, toc-relative, and got-indirect 1208 // relocations, proceed in terms of the corresponding ADDR16 relocation type. 1209 std::tie(type, val) = toAddr16Rel(type, val); 1210 1211 switch (type) { 1212 case R_PPC64_ADDR14: { 1213 checkAlignment(loc, val, 4, rel); 1214 // Preserve the AA/LK bits in the branch instruction 1215 uint8_t aalk = loc[3]; 1216 write16(loc + 2, (aalk & 3) | (val & 0xfffc)); 1217 break; 1218 } 1219 case R_PPC64_ADDR16: 1220 checkIntUInt(loc, val, 16, rel); 1221 write16(loc, val); 1222 break; 1223 case R_PPC64_ADDR32: 1224 checkIntUInt(loc, val, 32, rel); 1225 write32(loc, val); 1226 break; 1227 case R_PPC64_ADDR16_DS: 1228 case R_PPC64_TPREL16_DS: { 1229 checkInt(loc, val, 16, rel); 1230 // DQ-form instructions use bits 28-31 as part of the instruction encoding 1231 // DS-form instructions only use bits 30-31. 1232 uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 0xf : 0x3; 1233 checkAlignment(loc, lo(val), mask + 1, rel); 1234 write16(loc, (read16(loc) & mask) | lo(val)); 1235 } break; 1236 case R_PPC64_ADDR16_HA: 1237 case R_PPC64_REL16_HA: 1238 case R_PPC64_TPREL16_HA: 1239 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) 1240 writeFromHalf16(loc, NOP); 1241 else { 1242 checkInt(loc, val + 0x8000, 32, rel); 1243 write16(loc, ha(val)); 1244 } 1245 break; 1246 case R_PPC64_ADDR16_HI: 1247 case R_PPC64_REL16_HI: 1248 case R_PPC64_TPREL16_HI: 1249 checkInt(loc, val, 32, rel); 1250 write16(loc, hi(val)); 1251 break; 1252 case R_PPC64_ADDR16_HIGH: 1253 write16(loc, hi(val)); 1254 break; 1255 case R_PPC64_ADDR16_HIGHER: 1256 case R_PPC64_TPREL16_HIGHER: 1257 write16(loc, higher(val)); 1258 break; 1259 case R_PPC64_ADDR16_HIGHERA: 1260 case R_PPC64_TPREL16_HIGHERA: 1261 write16(loc, highera(val)); 1262 break; 1263 case R_PPC64_ADDR16_HIGHEST: 1264 case R_PPC64_TPREL16_HIGHEST: 1265 write16(loc, highest(val)); 1266 break; 1267 case R_PPC64_ADDR16_HIGHESTA: 1268 case R_PPC64_TPREL16_HIGHESTA: 1269 write16(loc, highesta(val)); 1270 break; 1271 case R_PPC64_ADDR16_LO: 1272 case R_PPC64_REL16_LO: 1273 case R_PPC64_TPREL16_LO: 1274 // When the high-adjusted part of a toc relocation evaluates to 0, it is 1275 // changed into a nop. The lo part then needs to be updated to use the 1276 // toc-pointer register r2, as the base register. 1277 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) { 1278 uint32_t insn = readFromHalf16(loc); 1279 if (isInstructionUpdateForm(insn)) 1280 error(getErrorLocation(loc) + 1281 "can't toc-optimize an update instruction: 0x" + 1282 utohexstr(insn)); 1283 writeFromHalf16(loc, (insn & 0xffe00000) | 0x00020000 | lo(val)); 1284 } else { 1285 write16(loc, lo(val)); 1286 } 1287 break; 1288 case R_PPC64_ADDR16_LO_DS: 1289 case R_PPC64_TPREL16_LO_DS: { 1290 // DQ-form instructions use bits 28-31 as part of the instruction encoding 1291 // DS-form instructions only use bits 30-31. 1292 uint32_t insn = readFromHalf16(loc); 1293 uint16_t mask = isDQFormInstruction(insn) ? 0xf : 0x3; 1294 checkAlignment(loc, lo(val), mask + 1, rel); 1295 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) { 1296 // When the high-adjusted part of a toc relocation evaluates to 0, it is 1297 // changed into a nop. The lo part then needs to be updated to use the toc 1298 // pointer register r2, as the base register. 1299 if (isInstructionUpdateForm(insn)) 1300 error(getErrorLocation(loc) + 1301 "Can't toc-optimize an update instruction: 0x" + 1302 Twine::utohexstr(insn)); 1303 insn &= 0xffe00000 | mask; 1304 writeFromHalf16(loc, insn | 0x00020000 | lo(val)); 1305 } else { 1306 write16(loc, (read16(loc) & mask) | lo(val)); 1307 } 1308 } break; 1309 case R_PPC64_TPREL16: 1310 checkInt(loc, val, 16, rel); 1311 write16(loc, val); 1312 break; 1313 case R_PPC64_REL32: 1314 checkInt(loc, val, 32, rel); 1315 write32(loc, val); 1316 break; 1317 case R_PPC64_ADDR64: 1318 case R_PPC64_REL64: 1319 case R_PPC64_TOC: 1320 write64(loc, val); 1321 break; 1322 case R_PPC64_REL14: { 1323 uint32_t mask = 0x0000FFFC; 1324 checkInt(loc, val, 16, rel); 1325 checkAlignment(loc, val, 4, rel); 1326 write32(loc, (read32(loc) & ~mask) | (val & mask)); 1327 break; 1328 } 1329 case R_PPC64_REL24: 1330 case R_PPC64_REL24_NOTOC: { 1331 uint32_t mask = 0x03FFFFFC; 1332 checkInt(loc, val, 26, rel); 1333 checkAlignment(loc, val, 4, rel); 1334 write32(loc, (read32(loc) & ~mask) | (val & mask)); 1335 break; 1336 } 1337 case R_PPC64_DTPREL64: 1338 write64(loc, val - dynamicThreadPointerOffset); 1339 break; 1340 case R_PPC64_DTPREL34: 1341 // The Dynamic Thread Vector actually points 0x8000 bytes past the start 1342 // of the TLS block. Therefore, in the case of R_PPC64_DTPREL34 we first 1343 // need to subtract that value then fallthrough to the general case. 1344 val -= dynamicThreadPointerOffset; 1345 LLVM_FALLTHROUGH; 1346 case R_PPC64_PCREL34: 1347 case R_PPC64_GOT_PCREL34: 1348 case R_PPC64_GOT_TLSGD_PCREL34: 1349 case R_PPC64_GOT_TLSLD_PCREL34: 1350 case R_PPC64_GOT_TPREL_PCREL34: 1351 case R_PPC64_TPREL34: { 1352 const uint64_t si0Mask = 0x00000003ffff0000; 1353 const uint64_t si1Mask = 0x000000000000ffff; 1354 const uint64_t fullMask = 0x0003ffff0000ffff; 1355 checkInt(loc, val, 34, rel); 1356 1357 uint64_t instr = readPrefixedInstruction(loc) & ~fullMask; 1358 writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) | 1359 (val & si1Mask)); 1360 break; 1361 } 1362 // If we encounter a PCREL_OPT relocation that we won't optimize. 1363 case R_PPC64_PCREL_OPT: 1364 break; 1365 default: 1366 llvm_unreachable("unknown relocation"); 1367 } 1368 } 1369 1370 bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file, 1371 uint64_t branchAddr, const Symbol &s, int64_t a) const { 1372 if (type != R_PPC64_REL14 && type != R_PPC64_REL24 && 1373 type != R_PPC64_REL24_NOTOC) 1374 return false; 1375 1376 // If a function is in the Plt it needs to be called with a call-stub. 1377 if (s.isInPlt()) 1378 return true; 1379 1380 // This check looks at the st_other bits of the callee with relocation 1381 // R_PPC64_REL14 or R_PPC64_REL24. If the value is 1, then the callee 1382 // clobbers the TOC and we need an R2 save stub. 1383 if (type != R_PPC64_REL24_NOTOC && (s.stOther >> 5) == 1) 1384 return true; 1385 1386 if (type == R_PPC64_REL24_NOTOC && (s.stOther >> 5) > 1) 1387 return true; 1388 1389 // An undefined weak symbol not in a PLT does not need a thunk. If it is 1390 // hidden, its binding has been converted to local, so we just check 1391 // isUndefined() here. A undefined non-weak symbol has been errored. 1392 if (s.isUndefined()) 1393 return false; 1394 1395 // If the offset exceeds the range of the branch type then it will need 1396 // a range-extending thunk. 1397 // See the comment in getRelocTargetVA() about R_PPC64_CALL. 1398 return !inBranchRange(type, branchAddr, 1399 s.getVA(a) + 1400 getPPC64GlobalEntryToLocalEntryOffset(s.stOther)); 1401 } 1402 1403 uint32_t PPC64::getThunkSectionSpacing() const { 1404 // See comment in Arch/ARM.cpp for a more detailed explanation of 1405 // getThunkSectionSpacing(). For PPC64 we pick the constant here based on 1406 // R_PPC64_REL24, which is used by unconditional branch instructions. 1407 // 0x2000000 = (1 << 24-1) * 4 1408 return 0x2000000; 1409 } 1410 1411 bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { 1412 int64_t offset = dst - src; 1413 if (type == R_PPC64_REL14) 1414 return isInt<16>(offset); 1415 if (type == R_PPC64_REL24 || type == R_PPC64_REL24_NOTOC) 1416 return isInt<26>(offset); 1417 llvm_unreachable("unsupported relocation type used in branch"); 1418 } 1419 1420 RelExpr PPC64::adjustTlsExpr(RelType type, RelExpr expr) const { 1421 if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE) 1422 return R_RELAX_TLS_GD_TO_IE_GOT_OFF; 1423 if (expr == R_RELAX_TLS_LD_TO_LE) 1424 return R_RELAX_TLS_LD_TO_LE_ABS; 1425 return expr; 1426 } 1427 1428 RelExpr PPC64::adjustGotPcExpr(RelType type, int64_t addend, 1429 const uint8_t *loc) const { 1430 if ((type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT) && 1431 config->pcRelOptimize) { 1432 // It only makes sense to optimize pld since paddi means that the address 1433 // of the object in the GOT is required rather than the object itself. 1434 if ((readPrefixedInstruction(loc) & 0xfc000000) == 0xe4000000) 1435 return R_PPC64_RELAX_GOT_PC; 1436 } 1437 return R_GOT_PC; 1438 } 1439 1440 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement. 1441 // The general dynamic code sequence for a global `x` uses 4 instructions. 1442 // Instruction Relocation Symbol 1443 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 1444 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 1445 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 1446 // R_PPC64_REL24 __tls_get_addr 1447 // nop None None 1448 // 1449 // Relaxing to initial-exec entails: 1450 // 1) Convert the addis/addi pair that builds the address of the tls_index 1451 // struct for 'x' to an addis/ld pair that loads an offset from a got-entry. 1452 // 2) Convert the call to __tls_get_addr to a nop. 1453 // 3) Convert the nop following the call to an add of the loaded offset to the 1454 // thread pointer. 1455 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is 1456 // used as the relaxation hint for both steps 2 and 3. 1457 void PPC64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, 1458 uint64_t val) const { 1459 switch (rel.type) { 1460 case R_PPC64_GOT_TLSGD16_HA: 1461 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to 1462 // addis rT, r2, sym@got@tprel@ha. 1463 relocateNoSym(loc, R_PPC64_GOT_TPREL16_HA, val); 1464 return; 1465 case R_PPC64_GOT_TLSGD16: 1466 case R_PPC64_GOT_TLSGD16_LO: { 1467 // Relax from addi r3, rA, sym@got@tlsgd@l to 1468 // ld r3, sym@got@tprel@l(rA) 1469 uint32_t ra = (readFromHalf16(loc) & (0x1f << 16)); 1470 writeFromHalf16(loc, 0xe8600000 | ra); 1471 relocateNoSym(loc, R_PPC64_GOT_TPREL16_LO_DS, val); 1472 return; 1473 } 1474 case R_PPC64_GOT_TLSGD_PCREL34: { 1475 // Relax from paddi r3, 0, sym@got@tlsgd@pcrel, 1 to 1476 // pld r3, sym@got@tprel@pcrel 1477 writePrefixedInstruction(loc, 0x04100000e4600000); 1478 relocateNoSym(loc, R_PPC64_GOT_TPREL_PCREL34, val); 1479 return; 1480 } 1481 case R_PPC64_TLSGD: { 1482 // PC Relative Relaxation: 1483 // Relax from bl __tls_get_addr@notoc(x@tlsgd) to 1484 // nop 1485 // TOC Relaxation: 1486 // Relax from bl __tls_get_addr(x@tlsgd) 1487 // nop 1488 // to 1489 // nop 1490 // add r3, r3, r13 1491 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc); 1492 if (locAsInt % 4 == 0) { 1493 write32(loc, NOP); // bl __tls_get_addr(sym@tlsgd) --> nop 1494 write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13 1495 } else if (locAsInt % 4 == 1) { 1496 // bl __tls_get_addr(sym@tlsgd) --> add r3, r3, r13 1497 write32(loc - 1, 0x7c636a14); 1498 } else { 1499 errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment"); 1500 } 1501 return; 1502 } 1503 default: 1504 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation"); 1505 } 1506 } 1507 1508 // The prologue for a split-stack function is expected to look roughly 1509 // like this: 1510 // .Lglobal_entry_point: 1511 // # TOC pointer initialization. 1512 // ... 1513 // .Llocal_entry_point: 1514 // # load the __private_ss member of the threads tcbhead. 1515 // ld r0,-0x7000-64(r13) 1516 // # subtract the functions stack size from the stack pointer. 1517 // addis r12, r1, ha(-stack-frame size) 1518 // addi r12, r12, l(-stack-frame size) 1519 // # compare needed to actual and branch to allocate_more_stack if more 1520 // # space is needed, otherwise fallthrough to 'normal' function body. 1521 // cmpld cr7,r12,r0 1522 // blt- cr7, .Lallocate_more_stack 1523 // 1524 // -) The allocate_more_stack block might be placed after the split-stack 1525 // prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body` 1526 // instead. 1527 // -) If either the addis or addi is not needed due to the stack size being 1528 // smaller then 32K or a multiple of 64K they will be replaced with a nop, 1529 // but there will always be 2 instructions the linker can overwrite for the 1530 // adjusted stack size. 1531 // 1532 // The linkers job here is to increase the stack size used in the addis/addi 1533 // pair by split-stack-size-adjust. 1534 // addis r12, r1, ha(-stack-frame size - split-stack-adjust-size) 1535 // addi r12, r12, l(-stack-frame size - split-stack-adjust-size) 1536 bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end, 1537 uint8_t stOther) const { 1538 // If the caller has a global entry point adjust the buffer past it. The start 1539 // of the split-stack prologue will be at the local entry point. 1540 loc += getPPC64GlobalEntryToLocalEntryOffset(stOther); 1541 1542 // At the very least we expect to see a load of some split-stack data from the 1543 // tcb, and 2 instructions that calculate the ending stack address this 1544 // function will require. If there is not enough room for at least 3 1545 // instructions it can't be a split-stack prologue. 1546 if (loc + 12 >= end) 1547 return false; 1548 1549 // First instruction must be `ld r0, -0x7000-64(r13)` 1550 if (read32(loc) != 0xe80d8fc0) 1551 return false; 1552 1553 int16_t hiImm = 0; 1554 int16_t loImm = 0; 1555 // First instruction can be either an addis if the frame size is larger then 1556 // 32K, or an addi if the size is less then 32K. 1557 int32_t firstInstr = read32(loc + 4); 1558 if (getPrimaryOpCode(firstInstr) == 15) { 1559 hiImm = firstInstr & 0xFFFF; 1560 } else if (getPrimaryOpCode(firstInstr) == 14) { 1561 loImm = firstInstr & 0xFFFF; 1562 } else { 1563 return false; 1564 } 1565 1566 // Second instruction is either an addi or a nop. If the first instruction was 1567 // an addi then LoImm is set and the second instruction must be a nop. 1568 uint32_t secondInstr = read32(loc + 8); 1569 if (!loImm && getPrimaryOpCode(secondInstr) == 14) { 1570 loImm = secondInstr & 0xFFFF; 1571 } else if (secondInstr != NOP) { 1572 return false; 1573 } 1574 1575 // The register operands of the first instruction should be the stack-pointer 1576 // (r1) as the input (RA) and r12 as the output (RT). If the second 1577 // instruction is not a nop, then it should use r12 as both input and output. 1578 auto checkRegOperands = [](uint32_t instr, uint8_t expectedRT, 1579 uint8_t expectedRA) { 1580 return ((instr & 0x3E00000) >> 21 == expectedRT) && 1581 ((instr & 0x1F0000) >> 16 == expectedRA); 1582 }; 1583 if (!checkRegOperands(firstInstr, 12, 1)) 1584 return false; 1585 if (secondInstr != NOP && !checkRegOperands(secondInstr, 12, 12)) 1586 return false; 1587 1588 int32_t stackFrameSize = (hiImm * 65536) + loImm; 1589 // Check that the adjusted size doesn't overflow what we can represent with 2 1590 // instructions. 1591 if (stackFrameSize < config->splitStackAdjustSize + INT32_MIN) { 1592 error(getErrorLocation(loc) + "split-stack prologue adjustment overflows"); 1593 return false; 1594 } 1595 1596 int32_t adjustedStackFrameSize = 1597 stackFrameSize - config->splitStackAdjustSize; 1598 1599 loImm = adjustedStackFrameSize & 0xFFFF; 1600 hiImm = (adjustedStackFrameSize + 0x8000) >> 16; 1601 if (hiImm) { 1602 write32(loc + 4, 0x3D810000 | (uint16_t)hiImm); 1603 // If the low immediate is zero the second instruction will be a nop. 1604 secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : NOP; 1605 write32(loc + 8, secondInstr); 1606 } else { 1607 // addi r12, r1, imm 1608 write32(loc + 4, (0x39810000) | (uint16_t)loImm); 1609 write32(loc + 8, NOP); 1610 } 1611 1612 return true; 1613 } 1614 1615 TargetInfo *elf::getPPC64TargetInfo() { 1616 static PPC64 target; 1617 return ⌖ 1618 } 1619