1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "llvm/BinaryFormat/ELF.h" 14 15 using namespace llvm; 16 using namespace llvm::object; 17 using namespace llvm::ELF; 18 using namespace lld; 19 using namespace lld::elf; 20 21 namespace { 22 template <class ELFT> class MIPS final : public TargetInfo { 23 public: 24 MIPS(Ctx &); 25 uint32_t calcEFlags() const override; 26 RelExpr getRelExpr(RelType type, const Symbol &s, 27 const uint8_t *loc) const override; 28 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 29 RelType getDynRel(RelType type) const override; 30 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 31 void writePltHeader(uint8_t *buf) const override; 32 void writePlt(uint8_t *buf, const Symbol &sym, 33 uint64_t pltEntryAddr) const override; 34 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 35 uint64_t branchAddr, const Symbol &s, 36 int64_t a) const override; 37 void relocate(uint8_t *loc, const Relocation &rel, 38 uint64_t val) const override; 39 bool usesOnlyLowPageBits(RelType type) const override; 40 }; 41 } // namespace 42 43 template <class ELFT> MIPS<ELFT>::MIPS(Ctx &ctx) : TargetInfo(ctx) { 44 gotPltHeaderEntriesNum = 2; 45 defaultMaxPageSize = 65536; 46 pltEntrySize = 16; 47 pltHeaderSize = 32; 48 copyRel = R_MIPS_COPY; 49 pltRel = R_MIPS_JUMP_SLOT; 50 needsThunks = true; 51 52 // Set `sigrie 1` as a trap instruction. 53 write32(ctx, trapInstr.data(), 0x04170001); 54 55 if (ELFT::Is64Bits) { 56 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 57 symbolicRel = R_MIPS_64; 58 tlsGotRel = R_MIPS_TLS_TPREL64; 59 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 60 tlsOffsetRel = R_MIPS_TLS_DTPREL64; 61 } else { 62 relativeRel = R_MIPS_REL32; 63 symbolicRel = R_MIPS_32; 64 tlsGotRel = R_MIPS_TLS_TPREL32; 65 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 66 tlsOffsetRel = R_MIPS_TLS_DTPREL32; 67 } 68 } 69 70 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 71 return calcMipsEFlags<ELFT>(ctx); 72 } 73 74 template <class ELFT> 75 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, 76 const uint8_t *loc) const { 77 // See comment in the calculateMipsRelChain. 78 if (ELFT::Is64Bits || ctx.arg.mipsN32Abi) 79 type.v &= 0xff; 80 81 switch (type) { 82 case R_MIPS_JALR: 83 // Older versions of clang would erroneously emit this relocation not only 84 // against functions (loaded from the GOT) but also against data symbols 85 // (e.g. a table of function pointers). When we encounter this, ignore the 86 // relocation and emit a warning instead. 87 if (!s.isFunc() && s.type != STT_NOTYPE) { 88 Warn(ctx) << getErrorLoc(ctx, loc) 89 << "found R_MIPS_JALR relocation against non-function symbol " 90 << &s << ". This is invalid and most likely a compiler bug."; 91 return R_NONE; 92 } 93 94 // If the target symbol is not preemptible and is not microMIPS, 95 // it might be possible to replace jalr/jr instruction by bal/b. 96 // It depends on the target symbol's offset. 97 if (!s.isPreemptible && !(s.getVA(ctx) & 0x1)) 98 return R_PC; 99 return R_NONE; 100 case R_MICROMIPS_JALR: 101 return R_NONE; 102 case R_MIPS_GPREL16: 103 case R_MIPS_GPREL32: 104 case R_MICROMIPS_GPREL16: 105 case R_MICROMIPS_GPREL7_S2: 106 return RE_MIPS_GOTREL; 107 case R_MIPS_26: 108 case R_MICROMIPS_26_S1: 109 return R_PLT; 110 case R_MICROMIPS_PC26_S1: 111 return R_PLT_PC; 112 case R_MIPS_HI16: 113 case R_MIPS_LO16: 114 case R_MIPS_HIGHER: 115 case R_MIPS_HIGHEST: 116 case R_MICROMIPS_HI16: 117 case R_MICROMIPS_LO16: 118 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 119 // offset between start of function and 'gp' value which by default 120 // equal to the start of .got section. In that case we consider these 121 // relocations as relative. 122 if (&s == ctx.sym.mipsGpDisp) 123 return RE_MIPS_GOT_GP_PC; 124 if (&s == ctx.sym.mipsLocalGp) 125 return RE_MIPS_GOT_GP; 126 [[fallthrough]]; 127 case R_MIPS_32: 128 case R_MIPS_64: 129 case R_MIPS_GOT_OFST: 130 case R_MIPS_SUB: 131 return R_ABS; 132 case R_MIPS_TLS_DTPREL_HI16: 133 case R_MIPS_TLS_DTPREL_LO16: 134 case R_MIPS_TLS_DTPREL32: 135 case R_MIPS_TLS_DTPREL64: 136 case R_MICROMIPS_TLS_DTPREL_HI16: 137 case R_MICROMIPS_TLS_DTPREL_LO16: 138 return R_DTPREL; 139 case R_MIPS_TLS_TPREL_HI16: 140 case R_MIPS_TLS_TPREL_LO16: 141 case R_MIPS_TLS_TPREL32: 142 case R_MIPS_TLS_TPREL64: 143 case R_MICROMIPS_TLS_TPREL_HI16: 144 case R_MICROMIPS_TLS_TPREL_LO16: 145 return R_TPREL; 146 case R_MIPS_PC32: 147 case R_MIPS_PC16: 148 case R_MIPS_PC19_S2: 149 case R_MIPS_PC21_S2: 150 case R_MIPS_PC26_S2: 151 case R_MIPS_PCHI16: 152 case R_MIPS_PCLO16: 153 case R_MICROMIPS_PC7_S1: 154 case R_MICROMIPS_PC10_S1: 155 case R_MICROMIPS_PC16_S1: 156 case R_MICROMIPS_PC18_S3: 157 case R_MICROMIPS_PC19_S2: 158 case R_MICROMIPS_PC23_S2: 159 case R_MICROMIPS_PC21_S1: 160 return R_PC; 161 case R_MIPS_GOT16: 162 case R_MICROMIPS_GOT16: 163 if (s.isLocal()) 164 return RE_MIPS_GOT_LOCAL_PAGE; 165 [[fallthrough]]; 166 case R_MIPS_CALL16: 167 case R_MIPS_GOT_DISP: 168 case R_MIPS_TLS_GOTTPREL: 169 case R_MICROMIPS_CALL16: 170 case R_MICROMIPS_TLS_GOTTPREL: 171 return RE_MIPS_GOT_OFF; 172 case R_MIPS_CALL_HI16: 173 case R_MIPS_CALL_LO16: 174 case R_MIPS_GOT_HI16: 175 case R_MIPS_GOT_LO16: 176 case R_MICROMIPS_CALL_HI16: 177 case R_MICROMIPS_CALL_LO16: 178 case R_MICROMIPS_GOT_HI16: 179 case R_MICROMIPS_GOT_LO16: 180 return RE_MIPS_GOT_OFF32; 181 case R_MIPS_GOT_PAGE: 182 return RE_MIPS_GOT_LOCAL_PAGE; 183 case R_MIPS_TLS_GD: 184 case R_MICROMIPS_TLS_GD: 185 return RE_MIPS_TLSGD; 186 case R_MIPS_TLS_LDM: 187 case R_MICROMIPS_TLS_LDM: 188 return RE_MIPS_TLSLD; 189 case R_MIPS_NONE: 190 return R_NONE; 191 default: 192 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v 193 << ") against symbol " << &s; 194 return R_NONE; 195 } 196 } 197 198 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { 199 if (type == symbolicRel) 200 return type; 201 return R_MIPS_NONE; 202 } 203 204 template <class ELFT> 205 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { 206 uint64_t va = ctx.in.plt->getVA(); 207 if (isMicroMips(ctx)) 208 va |= 1; 209 write32(ctx, buf, va); 210 } 211 212 template <endianness E> 213 static uint32_t readShuffle(Ctx &ctx, const uint8_t *loc) { 214 // The major opcode of a microMIPS instruction needs to appear 215 // in the first 16-bit word (lowest address) for efficient hardware 216 // decode so that it knows if the instruction is 16-bit or 32-bit 217 // as early as possible. To do so, little-endian binaries keep 16-bit 218 // words in a big-endian order. That is why we have to swap these 219 // words to get a correct value. 220 uint32_t v = read32(ctx, loc); 221 if (E == llvm::endianness::little) 222 return (v << 16) | (v >> 16); 223 return v; 224 } 225 226 static void writeValue(Ctx &ctx, uint8_t *loc, uint64_t v, uint8_t bitsSize, 227 uint8_t shift) { 228 uint32_t instr = read32(ctx, loc); 229 uint32_t mask = 0xffffffff >> (32 - bitsSize); 230 uint32_t data = (instr & ~mask) | ((v >> shift) & mask); 231 write32(ctx, loc, data); 232 } 233 234 template <endianness E> 235 static void writeShuffle(Ctx &ctx, uint8_t *loc, uint64_t v, uint8_t bitsSize, 236 uint8_t shift) { 237 // See comments in readShuffle for purpose of this code. 238 uint16_t *words = (uint16_t *)loc; 239 if (E == llvm::endianness::little) 240 std::swap(words[0], words[1]); 241 242 writeValue(ctx, loc, v, bitsSize, shift); 243 244 if (E == llvm::endianness::little) 245 std::swap(words[0], words[1]); 246 } 247 248 template <endianness E> 249 static void writeMicroRelocation16(Ctx &ctx, uint8_t *loc, uint64_t v, 250 uint8_t bitsSize, uint8_t shift) { 251 uint16_t instr = read16(ctx, loc); 252 uint16_t mask = 0xffff >> (16 - bitsSize); 253 uint16_t data = (instr & ~mask) | ((v >> shift) & mask); 254 write16(ctx, loc, data); 255 } 256 257 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { 258 if (isMicroMips(ctx)) { 259 uint64_t gotPlt = ctx.in.gotPlt->getVA(); 260 uint64_t plt = ctx.in.plt->getVA(); 261 // Overwrite trap instructions written by Writer::writeTrapInstr. 262 memset(buf, 0, pltHeaderSize); 263 264 write16(ctx, buf, 265 isMipsR6(ctx) ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 266 write16(ctx, buf + 4, 0xff23); // lw $25, 0($3) 267 write16(ctx, buf + 8, 0x0535); // subu16 $2, $2, $3 268 write16(ctx, buf + 10, 0x2525); // srl16 $2, $2, 2 269 write16(ctx, buf + 12, 0x3302); // addiu $24, $2, -2 270 write16(ctx, buf + 14, 0xfffe); 271 write16(ctx, buf + 16, 0x0dff); // move $15, $31 272 if (isMipsR6(ctx)) { 273 write16(ctx, buf + 18, 0x0f83); // move $28, $3 274 write16(ctx, buf + 20, 0x472b); // jalrc $25 275 write16(ctx, buf + 22, 0x0c00); // nop 276 relocateNoSym(buf, R_MICROMIPS_PC19_S2, gotPlt - plt); 277 } else { 278 write16(ctx, buf + 18, 0x45f9); // jalrc $25 279 write16(ctx, buf + 20, 0x0f83); // move $28, $3 280 write16(ctx, buf + 22, 0x0c00); // nop 281 relocateNoSym(buf, R_MICROMIPS_PC23_S2, gotPlt - plt); 282 } 283 return; 284 } 285 286 if (ctx.arg.mipsN32Abi) { 287 write32(ctx, buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 288 write32(ctx, buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 289 write32(ctx, buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 290 write32(ctx, buf + 12, 0x030ec023); // subu $24, $24, $14 291 write32(ctx, buf + 16, 0x03e07825); // move $15, $31 292 write32(ctx, buf + 20, 0x0018c082); // srl $24, $24, 2 293 } else if (ELFT::Is64Bits) { 294 write32(ctx, buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 295 write32(ctx, buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 296 write32(ctx, buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 297 write32(ctx, buf + 12, 0x030ec023); // subu $24, $24, $14 298 write32(ctx, buf + 16, 0x03e07825); // move $15, $31 299 write32(ctx, buf + 20, 0x0018c0c2); // srl $24, $24, 3 300 } else { 301 write32(ctx, buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 302 write32(ctx, buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 303 write32(ctx, buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 304 write32(ctx, buf + 12, 0x031cc023); // subu $24, $24, $28 305 write32(ctx, buf + 16, 0x03e07825); // move $15, $31 306 write32(ctx, buf + 20, 0x0018c082); // srl $24, $24, 2 307 } 308 309 uint32_t jalrInst = ctx.arg.zHazardplt ? 0x0320fc09 : 0x0320f809; 310 write32(ctx, buf + 24, jalrInst); // jalr.hb $25 or jalr $25 311 write32(ctx, buf + 28, 0x2718fffe); // subu $24, $24, 2 312 313 uint64_t gotPlt = ctx.in.gotPlt->getVA(); 314 writeValue(ctx, buf, gotPlt + 0x8000, 16, 16); 315 writeValue(ctx, buf + 4, gotPlt, 16, 0); 316 writeValue(ctx, buf + 8, gotPlt, 16, 0); 317 } 318 319 template <class ELFT> 320 void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym, 321 uint64_t pltEntryAddr) const { 322 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx); 323 if (isMicroMips(ctx)) { 324 // Overwrite trap instructions written by Writer::writeTrapInstr. 325 memset(buf, 0, pltEntrySize); 326 327 if (isMipsR6(ctx)) { 328 write16(ctx, buf, 0x7840); // addiupc $2, (GOTPLT) - . 329 write16(ctx, buf + 4, 0xff22); // lw $25, 0($2) 330 write16(ctx, buf + 8, 0x0f02); // move $24, $2 331 write16(ctx, buf + 10, 0x4723); // jrc $25 / jr16 $25 332 relocateNoSym(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr); 333 } else { 334 write16(ctx, buf, 0x7900); // addiupc $2, (GOTPLT) - . 335 write16(ctx, buf + 4, 0xff22); // lw $25, 0($2) 336 write16(ctx, buf + 8, 0x4599); // jrc $25 / jr16 $25 337 write16(ctx, buf + 10, 0x0f02); // move $24, $2 338 relocateNoSym(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr); 339 } 340 return; 341 } 342 343 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000; 344 uint32_t jrInst = isMipsR6(ctx) 345 ? (ctx.arg.zHazardplt ? 0x03200409 : 0x03200009) 346 : (ctx.arg.zHazardplt ? 0x03200408 : 0x03200008); 347 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000; 348 349 write32(ctx, buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 350 write32(ctx, buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15) 351 write32(ctx, buf + 8, jrInst); // jr $25 / jr.hb $25 352 write32(ctx, buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry) 353 writeValue(ctx, buf, gotPltEntryAddr + 0x8000, 16, 16); 354 writeValue(ctx, buf + 4, gotPltEntryAddr, 16, 0); 355 writeValue(ctx, buf + 12, gotPltEntryAddr, 16, 0); 356 } 357 358 template <class ELFT> 359 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, 360 uint64_t branchAddr, const Symbol &s, 361 int64_t /*a*/) const { 362 // Any MIPS PIC code function is invoked with its address in register $t9. 363 // So if we have a branch instruction from non-PIC code to the PIC one 364 // we cannot make the jump directly and need to create a small stubs 365 // to save the target function address. 366 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 367 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 && 368 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1) 369 return false; 370 auto *f = dyn_cast<ObjFile<ELFT>>(file); 371 if (!f) 372 return false; 373 // If current file has PIC code, LA25 stub is not required. 374 if (f->getObj().getHeader().e_flags & EF_MIPS_PIC) 375 return false; 376 auto *d = dyn_cast<Defined>(&s); 377 // LA25 is required if target file has PIC code 378 // or target symbol is a PIC symbol. 379 return d && isMipsPIC<ELFT>(d); 380 } 381 382 template <class ELFT> 383 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const { 384 const endianness e = ELFT::Endianness; 385 switch (type) { 386 case R_MIPS_32: 387 case R_MIPS_REL32: 388 case R_MIPS_GPREL32: 389 case R_MIPS_TLS_DTPREL32: 390 case R_MIPS_TLS_DTPMOD32: 391 case R_MIPS_TLS_TPREL32: 392 return SignExtend64<32>(read32(ctx, buf)); 393 case R_MIPS_26: 394 // FIXME (simon): If the relocation target symbol is not a PLT entry 395 // we should use another expression for calculation: 396 // ((A << 2) | (P & 0xf0000000)) >> 2 397 return SignExtend64<28>(read32(ctx, buf) << 2); 398 case R_MIPS_CALL_HI16: 399 case R_MIPS_GOT16: 400 case R_MIPS_GOT_HI16: 401 case R_MIPS_HI16: 402 case R_MIPS_PCHI16: 403 return SignExtend64<16>(read32(ctx, buf)) << 16; 404 case R_MIPS_CALL16: 405 case R_MIPS_CALL_LO16: 406 case R_MIPS_GOT_LO16: 407 case R_MIPS_GPREL16: 408 case R_MIPS_LO16: 409 case R_MIPS_PCLO16: 410 case R_MIPS_TLS_DTPREL_HI16: 411 case R_MIPS_TLS_DTPREL_LO16: 412 case R_MIPS_TLS_GD: 413 case R_MIPS_TLS_GOTTPREL: 414 case R_MIPS_TLS_LDM: 415 case R_MIPS_TLS_TPREL_HI16: 416 case R_MIPS_TLS_TPREL_LO16: 417 return SignExtend64<16>(read32(ctx, buf)); 418 case R_MICROMIPS_GOT16: 419 case R_MICROMIPS_HI16: 420 return SignExtend64<16>(readShuffle<e>(ctx, buf)) << 16; 421 case R_MICROMIPS_CALL16: 422 case R_MICROMIPS_GPREL16: 423 case R_MICROMIPS_LO16: 424 case R_MICROMIPS_TLS_DTPREL_HI16: 425 case R_MICROMIPS_TLS_DTPREL_LO16: 426 case R_MICROMIPS_TLS_GD: 427 case R_MICROMIPS_TLS_GOTTPREL: 428 case R_MICROMIPS_TLS_LDM: 429 case R_MICROMIPS_TLS_TPREL_HI16: 430 case R_MICROMIPS_TLS_TPREL_LO16: 431 return SignExtend64<16>(readShuffle<e>(ctx, buf)); 432 case R_MICROMIPS_GPREL7_S2: 433 return SignExtend64<9>(readShuffle<e>(ctx, buf) << 2); 434 case R_MIPS_PC16: 435 return SignExtend64<18>(read32(ctx, buf) << 2); 436 case R_MIPS_PC19_S2: 437 return SignExtend64<21>(read32(ctx, buf) << 2); 438 case R_MIPS_PC21_S2: 439 return SignExtend64<23>(read32(ctx, buf) << 2); 440 case R_MIPS_PC26_S2: 441 return SignExtend64<28>(read32(ctx, buf) << 2); 442 case R_MIPS_PC32: 443 return SignExtend64<32>(read32(ctx, buf)); 444 case R_MICROMIPS_26_S1: 445 return SignExtend64<27>(readShuffle<e>(ctx, buf) << 1); 446 case R_MICROMIPS_PC7_S1: 447 return SignExtend64<8>(read16(ctx, buf) << 1); 448 case R_MICROMIPS_PC10_S1: 449 return SignExtend64<11>(read16(ctx, buf) << 1); 450 case R_MICROMIPS_PC16_S1: 451 return SignExtend64<17>(readShuffle<e>(ctx, buf) << 1); 452 case R_MICROMIPS_PC18_S3: 453 return SignExtend64<21>(readShuffle<e>(ctx, buf) << 3); 454 case R_MICROMIPS_PC19_S2: 455 return SignExtend64<21>(readShuffle<e>(ctx, buf) << 2); 456 case R_MICROMIPS_PC21_S1: 457 return SignExtend64<22>(readShuffle<e>(ctx, buf) << 1); 458 case R_MICROMIPS_PC23_S2: 459 return SignExtend64<25>(readShuffle<e>(ctx, buf) << 2); 460 case R_MICROMIPS_PC26_S1: 461 return SignExtend64<27>(readShuffle<e>(ctx, buf) << 1); 462 case R_MIPS_64: 463 case R_MIPS_TLS_DTPMOD64: 464 case R_MIPS_TLS_DTPREL64: 465 case R_MIPS_TLS_TPREL64: 466 case (R_MIPS_64 << 8) | R_MIPS_REL32: 467 return read64(ctx, buf); 468 case R_MIPS_COPY: 469 return ctx.arg.is64 ? read64(ctx, buf) : read32(ctx, buf); 470 case R_MIPS_NONE: 471 case R_MIPS_JUMP_SLOT: 472 case R_MIPS_JALR: 473 // These relocations are defined as not having an implicit addend. 474 return 0; 475 default: 476 InternalErr(ctx, buf) << "cannot read addend for relocation " << type; 477 return 0; 478 } 479 } 480 481 static std::pair<uint32_t, uint64_t> 482 calculateMipsRelChain(Ctx &ctx, uint8_t *loc, uint32_t type, uint64_t val) { 483 // MIPS N64 ABI packs multiple relocations into the single relocation 484 // record. In general, all up to three relocations can have arbitrary 485 // types. In fact, Clang and GCC uses only a few combinations. For now, 486 // we support two of them. That is allow to pass at least all LLVM 487 // test suite cases. 488 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 489 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 490 // The first relocation is a 'real' relocation which is calculated 491 // using the corresponding symbol's value. The second and the third 492 // relocations used to modify result of the first one: extend it to 493 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 494 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 495 uint32_t type2 = (type >> 8) & 0xff; 496 uint32_t type3 = (type >> 16) & 0xff; 497 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE) 498 return std::make_pair(type, val); 499 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE) 500 return std::make_pair(type2, val); 501 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16)) 502 return std::make_pair(type3, -val); 503 Err(ctx) << getErrorLoc(ctx, loc) << "unsupported relocations combination " 504 << type; 505 return std::make_pair(type & 0xff, val); 506 } 507 508 static bool isBranchReloc(RelType type) { 509 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 || 510 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16; 511 } 512 513 static bool isMicroBranchReloc(RelType type) { 514 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 || 515 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1; 516 } 517 518 template <class ELFT> 519 static uint64_t fixupCrossModeJump(Ctx &ctx, uint8_t *loc, RelType type, 520 uint64_t val) { 521 // Here we need to detect jump/branch from regular MIPS code 522 // to a microMIPS target and vice versa. In that cases jump 523 // instructions need to be replaced by their "cross-mode" 524 // equivalents. 525 const endianness e = ELFT::Endianness; 526 bool isMicroTgt = val & 0x1; 527 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) || 528 (!isMicroTgt && isMicroBranchReloc(type)); 529 if (!isCrossJump) 530 return val; 531 532 switch (type) { 533 case R_MIPS_26: { 534 uint32_t inst = read32(ctx, loc) >> 26; 535 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX 536 writeValue(ctx, loc, 0x1d << 26, 32, 0); 537 return val; 538 } 539 break; 540 } 541 case R_MICROMIPS_26_S1: { 542 uint32_t inst = readShuffle<e>(ctx, loc) >> 26; 543 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32 544 val >>= 1; 545 writeShuffle<e>(ctx, loc, 0x3c << 26, 32, 0); 546 return val; 547 } 548 break; 549 } 550 case R_MIPS_PC26_S2: 551 case R_MIPS_PC21_S2: 552 case R_MIPS_PC16: 553 case R_MICROMIPS_PC16_S1: 554 case R_MICROMIPS_PC10_S1: 555 case R_MICROMIPS_PC7_S1: 556 // FIXME (simon): Support valid branch relocations. 557 break; 558 default: 559 llvm_unreachable("unexpected jump/branch relocation"); 560 } 561 562 ErrAlways(ctx) 563 << getErrorLoc(ctx, loc) 564 << "unsupported jump/branch instruction between ISA modes referenced by " 565 << type << " relocation"; 566 return val; 567 } 568 569 template <class ELFT> 570 void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel, 571 uint64_t val) const { 572 const endianness e = ELFT::Endianness; 573 RelType type = rel.type; 574 575 if (ELFT::Is64Bits || ctx.arg.mipsN32Abi) 576 std::tie(type, val) = calculateMipsRelChain(ctx, loc, type, val); 577 578 // Detect cross-mode jump/branch and fix instruction. 579 val = fixupCrossModeJump<ELFT>(ctx, loc, type, val); 580 581 // Thread pointer and DRP offsets from the start of TLS data area. 582 // https://www.linux-mips.org/wiki/NPTL 583 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 || 584 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 || 585 type == R_MICROMIPS_TLS_DTPREL_HI16 || 586 type == R_MICROMIPS_TLS_DTPREL_LO16) { 587 val -= 0x8000; 588 } 589 590 switch (type) { 591 case R_MIPS_32: 592 case R_MIPS_GPREL32: 593 case R_MIPS_TLS_DTPREL32: 594 case R_MIPS_TLS_TPREL32: 595 write32(ctx, loc, val); 596 break; 597 case R_MIPS_64: 598 case R_MIPS_TLS_DTPREL64: 599 case R_MIPS_TLS_TPREL64: 600 write64(ctx, loc, val); 601 break; 602 case R_MIPS_26: 603 writeValue(ctx, loc, val, 26, 2); 604 break; 605 case R_MIPS_GOT16: 606 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 607 // is updated addend (not a GOT index). In that case write high 16 bits 608 // to store a correct addend value. 609 if (ctx.arg.relocatable) { 610 writeValue(ctx, loc, val + 0x8000, 16, 16); 611 } else { 612 checkInt(ctx, loc, val, 16, rel); 613 writeValue(ctx, loc, val, 16, 0); 614 } 615 break; 616 case R_MICROMIPS_GOT16: 617 if (ctx.arg.relocatable) { 618 writeShuffle<e>(ctx, loc, val + 0x8000, 16, 16); 619 } else { 620 checkInt(ctx, loc, val, 16, rel); 621 writeShuffle<e>(ctx, loc, val, 16, 0); 622 } 623 break; 624 case R_MIPS_CALL16: 625 case R_MIPS_GOT_DISP: 626 case R_MIPS_GOT_PAGE: 627 case R_MIPS_GPREL16: 628 case R_MIPS_TLS_GD: 629 case R_MIPS_TLS_GOTTPREL: 630 case R_MIPS_TLS_LDM: 631 checkInt(ctx, loc, val, 16, rel); 632 [[fallthrough]]; 633 case R_MIPS_CALL_LO16: 634 case R_MIPS_GOT_LO16: 635 case R_MIPS_GOT_OFST: 636 case R_MIPS_LO16: 637 case R_MIPS_PCLO16: 638 case R_MIPS_TLS_DTPREL_LO16: 639 case R_MIPS_TLS_TPREL_LO16: 640 writeValue(ctx, loc, val, 16, 0); 641 break; 642 case R_MICROMIPS_GPREL16: 643 case R_MICROMIPS_TLS_GD: 644 case R_MICROMIPS_TLS_LDM: 645 checkInt(ctx, loc, val, 16, rel); 646 writeShuffle<e>(ctx, loc, val, 16, 0); 647 break; 648 case R_MICROMIPS_CALL16: 649 case R_MICROMIPS_CALL_LO16: 650 case R_MICROMIPS_LO16: 651 case R_MICROMIPS_TLS_DTPREL_LO16: 652 case R_MICROMIPS_TLS_GOTTPREL: 653 case R_MICROMIPS_TLS_TPREL_LO16: 654 writeShuffle<e>(ctx, loc, val, 16, 0); 655 break; 656 case R_MICROMIPS_GPREL7_S2: 657 checkInt(ctx, loc, val, 7, rel); 658 writeShuffle<e>(ctx, loc, val, 7, 2); 659 break; 660 case R_MIPS_CALL_HI16: 661 case R_MIPS_GOT_HI16: 662 case R_MIPS_HI16: 663 case R_MIPS_PCHI16: 664 case R_MIPS_TLS_DTPREL_HI16: 665 case R_MIPS_TLS_TPREL_HI16: 666 writeValue(ctx, loc, val + 0x8000, 16, 16); 667 break; 668 case R_MICROMIPS_CALL_HI16: 669 case R_MICROMIPS_GOT_HI16: 670 case R_MICROMIPS_HI16: 671 case R_MICROMIPS_TLS_DTPREL_HI16: 672 case R_MICROMIPS_TLS_TPREL_HI16: 673 writeShuffle<e>(ctx, loc, val + 0x8000, 16, 16); 674 break; 675 case R_MIPS_HIGHER: 676 writeValue(ctx, loc, val + 0x80008000, 16, 32); 677 break; 678 case R_MIPS_HIGHEST: 679 writeValue(ctx, loc, val + 0x800080008000, 16, 48); 680 break; 681 case R_MIPS_JALR: 682 val -= 4; 683 // Replace jalr/jr instructions by bal/b if the target 684 // offset fits into the 18-bit range. 685 if (isInt<18>(val)) { 686 switch (read32(ctx, loc)) { 687 case 0x0320f809: // jalr $25 => bal sym 688 write32(ctx, loc, 0x04110000 | ((val >> 2) & 0xffff)); 689 break; 690 case 0x03200008: // jr $25 => b sym 691 write32(ctx, loc, 0x10000000 | ((val >> 2) & 0xffff)); 692 break; 693 } 694 } 695 break; 696 case R_MICROMIPS_JALR: 697 // Ignore this optimization relocation for now 698 break; 699 case R_MIPS_PC16: 700 checkAlignment(ctx, loc, val, 4, rel); 701 checkInt(ctx, loc, val, 18, rel); 702 writeValue(ctx, loc, val, 16, 2); 703 break; 704 case R_MIPS_PC19_S2: 705 checkAlignment(ctx, loc, val, 4, rel); 706 checkInt(ctx, loc, val, 21, rel); 707 writeValue(ctx, loc, val, 19, 2); 708 break; 709 case R_MIPS_PC21_S2: 710 checkAlignment(ctx, loc, val, 4, rel); 711 checkInt(ctx, loc, val, 23, rel); 712 writeValue(ctx, loc, val, 21, 2); 713 break; 714 case R_MIPS_PC26_S2: 715 checkAlignment(ctx, loc, val, 4, rel); 716 checkInt(ctx, loc, val, 28, rel); 717 writeValue(ctx, loc, val, 26, 2); 718 break; 719 case R_MIPS_PC32: 720 writeValue(ctx, loc, val, 32, 0); 721 break; 722 case R_MICROMIPS_26_S1: 723 case R_MICROMIPS_PC26_S1: 724 checkInt(ctx, loc, val, 27, rel); 725 writeShuffle<e>(ctx, loc, val, 26, 1); 726 break; 727 case R_MICROMIPS_PC7_S1: 728 checkInt(ctx, loc, val, 8, rel); 729 writeMicroRelocation16<e>(ctx, loc, val, 7, 1); 730 break; 731 case R_MICROMIPS_PC10_S1: 732 checkInt(ctx, loc, val, 11, rel); 733 writeMicroRelocation16<e>(ctx, loc, val, 10, 1); 734 break; 735 case R_MICROMIPS_PC16_S1: 736 checkInt(ctx, loc, val, 17, rel); 737 writeShuffle<e>(ctx, loc, val, 16, 1); 738 break; 739 case R_MICROMIPS_PC18_S3: 740 checkInt(ctx, loc, val, 21, rel); 741 writeShuffle<e>(ctx, loc, val, 18, 3); 742 break; 743 case R_MICROMIPS_PC19_S2: 744 checkInt(ctx, loc, val, 21, rel); 745 writeShuffle<e>(ctx, loc, val, 19, 2); 746 break; 747 case R_MICROMIPS_PC21_S1: 748 checkInt(ctx, loc, val, 22, rel); 749 writeShuffle<e>(ctx, loc, val, 21, 1); 750 break; 751 case R_MICROMIPS_PC23_S2: 752 checkInt(ctx, loc, val, 25, rel); 753 writeShuffle<e>(ctx, loc, val, 23, 2); 754 break; 755 default: 756 llvm_unreachable("unknown relocation"); 757 } 758 } 759 760 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const { 761 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST || 762 type == R_MICROMIPS_LO16; 763 } 764 765 // Return true if the symbol is a PIC function. 766 template <class ELFT> bool elf::isMipsPIC(const Defined *sym) { 767 if (!sym->isFunc()) 768 return false; 769 770 if (sym->stOther & STO_MIPS_PIC) 771 return true; 772 773 if (!sym->section) 774 return false; 775 776 InputFile *file = cast<InputSectionBase>(sym->section)->file; 777 if (!file || file->isInternal()) 778 return false; 779 780 return cast<ObjFile<ELFT>>(file)->getObj().getHeader().e_flags & EF_MIPS_PIC; 781 } 782 783 void elf::setMipsTargetInfo(Ctx &ctx) { 784 switch (ctx.arg.ekind) { 785 case ELF32LEKind: { 786 ctx.target.reset(new MIPS<ELF32LE>(ctx)); 787 return; 788 } 789 case ELF32BEKind: { 790 ctx.target.reset(new MIPS<ELF32BE>(ctx)); 791 return; 792 } 793 case ELF64LEKind: { 794 ctx.target.reset(new MIPS<ELF64LE>(ctx)); 795 return; 796 } 797 case ELF64BEKind: { 798 ctx.target.reset(new MIPS<ELF64BE>(ctx)); 799 return; 800 } 801 default: 802 llvm_unreachable("unsupported target"); 803 } 804 } 805 806 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 807 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 808 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 809 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 810