1 //===-- Hexagon.cpp -------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/Object/ELF.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 using namespace llvm::object; 20 using namespace llvm::support::endian; 21 using namespace llvm::ELF; 22 using namespace lld; 23 using namespace lld::elf; 24 25 namespace { 26 class Hexagon final : public TargetInfo { 27 public: 28 Hexagon(); 29 uint32_t calcEFlags() const override; 30 RelExpr getRelExpr(RelType type, const Symbol &s, 31 const uint8_t *loc) const override; 32 RelType getDynRel(RelType type) const override; 33 void relocate(uint8_t *loc, const Relocation &rel, 34 uint64_t val) const override; 35 void writePltHeader(uint8_t *buf) const override; 36 void writePlt(uint8_t *buf, const Symbol &sym, 37 uint64_t pltEntryAddr) const override; 38 }; 39 } // namespace 40 41 Hexagon::Hexagon() { 42 pltRel = R_HEX_JMP_SLOT; 43 relativeRel = R_HEX_RELATIVE; 44 gotRel = R_HEX_GLOB_DAT; 45 symbolicRel = R_HEX_32; 46 47 gotBaseSymInGotPlt = true; 48 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The 49 // next 3 are reserved for the dynamic loader. 50 gotPltHeaderEntriesNum = 4; 51 52 pltEntrySize = 16; 53 pltHeaderSize = 32; 54 55 // Hexagon Linux uses 64K pages by default. 56 defaultMaxPageSize = 0x10000; 57 tlsGotRel = R_HEX_TPREL_32; 58 tlsModuleIndexRel = R_HEX_DTPMOD_32; 59 tlsOffsetRel = R_HEX_DTPREL_32; 60 } 61 62 uint32_t Hexagon::calcEFlags() const { 63 assert(!objectFiles.empty()); 64 65 // The architecture revision must always be equal to or greater than 66 // greatest revision in the list of inputs. 67 uint32_t ret = 0; 68 for (InputFile *f : objectFiles) { 69 uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags; 70 if (eflags > ret) 71 ret = eflags; 72 } 73 return ret; 74 } 75 76 static uint32_t applyMask(uint32_t mask, uint32_t data) { 77 uint32_t result = 0; 78 size_t off = 0; 79 80 for (size_t bit = 0; bit != 32; ++bit) { 81 uint32_t valBit = (data >> off) & 1; 82 uint32_t maskBit = (mask >> bit) & 1; 83 if (maskBit) { 84 result |= (valBit << bit); 85 ++off; 86 } 87 } 88 return result; 89 } 90 91 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s, 92 const uint8_t *loc) const { 93 switch (type) { 94 case R_HEX_NONE: 95 return R_NONE; 96 case R_HEX_6_X: 97 case R_HEX_8_X: 98 case R_HEX_9_X: 99 case R_HEX_10_X: 100 case R_HEX_11_X: 101 case R_HEX_12_X: 102 case R_HEX_16_X: 103 case R_HEX_32: 104 case R_HEX_32_6_X: 105 case R_HEX_HI16: 106 case R_HEX_LO16: 107 case R_HEX_DTPREL_32: 108 return R_ABS; 109 case R_HEX_B9_PCREL: 110 case R_HEX_B13_PCREL: 111 case R_HEX_B15_PCREL: 112 case R_HEX_6_PCREL_X: 113 case R_HEX_32_PCREL: 114 return R_PC; 115 case R_HEX_B9_PCREL_X: 116 case R_HEX_B15_PCREL_X: 117 case R_HEX_B22_PCREL: 118 case R_HEX_PLT_B22_PCREL: 119 case R_HEX_B22_PCREL_X: 120 case R_HEX_B32_PCREL_X: 121 case R_HEX_GD_PLT_B22_PCREL: 122 case R_HEX_GD_PLT_B22_PCREL_X: 123 case R_HEX_GD_PLT_B32_PCREL_X: 124 return R_PLT_PC; 125 case R_HEX_IE_32_6_X: 126 case R_HEX_IE_16_X: 127 case R_HEX_IE_HI16: 128 case R_HEX_IE_LO16: 129 return R_GOT; 130 case R_HEX_GD_GOT_11_X: 131 case R_HEX_GD_GOT_16_X: 132 case R_HEX_GD_GOT_32_6_X: 133 return R_TLSGD_GOTPLT; 134 case R_HEX_GOTREL_11_X: 135 case R_HEX_GOTREL_16_X: 136 case R_HEX_GOTREL_32_6_X: 137 case R_HEX_GOTREL_HI16: 138 case R_HEX_GOTREL_LO16: 139 return R_GOTPLTREL; 140 case R_HEX_GOT_11_X: 141 case R_HEX_GOT_16_X: 142 case R_HEX_GOT_32_6_X: 143 return R_GOTPLT; 144 case R_HEX_IE_GOT_11_X: 145 case R_HEX_IE_GOT_16_X: 146 case R_HEX_IE_GOT_32_6_X: 147 case R_HEX_IE_GOT_HI16: 148 case R_HEX_IE_GOT_LO16: 149 config->hasTlsIe = true; 150 return R_GOTPLT; 151 case R_HEX_TPREL_11_X: 152 case R_HEX_TPREL_16: 153 case R_HEX_TPREL_16_X: 154 case R_HEX_TPREL_32_6_X: 155 case R_HEX_TPREL_HI16: 156 case R_HEX_TPREL_LO16: 157 return R_TPREL; 158 default: 159 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 160 ") against symbol " + toString(s)); 161 return R_NONE; 162 } 163 } 164 165 // There are (arguably too) many relocation masks for the DSP's 166 // R_HEX_6_X type. The table below is used to select the correct mask 167 // for the given instruction. 168 struct InstructionMask { 169 uint32_t cmpMask; 170 uint32_t relocMask; 171 }; 172 static const InstructionMask r6[] = { 173 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 174 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 175 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 176 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, 177 {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0}, 178 {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0}, 179 {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000}, 180 {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60}, 181 {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60}, 182 {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f}, 183 {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078}, 184 {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0}, 185 {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}}; 186 187 static bool isDuplex(uint32_t insn) { 188 // Duplex forms have a fixed mask and parse bits 15:14 are always 189 // zero. Non-duplex insns will always have at least one bit set in the 190 // parse field. 191 return (0xC000 & insn) == 0; 192 } 193 194 static uint32_t findMaskR6(uint32_t insn) { 195 if (isDuplex(insn)) 196 return 0x03f00000; 197 198 for (InstructionMask i : r6) 199 if ((0xff000000 & insn) == i.cmpMask) 200 return i.relocMask; 201 202 error("unrecognized instruction for 6_X relocation: 0x" + 203 utohexstr(insn)); 204 return 0; 205 } 206 207 static uint32_t findMaskR8(uint32_t insn) { 208 if ((0xff000000 & insn) == 0xde000000) 209 return 0x00e020e8; 210 if ((0xff000000 & insn) == 0x3c000000) 211 return 0x0000207f; 212 return 0x00001fe0; 213 } 214 215 static uint32_t findMaskR11(uint32_t insn) { 216 if ((0xff000000 & insn) == 0xa1000000) 217 return 0x060020ff; 218 return 0x06003fe0; 219 } 220 221 static uint32_t findMaskR16(uint32_t insn) { 222 if ((0xff000000 & insn) == 0x48000000) 223 return 0x061f20ff; 224 if ((0xff000000 & insn) == 0x49000000) 225 return 0x061f3fe0; 226 if ((0xff000000 & insn) == 0x78000000) 227 return 0x00df3fe0; 228 if ((0xff000000 & insn) == 0xb0000000) 229 return 0x0fe03fe0; 230 231 if (isDuplex(insn)) 232 return 0x03f00000; 233 234 for (InstructionMask i : r6) 235 if ((0xff000000 & insn) == i.cmpMask) 236 return i.relocMask; 237 238 error("unrecognized instruction for 16_X type: 0x" + 239 utohexstr(insn)); 240 return 0; 241 } 242 243 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 244 245 void Hexagon::relocate(uint8_t *loc, const Relocation &rel, 246 uint64_t val) const { 247 switch (rel.type) { 248 case R_HEX_NONE: 249 break; 250 case R_HEX_6_PCREL_X: 251 case R_HEX_6_X: 252 or32le(loc, applyMask(findMaskR6(read32le(loc)), val)); 253 break; 254 case R_HEX_8_X: 255 or32le(loc, applyMask(findMaskR8(read32le(loc)), val)); 256 break; 257 case R_HEX_9_X: 258 or32le(loc, applyMask(0x00003fe0, val & 0x3f)); 259 break; 260 case R_HEX_10_X: 261 or32le(loc, applyMask(0x00203fe0, val & 0x3f)); 262 break; 263 case R_HEX_11_X: 264 case R_HEX_GD_GOT_11_X: 265 case R_HEX_IE_GOT_11_X: 266 case R_HEX_GOT_11_X: 267 case R_HEX_GOTREL_11_X: 268 case R_HEX_TPREL_11_X: 269 or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f)); 270 break; 271 case R_HEX_12_X: 272 or32le(loc, applyMask(0x000007e0, val)); 273 break; 274 case R_HEX_16_X: // These relocs only have 6 effective bits. 275 case R_HEX_IE_16_X: 276 case R_HEX_IE_GOT_16_X: 277 case R_HEX_GD_GOT_16_X: 278 case R_HEX_GOT_16_X: 279 case R_HEX_GOTREL_16_X: 280 case R_HEX_TPREL_16_X: 281 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f)); 282 break; 283 case R_HEX_TPREL_16: 284 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0xffff)); 285 break; 286 case R_HEX_32: 287 case R_HEX_32_PCREL: 288 case R_HEX_DTPREL_32: 289 or32le(loc, val); 290 break; 291 case R_HEX_32_6_X: 292 case R_HEX_GD_GOT_32_6_X: 293 case R_HEX_GOT_32_6_X: 294 case R_HEX_GOTREL_32_6_X: 295 case R_HEX_IE_GOT_32_6_X: 296 case R_HEX_IE_32_6_X: 297 case R_HEX_TPREL_32_6_X: 298 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 299 break; 300 case R_HEX_B9_PCREL: 301 checkInt(loc, val, 11, rel); 302 or32le(loc, applyMask(0x003000fe, val >> 2)); 303 break; 304 case R_HEX_B9_PCREL_X: 305 or32le(loc, applyMask(0x003000fe, val & 0x3f)); 306 break; 307 case R_HEX_B13_PCREL: 308 checkInt(loc, val, 15, rel); 309 or32le(loc, applyMask(0x00202ffe, val >> 2)); 310 break; 311 case R_HEX_B15_PCREL: 312 checkInt(loc, val, 17, rel); 313 or32le(loc, applyMask(0x00df20fe, val >> 2)); 314 break; 315 case R_HEX_B15_PCREL_X: 316 or32le(loc, applyMask(0x00df20fe, val & 0x3f)); 317 break; 318 case R_HEX_B22_PCREL: 319 case R_HEX_GD_PLT_B22_PCREL: 320 case R_HEX_PLT_B22_PCREL: 321 checkInt(loc, val, 22, rel); 322 or32le(loc, applyMask(0x1ff3ffe, val >> 2)); 323 break; 324 case R_HEX_B22_PCREL_X: 325 case R_HEX_GD_PLT_B22_PCREL_X: 326 or32le(loc, applyMask(0x1ff3ffe, val & 0x3f)); 327 break; 328 case R_HEX_B32_PCREL_X: 329 case R_HEX_GD_PLT_B32_PCREL_X: 330 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 331 break; 332 case R_HEX_GOTREL_HI16: 333 case R_HEX_HI16: 334 case R_HEX_IE_GOT_HI16: 335 case R_HEX_IE_HI16: 336 case R_HEX_TPREL_HI16: 337 or32le(loc, applyMask(0x00c03fff, val >> 16)); 338 break; 339 case R_HEX_GOTREL_LO16: 340 case R_HEX_LO16: 341 case R_HEX_IE_GOT_LO16: 342 case R_HEX_IE_LO16: 343 case R_HEX_TPREL_LO16: 344 or32le(loc, applyMask(0x00c03fff, val)); 345 break; 346 default: 347 llvm_unreachable("unknown relocation"); 348 } 349 } 350 351 void Hexagon::writePltHeader(uint8_t *buf) const { 352 const uint8_t pltData[] = { 353 0x00, 0x40, 0x00, 0x00, // { immext (#0) 354 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0 355 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn 356 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2 357 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1 358 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn 359 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker 360 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment 361 }; 362 memcpy(buf, pltData, sizeof(pltData)); 363 364 // Offset from PLT0 to the GOT. 365 uint64_t off = in.gotPlt->getVA() - in.plt->getVA(); 366 relocateNoSym(buf, R_HEX_B32_PCREL_X, off); 367 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, off); 368 } 369 370 void Hexagon::writePlt(uint8_t *buf, const Symbol &sym, 371 uint64_t pltEntryAddr) const { 372 const uint8_t inst[] = { 373 0x00, 0x40, 0x00, 0x00, // { immext (#0) 374 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) } 375 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14) 376 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 377 }; 378 memcpy(buf, inst, sizeof(inst)); 379 380 uint64_t gotPltEntryAddr = sym.getGotPltVA(); 381 relocateNoSym(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr); 382 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr); 383 } 384 385 RelType Hexagon::getDynRel(RelType type) const { 386 if (type == R_HEX_32) 387 return type; 388 return R_HEX_NONE; 389 } 390 391 TargetInfo *elf::getHexagonTargetInfo() { 392 static Hexagon target; 393 return ⌖ 394 } 395