1 //===- ARMErrataFix.cpp ---------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // This file implements Section Patching for the purpose of working around the 9 // Cortex-a8 erratum 657417 "A 32bit branch instruction that spans 2 4K regions 10 // can result in an incorrect instruction fetch or processor deadlock." The 11 // erratum affects all but r1p7, r2p5, r2p6, r3p1 and r3p2 revisions of the 12 // Cortex-A8. A high level description of the patching technique is given in 13 // the opening comment of AArch64ErrataFix.cpp. 14 //===----------------------------------------------------------------------===// 15 16 #include "ARMErrataFix.h" 17 18 #include "Config.h" 19 #include "LinkerScript.h" 20 #include "OutputSections.h" 21 #include "Relocations.h" 22 #include "Symbols.h" 23 #include "SyntheticSections.h" 24 #include "Target.h" 25 #include "lld/Common/CommonLinkerContext.h" 26 #include "lld/Common/Strings.h" 27 #include "llvm/Support/Endian.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <algorithm> 30 31 using namespace llvm; 32 using namespace llvm::ELF; 33 using namespace llvm::object; 34 using namespace llvm::support; 35 using namespace llvm::support::endian; 36 using namespace lld; 37 using namespace lld::elf; 38 39 // The documented title for Erratum 657417 is: 40 // "A 32bit branch instruction that spans two 4K regions can result in an 41 // incorrect instruction fetch or processor deadlock". Graphically using a 42 // 32-bit B.w instruction encoded as a pair of halfwords 0xf7fe 0xbfff 43 // xxxxxx000 // Memory region 1 start 44 // target: 45 // ... 46 // xxxxxxffe f7fe // First halfword of branch to target: 47 // xxxxxx000 // Memory region 2 start 48 // xxxxxx002 bfff // Second halfword of branch to target: 49 // 50 // The specific trigger conditions that can be detected at link time are: 51 // - There is a 32-bit Thumb-2 branch instruction with an address of the form 52 // xxxxxxFFE. The first 2 bytes of the instruction are in 4KiB region 1, the 53 // second 2 bytes are in region 2. 54 // - The branch instruction is one of BLX, BL, B.w BCC.w 55 // - The instruction preceding the branch is a 32-bit non-branch instruction. 56 // - The target of the branch is in region 1. 57 // 58 // The linker mitigation for the fix is to redirect any branch that meets the 59 // erratum conditions to a patch section containing a branch to the target. 60 // 61 // As adding patch sections may move branches onto region boundaries the patch 62 // must iterate until no more patches are added. 63 // 64 // Example, before: 65 // 00000FFA func: NOP.w // 32-bit Thumb function 66 // 00000FFE B.W func // 32-bit branch spanning 2 regions, dest in 1st. 67 // Example, after: 68 // 00000FFA func: NOP.w // 32-bit Thumb function 69 // 00000FFE B.w __CortexA8657417_00000FFE 70 // 00001002 2 - bytes padding 71 // 00001004 __CortexA8657417_00000FFE: B.w func 72 73 class elf::Patch657417Section : public SyntheticSection { 74 public: 75 Patch657417Section(InputSection *p, uint64_t off, uint32_t instr, bool isARM); 76 77 void writeTo(uint8_t *buf) override; 78 79 size_t getSize() const override { return 4; } 80 81 // Get the virtual address of the branch instruction at patcheeOffset. 82 uint64_t getBranchAddr() const; 83 84 static bool classof(const SectionBase *d) { 85 return d->kind() == InputSectionBase::Synthetic && d->name ==".text.patch"; 86 } 87 88 // The Section we are patching. 89 const InputSection *patchee; 90 // The offset of the instruction in the Patchee section we are patching. 91 uint64_t patcheeOffset; 92 // A label for the start of the Patch that we can use as a relocation target. 93 Symbol *patchSym; 94 // A decoding of the branch instruction at patcheeOffset. 95 uint32_t instr; 96 // True If the patch is to be written in ARM state, otherwise the patch will 97 // be written in Thumb state. 98 bool isARM; 99 }; 100 101 // Return true if the half-word, when taken as the first of a pair of halfwords 102 // is the first half of a 32-bit instruction. 103 // Reference from ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition 104 // section A6.3: 32-bit Thumb instruction encoding 105 // | HW1 | HW2 | 106 // | 1 1 1 | op1 (2) | op2 (7) | x (4) |op| x (15) | 107 // With op1 == 0b00, a 16-bit instruction is encoded. 108 // 109 // We test only the first halfword, looking for op != 0b00. 110 static bool is32bitInstruction(uint16_t hw) { 111 return (hw & 0xe000) == 0xe000 && (hw & 0x1800) != 0x0000; 112 } 113 114 // Reference from ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition 115 // section A6.3.4 Branches and miscellaneous control. 116 // | HW1 | HW2 | 117 // | 1 1 1 | 1 0 | op (7) | x (4) | 1 | op1 (3) | op2 (4) | imm8 (8) | 118 // op1 == 0x0 op != x111xxx | Conditional branch (Bcc.W) 119 // op1 == 0x1 | Branch (B.W) 120 // op1 == 1x0 | Branch with Link and Exchange (BLX.w) 121 // op1 == 1x1 | Branch with Link (BL.W) 122 123 static bool isBcc(uint32_t instr) { 124 return (instr & 0xf800d000) == 0xf0008000 && 125 (instr & 0x03800000) != 0x03800000; 126 } 127 128 static bool isB(uint32_t instr) { return (instr & 0xf800d000) == 0xf0009000; } 129 130 static bool isBLX(uint32_t instr) { return (instr & 0xf800d000) == 0xf000c000; } 131 132 static bool isBL(uint32_t instr) { return (instr & 0xf800d000) == 0xf000d000; } 133 134 static bool is32bitBranch(uint32_t instr) { 135 return isBcc(instr) || isB(instr) || isBL(instr) || isBLX(instr); 136 } 137 138 Patch657417Section::Patch657417Section(InputSection *p, uint64_t off, 139 uint32_t instr, bool isARM) 140 : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 4, 141 ".text.patch"), 142 patchee(p), patcheeOffset(off), instr(instr), isARM(isARM) { 143 parent = p->getParent(); 144 patchSym = addSyntheticLocal( 145 saver().save("__CortexA8657417_" + utohexstr(getBranchAddr())), STT_FUNC, 146 isARM ? 0 : 1, getSize(), *this); 147 addSyntheticLocal(saver().save(isARM ? "$a" : "$t"), STT_NOTYPE, 0, 0, *this); 148 } 149 150 uint64_t Patch657417Section::getBranchAddr() const { 151 return patchee->getVA(patcheeOffset); 152 } 153 154 // Given a branch instruction instr at sourceAddr work out its destination 155 // address. This is only used when the branch instruction has no relocation. 156 static uint64_t getThumbDestAddr(uint64_t sourceAddr, uint32_t instr) { 157 uint8_t buf[4]; 158 write16le(buf, instr >> 16); 159 write16le(buf + 2, instr & 0x0000ffff); 160 int64_t offset; 161 if (isBcc(instr)) 162 offset = target->getImplicitAddend(buf, R_ARM_THM_JUMP19); 163 else if (isB(instr)) 164 offset = target->getImplicitAddend(buf, R_ARM_THM_JUMP24); 165 else 166 offset = target->getImplicitAddend(buf, R_ARM_THM_CALL); 167 // A BLX instruction from Thumb to Arm may have an address that is 168 // not 4-byte aligned. As Arm instructions are always 4-byte aligned 169 // the instruction is calculated (from Arm ARM): 170 // targetAddress = Align(PC, 4) + imm32 171 // where 172 // Align(x, y) = y * (x Div y) 173 // which corresponds to alignDown. 174 if (isBLX(instr)) 175 sourceAddr = alignDown(sourceAddr, 4); 176 return sourceAddr + offset + 4; 177 } 178 179 void Patch657417Section::writeTo(uint8_t *buf) { 180 // The base instruction of the patch is always a 32-bit unconditional branch. 181 if (isARM) 182 write32le(buf, 0xea000000); 183 else 184 write32le(buf, 0x9000f000); 185 // If we have a relocation then apply it. 186 if (!relocations.empty()) { 187 relocateAlloc(buf, buf + getSize()); 188 return; 189 } 190 191 // If we don't have a relocation then we must calculate and write the offset 192 // ourselves. 193 // Get the destination offset from the addend in the branch instruction. 194 // We cannot use the instruction in the patchee section as this will have 195 // been altered to point to us! 196 uint64_t s = getThumbDestAddr(getBranchAddr(), instr); 197 // A BLX changes the state of the branch in the patch to Arm state, which 198 // has a PC Bias of 8, whereas in all other cases the branch is in Thumb 199 // state with a PC Bias of 4. 200 uint64_t pcBias = isBLX(instr) ? 8 : 4; 201 uint64_t p = getVA(pcBias); 202 target->relocateNoSym(buf, isARM ? R_ARM_JUMP24 : R_ARM_THM_JUMP24, s - p); 203 } 204 205 // Given a branch instruction spanning two 4KiB regions, at offset off from the 206 // start of isec, return true if the destination of the branch is within the 207 // first of the two 4Kib regions. 208 static bool branchDestInFirstRegion(const InputSection *isec, uint64_t off, 209 uint32_t instr, const Relocation *r) { 210 uint64_t sourceAddr = isec->getVA(0) + off; 211 assert((sourceAddr & 0xfff) == 0xffe); 212 uint64_t destAddr = sourceAddr; 213 // If there is a branch relocation at the same offset we must use this to 214 // find the destination address as the branch could be indirected via a thunk 215 // or the PLT. 216 if (r) { 217 uint64_t dst = (r->expr == R_PLT_PC) ? r->sym->getPltVA() : r->sym->getVA(); 218 // Account for Thumb PC bias, usually cancelled to 0 by addend of -4. 219 destAddr = dst + r->addend + 4; 220 } else { 221 // If there is no relocation, we must have an intra-section branch 222 // We must extract the offset from the addend manually. 223 destAddr = getThumbDestAddr(sourceAddr, instr); 224 } 225 226 return (destAddr & 0xfffff000) == (sourceAddr & 0xfffff000); 227 } 228 229 // Return true if a branch can reach a patch section placed after isec. 230 // The Bcc.w instruction has a range of 1 MiB, all others have 16 MiB. 231 static bool patchInRange(const InputSection *isec, uint64_t off, 232 uint32_t instr) { 233 234 // We need the branch at source to reach a patch section placed immediately 235 // after isec. As there can be more than one patch in the patch section we 236 // add 0x100 as contingency to account for worst case of 1 branch every 4KiB 237 // for a 1 MiB range. 238 return target->inBranchRange( 239 isBcc(instr) ? R_ARM_THM_JUMP19 : R_ARM_THM_JUMP24, isec->getVA(off), 240 isec->getVA() + isec->getSize() + 0x100); 241 } 242 243 struct ScanResult { 244 // Offset of branch within its InputSection. 245 uint64_t off; 246 // Cached decoding of the branch instruction. 247 uint32_t instr; 248 // Branch relocation at off. Will be nullptr if no relocation exists. 249 Relocation *rel; 250 }; 251 252 // Detect the erratum sequence, returning the offset of the branch instruction 253 // and a decoding of the branch. If the erratum sequence is not found then 254 // return an offset of 0 for the branch. 0 is a safe value to use for no patch 255 // as there must be at least one 32-bit non-branch instruction before the 256 // branch so the minimum offset for a patch is 4. 257 static ScanResult scanCortexA8Errata657417(InputSection *isec, uint64_t &off, 258 uint64_t limit) { 259 uint64_t isecAddr = isec->getVA(0); 260 // Advance Off so that (isecAddr + off) modulo 0x1000 is at least 0xffa. We 261 // need to check for a 32-bit instruction immediately before a 32-bit branch 262 // at 0xffe modulo 0x1000. 263 off = alignTo(isecAddr + off, 0x1000, 0xffa) - isecAddr; 264 if (off >= limit || limit - off < 8) { 265 // Need at least 2 4-byte sized instructions to trigger erratum. 266 off = limit; 267 return {0, 0, nullptr}; 268 } 269 270 ScanResult scanRes = {0, 0, nullptr}; 271 const uint8_t *buf = isec->data().begin(); 272 // ARMv7-A Thumb 32-bit instructions are encoded 2 consecutive 273 // little-endian halfwords. 274 const ulittle16_t *instBuf = reinterpret_cast<const ulittle16_t *>(buf + off); 275 uint16_t hw11 = *instBuf++; 276 uint16_t hw12 = *instBuf++; 277 uint16_t hw21 = *instBuf++; 278 uint16_t hw22 = *instBuf++; 279 if (is32bitInstruction(hw11) && is32bitInstruction(hw21)) { 280 uint32_t instr1 = (hw11 << 16) | hw12; 281 uint32_t instr2 = (hw21 << 16) | hw22; 282 if (!is32bitBranch(instr1) && is32bitBranch(instr2)) { 283 // Find a relocation for the branch if it exists. This will be used 284 // to determine the target. 285 uint64_t branchOff = off + 4; 286 auto relIt = llvm::find_if(isec->relocations, [=](const Relocation &r) { 287 return r.offset == branchOff && 288 (r.type == R_ARM_THM_JUMP19 || r.type == R_ARM_THM_JUMP24 || 289 r.type == R_ARM_THM_CALL); 290 }); 291 if (relIt != isec->relocations.end()) 292 scanRes.rel = &(*relIt); 293 if (branchDestInFirstRegion(isec, branchOff, instr2, scanRes.rel)) { 294 if (patchInRange(isec, branchOff, instr2)) { 295 scanRes.off = branchOff; 296 scanRes.instr = instr2; 297 } else { 298 warn(toString(isec->file) + 299 ": skipping cortex-a8 657417 erratum sequence, section " + 300 isec->name + " is too large to patch"); 301 } 302 } 303 } 304 } 305 off += 0x1000; 306 return scanRes; 307 } 308 309 void ARMErr657417Patcher::init() { 310 // The Arm ABI permits a mix of ARM, Thumb and Data in the same 311 // InputSection. We must only scan Thumb instructions to avoid false 312 // matches. We use the mapping symbols in the InputObjects to identify this 313 // data, caching the results in sectionMap so we don't have to recalculate 314 // it each pass. 315 316 // The ABI Section 4.5.5 Mapping symbols; defines local symbols that describe 317 // half open intervals [Symbol Value, Next Symbol Value) of code and data 318 // within sections. If there is no next symbol then the half open interval is 319 // [Symbol Value, End of section). The type, code or data, is determined by 320 // the mapping symbol name, $a for Arm code, $t for Thumb code, $d for data. 321 auto isArmMapSymbol = [](const Symbol *s) { 322 return s->getName() == "$a" || s->getName().startswith("$a."); 323 }; 324 auto isThumbMapSymbol = [](const Symbol *s) { 325 return s->getName() == "$t" || s->getName().startswith("$t."); 326 }; 327 auto isDataMapSymbol = [](const Symbol *s) { 328 return s->getName() == "$d" || s->getName().startswith("$d."); 329 }; 330 331 // Collect mapping symbols for every executable InputSection. 332 for (ELFFileBase *file : objectFiles) { 333 for (Symbol *s : file->getLocalSymbols()) { 334 auto *def = dyn_cast<Defined>(s); 335 if (!def) 336 continue; 337 if (!isArmMapSymbol(def) && !isThumbMapSymbol(def) && 338 !isDataMapSymbol(def)) 339 continue; 340 if (auto *sec = dyn_cast_or_null<InputSection>(def->section)) 341 if (sec->flags & SHF_EXECINSTR) 342 sectionMap[sec].push_back(def); 343 } 344 } 345 // For each InputSection make sure the mapping symbols are in sorted in 346 // ascending order and are in alternating Thumb, non-Thumb order. 347 for (auto &kv : sectionMap) { 348 std::vector<const Defined *> &mapSyms = kv.second; 349 llvm::stable_sort(mapSyms, [](const Defined *a, const Defined *b) { 350 return a->value < b->value; 351 }); 352 mapSyms.erase(std::unique(mapSyms.begin(), mapSyms.end(), 353 [=](const Defined *a, const Defined *b) { 354 return (isThumbMapSymbol(a) == 355 isThumbMapSymbol(b)); 356 }), 357 mapSyms.end()); 358 // Always start with a Thumb Mapping Symbol 359 if (!mapSyms.empty() && !isThumbMapSymbol(mapSyms.front())) 360 mapSyms.erase(mapSyms.begin()); 361 } 362 initialized = true; 363 } 364 365 void ARMErr657417Patcher::insertPatches( 366 InputSectionDescription &isd, std::vector<Patch657417Section *> &patches) { 367 uint64_t spacing = 0x100000 - 0x7500; 368 uint64_t isecLimit; 369 uint64_t prevIsecLimit = isd.sections.front()->outSecOff; 370 uint64_t patchUpperBound = prevIsecLimit + spacing; 371 uint64_t outSecAddr = isd.sections.front()->getParent()->addr; 372 373 // Set the outSecOff of patches to the place where we want to insert them. 374 // We use a similar strategy to initial thunk placement, using 1 MiB as the 375 // range of the Thumb-2 conditional branch with a contingency accounting for 376 // thunk generation. 377 auto patchIt = patches.begin(); 378 auto patchEnd = patches.end(); 379 for (const InputSection *isec : isd.sections) { 380 isecLimit = isec->outSecOff + isec->getSize(); 381 if (isecLimit > patchUpperBound) { 382 for (; patchIt != patchEnd; ++patchIt) { 383 if ((*patchIt)->getBranchAddr() - outSecAddr >= prevIsecLimit) 384 break; 385 (*patchIt)->outSecOff = prevIsecLimit; 386 } 387 patchUpperBound = prevIsecLimit + spacing; 388 } 389 prevIsecLimit = isecLimit; 390 } 391 for (; patchIt != patchEnd; ++patchIt) 392 (*patchIt)->outSecOff = isecLimit; 393 394 // Merge all patch sections. We use the outSecOff assigned above to 395 // determine the insertion point. This is ok as we only merge into an 396 // InputSectionDescription once per pass, and at the end of the pass 397 // assignAddresses() will recalculate all the outSecOff values. 398 SmallVector<InputSection *, 0> tmp; 399 tmp.reserve(isd.sections.size() + patches.size()); 400 auto mergeCmp = [](const InputSection *a, const InputSection *b) { 401 if (a->outSecOff != b->outSecOff) 402 return a->outSecOff < b->outSecOff; 403 return isa<Patch657417Section>(a) && !isa<Patch657417Section>(b); 404 }; 405 std::merge(isd.sections.begin(), isd.sections.end(), patches.begin(), 406 patches.end(), std::back_inserter(tmp), mergeCmp); 407 isd.sections = std::move(tmp); 408 } 409 410 // Given a branch instruction described by ScanRes redirect it to a patch 411 // section containing an unconditional branch instruction to the target. 412 // Ensure that this patch section is 4-byte aligned so that the branch cannot 413 // span two 4 KiB regions. Place the patch section so that it is always after 414 // isec so the branch we are patching always goes forwards. 415 static void implementPatch(ScanResult sr, InputSection *isec, 416 std::vector<Patch657417Section *> &patches) { 417 418 log("detected cortex-a8-657419 erratum sequence starting at " + 419 utohexstr(isec->getVA(sr.off)) + " in unpatched output."); 420 Patch657417Section *psec; 421 // We have two cases to deal with. 422 // Case 1. There is a relocation at patcheeOffset to a symbol. The 423 // unconditional branch in the patch must have a relocation so that any 424 // further redirection via the PLT or a Thunk happens as normal. At 425 // patcheeOffset we redirect the existing relocation to a Symbol defined at 426 // the start of the patch section. 427 // 428 // Case 2. There is no relocation at patcheeOffset. We are unlikely to have 429 // a symbol that we can use as a target for a relocation in the patch section. 430 // Luckily we know that the destination cannot be indirected via the PLT or 431 // a Thunk so we can just write the destination directly. 432 if (sr.rel) { 433 // Case 1. We have an existing relocation to redirect to patch and a 434 // Symbol target. 435 436 // Create a branch relocation for the unconditional branch in the patch. 437 // This can be redirected via the PLT or Thunks. 438 RelType patchRelType = R_ARM_THM_JUMP24; 439 int64_t patchRelAddend = sr.rel->addend; 440 bool destIsARM = false; 441 if (isBL(sr.instr) || isBLX(sr.instr)) { 442 // The final target of the branch may be ARM or Thumb, if the target 443 // is ARM then we write the patch in ARM state to avoid a state change 444 // Thunk from the patch to the target. 445 uint64_t dstSymAddr = (sr.rel->expr == R_PLT_PC) ? sr.rel->sym->getPltVA() 446 : sr.rel->sym->getVA(); 447 destIsARM = (dstSymAddr & 1) == 0; 448 } 449 psec = make<Patch657417Section>(isec, sr.off, sr.instr, destIsARM); 450 if (destIsARM) { 451 // The patch will be in ARM state. Use an ARM relocation and account for 452 // the larger ARM PC-bias of 8 rather than Thumb's 4. 453 patchRelType = R_ARM_JUMP24; 454 patchRelAddend -= 4; 455 } 456 psec->relocations.push_back( 457 Relocation{sr.rel->expr, patchRelType, 0, patchRelAddend, sr.rel->sym}); 458 // Redirect the existing branch relocation to the patch. 459 sr.rel->expr = R_PC; 460 sr.rel->addend = -4; 461 sr.rel->sym = psec->patchSym; 462 } else { 463 // Case 2. We do not have a relocation to the patch. Add a relocation of the 464 // appropriate type to the patch at patcheeOffset. 465 466 // The destination is ARM if we have a BLX. 467 psec = make<Patch657417Section>(isec, sr.off, sr.instr, isBLX(sr.instr)); 468 RelType type; 469 if (isBcc(sr.instr)) 470 type = R_ARM_THM_JUMP19; 471 else if (isB(sr.instr)) 472 type = R_ARM_THM_JUMP24; 473 else 474 type = R_ARM_THM_CALL; 475 isec->relocations.push_back( 476 Relocation{R_PC, type, sr.off, -4, psec->patchSym}); 477 } 478 patches.push_back(psec); 479 } 480 481 // Scan all the instructions in InputSectionDescription, for each instance of 482 // the erratum sequence create a Patch657417Section. We return the list of 483 // Patch657417Sections that need to be applied to the InputSectionDescription. 484 std::vector<Patch657417Section *> 485 ARMErr657417Patcher::patchInputSectionDescription( 486 InputSectionDescription &isd) { 487 std::vector<Patch657417Section *> patches; 488 for (InputSection *isec : isd.sections) { 489 // LLD doesn't use the erratum sequence in SyntheticSections. 490 if (isa<SyntheticSection>(isec)) 491 continue; 492 // Use sectionMap to make sure we only scan Thumb code and not Arm or inline 493 // data. We have already sorted mapSyms in ascending order and removed 494 // consecutive mapping symbols of the same type. Our range of executable 495 // instructions to scan is therefore [thumbSym->value, nonThumbSym->value) 496 // or [thumbSym->value, section size). 497 std::vector<const Defined *> &mapSyms = sectionMap[isec]; 498 499 auto thumbSym = mapSyms.begin(); 500 while (thumbSym != mapSyms.end()) { 501 auto nonThumbSym = std::next(thumbSym); 502 uint64_t off = (*thumbSym)->value; 503 uint64_t limit = (nonThumbSym == mapSyms.end()) ? isec->data().size() 504 : (*nonThumbSym)->value; 505 506 while (off < limit) { 507 ScanResult sr = scanCortexA8Errata657417(isec, off, limit); 508 if (sr.off) 509 implementPatch(sr, isec, patches); 510 } 511 if (nonThumbSym == mapSyms.end()) 512 break; 513 thumbSym = std::next(nonThumbSym); 514 } 515 } 516 return patches; 517 } 518 519 bool ARMErr657417Patcher::createFixes() { 520 if (!initialized) 521 init(); 522 523 bool addressesChanged = false; 524 for (OutputSection *os : outputSections) { 525 if (!(os->flags & SHF_ALLOC) || !(os->flags & SHF_EXECINSTR)) 526 continue; 527 for (SectionCommand *cmd : os->commands) 528 if (auto *isd = dyn_cast<InputSectionDescription>(cmd)) { 529 std::vector<Patch657417Section *> patches = 530 patchInputSectionDescription(*isd); 531 if (!patches.empty()) { 532 insertPatches(*isd, patches); 533 addressesChanged = true; 534 } 535 } 536 } 537 return addressesChanged; 538 } 539