xref: /freebsd/contrib/llvm-project/lld/COFF/Chunks.cpp (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 //===- Chunks.cpp ---------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Chunks.h"
10 #include "InputFiles.h"
11 #include "Symbols.h"
12 #include "Writer.h"
13 #include "SymbolTable.h"
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/Object/COFF.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/Endian.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include <algorithm>
22 
23 using namespace llvm;
24 using namespace llvm::object;
25 using namespace llvm::support::endian;
26 using namespace llvm::COFF;
27 using llvm::support::ulittle32_t;
28 
29 namespace lld {
30 namespace coff {
31 
32 SectionChunk::SectionChunk(ObjFile *f, const coff_section *h)
33     : Chunk(SectionKind), file(f), header(h), repl(this) {
34   // Initialize relocs.
35   setRelocs(file->getCOFFObj()->getRelocations(header));
36 
37   // Initialize sectionName.
38   StringRef sectionName;
39   if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(header))
40     sectionName = *e;
41   sectionNameData = sectionName.data();
42   sectionNameSize = sectionName.size();
43 
44   setAlignment(header->getAlignment());
45 
46   hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
47 
48   // If linker GC is disabled, every chunk starts out alive.  If linker GC is
49   // enabled, treat non-comdat sections as roots. Generally optimized object
50   // files will be built with -ffunction-sections or /Gy, so most things worth
51   // stripping will be in a comdat.
52   live = !config->doGC || !isCOMDAT();
53 }
54 
55 // SectionChunk is one of the most frequently allocated classes, so it is
56 // important to keep it as compact as possible. As of this writing, the number
57 // below is the size of this class on x64 platforms.
58 static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly");
59 
60 static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); }
61 static void add32(uint8_t *p, int32_t v) { write32le(p, read32le(p) + v); }
62 static void add64(uint8_t *p, int64_t v) { write64le(p, read64le(p) + v); }
63 static void or16(uint8_t *p, uint16_t v) { write16le(p, read16le(p) | v); }
64 static void or32(uint8_t *p, uint32_t v) { write32le(p, read32le(p) | v); }
65 
66 // Verify that given sections are appropriate targets for SECREL
67 // relocations. This check is relaxed because unfortunately debug
68 // sections have section-relative relocations against absolute symbols.
69 static bool checkSecRel(const SectionChunk *sec, OutputSection *os) {
70   if (os)
71     return true;
72   if (sec->isCodeView())
73     return false;
74   error("SECREL relocation cannot be applied to absolute symbols");
75   return false;
76 }
77 
78 static void applySecRel(const SectionChunk *sec, uint8_t *off,
79                         OutputSection *os, uint64_t s) {
80   if (!checkSecRel(sec, os))
81     return;
82   uint64_t secRel = s - os->getRVA();
83   if (secRel > UINT32_MAX) {
84     error("overflow in SECREL relocation in section: " + sec->getSectionName());
85     return;
86   }
87   add32(off, secRel);
88 }
89 
90 static void applySecIdx(uint8_t *off, OutputSection *os) {
91   // Absolute symbol doesn't have section index, but section index relocation
92   // against absolute symbol should be resolved to one plus the last output
93   // section index. This is required for compatibility with MSVC.
94   if (os)
95     add16(off, os->sectionIndex);
96   else
97     add16(off, DefinedAbsolute::numOutputSections + 1);
98 }
99 
100 void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os,
101                                uint64_t s, uint64_t p) const {
102   switch (type) {
103   case IMAGE_REL_AMD64_ADDR32:   add32(off, s + config->imageBase); break;
104   case IMAGE_REL_AMD64_ADDR64:   add64(off, s + config->imageBase); break;
105   case IMAGE_REL_AMD64_ADDR32NB: add32(off, s); break;
106   case IMAGE_REL_AMD64_REL32:    add32(off, s - p - 4); break;
107   case IMAGE_REL_AMD64_REL32_1:  add32(off, s - p - 5); break;
108   case IMAGE_REL_AMD64_REL32_2:  add32(off, s - p - 6); break;
109   case IMAGE_REL_AMD64_REL32_3:  add32(off, s - p - 7); break;
110   case IMAGE_REL_AMD64_REL32_4:  add32(off, s - p - 8); break;
111   case IMAGE_REL_AMD64_REL32_5:  add32(off, s - p - 9); break;
112   case IMAGE_REL_AMD64_SECTION:  applySecIdx(off, os); break;
113   case IMAGE_REL_AMD64_SECREL:   applySecRel(this, off, os, s); break;
114   default:
115     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
116           toString(file));
117   }
118 }
119 
120 void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os,
121                                uint64_t s, uint64_t p) const {
122   switch (type) {
123   case IMAGE_REL_I386_ABSOLUTE: break;
124   case IMAGE_REL_I386_DIR32:    add32(off, s + config->imageBase); break;
125   case IMAGE_REL_I386_DIR32NB:  add32(off, s); break;
126   case IMAGE_REL_I386_REL32:    add32(off, s - p - 4); break;
127   case IMAGE_REL_I386_SECTION:  applySecIdx(off, os); break;
128   case IMAGE_REL_I386_SECREL:   applySecRel(this, off, os, s); break;
129   default:
130     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
131           toString(file));
132   }
133 }
134 
135 static void applyMOV(uint8_t *off, uint16_t v) {
136   write16le(off, (read16le(off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf));
137   write16le(off + 2, (read16le(off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff));
138 }
139 
140 static uint16_t readMOV(uint8_t *off, bool movt) {
141   uint16_t op1 = read16le(off);
142   if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240))
143     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
144           " instruction in MOV32T relocation");
145   uint16_t op2 = read16le(off + 2);
146   if ((op2 & 0x8000) != 0)
147     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
148           " instruction in MOV32T relocation");
149   return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) |
150          ((op1 & 0x000f) << 12);
151 }
152 
153 void applyMOV32T(uint8_t *off, uint32_t v) {
154   uint16_t immW = readMOV(off, false);    // read MOVW operand
155   uint16_t immT = readMOV(off + 4, true); // read MOVT operand
156   uint32_t imm = immW | (immT << 16);
157   v += imm;                         // add the immediate offset
158   applyMOV(off, v);           // set MOVW operand
159   applyMOV(off + 4, v >> 16); // set MOVT operand
160 }
161 
162 static void applyBranch20T(uint8_t *off, int32_t v) {
163   if (!isInt<21>(v))
164     error("relocation out of range");
165   uint32_t s = v < 0 ? 1 : 0;
166   uint32_t j1 = (v >> 19) & 1;
167   uint32_t j2 = (v >> 18) & 1;
168   or16(off, (s << 10) | ((v >> 12) & 0x3f));
169   or16(off + 2, (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
170 }
171 
172 void applyBranch24T(uint8_t *off, int32_t v) {
173   if (!isInt<25>(v))
174     error("relocation out of range");
175   uint32_t s = v < 0 ? 1 : 0;
176   uint32_t j1 = ((~v >> 23) & 1) ^ s;
177   uint32_t j2 = ((~v >> 22) & 1) ^ s;
178   or16(off, (s << 10) | ((v >> 12) & 0x3ff));
179   // Clear out the J1 and J2 bits which may be set.
180   write16le(off + 2, (read16le(off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
181 }
182 
183 void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os,
184                                uint64_t s, uint64_t p) const {
185   // Pointer to thumb code must have the LSB set.
186   uint64_t sx = s;
187   if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
188     sx |= 1;
189   switch (type) {
190   case IMAGE_REL_ARM_ADDR32:    add32(off, sx + config->imageBase); break;
191   case IMAGE_REL_ARM_ADDR32NB:  add32(off, sx); break;
192   case IMAGE_REL_ARM_MOV32T:    applyMOV32T(off, sx + config->imageBase); break;
193   case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, sx - p - 4); break;
194   case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, sx - p - 4); break;
195   case IMAGE_REL_ARM_BLX23T:    applyBranch24T(off, sx - p - 4); break;
196   case IMAGE_REL_ARM_SECTION:   applySecIdx(off, os); break;
197   case IMAGE_REL_ARM_SECREL:    applySecRel(this, off, os, s); break;
198   case IMAGE_REL_ARM_REL32:     add32(off, sx - p - 4); break;
199   default:
200     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
201           toString(file));
202   }
203 }
204 
205 // Interpret the existing immediate value as a byte offset to the
206 // target symbol, then update the instruction with the immediate as
207 // the page offset from the current instruction to the target.
208 void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) {
209   uint32_t orig = read32le(off);
210   uint64_t imm = ((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC);
211   s += imm;
212   imm = (s >> shift) - (p >> shift);
213   uint32_t immLo = (imm & 0x3) << 29;
214   uint32_t immHi = (imm & 0x1FFFFC) << 3;
215   uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
216   write32le(off, (orig & ~mask) | immLo | immHi);
217 }
218 
219 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
220 // Optionally limit the range of the written immediate by one or more bits
221 // (rangeLimit).
222 void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) {
223   uint32_t orig = read32le(off);
224   imm += (orig >> 10) & 0xFFF;
225   orig &= ~(0xFFF << 10);
226   write32le(off, orig | ((imm & (0xFFF >> rangeLimit)) << 10));
227 }
228 
229 // Add the 12 bit page offset to the existing immediate.
230 // Ldr/str instructions store the opcode immediate scaled
231 // by the load/store size (giving a larger range for larger
232 // loads/stores). The immediate is always (both before and after
233 // fixing up the relocation) stored scaled similarly.
234 // Even if larger loads/stores have a larger range, limit the
235 // effective offset to 12 bit, since it is intended to be a
236 // page offset.
237 static void applyArm64Ldr(uint8_t *off, uint64_t imm) {
238   uint32_t orig = read32le(off);
239   uint32_t size = orig >> 30;
240   // 0x04000000 indicates SIMD/FP registers
241   // 0x00800000 indicates 128 bit
242   if ((orig & 0x4800000) == 0x4800000)
243     size += 4;
244   if ((imm & ((1 << size) - 1)) != 0)
245     error("misaligned ldr/str offset");
246   applyArm64Imm(off, imm >> size, size);
247 }
248 
249 static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off,
250                               OutputSection *os, uint64_t s) {
251   if (checkSecRel(sec, os))
252     applyArm64Imm(off, (s - os->getRVA()) & 0xfff, 0);
253 }
254 
255 static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off,
256                                OutputSection *os, uint64_t s) {
257   if (!checkSecRel(sec, os))
258     return;
259   uint64_t secRel = (s - os->getRVA()) >> 12;
260   if (0xfff < secRel) {
261     error("overflow in SECREL_HIGH12A relocation in section: " +
262           sec->getSectionName());
263     return;
264   }
265   applyArm64Imm(off, secRel & 0xfff, 0);
266 }
267 
268 static void applySecRelLdr(const SectionChunk *sec, uint8_t *off,
269                            OutputSection *os, uint64_t s) {
270   if (checkSecRel(sec, os))
271     applyArm64Ldr(off, (s - os->getRVA()) & 0xfff);
272 }
273 
274 void applyArm64Branch26(uint8_t *off, int64_t v) {
275   if (!isInt<28>(v))
276     error("relocation out of range");
277   or32(off, (v & 0x0FFFFFFC) >> 2);
278 }
279 
280 static void applyArm64Branch19(uint8_t *off, int64_t v) {
281   if (!isInt<21>(v))
282     error("relocation out of range");
283   or32(off, (v & 0x001FFFFC) << 3);
284 }
285 
286 static void applyArm64Branch14(uint8_t *off, int64_t v) {
287   if (!isInt<16>(v))
288     error("relocation out of range");
289   or32(off, (v & 0x0000FFFC) << 3);
290 }
291 
292 void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os,
293                                  uint64_t s, uint64_t p) const {
294   switch (type) {
295   case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, 12); break;
296   case IMAGE_REL_ARM64_REL21:          applyArm64Addr(off, s, p, 0); break;
297   case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, s & 0xfff, 0); break;
298   case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, s & 0xfff); break;
299   case IMAGE_REL_ARM64_BRANCH26:       applyArm64Branch26(off, s - p); break;
300   case IMAGE_REL_ARM64_BRANCH19:       applyArm64Branch19(off, s - p); break;
301   case IMAGE_REL_ARM64_BRANCH14:       applyArm64Branch14(off, s - p); break;
302   case IMAGE_REL_ARM64_ADDR32:         add32(off, s + config->imageBase); break;
303   case IMAGE_REL_ARM64_ADDR32NB:       add32(off, s); break;
304   case IMAGE_REL_ARM64_ADDR64:         add64(off, s + config->imageBase); break;
305   case IMAGE_REL_ARM64_SECREL:         applySecRel(this, off, os, s); break;
306   case IMAGE_REL_ARM64_SECREL_LOW12A:  applySecRelLow12A(this, off, os, s); break;
307   case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, off, os, s); break;
308   case IMAGE_REL_ARM64_SECREL_LOW12L:  applySecRelLdr(this, off, os, s); break;
309   case IMAGE_REL_ARM64_SECTION:        applySecIdx(off, os); break;
310   case IMAGE_REL_ARM64_REL32:          add32(off, s - p - 4); break;
311   default:
312     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
313           toString(file));
314   }
315 }
316 
317 static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk,
318                                              Defined *sym,
319                                              const coff_relocation &rel) {
320   // Don't report these errors when the relocation comes from a debug info
321   // section or in mingw mode. MinGW mode object files (built by GCC) can
322   // have leftover sections with relocations against discarded comdat
323   // sections. Such sections are left as is, with relocations untouched.
324   if (fromChunk->isCodeView() || fromChunk->isDWARF() || config->mingw)
325     return;
326 
327   // Get the name of the symbol. If it's null, it was discarded early, so we
328   // have to go back to the object file.
329   ObjFile *file = fromChunk->file;
330   StringRef name;
331   if (sym) {
332     name = sym->getName();
333   } else {
334     COFFSymbolRef coffSym =
335         check(file->getCOFFObj()->getSymbol(rel.SymbolTableIndex));
336     name = check(file->getCOFFObj()->getSymbolName(coffSym));
337   }
338 
339   std::vector<std::string> symbolLocations =
340       getSymbolLocations(file, rel.SymbolTableIndex);
341 
342   std::string out;
343   llvm::raw_string_ostream os(out);
344   os << "relocation against symbol in discarded section: " + name;
345   for (const std::string &s : symbolLocations)
346     os << s;
347   error(os.str());
348 }
349 
350 void SectionChunk::writeTo(uint8_t *buf) const {
351   if (!hasData)
352     return;
353   // Copy section contents from source object file to output file.
354   ArrayRef<uint8_t> a = getContents();
355   if (!a.empty())
356     memcpy(buf, a.data(), a.size());
357 
358   // Apply relocations.
359   size_t inputSize = getSize();
360   for (size_t i = 0, e = relocsSize; i < e; i++) {
361     const coff_relocation &rel = relocsData[i];
362 
363     // Check for an invalid relocation offset. This check isn't perfect, because
364     // we don't have the relocation size, which is only known after checking the
365     // machine and relocation type. As a result, a relocation may overwrite the
366     // beginning of the following input section.
367     if (rel.VirtualAddress >= inputSize) {
368       error("relocation points beyond the end of its parent section");
369       continue;
370     }
371 
372     uint8_t *off = buf + rel.VirtualAddress;
373 
374     auto *sym =
375         dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
376 
377     // Get the output section of the symbol for this relocation.  The output
378     // section is needed to compute SECREL and SECTION relocations used in debug
379     // info.
380     Chunk *c = sym ? sym->getChunk() : nullptr;
381     OutputSection *os = c ? c->getOutputSection() : nullptr;
382 
383     // Skip the relocation if it refers to a discarded section, and diagnose it
384     // as an error if appropriate. If a symbol was discarded early, it may be
385     // null. If it was discarded late, the output section will be null, unless
386     // it was an absolute or synthetic symbol.
387     if (!sym ||
388         (!os && !isa<DefinedAbsolute>(sym) && !isa<DefinedSynthetic>(sym))) {
389       maybeReportRelocationToDiscarded(this, sym, rel);
390       continue;
391     }
392 
393     uint64_t s = sym->getRVA();
394 
395     // Compute the RVA of the relocation for relative relocations.
396     uint64_t p = rva + rel.VirtualAddress;
397     switch (config->machine) {
398     case AMD64:
399       applyRelX64(off, rel.Type, os, s, p);
400       break;
401     case I386:
402       applyRelX86(off, rel.Type, os, s, p);
403       break;
404     case ARMNT:
405       applyRelARM(off, rel.Type, os, s, p);
406       break;
407     case ARM64:
408       applyRelARM64(off, rel.Type, os, s, p);
409       break;
410     default:
411       llvm_unreachable("unknown machine type");
412     }
413   }
414 }
415 
416 void SectionChunk::addAssociative(SectionChunk *child) {
417   // Insert this child at the head of the list.
418   assert(child->assocChildren == nullptr &&
419          "associated sections cannot have their own associated children");
420   child->assocChildren = assocChildren;
421   assocChildren = child;
422 }
423 
424 static uint8_t getBaserelType(const coff_relocation &rel) {
425   switch (config->machine) {
426   case AMD64:
427     if (rel.Type == IMAGE_REL_AMD64_ADDR64)
428       return IMAGE_REL_BASED_DIR64;
429     return IMAGE_REL_BASED_ABSOLUTE;
430   case I386:
431     if (rel.Type == IMAGE_REL_I386_DIR32)
432       return IMAGE_REL_BASED_HIGHLOW;
433     return IMAGE_REL_BASED_ABSOLUTE;
434   case ARMNT:
435     if (rel.Type == IMAGE_REL_ARM_ADDR32)
436       return IMAGE_REL_BASED_HIGHLOW;
437     if (rel.Type == IMAGE_REL_ARM_MOV32T)
438       return IMAGE_REL_BASED_ARM_MOV32T;
439     return IMAGE_REL_BASED_ABSOLUTE;
440   case ARM64:
441     if (rel.Type == IMAGE_REL_ARM64_ADDR64)
442       return IMAGE_REL_BASED_DIR64;
443     return IMAGE_REL_BASED_ABSOLUTE;
444   default:
445     llvm_unreachable("unknown machine type");
446   }
447 }
448 
449 // Windows-specific.
450 // Collect all locations that contain absolute addresses, which need to be
451 // fixed by the loader if load-time relocation is needed.
452 // Only called when base relocation is enabled.
453 void SectionChunk::getBaserels(std::vector<Baserel> *res) {
454   for (size_t i = 0, e = relocsSize; i < e; i++) {
455     const coff_relocation &rel = relocsData[i];
456     uint8_t ty = getBaserelType(rel);
457     if (ty == IMAGE_REL_BASED_ABSOLUTE)
458       continue;
459     Symbol *target = file->getSymbol(rel.SymbolTableIndex);
460     if (!target || isa<DefinedAbsolute>(target))
461       continue;
462     res->emplace_back(rva + rel.VirtualAddress, ty);
463   }
464 }
465 
466 // MinGW specific.
467 // Check whether a static relocation of type Type can be deferred and
468 // handled at runtime as a pseudo relocation (for references to a module
469 // local variable, which turned out to actually need to be imported from
470 // another DLL) This returns the size the relocation is supposed to update,
471 // in bits, or 0 if the relocation cannot be handled as a runtime pseudo
472 // relocation.
473 static int getRuntimePseudoRelocSize(uint16_t type) {
474   // Relocations that either contain an absolute address, or a plain
475   // relative offset, since the runtime pseudo reloc implementation
476   // adds 8/16/32/64 bit values to a memory address.
477   //
478   // Given a pseudo relocation entry,
479   //
480   // typedef struct {
481   //   DWORD sym;
482   //   DWORD target;
483   //   DWORD flags;
484   // } runtime_pseudo_reloc_item_v2;
485   //
486   // the runtime relocation performs this adjustment:
487   //     *(base + .target) += *(base + .sym) - (base + .sym)
488   //
489   // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
490   // IMAGE_REL_I386_DIR32, where the memory location initially contains
491   // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
492   // where the memory location originally contains the relative offset to the
493   // IAT slot.
494   //
495   // This requires the target address to be writable, either directly out of
496   // the image, or temporarily changed at runtime with VirtualProtect.
497   // Since this only operates on direct address values, it doesn't work for
498   // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
499   switch (config->machine) {
500   case AMD64:
501     switch (type) {
502     case IMAGE_REL_AMD64_ADDR64:
503       return 64;
504     case IMAGE_REL_AMD64_ADDR32:
505     case IMAGE_REL_AMD64_REL32:
506     case IMAGE_REL_AMD64_REL32_1:
507     case IMAGE_REL_AMD64_REL32_2:
508     case IMAGE_REL_AMD64_REL32_3:
509     case IMAGE_REL_AMD64_REL32_4:
510     case IMAGE_REL_AMD64_REL32_5:
511       return 32;
512     default:
513       return 0;
514     }
515   case I386:
516     switch (type) {
517     case IMAGE_REL_I386_DIR32:
518     case IMAGE_REL_I386_REL32:
519       return 32;
520     default:
521       return 0;
522     }
523   case ARMNT:
524     switch (type) {
525     case IMAGE_REL_ARM_ADDR32:
526       return 32;
527     default:
528       return 0;
529     }
530   case ARM64:
531     switch (type) {
532     case IMAGE_REL_ARM64_ADDR64:
533       return 64;
534     case IMAGE_REL_ARM64_ADDR32:
535       return 32;
536     default:
537       return 0;
538     }
539   default:
540     llvm_unreachable("unknown machine type");
541   }
542 }
543 
544 // MinGW specific.
545 // Append information to the provided vector about all relocations that
546 // need to be handled at runtime as runtime pseudo relocations (references
547 // to a module local variable, which turned out to actually need to be
548 // imported from another DLL).
549 void SectionChunk::getRuntimePseudoRelocs(
550     std::vector<RuntimePseudoReloc> &res) {
551   for (const coff_relocation &rel : getRelocs()) {
552     auto *target =
553         dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
554     if (!target || !target->isRuntimePseudoReloc)
555       continue;
556     int sizeInBits = getRuntimePseudoRelocSize(rel.Type);
557     if (sizeInBits == 0) {
558       error("unable to automatically import from " + target->getName() +
559             " with relocation type " +
560             file->getCOFFObj()->getRelocationTypeName(rel.Type) + " in " +
561             toString(file));
562       continue;
563     }
564     // sizeInBits is used to initialize the Flags field; currently no
565     // other flags are defined.
566     res.emplace_back(
567         RuntimePseudoReloc(target, this, rel.VirtualAddress, sizeInBits));
568   }
569 }
570 
571 bool SectionChunk::isCOMDAT() const {
572   return header->Characteristics & IMAGE_SCN_LNK_COMDAT;
573 }
574 
575 void SectionChunk::printDiscardedMessage() const {
576   // Removed by dead-stripping. If it's removed by ICF, ICF already
577   // printed out the name, so don't repeat that here.
578   if (sym && this == repl)
579     message("Discarded " + sym->getName());
580 }
581 
582 StringRef SectionChunk::getDebugName() const {
583   if (sym)
584     return sym->getName();
585   return "";
586 }
587 
588 ArrayRef<uint8_t> SectionChunk::getContents() const {
589   ArrayRef<uint8_t> a;
590   cantFail(file->getCOFFObj()->getSectionContents(header, a));
591   return a;
592 }
593 
594 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
595   assert(isCodeView());
596   return consumeDebugMagic(getContents(), getSectionName());
597 }
598 
599 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data,
600                                                   StringRef sectionName) {
601   if (data.empty())
602     return {};
603 
604   // First 4 bytes are section magic.
605   if (data.size() < 4)
606     fatal("the section is too short: " + sectionName);
607 
608   if (!sectionName.startswith(".debug$"))
609     fatal("invalid section: " + sectionName);
610 
611   uint32_t magic = support::endian::read32le(data.data());
612   uint32_t expectedMagic = sectionName == ".debug$H"
613                                ? DEBUG_HASHES_SECTION_MAGIC
614                                : DEBUG_SECTION_MAGIC;
615   if (magic != expectedMagic) {
616     warn("ignoring section " + sectionName + " with unrecognized magic 0x" +
617          utohexstr(magic));
618     return {};
619   }
620   return data.slice(4);
621 }
622 
623 SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections,
624                                        StringRef name) {
625   for (SectionChunk *c : sections)
626     if (c->getSectionName() == name)
627       return c;
628   return nullptr;
629 }
630 
631 void SectionChunk::replace(SectionChunk *other) {
632   p2Align = std::max(p2Align, other->p2Align);
633   other->repl = repl;
634   other->live = false;
635 }
636 
637 uint32_t SectionChunk::getSectionNumber() const {
638   DataRefImpl r;
639   r.p = reinterpret_cast<uintptr_t>(header);
640   SectionRef s(r, file->getCOFFObj());
641   return s.getIndex() + 1;
642 }
643 
644 CommonChunk::CommonChunk(const COFFSymbolRef s) : sym(s) {
645   // The value of a common symbol is its size. Align all common symbols smaller
646   // than 32 bytes naturally, i.e. round the size up to the next power of two.
647   // This is what MSVC link.exe does.
648   setAlignment(std::min(32U, uint32_t(PowerOf2Ceil(sym.getValue()))));
649   hasData = false;
650 }
651 
652 uint32_t CommonChunk::getOutputCharacteristics() const {
653   return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
654          IMAGE_SCN_MEM_WRITE;
655 }
656 
657 void StringChunk::writeTo(uint8_t *buf) const {
658   memcpy(buf, str.data(), str.size());
659   buf[str.size()] = '\0';
660 }
661 
662 ImportThunkChunkX64::ImportThunkChunkX64(Defined *s) : ImportThunkChunk(s) {
663   // Intel Optimization Manual says that all branch targets
664   // should be 16-byte aligned. MSVC linker does this too.
665   setAlignment(16);
666 }
667 
668 void ImportThunkChunkX64::writeTo(uint8_t *buf) const {
669   memcpy(buf, importThunkX86, sizeof(importThunkX86));
670   // The first two bytes is a JMP instruction. Fill its operand.
671   write32le(buf + 2, impSymbol->getRVA() - rva - getSize());
672 }
673 
674 void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) {
675   res->emplace_back(getRVA() + 2);
676 }
677 
678 void ImportThunkChunkX86::writeTo(uint8_t *buf) const {
679   memcpy(buf, importThunkX86, sizeof(importThunkX86));
680   // The first two bytes is a JMP instruction. Fill its operand.
681   write32le(buf + 2,
682             impSymbol->getRVA() + config->imageBase);
683 }
684 
685 void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) {
686   res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T);
687 }
688 
689 void ImportThunkChunkARM::writeTo(uint8_t *buf) const {
690   memcpy(buf, importThunkARM, sizeof(importThunkARM));
691   // Fix mov.w and mov.t operands.
692   applyMOV32T(buf, impSymbol->getRVA() + config->imageBase);
693 }
694 
695 void ImportThunkChunkARM64::writeTo(uint8_t *buf) const {
696   int64_t off = impSymbol->getRVA() & 0xfff;
697   memcpy(buf, importThunkARM64, sizeof(importThunkARM64));
698   applyArm64Addr(buf, impSymbol->getRVA(), rva, 12);
699   applyArm64Ldr(buf + 4, off);
700 }
701 
702 // A Thumb2, PIC, non-interworking range extension thunk.
703 const uint8_t armThunk[] = {
704     0x40, 0xf2, 0x00, 0x0c, // P:  movw ip,:lower16:S - (P + (L1-P) + 4)
705     0xc0, 0xf2, 0x00, 0x0c, //     movt ip,:upper16:S - (P + (L1-P) + 4)
706     0xe7, 0x44,             // L1: add  pc, ip
707 };
708 
709 size_t RangeExtensionThunkARM::getSize() const {
710   assert(config->machine == ARMNT);
711   return sizeof(armThunk);
712 }
713 
714 void RangeExtensionThunkARM::writeTo(uint8_t *buf) const {
715   assert(config->machine == ARMNT);
716   uint64_t offset = target->getRVA() - rva - 12;
717   memcpy(buf, armThunk, sizeof(armThunk));
718   applyMOV32T(buf, uint32_t(offset));
719 }
720 
721 // A position independent ARM64 adrp+add thunk, with a maximum range of
722 // +/- 4 GB, which is enough for any PE-COFF.
723 const uint8_t arm64Thunk[] = {
724     0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
725     0x10, 0x02, 0x00, 0x91, // add  x16, x16, :lo12:Dest
726     0x00, 0x02, 0x1f, 0xd6, // br   x16
727 };
728 
729 size_t RangeExtensionThunkARM64::getSize() const {
730   assert(config->machine == ARM64);
731   return sizeof(arm64Thunk);
732 }
733 
734 void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
735   assert(config->machine == ARM64);
736   memcpy(buf, arm64Thunk, sizeof(arm64Thunk));
737   applyArm64Addr(buf + 0, target->getRVA(), rva, 12);
738   applyArm64Imm(buf + 4, target->getRVA() & 0xfff, 0);
739 }
740 
741 void LocalImportChunk::getBaserels(std::vector<Baserel> *res) {
742   res->emplace_back(getRVA());
743 }
744 
745 size_t LocalImportChunk::getSize() const { return config->wordsize; }
746 
747 void LocalImportChunk::writeTo(uint8_t *buf) const {
748   if (config->is64()) {
749     write64le(buf, sym->getRVA() + config->imageBase);
750   } else {
751     write32le(buf, sym->getRVA() + config->imageBase);
752   }
753 }
754 
755 void RVATableChunk::writeTo(uint8_t *buf) const {
756   ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf);
757   size_t cnt = 0;
758   for (const ChunkAndOffset &co : syms)
759     begin[cnt++] = co.inputChunk->getRVA() + co.offset;
760   std::sort(begin, begin + cnt);
761   assert(std::unique(begin, begin + cnt) == begin + cnt &&
762          "RVA tables should be de-duplicated");
763 }
764 
765 // MinGW specific, for the "automatic import of variables from DLLs" feature.
766 size_t PseudoRelocTableChunk::getSize() const {
767   if (relocs.empty())
768     return 0;
769   return 12 + 12 * relocs.size();
770 }
771 
772 // MinGW specific.
773 void PseudoRelocTableChunk::writeTo(uint8_t *buf) const {
774   if (relocs.empty())
775     return;
776 
777   ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf);
778   // This is the list header, to signal the runtime pseudo relocation v2
779   // format.
780   table[0] = 0;
781   table[1] = 0;
782   table[2] = 1;
783 
784   size_t idx = 3;
785   for (const RuntimePseudoReloc &rpr : relocs) {
786     table[idx + 0] = rpr.sym->getRVA();
787     table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset;
788     table[idx + 2] = rpr.flags;
789     idx += 3;
790   }
791 }
792 
793 // Windows-specific. This class represents a block in .reloc section.
794 // The format is described here.
795 //
796 // On Windows, each DLL is linked against a fixed base address and
797 // usually loaded to that address. However, if there's already another
798 // DLL that overlaps, the loader has to relocate it. To do that, DLLs
799 // contain .reloc sections which contain offsets that need to be fixed
800 // up at runtime. If the loader finds that a DLL cannot be loaded to its
801 // desired base address, it loads it to somewhere else, and add <actual
802 // base address> - <desired base address> to each offset that is
803 // specified by the .reloc section. In ELF terms, .reloc sections
804 // contain relative relocations in REL format (as opposed to RELA.)
805 //
806 // This already significantly reduces the size of relocations compared
807 // to ELF .rel.dyn, but Windows does more to reduce it (probably because
808 // it was invented for PCs in the late '80s or early '90s.)  Offsets in
809 // .reloc are grouped by page where the page size is 12 bits, and
810 // offsets sharing the same page address are stored consecutively to
811 // represent them with less space. This is very similar to the page
812 // table which is grouped by (multiple stages of) pages.
813 //
814 // For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
815 // 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
816 // bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
817 // are represented like this:
818 //
819 //   0x00000  -- page address (4 bytes)
820 //   16       -- size of this block (4 bytes)
821 //     0xA030 -- entries (2 bytes each)
822 //     0xA500
823 //     0xA700
824 //     0xAA00
825 //   0x20000  -- page address (4 bytes)
826 //   12       -- size of this block (4 bytes)
827 //     0xA004 -- entries (2 bytes each)
828 //     0xA008
829 //
830 // Usually we have a lot of relocations for each page, so the number of
831 // bytes for one .reloc entry is close to 2 bytes on average.
832 BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) {
833   // Block header consists of 4 byte page RVA and 4 byte block size.
834   // Each entry is 2 byte. Last entry may be padding.
835   data.resize(alignTo((end - begin) * 2 + 8, 4));
836   uint8_t *p = data.data();
837   write32le(p, page);
838   write32le(p + 4, data.size());
839   p += 8;
840   for (Baserel *i = begin; i != end; ++i) {
841     write16le(p, (i->type << 12) | (i->rva - page));
842     p += 2;
843   }
844 }
845 
846 void BaserelChunk::writeTo(uint8_t *buf) const {
847   memcpy(buf, data.data(), data.size());
848 }
849 
850 uint8_t Baserel::getDefaultType() {
851   switch (config->machine) {
852   case AMD64:
853   case ARM64:
854     return IMAGE_REL_BASED_DIR64;
855   case I386:
856   case ARMNT:
857     return IMAGE_REL_BASED_HIGHLOW;
858   default:
859     llvm_unreachable("unknown machine type");
860   }
861 }
862 
863 MergeChunk *MergeChunk::instances[Log2MaxSectionAlignment + 1] = {};
864 
865 MergeChunk::MergeChunk(uint32_t alignment)
866     : builder(StringTableBuilder::RAW, alignment) {
867   setAlignment(alignment);
868 }
869 
870 void MergeChunk::addSection(SectionChunk *c) {
871   assert(isPowerOf2_32(c->getAlignment()));
872   uint8_t p2Align = llvm::Log2_32(c->getAlignment());
873   assert(p2Align < array_lengthof(instances));
874   auto *&mc = instances[p2Align];
875   if (!mc)
876     mc = make<MergeChunk>(c->getAlignment());
877   mc->sections.push_back(c);
878 }
879 
880 void MergeChunk::finalizeContents() {
881   assert(!finalized && "should only finalize once");
882   for (SectionChunk *c : sections)
883     if (c->live)
884       builder.add(toStringRef(c->getContents()));
885   builder.finalize();
886   finalized = true;
887 }
888 
889 void MergeChunk::assignSubsectionRVAs() {
890   for (SectionChunk *c : sections) {
891     if (!c->live)
892       continue;
893     size_t off = builder.getOffset(toStringRef(c->getContents()));
894     c->setRVA(rva + off);
895   }
896 }
897 
898 uint32_t MergeChunk::getOutputCharacteristics() const {
899   return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
900 }
901 
902 size_t MergeChunk::getSize() const {
903   return builder.getSize();
904 }
905 
906 void MergeChunk::writeTo(uint8_t *buf) const {
907   builder.write(buf);
908 }
909 
910 // MinGW specific.
911 size_t AbsolutePointerChunk::getSize() const { return config->wordsize; }
912 
913 void AbsolutePointerChunk::writeTo(uint8_t *buf) const {
914   if (config->is64()) {
915     write64le(buf, value);
916   } else {
917     write32le(buf, value);
918   }
919 }
920 
921 } // namespace coff
922 } // namespace lld
923