1 //===- Chunks.cpp ---------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "Chunks.h" 10 #include "COFFLinkerContext.h" 11 #include "InputFiles.h" 12 #include "SymbolTable.h" 13 #include "Symbols.h" 14 #include "Writer.h" 15 #include "llvm/ADT/STLExtras.h" 16 #include "llvm/ADT/Twine.h" 17 #include "llvm/BinaryFormat/COFF.h" 18 #include "llvm/Object/COFF.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/Endian.h" 21 #include "llvm/Support/raw_ostream.h" 22 #include <algorithm> 23 #include <iterator> 24 25 using namespace llvm; 26 using namespace llvm::object; 27 using namespace llvm::support::endian; 28 using namespace llvm::COFF; 29 using llvm::support::ulittle32_t; 30 31 namespace lld::coff { 32 33 SectionChunk::SectionChunk(ObjFile *f, const coff_section *h) 34 : Chunk(SectionKind), file(f), header(h), repl(this) { 35 // Initialize relocs. 36 if (file) 37 setRelocs(file->getCOFFObj()->getRelocations(header)); 38 39 // Initialize sectionName. 40 StringRef sectionName; 41 if (file) { 42 if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(header)) 43 sectionName = *e; 44 } 45 sectionNameData = sectionName.data(); 46 sectionNameSize = sectionName.size(); 47 48 setAlignment(header->getAlignment()); 49 50 hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA); 51 52 // If linker GC is disabled, every chunk starts out alive. If linker GC is 53 // enabled, treat non-comdat sections as roots. Generally optimized object 54 // files will be built with -ffunction-sections or /Gy, so most things worth 55 // stripping will be in a comdat. 56 if (file) 57 live = !file->ctx.config.doGC || !isCOMDAT(); 58 else 59 live = true; 60 } 61 62 // SectionChunk is one of the most frequently allocated classes, so it is 63 // important to keep it as compact as possible. As of this writing, the number 64 // below is the size of this class on x64 platforms. 65 static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly"); 66 67 static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); } 68 static void add32(uint8_t *p, int32_t v) { write32le(p, read32le(p) + v); } 69 static void add64(uint8_t *p, int64_t v) { write64le(p, read64le(p) + v); } 70 static void or16(uint8_t *p, uint16_t v) { write16le(p, read16le(p) | v); } 71 static void or32(uint8_t *p, uint32_t v) { write32le(p, read32le(p) | v); } 72 73 // Verify that given sections are appropriate targets for SECREL 74 // relocations. This check is relaxed because unfortunately debug 75 // sections have section-relative relocations against absolute symbols. 76 static bool checkSecRel(const SectionChunk *sec, OutputSection *os) { 77 if (os) 78 return true; 79 if (sec->isCodeView()) 80 return false; 81 error("SECREL relocation cannot be applied to absolute symbols"); 82 return false; 83 } 84 85 static void applySecRel(const SectionChunk *sec, uint8_t *off, 86 OutputSection *os, uint64_t s) { 87 if (!checkSecRel(sec, os)) 88 return; 89 uint64_t secRel = s - os->getRVA(); 90 if (secRel > UINT32_MAX) { 91 error("overflow in SECREL relocation in section: " + sec->getSectionName()); 92 return; 93 } 94 add32(off, secRel); 95 } 96 97 static void applySecIdx(uint8_t *off, OutputSection *os, 98 unsigned numOutputSections) { 99 // numOutputSections is the largest valid section index. Make sure that 100 // it fits in 16 bits. 101 assert(numOutputSections <= 0xffff && "size of outputSections is too big"); 102 103 // Absolute symbol doesn't have section index, but section index relocation 104 // against absolute symbol should be resolved to one plus the last output 105 // section index. This is required for compatibility with MSVC. 106 if (os) 107 add16(off, os->sectionIndex); 108 else 109 add16(off, numOutputSections + 1); 110 } 111 112 void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os, 113 uint64_t s, uint64_t p, 114 uint64_t imageBase) const { 115 switch (type) { 116 case IMAGE_REL_AMD64_ADDR32: 117 add32(off, s + imageBase); 118 break; 119 case IMAGE_REL_AMD64_ADDR64: 120 add64(off, s + imageBase); 121 break; 122 case IMAGE_REL_AMD64_ADDR32NB: add32(off, s); break; 123 case IMAGE_REL_AMD64_REL32: add32(off, s - p - 4); break; 124 case IMAGE_REL_AMD64_REL32_1: add32(off, s - p - 5); break; 125 case IMAGE_REL_AMD64_REL32_2: add32(off, s - p - 6); break; 126 case IMAGE_REL_AMD64_REL32_3: add32(off, s - p - 7); break; 127 case IMAGE_REL_AMD64_REL32_4: add32(off, s - p - 8); break; 128 case IMAGE_REL_AMD64_REL32_5: add32(off, s - p - 9); break; 129 case IMAGE_REL_AMD64_SECTION: 130 applySecIdx(off, os, file->ctx.outputSections.size()); 131 break; 132 case IMAGE_REL_AMD64_SECREL: applySecRel(this, off, os, s); break; 133 default: 134 error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " + 135 toString(file)); 136 } 137 } 138 139 void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os, 140 uint64_t s, uint64_t p, 141 uint64_t imageBase) const { 142 switch (type) { 143 case IMAGE_REL_I386_ABSOLUTE: break; 144 case IMAGE_REL_I386_DIR32: 145 add32(off, s + imageBase); 146 break; 147 case IMAGE_REL_I386_DIR32NB: add32(off, s); break; 148 case IMAGE_REL_I386_REL32: add32(off, s - p - 4); break; 149 case IMAGE_REL_I386_SECTION: 150 applySecIdx(off, os, file->ctx.outputSections.size()); 151 break; 152 case IMAGE_REL_I386_SECREL: applySecRel(this, off, os, s); break; 153 default: 154 error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " + 155 toString(file)); 156 } 157 } 158 159 static void applyMOV(uint8_t *off, uint16_t v) { 160 write16le(off, (read16le(off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf)); 161 write16le(off + 2, (read16le(off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff)); 162 } 163 164 static uint16_t readMOV(uint8_t *off, bool movt) { 165 uint16_t op1 = read16le(off); 166 if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240)) 167 error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") + 168 " instruction in MOV32T relocation"); 169 uint16_t op2 = read16le(off + 2); 170 if ((op2 & 0x8000) != 0) 171 error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") + 172 " instruction in MOV32T relocation"); 173 return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) | 174 ((op1 & 0x000f) << 12); 175 } 176 177 void applyMOV32T(uint8_t *off, uint32_t v) { 178 uint16_t immW = readMOV(off, false); // read MOVW operand 179 uint16_t immT = readMOV(off + 4, true); // read MOVT operand 180 uint32_t imm = immW | (immT << 16); 181 v += imm; // add the immediate offset 182 applyMOV(off, v); // set MOVW operand 183 applyMOV(off + 4, v >> 16); // set MOVT operand 184 } 185 186 static void applyBranch20T(uint8_t *off, int32_t v) { 187 if (!isInt<21>(v)) 188 error("relocation out of range"); 189 uint32_t s = v < 0 ? 1 : 0; 190 uint32_t j1 = (v >> 19) & 1; 191 uint32_t j2 = (v >> 18) & 1; 192 or16(off, (s << 10) | ((v >> 12) & 0x3f)); 193 or16(off + 2, (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff)); 194 } 195 196 void applyBranch24T(uint8_t *off, int32_t v) { 197 if (!isInt<25>(v)) 198 error("relocation out of range"); 199 uint32_t s = v < 0 ? 1 : 0; 200 uint32_t j1 = ((~v >> 23) & 1) ^ s; 201 uint32_t j2 = ((~v >> 22) & 1) ^ s; 202 or16(off, (s << 10) | ((v >> 12) & 0x3ff)); 203 // Clear out the J1 and J2 bits which may be set. 204 write16le(off + 2, (read16le(off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff)); 205 } 206 207 void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os, 208 uint64_t s, uint64_t p, 209 uint64_t imageBase) const { 210 // Pointer to thumb code must have the LSB set. 211 uint64_t sx = s; 212 if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE)) 213 sx |= 1; 214 switch (type) { 215 case IMAGE_REL_ARM_ADDR32: 216 add32(off, sx + imageBase); 217 break; 218 case IMAGE_REL_ARM_ADDR32NB: add32(off, sx); break; 219 case IMAGE_REL_ARM_MOV32T: 220 applyMOV32T(off, sx + imageBase); 221 break; 222 case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, sx - p - 4); break; 223 case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, sx - p - 4); break; 224 case IMAGE_REL_ARM_BLX23T: applyBranch24T(off, sx - p - 4); break; 225 case IMAGE_REL_ARM_SECTION: 226 applySecIdx(off, os, file->ctx.outputSections.size()); 227 break; 228 case IMAGE_REL_ARM_SECREL: applySecRel(this, off, os, s); break; 229 case IMAGE_REL_ARM_REL32: add32(off, sx - p - 4); break; 230 default: 231 error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " + 232 toString(file)); 233 } 234 } 235 236 // Interpret the existing immediate value as a byte offset to the 237 // target symbol, then update the instruction with the immediate as 238 // the page offset from the current instruction to the target. 239 void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) { 240 uint32_t orig = read32le(off); 241 int64_t imm = 242 SignExtend64<21>(((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC)); 243 s += imm; 244 imm = (s >> shift) - (p >> shift); 245 uint32_t immLo = (imm & 0x3) << 29; 246 uint32_t immHi = (imm & 0x1FFFFC) << 3; 247 uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3); 248 write32le(off, (orig & ~mask) | immLo | immHi); 249 } 250 251 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 252 // Optionally limit the range of the written immediate by one or more bits 253 // (rangeLimit). 254 void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) { 255 uint32_t orig = read32le(off); 256 imm += (orig >> 10) & 0xFFF; 257 orig &= ~(0xFFF << 10); 258 write32le(off, orig | ((imm & (0xFFF >> rangeLimit)) << 10)); 259 } 260 261 // Add the 12 bit page offset to the existing immediate. 262 // Ldr/str instructions store the opcode immediate scaled 263 // by the load/store size (giving a larger range for larger 264 // loads/stores). The immediate is always (both before and after 265 // fixing up the relocation) stored scaled similarly. 266 // Even if larger loads/stores have a larger range, limit the 267 // effective offset to 12 bit, since it is intended to be a 268 // page offset. 269 static void applyArm64Ldr(uint8_t *off, uint64_t imm) { 270 uint32_t orig = read32le(off); 271 uint32_t size = orig >> 30; 272 // 0x04000000 indicates SIMD/FP registers 273 // 0x00800000 indicates 128 bit 274 if ((orig & 0x4800000) == 0x4800000) 275 size += 4; 276 if ((imm & ((1 << size) - 1)) != 0) 277 error("misaligned ldr/str offset"); 278 applyArm64Imm(off, imm >> size, size); 279 } 280 281 static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off, 282 OutputSection *os, uint64_t s) { 283 if (checkSecRel(sec, os)) 284 applyArm64Imm(off, (s - os->getRVA()) & 0xfff, 0); 285 } 286 287 static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off, 288 OutputSection *os, uint64_t s) { 289 if (!checkSecRel(sec, os)) 290 return; 291 uint64_t secRel = (s - os->getRVA()) >> 12; 292 if (0xfff < secRel) { 293 error("overflow in SECREL_HIGH12A relocation in section: " + 294 sec->getSectionName()); 295 return; 296 } 297 applyArm64Imm(off, secRel & 0xfff, 0); 298 } 299 300 static void applySecRelLdr(const SectionChunk *sec, uint8_t *off, 301 OutputSection *os, uint64_t s) { 302 if (checkSecRel(sec, os)) 303 applyArm64Ldr(off, (s - os->getRVA()) & 0xfff); 304 } 305 306 void applyArm64Branch26(uint8_t *off, int64_t v) { 307 if (!isInt<28>(v)) 308 error("relocation out of range"); 309 or32(off, (v & 0x0FFFFFFC) >> 2); 310 } 311 312 static void applyArm64Branch19(uint8_t *off, int64_t v) { 313 if (!isInt<21>(v)) 314 error("relocation out of range"); 315 or32(off, (v & 0x001FFFFC) << 3); 316 } 317 318 static void applyArm64Branch14(uint8_t *off, int64_t v) { 319 if (!isInt<16>(v)) 320 error("relocation out of range"); 321 or32(off, (v & 0x0000FFFC) << 3); 322 } 323 324 void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os, 325 uint64_t s, uint64_t p, 326 uint64_t imageBase) const { 327 switch (type) { 328 case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, 12); break; 329 case IMAGE_REL_ARM64_REL21: applyArm64Addr(off, s, p, 0); break; 330 case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, s & 0xfff, 0); break; 331 case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, s & 0xfff); break; 332 case IMAGE_REL_ARM64_BRANCH26: applyArm64Branch26(off, s - p); break; 333 case IMAGE_REL_ARM64_BRANCH19: applyArm64Branch19(off, s - p); break; 334 case IMAGE_REL_ARM64_BRANCH14: applyArm64Branch14(off, s - p); break; 335 case IMAGE_REL_ARM64_ADDR32: 336 add32(off, s + imageBase); 337 break; 338 case IMAGE_REL_ARM64_ADDR32NB: add32(off, s); break; 339 case IMAGE_REL_ARM64_ADDR64: 340 add64(off, s + imageBase); 341 break; 342 case IMAGE_REL_ARM64_SECREL: applySecRel(this, off, os, s); break; 343 case IMAGE_REL_ARM64_SECREL_LOW12A: applySecRelLow12A(this, off, os, s); break; 344 case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, off, os, s); break; 345 case IMAGE_REL_ARM64_SECREL_LOW12L: applySecRelLdr(this, off, os, s); break; 346 case IMAGE_REL_ARM64_SECTION: 347 applySecIdx(off, os, file->ctx.outputSections.size()); 348 break; 349 case IMAGE_REL_ARM64_REL32: add32(off, s - p - 4); break; 350 default: 351 error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " + 352 toString(file)); 353 } 354 } 355 356 static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk, 357 Defined *sym, 358 const coff_relocation &rel, 359 bool isMinGW) { 360 // Don't report these errors when the relocation comes from a debug info 361 // section or in mingw mode. MinGW mode object files (built by GCC) can 362 // have leftover sections with relocations against discarded comdat 363 // sections. Such sections are left as is, with relocations untouched. 364 if (fromChunk->isCodeView() || fromChunk->isDWARF() || isMinGW) 365 return; 366 367 // Get the name of the symbol. If it's null, it was discarded early, so we 368 // have to go back to the object file. 369 ObjFile *file = fromChunk->file; 370 StringRef name; 371 if (sym) { 372 name = sym->getName(); 373 } else { 374 COFFSymbolRef coffSym = 375 check(file->getCOFFObj()->getSymbol(rel.SymbolTableIndex)); 376 name = check(file->getCOFFObj()->getSymbolName(coffSym)); 377 } 378 379 std::vector<std::string> symbolLocations = 380 getSymbolLocations(file, rel.SymbolTableIndex); 381 382 std::string out; 383 llvm::raw_string_ostream os(out); 384 os << "relocation against symbol in discarded section: " + name; 385 for (const std::string &s : symbolLocations) 386 os << s; 387 error(os.str()); 388 } 389 390 void SectionChunk::writeTo(uint8_t *buf) const { 391 if (!hasData) 392 return; 393 // Copy section contents from source object file to output file. 394 ArrayRef<uint8_t> a = getContents(); 395 if (!a.empty()) 396 memcpy(buf, a.data(), a.size()); 397 398 // Apply relocations. 399 size_t inputSize = getSize(); 400 for (const coff_relocation &rel : getRelocs()) { 401 // Check for an invalid relocation offset. This check isn't perfect, because 402 // we don't have the relocation size, which is only known after checking the 403 // machine and relocation type. As a result, a relocation may overwrite the 404 // beginning of the following input section. 405 if (rel.VirtualAddress >= inputSize) { 406 error("relocation points beyond the end of its parent section"); 407 continue; 408 } 409 410 applyRelocation(buf + rel.VirtualAddress, rel); 411 } 412 } 413 414 void SectionChunk::applyRelocation(uint8_t *off, 415 const coff_relocation &rel) const { 416 auto *sym = dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex)); 417 418 // Get the output section of the symbol for this relocation. The output 419 // section is needed to compute SECREL and SECTION relocations used in debug 420 // info. 421 Chunk *c = sym ? sym->getChunk() : nullptr; 422 OutputSection *os = c ? file->ctx.getOutputSection(c) : nullptr; 423 424 // Skip the relocation if it refers to a discarded section, and diagnose it 425 // as an error if appropriate. If a symbol was discarded early, it may be 426 // null. If it was discarded late, the output section will be null, unless 427 // it was an absolute or synthetic symbol. 428 if (!sym || 429 (!os && !isa<DefinedAbsolute>(sym) && !isa<DefinedSynthetic>(sym))) { 430 maybeReportRelocationToDiscarded(this, sym, rel, file->ctx.config.mingw); 431 return; 432 } 433 434 uint64_t s = sym->getRVA(); 435 436 // Compute the RVA of the relocation for relative relocations. 437 uint64_t p = rva + rel.VirtualAddress; 438 uint64_t imageBase = file->ctx.config.imageBase; 439 switch (file->ctx.config.machine) { 440 case AMD64: 441 applyRelX64(off, rel.Type, os, s, p, imageBase); 442 break; 443 case I386: 444 applyRelX86(off, rel.Type, os, s, p, imageBase); 445 break; 446 case ARMNT: 447 applyRelARM(off, rel.Type, os, s, p, imageBase); 448 break; 449 case ARM64: 450 applyRelARM64(off, rel.Type, os, s, p, imageBase); 451 break; 452 default: 453 llvm_unreachable("unknown machine type"); 454 } 455 } 456 457 // Defend against unsorted relocations. This may be overly conservative. 458 void SectionChunk::sortRelocations() { 459 auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) { 460 return l.VirtualAddress < r.VirtualAddress; 461 }; 462 if (llvm::is_sorted(getRelocs(), cmpByVa)) 463 return; 464 warn("some relocations in " + file->getName() + " are not sorted"); 465 MutableArrayRef<coff_relocation> newRelocs( 466 bAlloc().Allocate<coff_relocation>(relocsSize), relocsSize); 467 memcpy(newRelocs.data(), relocsData, relocsSize * sizeof(coff_relocation)); 468 llvm::sort(newRelocs, cmpByVa); 469 setRelocs(newRelocs); 470 } 471 472 // Similar to writeTo, but suitable for relocating a subsection of the overall 473 // section. 474 void SectionChunk::writeAndRelocateSubsection(ArrayRef<uint8_t> sec, 475 ArrayRef<uint8_t> subsec, 476 uint32_t &nextRelocIndex, 477 uint8_t *buf) const { 478 assert(!subsec.empty() && !sec.empty()); 479 assert(sec.begin() <= subsec.begin() && subsec.end() <= sec.end() && 480 "subsection is not part of this section"); 481 size_t vaBegin = std::distance(sec.begin(), subsec.begin()); 482 size_t vaEnd = std::distance(sec.begin(), subsec.end()); 483 memcpy(buf, subsec.data(), subsec.size()); 484 for (; nextRelocIndex < relocsSize; ++nextRelocIndex) { 485 const coff_relocation &rel = relocsData[nextRelocIndex]; 486 // Only apply relocations that apply to this subsection. These checks 487 // assume that all subsections completely contain their relocations. 488 // Relocations must not straddle the beginning or end of a subsection. 489 if (rel.VirtualAddress < vaBegin) 490 continue; 491 if (rel.VirtualAddress + 1 >= vaEnd) 492 break; 493 applyRelocation(&buf[rel.VirtualAddress - vaBegin], rel); 494 } 495 } 496 497 void SectionChunk::addAssociative(SectionChunk *child) { 498 // Insert the child section into the list of associated children. Keep the 499 // list ordered by section name so that ICF does not depend on section order. 500 assert(child->assocChildren == nullptr && 501 "associated sections cannot have their own associated children"); 502 SectionChunk *prev = this; 503 SectionChunk *next = assocChildren; 504 for (; next != nullptr; prev = next, next = next->assocChildren) { 505 if (next->getSectionName() <= child->getSectionName()) 506 break; 507 } 508 509 // Insert child between prev and next. 510 assert(prev->assocChildren == next); 511 prev->assocChildren = child; 512 child->assocChildren = next; 513 } 514 515 static uint8_t getBaserelType(const coff_relocation &rel, 516 llvm::COFF::MachineTypes machine) { 517 switch (machine) { 518 case AMD64: 519 if (rel.Type == IMAGE_REL_AMD64_ADDR64) 520 return IMAGE_REL_BASED_DIR64; 521 if (rel.Type == IMAGE_REL_AMD64_ADDR32) 522 return IMAGE_REL_BASED_HIGHLOW; 523 return IMAGE_REL_BASED_ABSOLUTE; 524 case I386: 525 if (rel.Type == IMAGE_REL_I386_DIR32) 526 return IMAGE_REL_BASED_HIGHLOW; 527 return IMAGE_REL_BASED_ABSOLUTE; 528 case ARMNT: 529 if (rel.Type == IMAGE_REL_ARM_ADDR32) 530 return IMAGE_REL_BASED_HIGHLOW; 531 if (rel.Type == IMAGE_REL_ARM_MOV32T) 532 return IMAGE_REL_BASED_ARM_MOV32T; 533 return IMAGE_REL_BASED_ABSOLUTE; 534 case ARM64: 535 if (rel.Type == IMAGE_REL_ARM64_ADDR64) 536 return IMAGE_REL_BASED_DIR64; 537 return IMAGE_REL_BASED_ABSOLUTE; 538 default: 539 llvm_unreachable("unknown machine type"); 540 } 541 } 542 543 // Windows-specific. 544 // Collect all locations that contain absolute addresses, which need to be 545 // fixed by the loader if load-time relocation is needed. 546 // Only called when base relocation is enabled. 547 void SectionChunk::getBaserels(std::vector<Baserel> *res) { 548 for (const coff_relocation &rel : getRelocs()) { 549 uint8_t ty = getBaserelType(rel, file->ctx.config.machine); 550 if (ty == IMAGE_REL_BASED_ABSOLUTE) 551 continue; 552 Symbol *target = file->getSymbol(rel.SymbolTableIndex); 553 if (!target || isa<DefinedAbsolute>(target)) 554 continue; 555 res->emplace_back(rva + rel.VirtualAddress, ty); 556 } 557 } 558 559 // MinGW specific. 560 // Check whether a static relocation of type Type can be deferred and 561 // handled at runtime as a pseudo relocation (for references to a module 562 // local variable, which turned out to actually need to be imported from 563 // another DLL) This returns the size the relocation is supposed to update, 564 // in bits, or 0 if the relocation cannot be handled as a runtime pseudo 565 // relocation. 566 static int getRuntimePseudoRelocSize(uint16_t type, 567 llvm::COFF::MachineTypes machine) { 568 // Relocations that either contain an absolute address, or a plain 569 // relative offset, since the runtime pseudo reloc implementation 570 // adds 8/16/32/64 bit values to a memory address. 571 // 572 // Given a pseudo relocation entry, 573 // 574 // typedef struct { 575 // DWORD sym; 576 // DWORD target; 577 // DWORD flags; 578 // } runtime_pseudo_reloc_item_v2; 579 // 580 // the runtime relocation performs this adjustment: 581 // *(base + .target) += *(base + .sym) - (base + .sym) 582 // 583 // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64, 584 // IMAGE_REL_I386_DIR32, where the memory location initially contains 585 // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32), 586 // where the memory location originally contains the relative offset to the 587 // IAT slot. 588 // 589 // This requires the target address to be writable, either directly out of 590 // the image, or temporarily changed at runtime with VirtualProtect. 591 // Since this only operates on direct address values, it doesn't work for 592 // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations. 593 switch (machine) { 594 case AMD64: 595 switch (type) { 596 case IMAGE_REL_AMD64_ADDR64: 597 return 64; 598 case IMAGE_REL_AMD64_ADDR32: 599 case IMAGE_REL_AMD64_REL32: 600 case IMAGE_REL_AMD64_REL32_1: 601 case IMAGE_REL_AMD64_REL32_2: 602 case IMAGE_REL_AMD64_REL32_3: 603 case IMAGE_REL_AMD64_REL32_4: 604 case IMAGE_REL_AMD64_REL32_5: 605 return 32; 606 default: 607 return 0; 608 } 609 case I386: 610 switch (type) { 611 case IMAGE_REL_I386_DIR32: 612 case IMAGE_REL_I386_REL32: 613 return 32; 614 default: 615 return 0; 616 } 617 case ARMNT: 618 switch (type) { 619 case IMAGE_REL_ARM_ADDR32: 620 return 32; 621 default: 622 return 0; 623 } 624 case ARM64: 625 switch (type) { 626 case IMAGE_REL_ARM64_ADDR64: 627 return 64; 628 case IMAGE_REL_ARM64_ADDR32: 629 return 32; 630 default: 631 return 0; 632 } 633 default: 634 llvm_unreachable("unknown machine type"); 635 } 636 } 637 638 // MinGW specific. 639 // Append information to the provided vector about all relocations that 640 // need to be handled at runtime as runtime pseudo relocations (references 641 // to a module local variable, which turned out to actually need to be 642 // imported from another DLL). 643 void SectionChunk::getRuntimePseudoRelocs( 644 std::vector<RuntimePseudoReloc> &res) { 645 for (const coff_relocation &rel : getRelocs()) { 646 auto *target = 647 dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex)); 648 if (!target || !target->isRuntimePseudoReloc) 649 continue; 650 int sizeInBits = 651 getRuntimePseudoRelocSize(rel.Type, file->ctx.config.machine); 652 if (sizeInBits == 0) { 653 error("unable to automatically import from " + target->getName() + 654 " with relocation type " + 655 file->getCOFFObj()->getRelocationTypeName(rel.Type) + " in " + 656 toString(file)); 657 continue; 658 } 659 // sizeInBits is used to initialize the Flags field; currently no 660 // other flags are defined. 661 res.emplace_back( 662 RuntimePseudoReloc(target, this, rel.VirtualAddress, sizeInBits)); 663 } 664 } 665 666 bool SectionChunk::isCOMDAT() const { 667 return header->Characteristics & IMAGE_SCN_LNK_COMDAT; 668 } 669 670 void SectionChunk::printDiscardedMessage() const { 671 // Removed by dead-stripping. If it's removed by ICF, ICF already 672 // printed out the name, so don't repeat that here. 673 if (sym && this == repl) 674 log("Discarded " + sym->getName()); 675 } 676 677 StringRef SectionChunk::getDebugName() const { 678 if (sym) 679 return sym->getName(); 680 return ""; 681 } 682 683 ArrayRef<uint8_t> SectionChunk::getContents() const { 684 ArrayRef<uint8_t> a; 685 cantFail(file->getCOFFObj()->getSectionContents(header, a)); 686 return a; 687 } 688 689 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() { 690 assert(isCodeView()); 691 return consumeDebugMagic(getContents(), getSectionName()); 692 } 693 694 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data, 695 StringRef sectionName) { 696 if (data.empty()) 697 return {}; 698 699 // First 4 bytes are section magic. 700 if (data.size() < 4) 701 fatal("the section is too short: " + sectionName); 702 703 if (!sectionName.startswith(".debug$")) 704 fatal("invalid section: " + sectionName); 705 706 uint32_t magic = support::endian::read32le(data.data()); 707 uint32_t expectedMagic = sectionName == ".debug$H" 708 ? DEBUG_HASHES_SECTION_MAGIC 709 : DEBUG_SECTION_MAGIC; 710 if (magic != expectedMagic) { 711 warn("ignoring section " + sectionName + " with unrecognized magic 0x" + 712 utohexstr(magic)); 713 return {}; 714 } 715 return data.slice(4); 716 } 717 718 SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections, 719 StringRef name) { 720 for (SectionChunk *c : sections) 721 if (c->getSectionName() == name) 722 return c; 723 return nullptr; 724 } 725 726 void SectionChunk::replace(SectionChunk *other) { 727 p2Align = std::max(p2Align, other->p2Align); 728 other->repl = repl; 729 other->live = false; 730 } 731 732 uint32_t SectionChunk::getSectionNumber() const { 733 DataRefImpl r; 734 r.p = reinterpret_cast<uintptr_t>(header); 735 SectionRef s(r, file->getCOFFObj()); 736 return s.getIndex() + 1; 737 } 738 739 CommonChunk::CommonChunk(const COFFSymbolRef s) : sym(s) { 740 // The value of a common symbol is its size. Align all common symbols smaller 741 // than 32 bytes naturally, i.e. round the size up to the next power of two. 742 // This is what MSVC link.exe does. 743 setAlignment(std::min(32U, uint32_t(PowerOf2Ceil(sym.getValue())))); 744 hasData = false; 745 } 746 747 uint32_t CommonChunk::getOutputCharacteristics() const { 748 return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ | 749 IMAGE_SCN_MEM_WRITE; 750 } 751 752 void StringChunk::writeTo(uint8_t *buf) const { 753 memcpy(buf, str.data(), str.size()); 754 buf[str.size()] = '\0'; 755 } 756 757 ImportThunkChunkX64::ImportThunkChunkX64(COFFLinkerContext &ctx, Defined *s) 758 : ImportThunkChunk(ctx, s) { 759 // Intel Optimization Manual says that all branch targets 760 // should be 16-byte aligned. MSVC linker does this too. 761 setAlignment(16); 762 } 763 764 void ImportThunkChunkX64::writeTo(uint8_t *buf) const { 765 memcpy(buf, importThunkX86, sizeof(importThunkX86)); 766 // The first two bytes is a JMP instruction. Fill its operand. 767 write32le(buf + 2, impSymbol->getRVA() - rva - getSize()); 768 } 769 770 void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) { 771 res->emplace_back(getRVA() + 2, ctx.config.machine); 772 } 773 774 void ImportThunkChunkX86::writeTo(uint8_t *buf) const { 775 memcpy(buf, importThunkX86, sizeof(importThunkX86)); 776 // The first two bytes is a JMP instruction. Fill its operand. 777 write32le(buf + 2, impSymbol->getRVA() + ctx.config.imageBase); 778 } 779 780 void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) { 781 res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T); 782 } 783 784 void ImportThunkChunkARM::writeTo(uint8_t *buf) const { 785 memcpy(buf, importThunkARM, sizeof(importThunkARM)); 786 // Fix mov.w and mov.t operands. 787 applyMOV32T(buf, impSymbol->getRVA() + ctx.config.imageBase); 788 } 789 790 void ImportThunkChunkARM64::writeTo(uint8_t *buf) const { 791 int64_t off = impSymbol->getRVA() & 0xfff; 792 memcpy(buf, importThunkARM64, sizeof(importThunkARM64)); 793 applyArm64Addr(buf, impSymbol->getRVA(), rva, 12); 794 applyArm64Ldr(buf + 4, off); 795 } 796 797 // A Thumb2, PIC, non-interworking range extension thunk. 798 const uint8_t armThunk[] = { 799 0x40, 0xf2, 0x00, 0x0c, // P: movw ip,:lower16:S - (P + (L1-P) + 4) 800 0xc0, 0xf2, 0x00, 0x0c, // movt ip,:upper16:S - (P + (L1-P) + 4) 801 0xe7, 0x44, // L1: add pc, ip 802 }; 803 804 size_t RangeExtensionThunkARM::getSize() const { 805 assert(ctx.config.machine == ARMNT); 806 (void)&ctx; 807 return sizeof(armThunk); 808 } 809 810 void RangeExtensionThunkARM::writeTo(uint8_t *buf) const { 811 assert(ctx.config.machine == ARMNT); 812 uint64_t offset = target->getRVA() - rva - 12; 813 memcpy(buf, armThunk, sizeof(armThunk)); 814 applyMOV32T(buf, uint32_t(offset)); 815 } 816 817 // A position independent ARM64 adrp+add thunk, with a maximum range of 818 // +/- 4 GB, which is enough for any PE-COFF. 819 const uint8_t arm64Thunk[] = { 820 0x10, 0x00, 0x00, 0x90, // adrp x16, Dest 821 0x10, 0x02, 0x00, 0x91, // add x16, x16, :lo12:Dest 822 0x00, 0x02, 0x1f, 0xd6, // br x16 823 }; 824 825 size_t RangeExtensionThunkARM64::getSize() const { 826 assert(ctx.config.machine == ARM64); 827 (void)&ctx; 828 return sizeof(arm64Thunk); 829 } 830 831 void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const { 832 assert(ctx.config.machine == ARM64); 833 memcpy(buf, arm64Thunk, sizeof(arm64Thunk)); 834 applyArm64Addr(buf + 0, target->getRVA(), rva, 12); 835 applyArm64Imm(buf + 4, target->getRVA() & 0xfff, 0); 836 } 837 838 LocalImportChunk::LocalImportChunk(COFFLinkerContext &c, Defined *s) 839 : sym(s), ctx(c) { 840 setAlignment(ctx.config.wordsize); 841 } 842 843 void LocalImportChunk::getBaserels(std::vector<Baserel> *res) { 844 res->emplace_back(getRVA(), ctx.config.machine); 845 } 846 847 size_t LocalImportChunk::getSize() const { return ctx.config.wordsize; } 848 849 void LocalImportChunk::writeTo(uint8_t *buf) const { 850 if (ctx.config.is64()) { 851 write64le(buf, sym->getRVA() + ctx.config.imageBase); 852 } else { 853 write32le(buf, sym->getRVA() + ctx.config.imageBase); 854 } 855 } 856 857 void RVATableChunk::writeTo(uint8_t *buf) const { 858 ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf); 859 size_t cnt = 0; 860 for (const ChunkAndOffset &co : syms) 861 begin[cnt++] = co.inputChunk->getRVA() + co.offset; 862 llvm::sort(begin, begin + cnt); 863 assert(std::unique(begin, begin + cnt) == begin + cnt && 864 "RVA tables should be de-duplicated"); 865 } 866 867 void RVAFlagTableChunk::writeTo(uint8_t *buf) const { 868 struct RVAFlag { 869 ulittle32_t rva; 870 uint8_t flag; 871 }; 872 auto flags = 873 MutableArrayRef(reinterpret_cast<RVAFlag *>(buf), syms.size()); 874 for (auto t : zip(syms, flags)) { 875 const auto &sym = std::get<0>(t); 876 auto &flag = std::get<1>(t); 877 flag.rva = sym.inputChunk->getRVA() + sym.offset; 878 flag.flag = 0; 879 } 880 llvm::sort(flags, 881 [](const RVAFlag &a, const RVAFlag &b) { return a.rva < b.rva; }); 882 assert(llvm::unique(flags, [](const RVAFlag &a, 883 const RVAFlag &b) { return a.rva == b.rva; }) == 884 flags.end() && 885 "RVA tables should be de-duplicated"); 886 } 887 888 // MinGW specific, for the "automatic import of variables from DLLs" feature. 889 size_t PseudoRelocTableChunk::getSize() const { 890 if (relocs.empty()) 891 return 0; 892 return 12 + 12 * relocs.size(); 893 } 894 895 // MinGW specific. 896 void PseudoRelocTableChunk::writeTo(uint8_t *buf) const { 897 if (relocs.empty()) 898 return; 899 900 ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf); 901 // This is the list header, to signal the runtime pseudo relocation v2 902 // format. 903 table[0] = 0; 904 table[1] = 0; 905 table[2] = 1; 906 907 size_t idx = 3; 908 for (const RuntimePseudoReloc &rpr : relocs) { 909 table[idx + 0] = rpr.sym->getRVA(); 910 table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset; 911 table[idx + 2] = rpr.flags; 912 idx += 3; 913 } 914 } 915 916 // Windows-specific. This class represents a block in .reloc section. 917 // The format is described here. 918 // 919 // On Windows, each DLL is linked against a fixed base address and 920 // usually loaded to that address. However, if there's already another 921 // DLL that overlaps, the loader has to relocate it. To do that, DLLs 922 // contain .reloc sections which contain offsets that need to be fixed 923 // up at runtime. If the loader finds that a DLL cannot be loaded to its 924 // desired base address, it loads it to somewhere else, and add <actual 925 // base address> - <desired base address> to each offset that is 926 // specified by the .reloc section. In ELF terms, .reloc sections 927 // contain relative relocations in REL format (as opposed to RELA.) 928 // 929 // This already significantly reduces the size of relocations compared 930 // to ELF .rel.dyn, but Windows does more to reduce it (probably because 931 // it was invented for PCs in the late '80s or early '90s.) Offsets in 932 // .reloc are grouped by page where the page size is 12 bits, and 933 // offsets sharing the same page address are stored consecutively to 934 // represent them with less space. This is very similar to the page 935 // table which is grouped by (multiple stages of) pages. 936 // 937 // For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00, 938 // 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4 939 // bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they 940 // are represented like this: 941 // 942 // 0x00000 -- page address (4 bytes) 943 // 16 -- size of this block (4 bytes) 944 // 0xA030 -- entries (2 bytes each) 945 // 0xA500 946 // 0xA700 947 // 0xAA00 948 // 0x20000 -- page address (4 bytes) 949 // 12 -- size of this block (4 bytes) 950 // 0xA004 -- entries (2 bytes each) 951 // 0xA008 952 // 953 // Usually we have a lot of relocations for each page, so the number of 954 // bytes for one .reloc entry is close to 2 bytes on average. 955 BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) { 956 // Block header consists of 4 byte page RVA and 4 byte block size. 957 // Each entry is 2 byte. Last entry may be padding. 958 data.resize(alignTo((end - begin) * 2 + 8, 4)); 959 uint8_t *p = data.data(); 960 write32le(p, page); 961 write32le(p + 4, data.size()); 962 p += 8; 963 for (Baserel *i = begin; i != end; ++i) { 964 write16le(p, (i->type << 12) | (i->rva - page)); 965 p += 2; 966 } 967 } 968 969 void BaserelChunk::writeTo(uint8_t *buf) const { 970 memcpy(buf, data.data(), data.size()); 971 } 972 973 uint8_t Baserel::getDefaultType(llvm::COFF::MachineTypes machine) { 974 switch (machine) { 975 case AMD64: 976 case ARM64: 977 return IMAGE_REL_BASED_DIR64; 978 case I386: 979 case ARMNT: 980 return IMAGE_REL_BASED_HIGHLOW; 981 default: 982 llvm_unreachable("unknown machine type"); 983 } 984 } 985 986 MergeChunk::MergeChunk(uint32_t alignment) 987 : builder(StringTableBuilder::RAW, llvm::Align(alignment)) { 988 setAlignment(alignment); 989 } 990 991 void MergeChunk::addSection(COFFLinkerContext &ctx, SectionChunk *c) { 992 assert(isPowerOf2_32(c->getAlignment())); 993 uint8_t p2Align = llvm::Log2_32(c->getAlignment()); 994 assert(p2Align < std::size(ctx.mergeChunkInstances)); 995 auto *&mc = ctx.mergeChunkInstances[p2Align]; 996 if (!mc) 997 mc = make<MergeChunk>(c->getAlignment()); 998 mc->sections.push_back(c); 999 } 1000 1001 void MergeChunk::finalizeContents() { 1002 assert(!finalized && "should only finalize once"); 1003 for (SectionChunk *c : sections) 1004 if (c->live) 1005 builder.add(toStringRef(c->getContents())); 1006 builder.finalize(); 1007 finalized = true; 1008 } 1009 1010 void MergeChunk::assignSubsectionRVAs() { 1011 for (SectionChunk *c : sections) { 1012 if (!c->live) 1013 continue; 1014 size_t off = builder.getOffset(toStringRef(c->getContents())); 1015 c->setRVA(rva + off); 1016 } 1017 } 1018 1019 uint32_t MergeChunk::getOutputCharacteristics() const { 1020 return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA; 1021 } 1022 1023 size_t MergeChunk::getSize() const { 1024 return builder.getSize(); 1025 } 1026 1027 void MergeChunk::writeTo(uint8_t *buf) const { 1028 builder.write(buf); 1029 } 1030 1031 // MinGW specific. 1032 size_t AbsolutePointerChunk::getSize() const { return ctx.config.wordsize; } 1033 1034 void AbsolutePointerChunk::writeTo(uint8_t *buf) const { 1035 if (ctx.config.is64()) { 1036 write64le(buf, value); 1037 } else { 1038 write32le(buf, value); 1039 } 1040 } 1041 1042 } // namespace lld::coff 1043