xref: /freebsd/contrib/llvm-project/libunwind/include/libunwind.h (revision 43a5ec4eb41567cc92586503212743d89686d78f) 
1 //===---------------------------- libunwind.h -----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 // Compatible with libunwind API documented at:
9 //   http://www.nongnu.org/libunwind/man/libunwind(3).html
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef __LIBUNWIND__
14 #define __LIBUNWIND__
15 
16 #include <__libunwind_config.h>
17 
18 #include <stdint.h>
19 #include <stddef.h>
20 
21 #ifdef __APPLE__
22   #if __clang__
23     #if __has_include(<Availability.h>)
24       #include <Availability.h>
25     #endif
26   #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
27     #include <Availability.h>
28   #endif
29 
30   #ifdef __arm__
31      #define LIBUNWIND_AVAIL __attribute__((unavailable))
32   #elif defined(__OSX_AVAILABLE_STARTING)
33     #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
34   #else
35     #include <AvailabilityMacros.h>
36     #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
37       #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
38     #else
39       #define LIBUNWIND_AVAIL __attribute__((unavailable))
40     #endif
41   #endif
42 #else
43   #define LIBUNWIND_AVAIL
44 #endif
45 
46 #if defined(_WIN32) && defined(__SEH__)
47   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16)))
48 #else
49   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR
50 #endif
51 
52 /* error codes */
53 enum {
54   UNW_ESUCCESS      = 0,     /* no error */
55   UNW_EUNSPEC       = -6540, /* unspecified (general) error */
56   UNW_ENOMEM        = -6541, /* out of memory */
57   UNW_EBADREG       = -6542, /* bad register number */
58   UNW_EREADONLYREG  = -6543, /* attempt to write read-only register */
59   UNW_ESTOPUNWIND   = -6544, /* stop unwinding */
60   UNW_EINVALIDIP    = -6545, /* invalid IP */
61   UNW_EBADFRAME     = -6546, /* bad frame */
62   UNW_EINVAL        = -6547, /* unsupported operation or bad value */
63   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
64   UNW_ENOINFO       = -6549  /* no unwind info found */
65 #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
66   , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
67 #endif
68 };
69 
70 struct unw_context_t {
71   uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
72 };
73 typedef struct unw_context_t unw_context_t;
74 
75 struct unw_cursor_t {
76   uint64_t data[_LIBUNWIND_CURSOR_SIZE];
77 } LIBUNWIND_CURSOR_ALIGNMENT_ATTR;
78 typedef struct unw_cursor_t unw_cursor_t;
79 
80 typedef struct unw_addr_space *unw_addr_space_t;
81 
82 typedef int unw_regnum_t;
83 typedef uintptr_t unw_word_t;
84 #if defined(__arm__) && !defined(__ARM_DWARF_EH__)
85 typedef uint64_t unw_fpreg_t;
86 #else
87 typedef double unw_fpreg_t;
88 #endif
89 
90 struct unw_proc_info_t {
91   unw_word_t  start_ip;         /* start address of function */
92   unw_word_t  end_ip;           /* address after end of function */
93   unw_word_t  lsda;             /* address of language specific data area, */
94                                 /*  or zero if not used */
95   unw_word_t  handler;          /* personality routine, or zero if not used */
96   unw_word_t  gp;               /* not used */
97   unw_word_t  flags;            /* not used */
98   uint32_t    format;           /* compact unwind encoding, or zero if none */
99   uint32_t    unwind_info_size; /* size of DWARF unwind info, or zero if none */
100   unw_word_t  unwind_info;      /* address of DWARF unwind info, or zero */
101   unw_word_t  extra;            /* mach_header of mach-o image containing func */
102 };
103 typedef struct unw_proc_info_t unw_proc_info_t;
104 
105 #ifdef __cplusplus
106 extern "C" {
107 #endif
108 
109 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
110 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
111 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
112 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
113 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
114 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
115 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t)  LIBUNWIND_AVAIL;
116 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
117 
118 #ifdef __arm__
119 /* Save VFP registers in FSTMX format (instead of FSTMD). */
120 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
121 #endif
122 
123 
124 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
125 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
126 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
127 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
128 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
129 //extern int       unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
130 
131 extern unw_addr_space_t unw_local_addr_space;
132 
133 #ifdef __cplusplus
134 }
135 #endif
136 
137 // architecture independent register numbers
138 enum {
139   UNW_REG_IP = -1, // instruction pointer
140   UNW_REG_SP = -2, // stack pointer
141 };
142 
143 // 32-bit x86 registers
144 enum {
145   UNW_X86_EAX = 0,
146   UNW_X86_ECX = 1,
147   UNW_X86_EDX = 2,
148   UNW_X86_EBX = 3,
149   UNW_X86_EBP = 4,
150   UNW_X86_ESP = 5,
151   UNW_X86_ESI = 6,
152   UNW_X86_EDI = 7
153 };
154 
155 // 64-bit x86_64 registers
156 enum {
157   UNW_X86_64_RAX = 0,
158   UNW_X86_64_RDX = 1,
159   UNW_X86_64_RCX = 2,
160   UNW_X86_64_RBX = 3,
161   UNW_X86_64_RSI = 4,
162   UNW_X86_64_RDI = 5,
163   UNW_X86_64_RBP = 6,
164   UNW_X86_64_RSP = 7,
165   UNW_X86_64_R8  = 8,
166   UNW_X86_64_R9  = 9,
167   UNW_X86_64_R10 = 10,
168   UNW_X86_64_R11 = 11,
169   UNW_X86_64_R12 = 12,
170   UNW_X86_64_R13 = 13,
171   UNW_X86_64_R14 = 14,
172   UNW_X86_64_R15 = 15,
173   UNW_X86_64_RIP = 16,
174   UNW_X86_64_XMM0 = 17,
175   UNW_X86_64_XMM1 = 18,
176   UNW_X86_64_XMM2 = 19,
177   UNW_X86_64_XMM3 = 20,
178   UNW_X86_64_XMM4 = 21,
179   UNW_X86_64_XMM5 = 22,
180   UNW_X86_64_XMM6 = 23,
181   UNW_X86_64_XMM7 = 24,
182   UNW_X86_64_XMM8 = 25,
183   UNW_X86_64_XMM9 = 26,
184   UNW_X86_64_XMM10 = 27,
185   UNW_X86_64_XMM11 = 28,
186   UNW_X86_64_XMM12 = 29,
187   UNW_X86_64_XMM13 = 30,
188   UNW_X86_64_XMM14 = 31,
189   UNW_X86_64_XMM15 = 32,
190 };
191 
192 
193 // 32-bit ppc register numbers
194 enum {
195   UNW_PPC_R0  = 0,
196   UNW_PPC_R1  = 1,
197   UNW_PPC_R2  = 2,
198   UNW_PPC_R3  = 3,
199   UNW_PPC_R4  = 4,
200   UNW_PPC_R5  = 5,
201   UNW_PPC_R6  = 6,
202   UNW_PPC_R7  = 7,
203   UNW_PPC_R8  = 8,
204   UNW_PPC_R9  = 9,
205   UNW_PPC_R10 = 10,
206   UNW_PPC_R11 = 11,
207   UNW_PPC_R12 = 12,
208   UNW_PPC_R13 = 13,
209   UNW_PPC_R14 = 14,
210   UNW_PPC_R15 = 15,
211   UNW_PPC_R16 = 16,
212   UNW_PPC_R17 = 17,
213   UNW_PPC_R18 = 18,
214   UNW_PPC_R19 = 19,
215   UNW_PPC_R20 = 20,
216   UNW_PPC_R21 = 21,
217   UNW_PPC_R22 = 22,
218   UNW_PPC_R23 = 23,
219   UNW_PPC_R24 = 24,
220   UNW_PPC_R25 = 25,
221   UNW_PPC_R26 = 26,
222   UNW_PPC_R27 = 27,
223   UNW_PPC_R28 = 28,
224   UNW_PPC_R29 = 29,
225   UNW_PPC_R30 = 30,
226   UNW_PPC_R31 = 31,
227   UNW_PPC_F0  = 32,
228   UNW_PPC_F1  = 33,
229   UNW_PPC_F2  = 34,
230   UNW_PPC_F3  = 35,
231   UNW_PPC_F4  = 36,
232   UNW_PPC_F5  = 37,
233   UNW_PPC_F6  = 38,
234   UNW_PPC_F7  = 39,
235   UNW_PPC_F8  = 40,
236   UNW_PPC_F9  = 41,
237   UNW_PPC_F10 = 42,
238   UNW_PPC_F11 = 43,
239   UNW_PPC_F12 = 44,
240   UNW_PPC_F13 = 45,
241   UNW_PPC_F14 = 46,
242   UNW_PPC_F15 = 47,
243   UNW_PPC_F16 = 48,
244   UNW_PPC_F17 = 49,
245   UNW_PPC_F18 = 50,
246   UNW_PPC_F19 = 51,
247   UNW_PPC_F20 = 52,
248   UNW_PPC_F21 = 53,
249   UNW_PPC_F22 = 54,
250   UNW_PPC_F23 = 55,
251   UNW_PPC_F24 = 56,
252   UNW_PPC_F25 = 57,
253   UNW_PPC_F26 = 58,
254   UNW_PPC_F27 = 59,
255   UNW_PPC_F28 = 60,
256   UNW_PPC_F29 = 61,
257   UNW_PPC_F30 = 62,
258   UNW_PPC_F31 = 63,
259   UNW_PPC_MQ  = 64,
260   UNW_PPC_LR  = 65,
261   UNW_PPC_CTR = 66,
262   UNW_PPC_AP  = 67,
263   UNW_PPC_CR0 = 68,
264   UNW_PPC_CR1 = 69,
265   UNW_PPC_CR2 = 70,
266   UNW_PPC_CR3 = 71,
267   UNW_PPC_CR4 = 72,
268   UNW_PPC_CR5 = 73,
269   UNW_PPC_CR6 = 74,
270   UNW_PPC_CR7 = 75,
271   UNW_PPC_XER = 76,
272   UNW_PPC_V0  = 77,
273   UNW_PPC_V1  = 78,
274   UNW_PPC_V2  = 79,
275   UNW_PPC_V3  = 80,
276   UNW_PPC_V4  = 81,
277   UNW_PPC_V5  = 82,
278   UNW_PPC_V6  = 83,
279   UNW_PPC_V7  = 84,
280   UNW_PPC_V8  = 85,
281   UNW_PPC_V9  = 86,
282   UNW_PPC_V10 = 87,
283   UNW_PPC_V11 = 88,
284   UNW_PPC_V12 = 89,
285   UNW_PPC_V13 = 90,
286   UNW_PPC_V14 = 91,
287   UNW_PPC_V15 = 92,
288   UNW_PPC_V16 = 93,
289   UNW_PPC_V17 = 94,
290   UNW_PPC_V18 = 95,
291   UNW_PPC_V19 = 96,
292   UNW_PPC_V20 = 97,
293   UNW_PPC_V21 = 98,
294   UNW_PPC_V22 = 99,
295   UNW_PPC_V23 = 100,
296   UNW_PPC_V24 = 101,
297   UNW_PPC_V25 = 102,
298   UNW_PPC_V26 = 103,
299   UNW_PPC_V27 = 104,
300   UNW_PPC_V28 = 105,
301   UNW_PPC_V29 = 106,
302   UNW_PPC_V30 = 107,
303   UNW_PPC_V31 = 108,
304   UNW_PPC_VRSAVE  = 109,
305   UNW_PPC_VSCR    = 110,
306   UNW_PPC_SPE_ACC = 111,
307   UNW_PPC_SPEFSCR = 112
308 };
309 
310 // 64-bit ppc register numbers
311 enum {
312   UNW_PPC64_R0      = 0,
313   UNW_PPC64_R1      = 1,
314   UNW_PPC64_R2      = 2,
315   UNW_PPC64_R3      = 3,
316   UNW_PPC64_R4      = 4,
317   UNW_PPC64_R5      = 5,
318   UNW_PPC64_R6      = 6,
319   UNW_PPC64_R7      = 7,
320   UNW_PPC64_R8      = 8,
321   UNW_PPC64_R9      = 9,
322   UNW_PPC64_R10     = 10,
323   UNW_PPC64_R11     = 11,
324   UNW_PPC64_R12     = 12,
325   UNW_PPC64_R13     = 13,
326   UNW_PPC64_R14     = 14,
327   UNW_PPC64_R15     = 15,
328   UNW_PPC64_R16     = 16,
329   UNW_PPC64_R17     = 17,
330   UNW_PPC64_R18     = 18,
331   UNW_PPC64_R19     = 19,
332   UNW_PPC64_R20     = 20,
333   UNW_PPC64_R21     = 21,
334   UNW_PPC64_R22     = 22,
335   UNW_PPC64_R23     = 23,
336   UNW_PPC64_R24     = 24,
337   UNW_PPC64_R25     = 25,
338   UNW_PPC64_R26     = 26,
339   UNW_PPC64_R27     = 27,
340   UNW_PPC64_R28     = 28,
341   UNW_PPC64_R29     = 29,
342   UNW_PPC64_R30     = 30,
343   UNW_PPC64_R31     = 31,
344   UNW_PPC64_F0      = 32,
345   UNW_PPC64_F1      = 33,
346   UNW_PPC64_F2      = 34,
347   UNW_PPC64_F3      = 35,
348   UNW_PPC64_F4      = 36,
349   UNW_PPC64_F5      = 37,
350   UNW_PPC64_F6      = 38,
351   UNW_PPC64_F7      = 39,
352   UNW_PPC64_F8      = 40,
353   UNW_PPC64_F9      = 41,
354   UNW_PPC64_F10     = 42,
355   UNW_PPC64_F11     = 43,
356   UNW_PPC64_F12     = 44,
357   UNW_PPC64_F13     = 45,
358   UNW_PPC64_F14     = 46,
359   UNW_PPC64_F15     = 47,
360   UNW_PPC64_F16     = 48,
361   UNW_PPC64_F17     = 49,
362   UNW_PPC64_F18     = 50,
363   UNW_PPC64_F19     = 51,
364   UNW_PPC64_F20     = 52,
365   UNW_PPC64_F21     = 53,
366   UNW_PPC64_F22     = 54,
367   UNW_PPC64_F23     = 55,
368   UNW_PPC64_F24     = 56,
369   UNW_PPC64_F25     = 57,
370   UNW_PPC64_F26     = 58,
371   UNW_PPC64_F27     = 59,
372   UNW_PPC64_F28     = 60,
373   UNW_PPC64_F29     = 61,
374   UNW_PPC64_F30     = 62,
375   UNW_PPC64_F31     = 63,
376   // 64: reserved
377   UNW_PPC64_LR      = 65,
378   UNW_PPC64_CTR     = 66,
379   // 67: reserved
380   UNW_PPC64_CR0     = 68,
381   UNW_PPC64_CR1     = 69,
382   UNW_PPC64_CR2     = 70,
383   UNW_PPC64_CR3     = 71,
384   UNW_PPC64_CR4     = 72,
385   UNW_PPC64_CR5     = 73,
386   UNW_PPC64_CR6     = 74,
387   UNW_PPC64_CR7     = 75,
388   UNW_PPC64_XER     = 76,
389   UNW_PPC64_V0      = 77,
390   UNW_PPC64_V1      = 78,
391   UNW_PPC64_V2      = 79,
392   UNW_PPC64_V3      = 80,
393   UNW_PPC64_V4      = 81,
394   UNW_PPC64_V5      = 82,
395   UNW_PPC64_V6      = 83,
396   UNW_PPC64_V7      = 84,
397   UNW_PPC64_V8      = 85,
398   UNW_PPC64_V9      = 86,
399   UNW_PPC64_V10     = 87,
400   UNW_PPC64_V11     = 88,
401   UNW_PPC64_V12     = 89,
402   UNW_PPC64_V13     = 90,
403   UNW_PPC64_V14     = 91,
404   UNW_PPC64_V15     = 92,
405   UNW_PPC64_V16     = 93,
406   UNW_PPC64_V17     = 94,
407   UNW_PPC64_V18     = 95,
408   UNW_PPC64_V19     = 96,
409   UNW_PPC64_V20     = 97,
410   UNW_PPC64_V21     = 98,
411   UNW_PPC64_V22     = 99,
412   UNW_PPC64_V23     = 100,
413   UNW_PPC64_V24     = 101,
414   UNW_PPC64_V25     = 102,
415   UNW_PPC64_V26     = 103,
416   UNW_PPC64_V27     = 104,
417   UNW_PPC64_V28     = 105,
418   UNW_PPC64_V29     = 106,
419   UNW_PPC64_V30     = 107,
420   UNW_PPC64_V31     = 108,
421   // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
422   // Borrowing VRSAVE number from PPC32.
423   UNW_PPC64_VRSAVE  = 109,
424   UNW_PPC64_VSCR    = 110,
425   UNW_PPC64_TFHAR   = 114,
426   UNW_PPC64_TFIAR   = 115,
427   UNW_PPC64_TEXASR  = 116,
428   UNW_PPC64_VS0     = UNW_PPC64_F0,
429   UNW_PPC64_VS1     = UNW_PPC64_F1,
430   UNW_PPC64_VS2     = UNW_PPC64_F2,
431   UNW_PPC64_VS3     = UNW_PPC64_F3,
432   UNW_PPC64_VS4     = UNW_PPC64_F4,
433   UNW_PPC64_VS5     = UNW_PPC64_F5,
434   UNW_PPC64_VS6     = UNW_PPC64_F6,
435   UNW_PPC64_VS7     = UNW_PPC64_F7,
436   UNW_PPC64_VS8     = UNW_PPC64_F8,
437   UNW_PPC64_VS9     = UNW_PPC64_F9,
438   UNW_PPC64_VS10    = UNW_PPC64_F10,
439   UNW_PPC64_VS11    = UNW_PPC64_F11,
440   UNW_PPC64_VS12    = UNW_PPC64_F12,
441   UNW_PPC64_VS13    = UNW_PPC64_F13,
442   UNW_PPC64_VS14    = UNW_PPC64_F14,
443   UNW_PPC64_VS15    = UNW_PPC64_F15,
444   UNW_PPC64_VS16    = UNW_PPC64_F16,
445   UNW_PPC64_VS17    = UNW_PPC64_F17,
446   UNW_PPC64_VS18    = UNW_PPC64_F18,
447   UNW_PPC64_VS19    = UNW_PPC64_F19,
448   UNW_PPC64_VS20    = UNW_PPC64_F20,
449   UNW_PPC64_VS21    = UNW_PPC64_F21,
450   UNW_PPC64_VS22    = UNW_PPC64_F22,
451   UNW_PPC64_VS23    = UNW_PPC64_F23,
452   UNW_PPC64_VS24    = UNW_PPC64_F24,
453   UNW_PPC64_VS25    = UNW_PPC64_F25,
454   UNW_PPC64_VS26    = UNW_PPC64_F26,
455   UNW_PPC64_VS27    = UNW_PPC64_F27,
456   UNW_PPC64_VS28    = UNW_PPC64_F28,
457   UNW_PPC64_VS29    = UNW_PPC64_F29,
458   UNW_PPC64_VS30    = UNW_PPC64_F30,
459   UNW_PPC64_VS31    = UNW_PPC64_F31,
460   UNW_PPC64_VS32    = UNW_PPC64_V0,
461   UNW_PPC64_VS33    = UNW_PPC64_V1,
462   UNW_PPC64_VS34    = UNW_PPC64_V2,
463   UNW_PPC64_VS35    = UNW_PPC64_V3,
464   UNW_PPC64_VS36    = UNW_PPC64_V4,
465   UNW_PPC64_VS37    = UNW_PPC64_V5,
466   UNW_PPC64_VS38    = UNW_PPC64_V6,
467   UNW_PPC64_VS39    = UNW_PPC64_V7,
468   UNW_PPC64_VS40    = UNW_PPC64_V8,
469   UNW_PPC64_VS41    = UNW_PPC64_V9,
470   UNW_PPC64_VS42    = UNW_PPC64_V10,
471   UNW_PPC64_VS43    = UNW_PPC64_V11,
472   UNW_PPC64_VS44    = UNW_PPC64_V12,
473   UNW_PPC64_VS45    = UNW_PPC64_V13,
474   UNW_PPC64_VS46    = UNW_PPC64_V14,
475   UNW_PPC64_VS47    = UNW_PPC64_V15,
476   UNW_PPC64_VS48    = UNW_PPC64_V16,
477   UNW_PPC64_VS49    = UNW_PPC64_V17,
478   UNW_PPC64_VS50    = UNW_PPC64_V18,
479   UNW_PPC64_VS51    = UNW_PPC64_V19,
480   UNW_PPC64_VS52    = UNW_PPC64_V20,
481   UNW_PPC64_VS53    = UNW_PPC64_V21,
482   UNW_PPC64_VS54    = UNW_PPC64_V22,
483   UNW_PPC64_VS55    = UNW_PPC64_V23,
484   UNW_PPC64_VS56    = UNW_PPC64_V24,
485   UNW_PPC64_VS57    = UNW_PPC64_V25,
486   UNW_PPC64_VS58    = UNW_PPC64_V26,
487   UNW_PPC64_VS59    = UNW_PPC64_V27,
488   UNW_PPC64_VS60    = UNW_PPC64_V28,
489   UNW_PPC64_VS61    = UNW_PPC64_V29,
490   UNW_PPC64_VS62    = UNW_PPC64_V30,
491   UNW_PPC64_VS63    = UNW_PPC64_V31
492 };
493 
494 // 64-bit ARM64 registers
495 enum {
496   UNW_ARM64_X0 = 0,
497   UNW_ARM64_X1 = 1,
498   UNW_ARM64_X2 = 2,
499   UNW_ARM64_X3 = 3,
500   UNW_ARM64_X4 = 4,
501   UNW_ARM64_X5 = 5,
502   UNW_ARM64_X6 = 6,
503   UNW_ARM64_X7 = 7,
504   UNW_ARM64_X8 = 8,
505   UNW_ARM64_X9 = 9,
506   UNW_ARM64_X10 = 10,
507   UNW_ARM64_X11 = 11,
508   UNW_ARM64_X12 = 12,
509   UNW_ARM64_X13 = 13,
510   UNW_ARM64_X14 = 14,
511   UNW_ARM64_X15 = 15,
512   UNW_ARM64_X16 = 16,
513   UNW_ARM64_X17 = 17,
514   UNW_ARM64_X18 = 18,
515   UNW_ARM64_X19 = 19,
516   UNW_ARM64_X20 = 20,
517   UNW_ARM64_X21 = 21,
518   UNW_ARM64_X22 = 22,
519   UNW_ARM64_X23 = 23,
520   UNW_ARM64_X24 = 24,
521   UNW_ARM64_X25 = 25,
522   UNW_ARM64_X26 = 26,
523   UNW_ARM64_X27 = 27,
524   UNW_ARM64_X28 = 28,
525   UNW_ARM64_X29 = 29,
526   UNW_ARM64_FP = 29,
527   UNW_ARM64_X30 = 30,
528   UNW_ARM64_LR = 30,
529   UNW_ARM64_X31 = 31,
530   UNW_ARM64_SP = 31,
531   UNW_ARM64_PC = 32,
532   // reserved block
533   UNW_ARM64_RA_SIGN_STATE = 34,
534   // reserved block
535   UNW_ARM64_D0 = 64,
536   UNW_ARM64_D1 = 65,
537   UNW_ARM64_D2 = 66,
538   UNW_ARM64_D3 = 67,
539   UNW_ARM64_D4 = 68,
540   UNW_ARM64_D5 = 69,
541   UNW_ARM64_D6 = 70,
542   UNW_ARM64_D7 = 71,
543   UNW_ARM64_D8 = 72,
544   UNW_ARM64_D9 = 73,
545   UNW_ARM64_D10 = 74,
546   UNW_ARM64_D11 = 75,
547   UNW_ARM64_D12 = 76,
548   UNW_ARM64_D13 = 77,
549   UNW_ARM64_D14 = 78,
550   UNW_ARM64_D15 = 79,
551   UNW_ARM64_D16 = 80,
552   UNW_ARM64_D17 = 81,
553   UNW_ARM64_D18 = 82,
554   UNW_ARM64_D19 = 83,
555   UNW_ARM64_D20 = 84,
556   UNW_ARM64_D21 = 85,
557   UNW_ARM64_D22 = 86,
558   UNW_ARM64_D23 = 87,
559   UNW_ARM64_D24 = 88,
560   UNW_ARM64_D25 = 89,
561   UNW_ARM64_D26 = 90,
562   UNW_ARM64_D27 = 91,
563   UNW_ARM64_D28 = 92,
564   UNW_ARM64_D29 = 93,
565   UNW_ARM64_D30 = 94,
566   UNW_ARM64_D31 = 95,
567 };
568 
569 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
570 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
571 // In this scheme, even though the 64-bit floating point registers D0-D31
572 // overlap physically with the 32-bit floating pointer registers S0-S31,
573 // they are given a non-overlapping range of register numbers.
574 //
575 // Commented out ranges are not preserved during unwinding.
576 enum {
577   UNW_ARM_R0  = 0,
578   UNW_ARM_R1  = 1,
579   UNW_ARM_R2  = 2,
580   UNW_ARM_R3  = 3,
581   UNW_ARM_R4  = 4,
582   UNW_ARM_R5  = 5,
583   UNW_ARM_R6  = 6,
584   UNW_ARM_R7  = 7,
585   UNW_ARM_R8  = 8,
586   UNW_ARM_R9  = 9,
587   UNW_ARM_R10 = 10,
588   UNW_ARM_R11 = 11,
589   UNW_ARM_R12 = 12,
590   UNW_ARM_SP  = 13,  // Logical alias for UNW_REG_SP
591   UNW_ARM_R13 = 13,
592   UNW_ARM_LR  = 14,
593   UNW_ARM_R14 = 14,
594   UNW_ARM_IP  = 15,  // Logical alias for UNW_REG_IP
595   UNW_ARM_R15 = 15,
596   // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
597   UNW_ARM_S0  = 64,
598   UNW_ARM_S1  = 65,
599   UNW_ARM_S2  = 66,
600   UNW_ARM_S3  = 67,
601   UNW_ARM_S4  = 68,
602   UNW_ARM_S5  = 69,
603   UNW_ARM_S6  = 70,
604   UNW_ARM_S7  = 71,
605   UNW_ARM_S8  = 72,
606   UNW_ARM_S9  = 73,
607   UNW_ARM_S10 = 74,
608   UNW_ARM_S11 = 75,
609   UNW_ARM_S12 = 76,
610   UNW_ARM_S13 = 77,
611   UNW_ARM_S14 = 78,
612   UNW_ARM_S15 = 79,
613   UNW_ARM_S16 = 80,
614   UNW_ARM_S17 = 81,
615   UNW_ARM_S18 = 82,
616   UNW_ARM_S19 = 83,
617   UNW_ARM_S20 = 84,
618   UNW_ARM_S21 = 85,
619   UNW_ARM_S22 = 86,
620   UNW_ARM_S23 = 87,
621   UNW_ARM_S24 = 88,
622   UNW_ARM_S25 = 89,
623   UNW_ARM_S26 = 90,
624   UNW_ARM_S27 = 91,
625   UNW_ARM_S28 = 92,
626   UNW_ARM_S29 = 93,
627   UNW_ARM_S30 = 94,
628   UNW_ARM_S31 = 95,
629   //  96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
630   // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
631   UNW_ARM_WR0 = 112,
632   UNW_ARM_WR1 = 113,
633   UNW_ARM_WR2 = 114,
634   UNW_ARM_WR3 = 115,
635   UNW_ARM_WR4 = 116,
636   UNW_ARM_WR5 = 117,
637   UNW_ARM_WR6 = 118,
638   UNW_ARM_WR7 = 119,
639   UNW_ARM_WR8 = 120,
640   UNW_ARM_WR9 = 121,
641   UNW_ARM_WR10 = 122,
642   UNW_ARM_WR11 = 123,
643   UNW_ARM_WR12 = 124,
644   UNW_ARM_WR13 = 125,
645   UNW_ARM_WR14 = 126,
646   UNW_ARM_WR15 = 127,
647   // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
648   // 134-143 -- Reserved
649   // 144-150 -- R8_USR-R14_USR
650   // 151-157 -- R8_FIQ-R14_FIQ
651   // 158-159 -- R13_IRQ-R14_IRQ
652   // 160-161 -- R13_ABT-R14_ABT
653   // 162-163 -- R13_UND-R14_UND
654   // 164-165 -- R13_SVC-R14_SVC
655   // 166-191 -- Reserved
656   UNW_ARM_WC0 = 192,
657   UNW_ARM_WC1 = 193,
658   UNW_ARM_WC2 = 194,
659   UNW_ARM_WC3 = 195,
660   // 196-199 -- wC4-wC7 (Intel wireless MMX control)
661   // 200-255 -- Reserved
662   UNW_ARM_D0  = 256,
663   UNW_ARM_D1  = 257,
664   UNW_ARM_D2  = 258,
665   UNW_ARM_D3  = 259,
666   UNW_ARM_D4  = 260,
667   UNW_ARM_D5  = 261,
668   UNW_ARM_D6  = 262,
669   UNW_ARM_D7  = 263,
670   UNW_ARM_D8  = 264,
671   UNW_ARM_D9  = 265,
672   UNW_ARM_D10 = 266,
673   UNW_ARM_D11 = 267,
674   UNW_ARM_D12 = 268,
675   UNW_ARM_D13 = 269,
676   UNW_ARM_D14 = 270,
677   UNW_ARM_D15 = 271,
678   UNW_ARM_D16 = 272,
679   UNW_ARM_D17 = 273,
680   UNW_ARM_D18 = 274,
681   UNW_ARM_D19 = 275,
682   UNW_ARM_D20 = 276,
683   UNW_ARM_D21 = 277,
684   UNW_ARM_D22 = 278,
685   UNW_ARM_D23 = 279,
686   UNW_ARM_D24 = 280,
687   UNW_ARM_D25 = 281,
688   UNW_ARM_D26 = 282,
689   UNW_ARM_D27 = 283,
690   UNW_ARM_D28 = 284,
691   UNW_ARM_D29 = 285,
692   UNW_ARM_D30 = 286,
693   UNW_ARM_D31 = 287,
694   // 288-319 -- Reserved for VFP/Neon
695   // 320-8191 -- Reserved
696   // 8192-16383 -- Unspecified vendor co-processor register.
697 };
698 
699 // OpenRISC1000 register numbers
700 enum {
701   UNW_OR1K_R0  = 0,
702   UNW_OR1K_R1  = 1,
703   UNW_OR1K_R2  = 2,
704   UNW_OR1K_R3  = 3,
705   UNW_OR1K_R4  = 4,
706   UNW_OR1K_R5  = 5,
707   UNW_OR1K_R6  = 6,
708   UNW_OR1K_R7  = 7,
709   UNW_OR1K_R8  = 8,
710   UNW_OR1K_R9  = 9,
711   UNW_OR1K_R10 = 10,
712   UNW_OR1K_R11 = 11,
713   UNW_OR1K_R12 = 12,
714   UNW_OR1K_R13 = 13,
715   UNW_OR1K_R14 = 14,
716   UNW_OR1K_R15 = 15,
717   UNW_OR1K_R16 = 16,
718   UNW_OR1K_R17 = 17,
719   UNW_OR1K_R18 = 18,
720   UNW_OR1K_R19 = 19,
721   UNW_OR1K_R20 = 20,
722   UNW_OR1K_R21 = 21,
723   UNW_OR1K_R22 = 22,
724   UNW_OR1K_R23 = 23,
725   UNW_OR1K_R24 = 24,
726   UNW_OR1K_R25 = 25,
727   UNW_OR1K_R26 = 26,
728   UNW_OR1K_R27 = 27,
729   UNW_OR1K_R28 = 28,
730   UNW_OR1K_R29 = 29,
731   UNW_OR1K_R30 = 30,
732   UNW_OR1K_R31 = 31,
733   UNW_OR1K_EPCR = 32,
734 };
735 
736 // MIPS registers
737 enum {
738   UNW_MIPS_R0  = 0,
739   UNW_MIPS_R1  = 1,
740   UNW_MIPS_R2  = 2,
741   UNW_MIPS_R3  = 3,
742   UNW_MIPS_R4  = 4,
743   UNW_MIPS_R5  = 5,
744   UNW_MIPS_R6  = 6,
745   UNW_MIPS_R7  = 7,
746   UNW_MIPS_R8  = 8,
747   UNW_MIPS_R9  = 9,
748   UNW_MIPS_R10 = 10,
749   UNW_MIPS_R11 = 11,
750   UNW_MIPS_R12 = 12,
751   UNW_MIPS_R13 = 13,
752   UNW_MIPS_R14 = 14,
753   UNW_MIPS_R15 = 15,
754   UNW_MIPS_R16 = 16,
755   UNW_MIPS_R17 = 17,
756   UNW_MIPS_R18 = 18,
757   UNW_MIPS_R19 = 19,
758   UNW_MIPS_R20 = 20,
759   UNW_MIPS_R21 = 21,
760   UNW_MIPS_R22 = 22,
761   UNW_MIPS_R23 = 23,
762   UNW_MIPS_R24 = 24,
763   UNW_MIPS_R25 = 25,
764   UNW_MIPS_R26 = 26,
765   UNW_MIPS_R27 = 27,
766   UNW_MIPS_R28 = 28,
767   UNW_MIPS_R29 = 29,
768   UNW_MIPS_R30 = 30,
769   UNW_MIPS_R31 = 31,
770   UNW_MIPS_F0  = 32,
771   UNW_MIPS_F1  = 33,
772   UNW_MIPS_F2  = 34,
773   UNW_MIPS_F3  = 35,
774   UNW_MIPS_F4  = 36,
775   UNW_MIPS_F5  = 37,
776   UNW_MIPS_F6  = 38,
777   UNW_MIPS_F7  = 39,
778   UNW_MIPS_F8  = 40,
779   UNW_MIPS_F9  = 41,
780   UNW_MIPS_F10 = 42,
781   UNW_MIPS_F11 = 43,
782   UNW_MIPS_F12 = 44,
783   UNW_MIPS_F13 = 45,
784   UNW_MIPS_F14 = 46,
785   UNW_MIPS_F15 = 47,
786   UNW_MIPS_F16 = 48,
787   UNW_MIPS_F17 = 49,
788   UNW_MIPS_F18 = 50,
789   UNW_MIPS_F19 = 51,
790   UNW_MIPS_F20 = 52,
791   UNW_MIPS_F21 = 53,
792   UNW_MIPS_F22 = 54,
793   UNW_MIPS_F23 = 55,
794   UNW_MIPS_F24 = 56,
795   UNW_MIPS_F25 = 57,
796   UNW_MIPS_F26 = 58,
797   UNW_MIPS_F27 = 59,
798   UNW_MIPS_F28 = 60,
799   UNW_MIPS_F29 = 61,
800   UNW_MIPS_F30 = 62,
801   UNW_MIPS_F31 = 63,
802   UNW_MIPS_HI = 64,
803   UNW_MIPS_LO = 65,
804 };
805 
806 // SPARC registers
807 enum {
808   UNW_SPARC_G0 = 0,
809   UNW_SPARC_G1 = 1,
810   UNW_SPARC_G2 = 2,
811   UNW_SPARC_G3 = 3,
812   UNW_SPARC_G4 = 4,
813   UNW_SPARC_G5 = 5,
814   UNW_SPARC_G6 = 6,
815   UNW_SPARC_G7 = 7,
816   UNW_SPARC_O0 = 8,
817   UNW_SPARC_O1 = 9,
818   UNW_SPARC_O2 = 10,
819   UNW_SPARC_O3 = 11,
820   UNW_SPARC_O4 = 12,
821   UNW_SPARC_O5 = 13,
822   UNW_SPARC_O6 = 14,
823   UNW_SPARC_O7 = 15,
824   UNW_SPARC_L0 = 16,
825   UNW_SPARC_L1 = 17,
826   UNW_SPARC_L2 = 18,
827   UNW_SPARC_L3 = 19,
828   UNW_SPARC_L4 = 20,
829   UNW_SPARC_L5 = 21,
830   UNW_SPARC_L6 = 22,
831   UNW_SPARC_L7 = 23,
832   UNW_SPARC_I0 = 24,
833   UNW_SPARC_I1 = 25,
834   UNW_SPARC_I2 = 26,
835   UNW_SPARC_I3 = 27,
836   UNW_SPARC_I4 = 28,
837   UNW_SPARC_I5 = 29,
838   UNW_SPARC_I6 = 30,
839   UNW_SPARC_I7 = 31,
840 };
841 
842 // Hexagon register numbers
843 enum {
844   UNW_HEXAGON_R0,
845   UNW_HEXAGON_R1,
846   UNW_HEXAGON_R2,
847   UNW_HEXAGON_R3,
848   UNW_HEXAGON_R4,
849   UNW_HEXAGON_R5,
850   UNW_HEXAGON_R6,
851   UNW_HEXAGON_R7,
852   UNW_HEXAGON_R8,
853   UNW_HEXAGON_R9,
854   UNW_HEXAGON_R10,
855   UNW_HEXAGON_R11,
856   UNW_HEXAGON_R12,
857   UNW_HEXAGON_R13,
858   UNW_HEXAGON_R14,
859   UNW_HEXAGON_R15,
860   UNW_HEXAGON_R16,
861   UNW_HEXAGON_R17,
862   UNW_HEXAGON_R18,
863   UNW_HEXAGON_R19,
864   UNW_HEXAGON_R20,
865   UNW_HEXAGON_R21,
866   UNW_HEXAGON_R22,
867   UNW_HEXAGON_R23,
868   UNW_HEXAGON_R24,
869   UNW_HEXAGON_R25,
870   UNW_HEXAGON_R26,
871   UNW_HEXAGON_R27,
872   UNW_HEXAGON_R28,
873   UNW_HEXAGON_R29,
874   UNW_HEXAGON_R30,
875   UNW_HEXAGON_R31,
876   UNW_HEXAGON_P3_0,
877   UNW_HEXAGON_PC,
878 };
879 
880 // RISC-V registers. These match the DWARF register numbers defined by section
881 // 4 of the RISC-V ELF psABI specification, which can be found at:
882 //
883 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
884 enum {
885   UNW_RISCV_X0  = 0,
886   UNW_RISCV_X1  = 1,
887   UNW_RISCV_X2  = 2,
888   UNW_RISCV_X3  = 3,
889   UNW_RISCV_X4  = 4,
890   UNW_RISCV_X5  = 5,
891   UNW_RISCV_X6  = 6,
892   UNW_RISCV_X7  = 7,
893   UNW_RISCV_X8  = 8,
894   UNW_RISCV_X9  = 9,
895   UNW_RISCV_X10 = 10,
896   UNW_RISCV_X11 = 11,
897   UNW_RISCV_X12 = 12,
898   UNW_RISCV_X13 = 13,
899   UNW_RISCV_X14 = 14,
900   UNW_RISCV_X15 = 15,
901   UNW_RISCV_X16 = 16,
902   UNW_RISCV_X17 = 17,
903   UNW_RISCV_X18 = 18,
904   UNW_RISCV_X19 = 19,
905   UNW_RISCV_X20 = 20,
906   UNW_RISCV_X21 = 21,
907   UNW_RISCV_X22 = 22,
908   UNW_RISCV_X23 = 23,
909   UNW_RISCV_X24 = 24,
910   UNW_RISCV_X25 = 25,
911   UNW_RISCV_X26 = 26,
912   UNW_RISCV_X27 = 27,
913   UNW_RISCV_X28 = 28,
914   UNW_RISCV_X29 = 29,
915   UNW_RISCV_X30 = 30,
916   UNW_RISCV_X31 = 31,
917   UNW_RISCV_F0  = 32,
918   UNW_RISCV_F1  = 33,
919   UNW_RISCV_F2  = 34,
920   UNW_RISCV_F3  = 35,
921   UNW_RISCV_F4  = 36,
922   UNW_RISCV_F5  = 37,
923   UNW_RISCV_F6  = 38,
924   UNW_RISCV_F7  = 39,
925   UNW_RISCV_F8  = 40,
926   UNW_RISCV_F9  = 41,
927   UNW_RISCV_F10 = 42,
928   UNW_RISCV_F11 = 43,
929   UNW_RISCV_F12 = 44,
930   UNW_RISCV_F13 = 45,
931   UNW_RISCV_F14 = 46,
932   UNW_RISCV_F15 = 47,
933   UNW_RISCV_F16 = 48,
934   UNW_RISCV_F17 = 49,
935   UNW_RISCV_F18 = 50,
936   UNW_RISCV_F19 = 51,
937   UNW_RISCV_F20 = 52,
938   UNW_RISCV_F21 = 53,
939   UNW_RISCV_F22 = 54,
940   UNW_RISCV_F23 = 55,
941   UNW_RISCV_F24 = 56,
942   UNW_RISCV_F25 = 57,
943   UNW_RISCV_F26 = 58,
944   UNW_RISCV_F27 = 59,
945   UNW_RISCV_F28 = 60,
946   UNW_RISCV_F29 = 61,
947   UNW_RISCV_F30 = 62,
948   UNW_RISCV_F31 = 63,
949 };
950 
951 // VE register numbers
952 enum {
953   UNW_VE_S0   = 0,
954   UNW_VE_S1   = 1,
955   UNW_VE_S2   = 2,
956   UNW_VE_S3   = 3,
957   UNW_VE_S4   = 4,
958   UNW_VE_S5   = 5,
959   UNW_VE_S6   = 6,
960   UNW_VE_S7   = 7,
961   UNW_VE_S8   = 8,
962   UNW_VE_S9   = 9,
963   UNW_VE_S10  = 10,
964   UNW_VE_S11  = 11,
965   UNW_VE_S12  = 12,
966   UNW_VE_S13  = 13,
967   UNW_VE_S14  = 14,
968   UNW_VE_S15  = 15,
969   UNW_VE_S16  = 16,
970   UNW_VE_S17  = 17,
971   UNW_VE_S18  = 18,
972   UNW_VE_S19  = 19,
973   UNW_VE_S20  = 20,
974   UNW_VE_S21  = 21,
975   UNW_VE_S22  = 22,
976   UNW_VE_S23  = 23,
977   UNW_VE_S24  = 24,
978   UNW_VE_S25  = 25,
979   UNW_VE_S26  = 26,
980   UNW_VE_S27  = 27,
981   UNW_VE_S28  = 28,
982   UNW_VE_S29  = 29,
983   UNW_VE_S30  = 30,
984   UNW_VE_S31  = 31,
985   UNW_VE_S32  = 32,
986   UNW_VE_S33  = 33,
987   UNW_VE_S34  = 34,
988   UNW_VE_S35  = 35,
989   UNW_VE_S36  = 36,
990   UNW_VE_S37  = 37,
991   UNW_VE_S38  = 38,
992   UNW_VE_S39  = 39,
993   UNW_VE_S40  = 40,
994   UNW_VE_S41  = 41,
995   UNW_VE_S42  = 42,
996   UNW_VE_S43  = 43,
997   UNW_VE_S44  = 44,
998   UNW_VE_S45  = 45,
999   UNW_VE_S46  = 46,
1000   UNW_VE_S47  = 47,
1001   UNW_VE_S48  = 48,
1002   UNW_VE_S49  = 49,
1003   UNW_VE_S50  = 50,
1004   UNW_VE_S51  = 51,
1005   UNW_VE_S52  = 52,
1006   UNW_VE_S53  = 53,
1007   UNW_VE_S54  = 54,
1008   UNW_VE_S55  = 55,
1009   UNW_VE_S56  = 56,
1010   UNW_VE_S57  = 57,
1011   UNW_VE_S58  = 58,
1012   UNW_VE_S59  = 59,
1013   UNW_VE_S60  = 60,
1014   UNW_VE_S61  = 61,
1015   UNW_VE_S62  = 62,
1016   UNW_VE_S63  = 63,
1017   UNW_VE_V0   = 64 + 0,
1018   UNW_VE_V1   = 64 + 1,
1019   UNW_VE_V2   = 64 + 2,
1020   UNW_VE_V3   = 64 + 3,
1021   UNW_VE_V4   = 64 + 4,
1022   UNW_VE_V5   = 64 + 5,
1023   UNW_VE_V6   = 64 + 6,
1024   UNW_VE_V7   = 64 + 7,
1025   UNW_VE_V8   = 64 + 8,
1026   UNW_VE_V9   = 64 + 9,
1027   UNW_VE_V10  = 64 + 10,
1028   UNW_VE_V11  = 64 + 11,
1029   UNW_VE_V12  = 64 + 12,
1030   UNW_VE_V13  = 64 + 13,
1031   UNW_VE_V14  = 64 + 14,
1032   UNW_VE_V15  = 64 + 15,
1033   UNW_VE_V16  = 64 + 16,
1034   UNW_VE_V17  = 64 + 17,
1035   UNW_VE_V18  = 64 + 18,
1036   UNW_VE_V19  = 64 + 19,
1037   UNW_VE_V20  = 64 + 20,
1038   UNW_VE_V21  = 64 + 21,
1039   UNW_VE_V22  = 64 + 22,
1040   UNW_VE_V23  = 64 + 23,
1041   UNW_VE_V24  = 64 + 24,
1042   UNW_VE_V25  = 64 + 25,
1043   UNW_VE_V26  = 64 + 26,
1044   UNW_VE_V27  = 64 + 27,
1045   UNW_VE_V28  = 64 + 28,
1046   UNW_VE_V29  = 64 + 29,
1047   UNW_VE_V30  = 64 + 30,
1048   UNW_VE_V31  = 64 + 31,
1049   UNW_VE_V32  = 64 + 32,
1050   UNW_VE_V33  = 64 + 33,
1051   UNW_VE_V34  = 64 + 34,
1052   UNW_VE_V35  = 64 + 35,
1053   UNW_VE_V36  = 64 + 36,
1054   UNW_VE_V37  = 64 + 37,
1055   UNW_VE_V38  = 64 + 38,
1056   UNW_VE_V39  = 64 + 39,
1057   UNW_VE_V40  = 64 + 40,
1058   UNW_VE_V41  = 64 + 41,
1059   UNW_VE_V42  = 64 + 42,
1060   UNW_VE_V43  = 64 + 43,
1061   UNW_VE_V44  = 64 + 44,
1062   UNW_VE_V45  = 64 + 45,
1063   UNW_VE_V46  = 64 + 46,
1064   UNW_VE_V47  = 64 + 47,
1065   UNW_VE_V48  = 64 + 48,
1066   UNW_VE_V49  = 64 + 49,
1067   UNW_VE_V50  = 64 + 50,
1068   UNW_VE_V51  = 64 + 51,
1069   UNW_VE_V52  = 64 + 52,
1070   UNW_VE_V53  = 64 + 53,
1071   UNW_VE_V54  = 64 + 54,
1072   UNW_VE_V55  = 64 + 55,
1073   UNW_VE_V56  = 64 + 56,
1074   UNW_VE_V57  = 64 + 57,
1075   UNW_VE_V58  = 64 + 58,
1076   UNW_VE_V59  = 64 + 59,
1077   UNW_VE_V60  = 64 + 60,
1078   UNW_VE_V61  = 64 + 61,
1079   UNW_VE_V62  = 64 + 62,
1080   UNW_VE_V63  = 64 + 63,
1081   UNW_VE_VM0  = 128 + 0,
1082   UNW_VE_VM1  = 128 + 1,
1083   UNW_VE_VM2  = 128 + 2,
1084   UNW_VE_VM3  = 128 + 3,
1085   UNW_VE_VM4  = 128 + 4,
1086   UNW_VE_VM5  = 128 + 5,
1087   UNW_VE_VM6  = 128 + 6,
1088   UNW_VE_VM7  = 128 + 7,
1089   UNW_VE_VM8  = 128 + 8,
1090   UNW_VE_VM9  = 128 + 9,
1091   UNW_VE_VM10 = 128 + 10,
1092   UNW_VE_VM11 = 128 + 11,
1093   UNW_VE_VM12 = 128 + 12,
1094   UNW_VE_VM13 = 128 + 13,
1095   UNW_VE_VM14 = 128 + 14,
1096   UNW_VE_VM15 = 128 + 15, // = 143
1097 
1098   // Following registers don't have DWARF register numbers.
1099   UNW_VE_VIXR = 144,
1100   UNW_VE_VL   = 145,
1101 };
1102 
1103 #endif
1104