10b57cec5SDimitry Andric //===---------------------------- libunwind.h -----------------------------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric // 80b57cec5SDimitry Andric // Compatible with libunwind API documented at: 90b57cec5SDimitry Andric // http://www.nongnu.org/libunwind/man/libunwind(3).html 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef __LIBUNWIND__ 140b57cec5SDimitry Andric #define __LIBUNWIND__ 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include <__libunwind_config.h> 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include <stdint.h> 190b57cec5SDimitry Andric #include <stddef.h> 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric #ifdef __APPLE__ 220b57cec5SDimitry Andric #if __clang__ 230b57cec5SDimitry Andric #if __has_include(<Availability.h>) 240b57cec5SDimitry Andric #include <Availability.h> 250b57cec5SDimitry Andric #endif 260b57cec5SDimitry Andric #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050 270b57cec5SDimitry Andric #include <Availability.h> 280b57cec5SDimitry Andric #endif 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric #ifdef __arm__ 310b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __attribute__((unavailable)) 320b57cec5SDimitry Andric #elif defined(__OSX_AVAILABLE_STARTING) 330b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0) 340b57cec5SDimitry Andric #else 350b57cec5SDimitry Andric #include <AvailabilityMacros.h> 360b57cec5SDimitry Andric #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 370b57cec5SDimitry Andric #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 380b57cec5SDimitry Andric #else 390b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __attribute__((unavailable)) 400b57cec5SDimitry Andric #endif 410b57cec5SDimitry Andric #endif 420b57cec5SDimitry Andric #else 430b57cec5SDimitry Andric #define LIBUNWIND_AVAIL 440b57cec5SDimitry Andric #endif 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric /* error codes */ 470b57cec5SDimitry Andric enum { 480b57cec5SDimitry Andric UNW_ESUCCESS = 0, /* no error */ 490b57cec5SDimitry Andric UNW_EUNSPEC = -6540, /* unspecified (general) error */ 500b57cec5SDimitry Andric UNW_ENOMEM = -6541, /* out of memory */ 510b57cec5SDimitry Andric UNW_EBADREG = -6542, /* bad register number */ 520b57cec5SDimitry Andric UNW_EREADONLYREG = -6543, /* attempt to write read-only register */ 530b57cec5SDimitry Andric UNW_ESTOPUNWIND = -6544, /* stop unwinding */ 540b57cec5SDimitry Andric UNW_EINVALIDIP = -6545, /* invalid IP */ 550b57cec5SDimitry Andric UNW_EBADFRAME = -6546, /* bad frame */ 560b57cec5SDimitry Andric UNW_EINVAL = -6547, /* unsupported operation or bad value */ 570b57cec5SDimitry Andric UNW_EBADVERSION = -6548, /* unwind info has unsupported version */ 580b57cec5SDimitry Andric UNW_ENOINFO = -6549 /* no unwind info found */ 590b57cec5SDimitry Andric #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY) 600b57cec5SDimitry Andric , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */ 610b57cec5SDimitry Andric #endif 620b57cec5SDimitry Andric }; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric struct unw_context_t { 650b57cec5SDimitry Andric uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; 660b57cec5SDimitry Andric }; 670b57cec5SDimitry Andric typedef struct unw_context_t unw_context_t; 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric struct unw_cursor_t { 700b57cec5SDimitry Andric uint64_t data[_LIBUNWIND_CURSOR_SIZE]; 710b57cec5SDimitry Andric }; 720b57cec5SDimitry Andric typedef struct unw_cursor_t unw_cursor_t; 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric typedef struct unw_addr_space *unw_addr_space_t; 750b57cec5SDimitry Andric 760b57cec5SDimitry Andric typedef int unw_regnum_t; 770b57cec5SDimitry Andric typedef uintptr_t unw_word_t; 780b57cec5SDimitry Andric #if defined(__arm__) && !defined(__ARM_DWARF_EH__) 790b57cec5SDimitry Andric typedef uint64_t unw_fpreg_t; 800b57cec5SDimitry Andric #else 810b57cec5SDimitry Andric typedef double unw_fpreg_t; 820b57cec5SDimitry Andric #endif 830b57cec5SDimitry Andric 840b57cec5SDimitry Andric struct unw_proc_info_t { 850b57cec5SDimitry Andric unw_word_t start_ip; /* start address of function */ 860b57cec5SDimitry Andric unw_word_t end_ip; /* address after end of function */ 870b57cec5SDimitry Andric unw_word_t lsda; /* address of language specific data area, */ 880b57cec5SDimitry Andric /* or zero if not used */ 890b57cec5SDimitry Andric unw_word_t handler; /* personality routine, or zero if not used */ 900b57cec5SDimitry Andric unw_word_t gp; /* not used */ 910b57cec5SDimitry Andric unw_word_t flags; /* not used */ 920b57cec5SDimitry Andric uint32_t format; /* compact unwind encoding, or zero if none */ 930b57cec5SDimitry Andric uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */ 940b57cec5SDimitry Andric unw_word_t unwind_info; /* address of DWARF unwind info, or zero */ 950b57cec5SDimitry Andric unw_word_t extra; /* mach_header of mach-o image containing func */ 960b57cec5SDimitry Andric }; 970b57cec5SDimitry Andric typedef struct unw_proc_info_t unw_proc_info_t; 980b57cec5SDimitry Andric 990b57cec5SDimitry Andric #ifdef __cplusplus 1000b57cec5SDimitry Andric extern "C" { 1010b57cec5SDimitry Andric #endif 1020b57cec5SDimitry Andric 1030b57cec5SDimitry Andric extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL; 1040b57cec5SDimitry Andric extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL; 1050b57cec5SDimitry Andric extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL; 1060b57cec5SDimitry Andric extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL; 1070b57cec5SDimitry Andric extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL; 1080b57cec5SDimitry Andric extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL; 1090b57cec5SDimitry Andric extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL; 1100b57cec5SDimitry Andric extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL; 1110b57cec5SDimitry Andric 1120b57cec5SDimitry Andric #ifdef __arm__ 1130b57cec5SDimitry Andric /* Save VFP registers in FSTMX format (instead of FSTMD). */ 1140b57cec5SDimitry Andric extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL; 1150b57cec5SDimitry Andric #endif 1160b57cec5SDimitry Andric 1170b57cec5SDimitry Andric 1180b57cec5SDimitry Andric extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 1190b57cec5SDimitry Andric extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL; 1200b57cec5SDimitry Andric extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 1210b57cec5SDimitry Andric extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL; 1220b57cec5SDimitry Andric extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL; 1230b57cec5SDimitry Andric //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*); 1240b57cec5SDimitry Andric 1250b57cec5SDimitry Andric extern unw_addr_space_t unw_local_addr_space; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric #ifdef __cplusplus 1280b57cec5SDimitry Andric } 1290b57cec5SDimitry Andric #endif 1300b57cec5SDimitry Andric 1310b57cec5SDimitry Andric // architecture independent register numbers 1320b57cec5SDimitry Andric enum { 1330b57cec5SDimitry Andric UNW_REG_IP = -1, // instruction pointer 1340b57cec5SDimitry Andric UNW_REG_SP = -2, // stack pointer 1350b57cec5SDimitry Andric }; 1360b57cec5SDimitry Andric 1370b57cec5SDimitry Andric // 32-bit x86 registers 1380b57cec5SDimitry Andric enum { 1390b57cec5SDimitry Andric UNW_X86_EAX = 0, 1400b57cec5SDimitry Andric UNW_X86_ECX = 1, 1410b57cec5SDimitry Andric UNW_X86_EDX = 2, 1420b57cec5SDimitry Andric UNW_X86_EBX = 3, 1430b57cec5SDimitry Andric UNW_X86_EBP = 4, 1440b57cec5SDimitry Andric UNW_X86_ESP = 5, 1450b57cec5SDimitry Andric UNW_X86_ESI = 6, 1460b57cec5SDimitry Andric UNW_X86_EDI = 7 1470b57cec5SDimitry Andric }; 1480b57cec5SDimitry Andric 1490b57cec5SDimitry Andric // 64-bit x86_64 registers 1500b57cec5SDimitry Andric enum { 1510b57cec5SDimitry Andric UNW_X86_64_RAX = 0, 1520b57cec5SDimitry Andric UNW_X86_64_RDX = 1, 1530b57cec5SDimitry Andric UNW_X86_64_RCX = 2, 1540b57cec5SDimitry Andric UNW_X86_64_RBX = 3, 1550b57cec5SDimitry Andric UNW_X86_64_RSI = 4, 1560b57cec5SDimitry Andric UNW_X86_64_RDI = 5, 1570b57cec5SDimitry Andric UNW_X86_64_RBP = 6, 1580b57cec5SDimitry Andric UNW_X86_64_RSP = 7, 1590b57cec5SDimitry Andric UNW_X86_64_R8 = 8, 1600b57cec5SDimitry Andric UNW_X86_64_R9 = 9, 1610b57cec5SDimitry Andric UNW_X86_64_R10 = 10, 1620b57cec5SDimitry Andric UNW_X86_64_R11 = 11, 1630b57cec5SDimitry Andric UNW_X86_64_R12 = 12, 1640b57cec5SDimitry Andric UNW_X86_64_R13 = 13, 1650b57cec5SDimitry Andric UNW_X86_64_R14 = 14, 1660b57cec5SDimitry Andric UNW_X86_64_R15 = 15, 1670b57cec5SDimitry Andric UNW_X86_64_RIP = 16, 1680b57cec5SDimitry Andric UNW_X86_64_XMM0 = 17, 1690b57cec5SDimitry Andric UNW_X86_64_XMM1 = 18, 1700b57cec5SDimitry Andric UNW_X86_64_XMM2 = 19, 1710b57cec5SDimitry Andric UNW_X86_64_XMM3 = 20, 1720b57cec5SDimitry Andric UNW_X86_64_XMM4 = 21, 1730b57cec5SDimitry Andric UNW_X86_64_XMM5 = 22, 1740b57cec5SDimitry Andric UNW_X86_64_XMM6 = 23, 1750b57cec5SDimitry Andric UNW_X86_64_XMM7 = 24, 1760b57cec5SDimitry Andric UNW_X86_64_XMM8 = 25, 1770b57cec5SDimitry Andric UNW_X86_64_XMM9 = 26, 1780b57cec5SDimitry Andric UNW_X86_64_XMM10 = 27, 1790b57cec5SDimitry Andric UNW_X86_64_XMM11 = 28, 1800b57cec5SDimitry Andric UNW_X86_64_XMM12 = 29, 1810b57cec5SDimitry Andric UNW_X86_64_XMM13 = 30, 1820b57cec5SDimitry Andric UNW_X86_64_XMM14 = 31, 1830b57cec5SDimitry Andric UNW_X86_64_XMM15 = 32, 1840b57cec5SDimitry Andric }; 1850b57cec5SDimitry Andric 1860b57cec5SDimitry Andric 1870b57cec5SDimitry Andric // 32-bit ppc register numbers 1880b57cec5SDimitry Andric enum { 1890b57cec5SDimitry Andric UNW_PPC_R0 = 0, 1900b57cec5SDimitry Andric UNW_PPC_R1 = 1, 1910b57cec5SDimitry Andric UNW_PPC_R2 = 2, 1920b57cec5SDimitry Andric UNW_PPC_R3 = 3, 1930b57cec5SDimitry Andric UNW_PPC_R4 = 4, 1940b57cec5SDimitry Andric UNW_PPC_R5 = 5, 1950b57cec5SDimitry Andric UNW_PPC_R6 = 6, 1960b57cec5SDimitry Andric UNW_PPC_R7 = 7, 1970b57cec5SDimitry Andric UNW_PPC_R8 = 8, 1980b57cec5SDimitry Andric UNW_PPC_R9 = 9, 1990b57cec5SDimitry Andric UNW_PPC_R10 = 10, 2000b57cec5SDimitry Andric UNW_PPC_R11 = 11, 2010b57cec5SDimitry Andric UNW_PPC_R12 = 12, 2020b57cec5SDimitry Andric UNW_PPC_R13 = 13, 2030b57cec5SDimitry Andric UNW_PPC_R14 = 14, 2040b57cec5SDimitry Andric UNW_PPC_R15 = 15, 2050b57cec5SDimitry Andric UNW_PPC_R16 = 16, 2060b57cec5SDimitry Andric UNW_PPC_R17 = 17, 2070b57cec5SDimitry Andric UNW_PPC_R18 = 18, 2080b57cec5SDimitry Andric UNW_PPC_R19 = 19, 2090b57cec5SDimitry Andric UNW_PPC_R20 = 20, 2100b57cec5SDimitry Andric UNW_PPC_R21 = 21, 2110b57cec5SDimitry Andric UNW_PPC_R22 = 22, 2120b57cec5SDimitry Andric UNW_PPC_R23 = 23, 2130b57cec5SDimitry Andric UNW_PPC_R24 = 24, 2140b57cec5SDimitry Andric UNW_PPC_R25 = 25, 2150b57cec5SDimitry Andric UNW_PPC_R26 = 26, 2160b57cec5SDimitry Andric UNW_PPC_R27 = 27, 2170b57cec5SDimitry Andric UNW_PPC_R28 = 28, 2180b57cec5SDimitry Andric UNW_PPC_R29 = 29, 2190b57cec5SDimitry Andric UNW_PPC_R30 = 30, 2200b57cec5SDimitry Andric UNW_PPC_R31 = 31, 2210b57cec5SDimitry Andric UNW_PPC_F0 = 32, 2220b57cec5SDimitry Andric UNW_PPC_F1 = 33, 2230b57cec5SDimitry Andric UNW_PPC_F2 = 34, 2240b57cec5SDimitry Andric UNW_PPC_F3 = 35, 2250b57cec5SDimitry Andric UNW_PPC_F4 = 36, 2260b57cec5SDimitry Andric UNW_PPC_F5 = 37, 2270b57cec5SDimitry Andric UNW_PPC_F6 = 38, 2280b57cec5SDimitry Andric UNW_PPC_F7 = 39, 2290b57cec5SDimitry Andric UNW_PPC_F8 = 40, 2300b57cec5SDimitry Andric UNW_PPC_F9 = 41, 2310b57cec5SDimitry Andric UNW_PPC_F10 = 42, 2320b57cec5SDimitry Andric UNW_PPC_F11 = 43, 2330b57cec5SDimitry Andric UNW_PPC_F12 = 44, 2340b57cec5SDimitry Andric UNW_PPC_F13 = 45, 2350b57cec5SDimitry Andric UNW_PPC_F14 = 46, 2360b57cec5SDimitry Andric UNW_PPC_F15 = 47, 2370b57cec5SDimitry Andric UNW_PPC_F16 = 48, 2380b57cec5SDimitry Andric UNW_PPC_F17 = 49, 2390b57cec5SDimitry Andric UNW_PPC_F18 = 50, 2400b57cec5SDimitry Andric UNW_PPC_F19 = 51, 2410b57cec5SDimitry Andric UNW_PPC_F20 = 52, 2420b57cec5SDimitry Andric UNW_PPC_F21 = 53, 2430b57cec5SDimitry Andric UNW_PPC_F22 = 54, 2440b57cec5SDimitry Andric UNW_PPC_F23 = 55, 2450b57cec5SDimitry Andric UNW_PPC_F24 = 56, 2460b57cec5SDimitry Andric UNW_PPC_F25 = 57, 2470b57cec5SDimitry Andric UNW_PPC_F26 = 58, 2480b57cec5SDimitry Andric UNW_PPC_F27 = 59, 2490b57cec5SDimitry Andric UNW_PPC_F28 = 60, 2500b57cec5SDimitry Andric UNW_PPC_F29 = 61, 2510b57cec5SDimitry Andric UNW_PPC_F30 = 62, 2520b57cec5SDimitry Andric UNW_PPC_F31 = 63, 2530b57cec5SDimitry Andric UNW_PPC_MQ = 64, 2540b57cec5SDimitry Andric UNW_PPC_LR = 65, 2550b57cec5SDimitry Andric UNW_PPC_CTR = 66, 2560b57cec5SDimitry Andric UNW_PPC_AP = 67, 2570b57cec5SDimitry Andric UNW_PPC_CR0 = 68, 2580b57cec5SDimitry Andric UNW_PPC_CR1 = 69, 2590b57cec5SDimitry Andric UNW_PPC_CR2 = 70, 2600b57cec5SDimitry Andric UNW_PPC_CR3 = 71, 2610b57cec5SDimitry Andric UNW_PPC_CR4 = 72, 2620b57cec5SDimitry Andric UNW_PPC_CR5 = 73, 2630b57cec5SDimitry Andric UNW_PPC_CR6 = 74, 2640b57cec5SDimitry Andric UNW_PPC_CR7 = 75, 2650b57cec5SDimitry Andric UNW_PPC_XER = 76, 2660b57cec5SDimitry Andric UNW_PPC_V0 = 77, 2670b57cec5SDimitry Andric UNW_PPC_V1 = 78, 2680b57cec5SDimitry Andric UNW_PPC_V2 = 79, 2690b57cec5SDimitry Andric UNW_PPC_V3 = 80, 2700b57cec5SDimitry Andric UNW_PPC_V4 = 81, 2710b57cec5SDimitry Andric UNW_PPC_V5 = 82, 2720b57cec5SDimitry Andric UNW_PPC_V6 = 83, 2730b57cec5SDimitry Andric UNW_PPC_V7 = 84, 2740b57cec5SDimitry Andric UNW_PPC_V8 = 85, 2750b57cec5SDimitry Andric UNW_PPC_V9 = 86, 2760b57cec5SDimitry Andric UNW_PPC_V10 = 87, 2770b57cec5SDimitry Andric UNW_PPC_V11 = 88, 2780b57cec5SDimitry Andric UNW_PPC_V12 = 89, 2790b57cec5SDimitry Andric UNW_PPC_V13 = 90, 2800b57cec5SDimitry Andric UNW_PPC_V14 = 91, 2810b57cec5SDimitry Andric UNW_PPC_V15 = 92, 2820b57cec5SDimitry Andric UNW_PPC_V16 = 93, 2830b57cec5SDimitry Andric UNW_PPC_V17 = 94, 2840b57cec5SDimitry Andric UNW_PPC_V18 = 95, 2850b57cec5SDimitry Andric UNW_PPC_V19 = 96, 2860b57cec5SDimitry Andric UNW_PPC_V20 = 97, 2870b57cec5SDimitry Andric UNW_PPC_V21 = 98, 2880b57cec5SDimitry Andric UNW_PPC_V22 = 99, 2890b57cec5SDimitry Andric UNW_PPC_V23 = 100, 2900b57cec5SDimitry Andric UNW_PPC_V24 = 101, 2910b57cec5SDimitry Andric UNW_PPC_V25 = 102, 2920b57cec5SDimitry Andric UNW_PPC_V26 = 103, 2930b57cec5SDimitry Andric UNW_PPC_V27 = 104, 2940b57cec5SDimitry Andric UNW_PPC_V28 = 105, 2950b57cec5SDimitry Andric UNW_PPC_V29 = 106, 2960b57cec5SDimitry Andric UNW_PPC_V30 = 107, 2970b57cec5SDimitry Andric UNW_PPC_V31 = 108, 2980b57cec5SDimitry Andric UNW_PPC_VRSAVE = 109, 2990b57cec5SDimitry Andric UNW_PPC_VSCR = 110, 3000b57cec5SDimitry Andric UNW_PPC_SPE_ACC = 111, 3010b57cec5SDimitry Andric UNW_PPC_SPEFSCR = 112 3020b57cec5SDimitry Andric }; 3030b57cec5SDimitry Andric 3040b57cec5SDimitry Andric // 64-bit ppc register numbers 3050b57cec5SDimitry Andric enum { 3060b57cec5SDimitry Andric UNW_PPC64_R0 = 0, 3070b57cec5SDimitry Andric UNW_PPC64_R1 = 1, 3080b57cec5SDimitry Andric UNW_PPC64_R2 = 2, 3090b57cec5SDimitry Andric UNW_PPC64_R3 = 3, 3100b57cec5SDimitry Andric UNW_PPC64_R4 = 4, 3110b57cec5SDimitry Andric UNW_PPC64_R5 = 5, 3120b57cec5SDimitry Andric UNW_PPC64_R6 = 6, 3130b57cec5SDimitry Andric UNW_PPC64_R7 = 7, 3140b57cec5SDimitry Andric UNW_PPC64_R8 = 8, 3150b57cec5SDimitry Andric UNW_PPC64_R9 = 9, 3160b57cec5SDimitry Andric UNW_PPC64_R10 = 10, 3170b57cec5SDimitry Andric UNW_PPC64_R11 = 11, 3180b57cec5SDimitry Andric UNW_PPC64_R12 = 12, 3190b57cec5SDimitry Andric UNW_PPC64_R13 = 13, 3200b57cec5SDimitry Andric UNW_PPC64_R14 = 14, 3210b57cec5SDimitry Andric UNW_PPC64_R15 = 15, 3220b57cec5SDimitry Andric UNW_PPC64_R16 = 16, 3230b57cec5SDimitry Andric UNW_PPC64_R17 = 17, 3240b57cec5SDimitry Andric UNW_PPC64_R18 = 18, 3250b57cec5SDimitry Andric UNW_PPC64_R19 = 19, 3260b57cec5SDimitry Andric UNW_PPC64_R20 = 20, 3270b57cec5SDimitry Andric UNW_PPC64_R21 = 21, 3280b57cec5SDimitry Andric UNW_PPC64_R22 = 22, 3290b57cec5SDimitry Andric UNW_PPC64_R23 = 23, 3300b57cec5SDimitry Andric UNW_PPC64_R24 = 24, 3310b57cec5SDimitry Andric UNW_PPC64_R25 = 25, 3320b57cec5SDimitry Andric UNW_PPC64_R26 = 26, 3330b57cec5SDimitry Andric UNW_PPC64_R27 = 27, 3340b57cec5SDimitry Andric UNW_PPC64_R28 = 28, 3350b57cec5SDimitry Andric UNW_PPC64_R29 = 29, 3360b57cec5SDimitry Andric UNW_PPC64_R30 = 30, 3370b57cec5SDimitry Andric UNW_PPC64_R31 = 31, 3380b57cec5SDimitry Andric UNW_PPC64_F0 = 32, 3390b57cec5SDimitry Andric UNW_PPC64_F1 = 33, 3400b57cec5SDimitry Andric UNW_PPC64_F2 = 34, 3410b57cec5SDimitry Andric UNW_PPC64_F3 = 35, 3420b57cec5SDimitry Andric UNW_PPC64_F4 = 36, 3430b57cec5SDimitry Andric UNW_PPC64_F5 = 37, 3440b57cec5SDimitry Andric UNW_PPC64_F6 = 38, 3450b57cec5SDimitry Andric UNW_PPC64_F7 = 39, 3460b57cec5SDimitry Andric UNW_PPC64_F8 = 40, 3470b57cec5SDimitry Andric UNW_PPC64_F9 = 41, 3480b57cec5SDimitry Andric UNW_PPC64_F10 = 42, 3490b57cec5SDimitry Andric UNW_PPC64_F11 = 43, 3500b57cec5SDimitry Andric UNW_PPC64_F12 = 44, 3510b57cec5SDimitry Andric UNW_PPC64_F13 = 45, 3520b57cec5SDimitry Andric UNW_PPC64_F14 = 46, 3530b57cec5SDimitry Andric UNW_PPC64_F15 = 47, 3540b57cec5SDimitry Andric UNW_PPC64_F16 = 48, 3550b57cec5SDimitry Andric UNW_PPC64_F17 = 49, 3560b57cec5SDimitry Andric UNW_PPC64_F18 = 50, 3570b57cec5SDimitry Andric UNW_PPC64_F19 = 51, 3580b57cec5SDimitry Andric UNW_PPC64_F20 = 52, 3590b57cec5SDimitry Andric UNW_PPC64_F21 = 53, 3600b57cec5SDimitry Andric UNW_PPC64_F22 = 54, 3610b57cec5SDimitry Andric UNW_PPC64_F23 = 55, 3620b57cec5SDimitry Andric UNW_PPC64_F24 = 56, 3630b57cec5SDimitry Andric UNW_PPC64_F25 = 57, 3640b57cec5SDimitry Andric UNW_PPC64_F26 = 58, 3650b57cec5SDimitry Andric UNW_PPC64_F27 = 59, 3660b57cec5SDimitry Andric UNW_PPC64_F28 = 60, 3670b57cec5SDimitry Andric UNW_PPC64_F29 = 61, 3680b57cec5SDimitry Andric UNW_PPC64_F30 = 62, 3690b57cec5SDimitry Andric UNW_PPC64_F31 = 63, 3700b57cec5SDimitry Andric // 64: reserved 3710b57cec5SDimitry Andric UNW_PPC64_LR = 65, 3720b57cec5SDimitry Andric UNW_PPC64_CTR = 66, 3730b57cec5SDimitry Andric // 67: reserved 3740b57cec5SDimitry Andric UNW_PPC64_CR0 = 68, 3750b57cec5SDimitry Andric UNW_PPC64_CR1 = 69, 3760b57cec5SDimitry Andric UNW_PPC64_CR2 = 70, 3770b57cec5SDimitry Andric UNW_PPC64_CR3 = 71, 3780b57cec5SDimitry Andric UNW_PPC64_CR4 = 72, 3790b57cec5SDimitry Andric UNW_PPC64_CR5 = 73, 3800b57cec5SDimitry Andric UNW_PPC64_CR6 = 74, 3810b57cec5SDimitry Andric UNW_PPC64_CR7 = 75, 3820b57cec5SDimitry Andric UNW_PPC64_XER = 76, 3830b57cec5SDimitry Andric UNW_PPC64_V0 = 77, 3840b57cec5SDimitry Andric UNW_PPC64_V1 = 78, 3850b57cec5SDimitry Andric UNW_PPC64_V2 = 79, 3860b57cec5SDimitry Andric UNW_PPC64_V3 = 80, 3870b57cec5SDimitry Andric UNW_PPC64_V4 = 81, 3880b57cec5SDimitry Andric UNW_PPC64_V5 = 82, 3890b57cec5SDimitry Andric UNW_PPC64_V6 = 83, 3900b57cec5SDimitry Andric UNW_PPC64_V7 = 84, 3910b57cec5SDimitry Andric UNW_PPC64_V8 = 85, 3920b57cec5SDimitry Andric UNW_PPC64_V9 = 86, 3930b57cec5SDimitry Andric UNW_PPC64_V10 = 87, 3940b57cec5SDimitry Andric UNW_PPC64_V11 = 88, 3950b57cec5SDimitry Andric UNW_PPC64_V12 = 89, 3960b57cec5SDimitry Andric UNW_PPC64_V13 = 90, 3970b57cec5SDimitry Andric UNW_PPC64_V14 = 91, 3980b57cec5SDimitry Andric UNW_PPC64_V15 = 92, 3990b57cec5SDimitry Andric UNW_PPC64_V16 = 93, 4000b57cec5SDimitry Andric UNW_PPC64_V17 = 94, 4010b57cec5SDimitry Andric UNW_PPC64_V18 = 95, 4020b57cec5SDimitry Andric UNW_PPC64_V19 = 96, 4030b57cec5SDimitry Andric UNW_PPC64_V20 = 97, 4040b57cec5SDimitry Andric UNW_PPC64_V21 = 98, 4050b57cec5SDimitry Andric UNW_PPC64_V22 = 99, 4060b57cec5SDimitry Andric UNW_PPC64_V23 = 100, 4070b57cec5SDimitry Andric UNW_PPC64_V24 = 101, 4080b57cec5SDimitry Andric UNW_PPC64_V25 = 102, 4090b57cec5SDimitry Andric UNW_PPC64_V26 = 103, 4100b57cec5SDimitry Andric UNW_PPC64_V27 = 104, 4110b57cec5SDimitry Andric UNW_PPC64_V28 = 105, 4120b57cec5SDimitry Andric UNW_PPC64_V29 = 106, 4130b57cec5SDimitry Andric UNW_PPC64_V30 = 107, 4140b57cec5SDimitry Andric UNW_PPC64_V31 = 108, 4150b57cec5SDimitry Andric // 109, 111-113: OpenPOWER ELF V2 ABI: reserved 4160b57cec5SDimitry Andric // Borrowing VRSAVE number from PPC32. 4170b57cec5SDimitry Andric UNW_PPC64_VRSAVE = 109, 4180b57cec5SDimitry Andric UNW_PPC64_VSCR = 110, 4190b57cec5SDimitry Andric UNW_PPC64_TFHAR = 114, 4200b57cec5SDimitry Andric UNW_PPC64_TFIAR = 115, 4210b57cec5SDimitry Andric UNW_PPC64_TEXASR = 116, 4220b57cec5SDimitry Andric UNW_PPC64_VS0 = UNW_PPC64_F0, 4230b57cec5SDimitry Andric UNW_PPC64_VS1 = UNW_PPC64_F1, 4240b57cec5SDimitry Andric UNW_PPC64_VS2 = UNW_PPC64_F2, 4250b57cec5SDimitry Andric UNW_PPC64_VS3 = UNW_PPC64_F3, 4260b57cec5SDimitry Andric UNW_PPC64_VS4 = UNW_PPC64_F4, 4270b57cec5SDimitry Andric UNW_PPC64_VS5 = UNW_PPC64_F5, 4280b57cec5SDimitry Andric UNW_PPC64_VS6 = UNW_PPC64_F6, 4290b57cec5SDimitry Andric UNW_PPC64_VS7 = UNW_PPC64_F7, 4300b57cec5SDimitry Andric UNW_PPC64_VS8 = UNW_PPC64_F8, 4310b57cec5SDimitry Andric UNW_PPC64_VS9 = UNW_PPC64_F9, 4320b57cec5SDimitry Andric UNW_PPC64_VS10 = UNW_PPC64_F10, 4330b57cec5SDimitry Andric UNW_PPC64_VS11 = UNW_PPC64_F11, 4340b57cec5SDimitry Andric UNW_PPC64_VS12 = UNW_PPC64_F12, 4350b57cec5SDimitry Andric UNW_PPC64_VS13 = UNW_PPC64_F13, 4360b57cec5SDimitry Andric UNW_PPC64_VS14 = UNW_PPC64_F14, 4370b57cec5SDimitry Andric UNW_PPC64_VS15 = UNW_PPC64_F15, 4380b57cec5SDimitry Andric UNW_PPC64_VS16 = UNW_PPC64_F16, 4390b57cec5SDimitry Andric UNW_PPC64_VS17 = UNW_PPC64_F17, 4400b57cec5SDimitry Andric UNW_PPC64_VS18 = UNW_PPC64_F18, 4410b57cec5SDimitry Andric UNW_PPC64_VS19 = UNW_PPC64_F19, 4420b57cec5SDimitry Andric UNW_PPC64_VS20 = UNW_PPC64_F20, 4430b57cec5SDimitry Andric UNW_PPC64_VS21 = UNW_PPC64_F21, 4440b57cec5SDimitry Andric UNW_PPC64_VS22 = UNW_PPC64_F22, 4450b57cec5SDimitry Andric UNW_PPC64_VS23 = UNW_PPC64_F23, 4460b57cec5SDimitry Andric UNW_PPC64_VS24 = UNW_PPC64_F24, 4470b57cec5SDimitry Andric UNW_PPC64_VS25 = UNW_PPC64_F25, 4480b57cec5SDimitry Andric UNW_PPC64_VS26 = UNW_PPC64_F26, 4490b57cec5SDimitry Andric UNW_PPC64_VS27 = UNW_PPC64_F27, 4500b57cec5SDimitry Andric UNW_PPC64_VS28 = UNW_PPC64_F28, 4510b57cec5SDimitry Andric UNW_PPC64_VS29 = UNW_PPC64_F29, 4520b57cec5SDimitry Andric UNW_PPC64_VS30 = UNW_PPC64_F30, 4530b57cec5SDimitry Andric UNW_PPC64_VS31 = UNW_PPC64_F31, 4540b57cec5SDimitry Andric UNW_PPC64_VS32 = UNW_PPC64_V0, 4550b57cec5SDimitry Andric UNW_PPC64_VS33 = UNW_PPC64_V1, 4560b57cec5SDimitry Andric UNW_PPC64_VS34 = UNW_PPC64_V2, 4570b57cec5SDimitry Andric UNW_PPC64_VS35 = UNW_PPC64_V3, 4580b57cec5SDimitry Andric UNW_PPC64_VS36 = UNW_PPC64_V4, 4590b57cec5SDimitry Andric UNW_PPC64_VS37 = UNW_PPC64_V5, 4600b57cec5SDimitry Andric UNW_PPC64_VS38 = UNW_PPC64_V6, 4610b57cec5SDimitry Andric UNW_PPC64_VS39 = UNW_PPC64_V7, 4620b57cec5SDimitry Andric UNW_PPC64_VS40 = UNW_PPC64_V8, 4630b57cec5SDimitry Andric UNW_PPC64_VS41 = UNW_PPC64_V9, 4640b57cec5SDimitry Andric UNW_PPC64_VS42 = UNW_PPC64_V10, 4650b57cec5SDimitry Andric UNW_PPC64_VS43 = UNW_PPC64_V11, 4660b57cec5SDimitry Andric UNW_PPC64_VS44 = UNW_PPC64_V12, 4670b57cec5SDimitry Andric UNW_PPC64_VS45 = UNW_PPC64_V13, 4680b57cec5SDimitry Andric UNW_PPC64_VS46 = UNW_PPC64_V14, 4690b57cec5SDimitry Andric UNW_PPC64_VS47 = UNW_PPC64_V15, 4700b57cec5SDimitry Andric UNW_PPC64_VS48 = UNW_PPC64_V16, 4710b57cec5SDimitry Andric UNW_PPC64_VS49 = UNW_PPC64_V17, 4720b57cec5SDimitry Andric UNW_PPC64_VS50 = UNW_PPC64_V18, 4730b57cec5SDimitry Andric UNW_PPC64_VS51 = UNW_PPC64_V19, 4740b57cec5SDimitry Andric UNW_PPC64_VS52 = UNW_PPC64_V20, 4750b57cec5SDimitry Andric UNW_PPC64_VS53 = UNW_PPC64_V21, 4760b57cec5SDimitry Andric UNW_PPC64_VS54 = UNW_PPC64_V22, 4770b57cec5SDimitry Andric UNW_PPC64_VS55 = UNW_PPC64_V23, 4780b57cec5SDimitry Andric UNW_PPC64_VS56 = UNW_PPC64_V24, 4790b57cec5SDimitry Andric UNW_PPC64_VS57 = UNW_PPC64_V25, 4800b57cec5SDimitry Andric UNW_PPC64_VS58 = UNW_PPC64_V26, 4810b57cec5SDimitry Andric UNW_PPC64_VS59 = UNW_PPC64_V27, 4820b57cec5SDimitry Andric UNW_PPC64_VS60 = UNW_PPC64_V28, 4830b57cec5SDimitry Andric UNW_PPC64_VS61 = UNW_PPC64_V29, 4840b57cec5SDimitry Andric UNW_PPC64_VS62 = UNW_PPC64_V30, 4850b57cec5SDimitry Andric UNW_PPC64_VS63 = UNW_PPC64_V31 4860b57cec5SDimitry Andric }; 4870b57cec5SDimitry Andric 4880b57cec5SDimitry Andric // 64-bit ARM64 registers 4890b57cec5SDimitry Andric enum { 4900b57cec5SDimitry Andric UNW_ARM64_X0 = 0, 4910b57cec5SDimitry Andric UNW_ARM64_X1 = 1, 4920b57cec5SDimitry Andric UNW_ARM64_X2 = 2, 4930b57cec5SDimitry Andric UNW_ARM64_X3 = 3, 4940b57cec5SDimitry Andric UNW_ARM64_X4 = 4, 4950b57cec5SDimitry Andric UNW_ARM64_X5 = 5, 4960b57cec5SDimitry Andric UNW_ARM64_X6 = 6, 4970b57cec5SDimitry Andric UNW_ARM64_X7 = 7, 4980b57cec5SDimitry Andric UNW_ARM64_X8 = 8, 4990b57cec5SDimitry Andric UNW_ARM64_X9 = 9, 5000b57cec5SDimitry Andric UNW_ARM64_X10 = 10, 5010b57cec5SDimitry Andric UNW_ARM64_X11 = 11, 5020b57cec5SDimitry Andric UNW_ARM64_X12 = 12, 5030b57cec5SDimitry Andric UNW_ARM64_X13 = 13, 5040b57cec5SDimitry Andric UNW_ARM64_X14 = 14, 5050b57cec5SDimitry Andric UNW_ARM64_X15 = 15, 5060b57cec5SDimitry Andric UNW_ARM64_X16 = 16, 5070b57cec5SDimitry Andric UNW_ARM64_X17 = 17, 5080b57cec5SDimitry Andric UNW_ARM64_X18 = 18, 5090b57cec5SDimitry Andric UNW_ARM64_X19 = 19, 5100b57cec5SDimitry Andric UNW_ARM64_X20 = 20, 5110b57cec5SDimitry Andric UNW_ARM64_X21 = 21, 5120b57cec5SDimitry Andric UNW_ARM64_X22 = 22, 5130b57cec5SDimitry Andric UNW_ARM64_X23 = 23, 5140b57cec5SDimitry Andric UNW_ARM64_X24 = 24, 5150b57cec5SDimitry Andric UNW_ARM64_X25 = 25, 5160b57cec5SDimitry Andric UNW_ARM64_X26 = 26, 5170b57cec5SDimitry Andric UNW_ARM64_X27 = 27, 5180b57cec5SDimitry Andric UNW_ARM64_X28 = 28, 5190b57cec5SDimitry Andric UNW_ARM64_X29 = 29, 5200b57cec5SDimitry Andric UNW_ARM64_FP = 29, 5210b57cec5SDimitry Andric UNW_ARM64_X30 = 30, 5220b57cec5SDimitry Andric UNW_ARM64_LR = 30, 5230b57cec5SDimitry Andric UNW_ARM64_X31 = 31, 5240b57cec5SDimitry Andric UNW_ARM64_SP = 31, 5250b57cec5SDimitry Andric // reserved block 5260b57cec5SDimitry Andric UNW_ARM64_RA_SIGN_STATE = 34, 5270b57cec5SDimitry Andric // reserved block 5280b57cec5SDimitry Andric UNW_ARM64_D0 = 64, 5290b57cec5SDimitry Andric UNW_ARM64_D1 = 65, 5300b57cec5SDimitry Andric UNW_ARM64_D2 = 66, 5310b57cec5SDimitry Andric UNW_ARM64_D3 = 67, 5320b57cec5SDimitry Andric UNW_ARM64_D4 = 68, 5330b57cec5SDimitry Andric UNW_ARM64_D5 = 69, 5340b57cec5SDimitry Andric UNW_ARM64_D6 = 70, 5350b57cec5SDimitry Andric UNW_ARM64_D7 = 71, 5360b57cec5SDimitry Andric UNW_ARM64_D8 = 72, 5370b57cec5SDimitry Andric UNW_ARM64_D9 = 73, 5380b57cec5SDimitry Andric UNW_ARM64_D10 = 74, 5390b57cec5SDimitry Andric UNW_ARM64_D11 = 75, 5400b57cec5SDimitry Andric UNW_ARM64_D12 = 76, 5410b57cec5SDimitry Andric UNW_ARM64_D13 = 77, 5420b57cec5SDimitry Andric UNW_ARM64_D14 = 78, 5430b57cec5SDimitry Andric UNW_ARM64_D15 = 79, 5440b57cec5SDimitry Andric UNW_ARM64_D16 = 80, 5450b57cec5SDimitry Andric UNW_ARM64_D17 = 81, 5460b57cec5SDimitry Andric UNW_ARM64_D18 = 82, 5470b57cec5SDimitry Andric UNW_ARM64_D19 = 83, 5480b57cec5SDimitry Andric UNW_ARM64_D20 = 84, 5490b57cec5SDimitry Andric UNW_ARM64_D21 = 85, 5500b57cec5SDimitry Andric UNW_ARM64_D22 = 86, 5510b57cec5SDimitry Andric UNW_ARM64_D23 = 87, 5520b57cec5SDimitry Andric UNW_ARM64_D24 = 88, 5530b57cec5SDimitry Andric UNW_ARM64_D25 = 89, 5540b57cec5SDimitry Andric UNW_ARM64_D26 = 90, 5550b57cec5SDimitry Andric UNW_ARM64_D27 = 91, 5560b57cec5SDimitry Andric UNW_ARM64_D28 = 92, 5570b57cec5SDimitry Andric UNW_ARM64_D29 = 93, 5580b57cec5SDimitry Andric UNW_ARM64_D30 = 94, 5590b57cec5SDimitry Andric UNW_ARM64_D31 = 95, 5600b57cec5SDimitry Andric }; 5610b57cec5SDimitry Andric 5620b57cec5SDimitry Andric // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1. 5630b57cec5SDimitry Andric // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3. 5640b57cec5SDimitry Andric // In this scheme, even though the 64-bit floating point registers D0-D31 5650b57cec5SDimitry Andric // overlap physically with the 32-bit floating pointer registers S0-S31, 5660b57cec5SDimitry Andric // they are given a non-overlapping range of register numbers. 5670b57cec5SDimitry Andric // 5680b57cec5SDimitry Andric // Commented out ranges are not preserved during unwinding. 5690b57cec5SDimitry Andric enum { 5700b57cec5SDimitry Andric UNW_ARM_R0 = 0, 5710b57cec5SDimitry Andric UNW_ARM_R1 = 1, 5720b57cec5SDimitry Andric UNW_ARM_R2 = 2, 5730b57cec5SDimitry Andric UNW_ARM_R3 = 3, 5740b57cec5SDimitry Andric UNW_ARM_R4 = 4, 5750b57cec5SDimitry Andric UNW_ARM_R5 = 5, 5760b57cec5SDimitry Andric UNW_ARM_R6 = 6, 5770b57cec5SDimitry Andric UNW_ARM_R7 = 7, 5780b57cec5SDimitry Andric UNW_ARM_R8 = 8, 5790b57cec5SDimitry Andric UNW_ARM_R9 = 9, 5800b57cec5SDimitry Andric UNW_ARM_R10 = 10, 5810b57cec5SDimitry Andric UNW_ARM_R11 = 11, 5820b57cec5SDimitry Andric UNW_ARM_R12 = 12, 5830b57cec5SDimitry Andric UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP 5840b57cec5SDimitry Andric UNW_ARM_R13 = 13, 5850b57cec5SDimitry Andric UNW_ARM_LR = 14, 5860b57cec5SDimitry Andric UNW_ARM_R14 = 14, 5870b57cec5SDimitry Andric UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP 5880b57cec5SDimitry Andric UNW_ARM_R15 = 15, 5890b57cec5SDimitry Andric // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31. 5900b57cec5SDimitry Andric UNW_ARM_S0 = 64, 5910b57cec5SDimitry Andric UNW_ARM_S1 = 65, 5920b57cec5SDimitry Andric UNW_ARM_S2 = 66, 5930b57cec5SDimitry Andric UNW_ARM_S3 = 67, 5940b57cec5SDimitry Andric UNW_ARM_S4 = 68, 5950b57cec5SDimitry Andric UNW_ARM_S5 = 69, 5960b57cec5SDimitry Andric UNW_ARM_S6 = 70, 5970b57cec5SDimitry Andric UNW_ARM_S7 = 71, 5980b57cec5SDimitry Andric UNW_ARM_S8 = 72, 5990b57cec5SDimitry Andric UNW_ARM_S9 = 73, 6000b57cec5SDimitry Andric UNW_ARM_S10 = 74, 6010b57cec5SDimitry Andric UNW_ARM_S11 = 75, 6020b57cec5SDimitry Andric UNW_ARM_S12 = 76, 6030b57cec5SDimitry Andric UNW_ARM_S13 = 77, 6040b57cec5SDimitry Andric UNW_ARM_S14 = 78, 6050b57cec5SDimitry Andric UNW_ARM_S15 = 79, 6060b57cec5SDimitry Andric UNW_ARM_S16 = 80, 6070b57cec5SDimitry Andric UNW_ARM_S17 = 81, 6080b57cec5SDimitry Andric UNW_ARM_S18 = 82, 6090b57cec5SDimitry Andric UNW_ARM_S19 = 83, 6100b57cec5SDimitry Andric UNW_ARM_S20 = 84, 6110b57cec5SDimitry Andric UNW_ARM_S21 = 85, 6120b57cec5SDimitry Andric UNW_ARM_S22 = 86, 6130b57cec5SDimitry Andric UNW_ARM_S23 = 87, 6140b57cec5SDimitry Andric UNW_ARM_S24 = 88, 6150b57cec5SDimitry Andric UNW_ARM_S25 = 89, 6160b57cec5SDimitry Andric UNW_ARM_S26 = 90, 6170b57cec5SDimitry Andric UNW_ARM_S27 = 91, 6180b57cec5SDimitry Andric UNW_ARM_S28 = 92, 6190b57cec5SDimitry Andric UNW_ARM_S29 = 93, 6200b57cec5SDimitry Andric UNW_ARM_S30 = 94, 6210b57cec5SDimitry Andric UNW_ARM_S31 = 95, 6220b57cec5SDimitry Andric // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP. 6230b57cec5SDimitry Andric // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX) 6240b57cec5SDimitry Andric UNW_ARM_WR0 = 112, 6250b57cec5SDimitry Andric UNW_ARM_WR1 = 113, 6260b57cec5SDimitry Andric UNW_ARM_WR2 = 114, 6270b57cec5SDimitry Andric UNW_ARM_WR3 = 115, 6280b57cec5SDimitry Andric UNW_ARM_WR4 = 116, 6290b57cec5SDimitry Andric UNW_ARM_WR5 = 117, 6300b57cec5SDimitry Andric UNW_ARM_WR6 = 118, 6310b57cec5SDimitry Andric UNW_ARM_WR7 = 119, 6320b57cec5SDimitry Andric UNW_ARM_WR8 = 120, 6330b57cec5SDimitry Andric UNW_ARM_WR9 = 121, 6340b57cec5SDimitry Andric UNW_ARM_WR10 = 122, 6350b57cec5SDimitry Andric UNW_ARM_WR11 = 123, 6360b57cec5SDimitry Andric UNW_ARM_WR12 = 124, 6370b57cec5SDimitry Andric UNW_ARM_WR13 = 125, 6380b57cec5SDimitry Andric UNW_ARM_WR14 = 126, 6390b57cec5SDimitry Andric UNW_ARM_WR15 = 127, 6400b57cec5SDimitry Andric // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} 6410b57cec5SDimitry Andric // 134-143 -- Reserved 6420b57cec5SDimitry Andric // 144-150 -- R8_USR-R14_USR 6430b57cec5SDimitry Andric // 151-157 -- R8_FIQ-R14_FIQ 6440b57cec5SDimitry Andric // 158-159 -- R13_IRQ-R14_IRQ 6450b57cec5SDimitry Andric // 160-161 -- R13_ABT-R14_ABT 6460b57cec5SDimitry Andric // 162-163 -- R13_UND-R14_UND 6470b57cec5SDimitry Andric // 164-165 -- R13_SVC-R14_SVC 6480b57cec5SDimitry Andric // 166-191 -- Reserved 6490b57cec5SDimitry Andric UNW_ARM_WC0 = 192, 6500b57cec5SDimitry Andric UNW_ARM_WC1 = 193, 6510b57cec5SDimitry Andric UNW_ARM_WC2 = 194, 6520b57cec5SDimitry Andric UNW_ARM_WC3 = 195, 6530b57cec5SDimitry Andric // 196-199 -- wC4-wC7 (Intel wireless MMX control) 6540b57cec5SDimitry Andric // 200-255 -- Reserved 6550b57cec5SDimitry Andric UNW_ARM_D0 = 256, 6560b57cec5SDimitry Andric UNW_ARM_D1 = 257, 6570b57cec5SDimitry Andric UNW_ARM_D2 = 258, 6580b57cec5SDimitry Andric UNW_ARM_D3 = 259, 6590b57cec5SDimitry Andric UNW_ARM_D4 = 260, 6600b57cec5SDimitry Andric UNW_ARM_D5 = 261, 6610b57cec5SDimitry Andric UNW_ARM_D6 = 262, 6620b57cec5SDimitry Andric UNW_ARM_D7 = 263, 6630b57cec5SDimitry Andric UNW_ARM_D8 = 264, 6640b57cec5SDimitry Andric UNW_ARM_D9 = 265, 6650b57cec5SDimitry Andric UNW_ARM_D10 = 266, 6660b57cec5SDimitry Andric UNW_ARM_D11 = 267, 6670b57cec5SDimitry Andric UNW_ARM_D12 = 268, 6680b57cec5SDimitry Andric UNW_ARM_D13 = 269, 6690b57cec5SDimitry Andric UNW_ARM_D14 = 270, 6700b57cec5SDimitry Andric UNW_ARM_D15 = 271, 6710b57cec5SDimitry Andric UNW_ARM_D16 = 272, 6720b57cec5SDimitry Andric UNW_ARM_D17 = 273, 6730b57cec5SDimitry Andric UNW_ARM_D18 = 274, 6740b57cec5SDimitry Andric UNW_ARM_D19 = 275, 6750b57cec5SDimitry Andric UNW_ARM_D20 = 276, 6760b57cec5SDimitry Andric UNW_ARM_D21 = 277, 6770b57cec5SDimitry Andric UNW_ARM_D22 = 278, 6780b57cec5SDimitry Andric UNW_ARM_D23 = 279, 6790b57cec5SDimitry Andric UNW_ARM_D24 = 280, 6800b57cec5SDimitry Andric UNW_ARM_D25 = 281, 6810b57cec5SDimitry Andric UNW_ARM_D26 = 282, 6820b57cec5SDimitry Andric UNW_ARM_D27 = 283, 6830b57cec5SDimitry Andric UNW_ARM_D28 = 284, 6840b57cec5SDimitry Andric UNW_ARM_D29 = 285, 6850b57cec5SDimitry Andric UNW_ARM_D30 = 286, 6860b57cec5SDimitry Andric UNW_ARM_D31 = 287, 6870b57cec5SDimitry Andric // 288-319 -- Reserved for VFP/Neon 6880b57cec5SDimitry Andric // 320-8191 -- Reserved 6890b57cec5SDimitry Andric // 8192-16383 -- Unspecified vendor co-processor register. 6900b57cec5SDimitry Andric }; 6910b57cec5SDimitry Andric 6920b57cec5SDimitry Andric // OpenRISC1000 register numbers 6930b57cec5SDimitry Andric enum { 6940b57cec5SDimitry Andric UNW_OR1K_R0 = 0, 6950b57cec5SDimitry Andric UNW_OR1K_R1 = 1, 6960b57cec5SDimitry Andric UNW_OR1K_R2 = 2, 6970b57cec5SDimitry Andric UNW_OR1K_R3 = 3, 6980b57cec5SDimitry Andric UNW_OR1K_R4 = 4, 6990b57cec5SDimitry Andric UNW_OR1K_R5 = 5, 7000b57cec5SDimitry Andric UNW_OR1K_R6 = 6, 7010b57cec5SDimitry Andric UNW_OR1K_R7 = 7, 7020b57cec5SDimitry Andric UNW_OR1K_R8 = 8, 7030b57cec5SDimitry Andric UNW_OR1K_R9 = 9, 7040b57cec5SDimitry Andric UNW_OR1K_R10 = 10, 7050b57cec5SDimitry Andric UNW_OR1K_R11 = 11, 7060b57cec5SDimitry Andric UNW_OR1K_R12 = 12, 7070b57cec5SDimitry Andric UNW_OR1K_R13 = 13, 7080b57cec5SDimitry Andric UNW_OR1K_R14 = 14, 7090b57cec5SDimitry Andric UNW_OR1K_R15 = 15, 7100b57cec5SDimitry Andric UNW_OR1K_R16 = 16, 7110b57cec5SDimitry Andric UNW_OR1K_R17 = 17, 7120b57cec5SDimitry Andric UNW_OR1K_R18 = 18, 7130b57cec5SDimitry Andric UNW_OR1K_R19 = 19, 7140b57cec5SDimitry Andric UNW_OR1K_R20 = 20, 7150b57cec5SDimitry Andric UNW_OR1K_R21 = 21, 7160b57cec5SDimitry Andric UNW_OR1K_R22 = 22, 7170b57cec5SDimitry Andric UNW_OR1K_R23 = 23, 7180b57cec5SDimitry Andric UNW_OR1K_R24 = 24, 7190b57cec5SDimitry Andric UNW_OR1K_R25 = 25, 7200b57cec5SDimitry Andric UNW_OR1K_R26 = 26, 7210b57cec5SDimitry Andric UNW_OR1K_R27 = 27, 7220b57cec5SDimitry Andric UNW_OR1K_R28 = 28, 7230b57cec5SDimitry Andric UNW_OR1K_R29 = 29, 7240b57cec5SDimitry Andric UNW_OR1K_R30 = 30, 7250b57cec5SDimitry Andric UNW_OR1K_R31 = 31, 7260b57cec5SDimitry Andric UNW_OR1K_EPCR = 32, 7270b57cec5SDimitry Andric }; 7280b57cec5SDimitry Andric 7290b57cec5SDimitry Andric // MIPS registers 7300b57cec5SDimitry Andric enum { 7310b57cec5SDimitry Andric UNW_MIPS_R0 = 0, 7320b57cec5SDimitry Andric UNW_MIPS_R1 = 1, 7330b57cec5SDimitry Andric UNW_MIPS_R2 = 2, 7340b57cec5SDimitry Andric UNW_MIPS_R3 = 3, 7350b57cec5SDimitry Andric UNW_MIPS_R4 = 4, 7360b57cec5SDimitry Andric UNW_MIPS_R5 = 5, 7370b57cec5SDimitry Andric UNW_MIPS_R6 = 6, 7380b57cec5SDimitry Andric UNW_MIPS_R7 = 7, 7390b57cec5SDimitry Andric UNW_MIPS_R8 = 8, 7400b57cec5SDimitry Andric UNW_MIPS_R9 = 9, 7410b57cec5SDimitry Andric UNW_MIPS_R10 = 10, 7420b57cec5SDimitry Andric UNW_MIPS_R11 = 11, 7430b57cec5SDimitry Andric UNW_MIPS_R12 = 12, 7440b57cec5SDimitry Andric UNW_MIPS_R13 = 13, 7450b57cec5SDimitry Andric UNW_MIPS_R14 = 14, 7460b57cec5SDimitry Andric UNW_MIPS_R15 = 15, 7470b57cec5SDimitry Andric UNW_MIPS_R16 = 16, 7480b57cec5SDimitry Andric UNW_MIPS_R17 = 17, 7490b57cec5SDimitry Andric UNW_MIPS_R18 = 18, 7500b57cec5SDimitry Andric UNW_MIPS_R19 = 19, 7510b57cec5SDimitry Andric UNW_MIPS_R20 = 20, 7520b57cec5SDimitry Andric UNW_MIPS_R21 = 21, 7530b57cec5SDimitry Andric UNW_MIPS_R22 = 22, 7540b57cec5SDimitry Andric UNW_MIPS_R23 = 23, 7550b57cec5SDimitry Andric UNW_MIPS_R24 = 24, 7560b57cec5SDimitry Andric UNW_MIPS_R25 = 25, 7570b57cec5SDimitry Andric UNW_MIPS_R26 = 26, 7580b57cec5SDimitry Andric UNW_MIPS_R27 = 27, 7590b57cec5SDimitry Andric UNW_MIPS_R28 = 28, 7600b57cec5SDimitry Andric UNW_MIPS_R29 = 29, 7610b57cec5SDimitry Andric UNW_MIPS_R30 = 30, 7620b57cec5SDimitry Andric UNW_MIPS_R31 = 31, 7630b57cec5SDimitry Andric UNW_MIPS_F0 = 32, 7640b57cec5SDimitry Andric UNW_MIPS_F1 = 33, 7650b57cec5SDimitry Andric UNW_MIPS_F2 = 34, 7660b57cec5SDimitry Andric UNW_MIPS_F3 = 35, 7670b57cec5SDimitry Andric UNW_MIPS_F4 = 36, 7680b57cec5SDimitry Andric UNW_MIPS_F5 = 37, 7690b57cec5SDimitry Andric UNW_MIPS_F6 = 38, 7700b57cec5SDimitry Andric UNW_MIPS_F7 = 39, 7710b57cec5SDimitry Andric UNW_MIPS_F8 = 40, 7720b57cec5SDimitry Andric UNW_MIPS_F9 = 41, 7730b57cec5SDimitry Andric UNW_MIPS_F10 = 42, 7740b57cec5SDimitry Andric UNW_MIPS_F11 = 43, 7750b57cec5SDimitry Andric UNW_MIPS_F12 = 44, 7760b57cec5SDimitry Andric UNW_MIPS_F13 = 45, 7770b57cec5SDimitry Andric UNW_MIPS_F14 = 46, 7780b57cec5SDimitry Andric UNW_MIPS_F15 = 47, 7790b57cec5SDimitry Andric UNW_MIPS_F16 = 48, 7800b57cec5SDimitry Andric UNW_MIPS_F17 = 49, 7810b57cec5SDimitry Andric UNW_MIPS_F18 = 50, 7820b57cec5SDimitry Andric UNW_MIPS_F19 = 51, 7830b57cec5SDimitry Andric UNW_MIPS_F20 = 52, 7840b57cec5SDimitry Andric UNW_MIPS_F21 = 53, 7850b57cec5SDimitry Andric UNW_MIPS_F22 = 54, 7860b57cec5SDimitry Andric UNW_MIPS_F23 = 55, 7870b57cec5SDimitry Andric UNW_MIPS_F24 = 56, 7880b57cec5SDimitry Andric UNW_MIPS_F25 = 57, 7890b57cec5SDimitry Andric UNW_MIPS_F26 = 58, 7900b57cec5SDimitry Andric UNW_MIPS_F27 = 59, 7910b57cec5SDimitry Andric UNW_MIPS_F28 = 60, 7920b57cec5SDimitry Andric UNW_MIPS_F29 = 61, 7930b57cec5SDimitry Andric UNW_MIPS_F30 = 62, 7940b57cec5SDimitry Andric UNW_MIPS_F31 = 63, 7950b57cec5SDimitry Andric UNW_MIPS_HI = 64, 7960b57cec5SDimitry Andric UNW_MIPS_LO = 65, 7970b57cec5SDimitry Andric }; 7980b57cec5SDimitry Andric 7990b57cec5SDimitry Andric // SPARC registers 8000b57cec5SDimitry Andric enum { 8010b57cec5SDimitry Andric UNW_SPARC_G0 = 0, 8020b57cec5SDimitry Andric UNW_SPARC_G1 = 1, 8030b57cec5SDimitry Andric UNW_SPARC_G2 = 2, 8040b57cec5SDimitry Andric UNW_SPARC_G3 = 3, 8050b57cec5SDimitry Andric UNW_SPARC_G4 = 4, 8060b57cec5SDimitry Andric UNW_SPARC_G5 = 5, 8070b57cec5SDimitry Andric UNW_SPARC_G6 = 6, 8080b57cec5SDimitry Andric UNW_SPARC_G7 = 7, 8090b57cec5SDimitry Andric UNW_SPARC_O0 = 8, 8100b57cec5SDimitry Andric UNW_SPARC_O1 = 9, 8110b57cec5SDimitry Andric UNW_SPARC_O2 = 10, 8120b57cec5SDimitry Andric UNW_SPARC_O3 = 11, 8130b57cec5SDimitry Andric UNW_SPARC_O4 = 12, 8140b57cec5SDimitry Andric UNW_SPARC_O5 = 13, 8150b57cec5SDimitry Andric UNW_SPARC_O6 = 14, 8160b57cec5SDimitry Andric UNW_SPARC_O7 = 15, 8170b57cec5SDimitry Andric UNW_SPARC_L0 = 16, 8180b57cec5SDimitry Andric UNW_SPARC_L1 = 17, 8190b57cec5SDimitry Andric UNW_SPARC_L2 = 18, 8200b57cec5SDimitry Andric UNW_SPARC_L3 = 19, 8210b57cec5SDimitry Andric UNW_SPARC_L4 = 20, 8220b57cec5SDimitry Andric UNW_SPARC_L5 = 21, 8230b57cec5SDimitry Andric UNW_SPARC_L6 = 22, 8240b57cec5SDimitry Andric UNW_SPARC_L7 = 23, 8250b57cec5SDimitry Andric UNW_SPARC_I0 = 24, 8260b57cec5SDimitry Andric UNW_SPARC_I1 = 25, 8270b57cec5SDimitry Andric UNW_SPARC_I2 = 26, 8280b57cec5SDimitry Andric UNW_SPARC_I3 = 27, 8290b57cec5SDimitry Andric UNW_SPARC_I4 = 28, 8300b57cec5SDimitry Andric UNW_SPARC_I5 = 29, 8310b57cec5SDimitry Andric UNW_SPARC_I6 = 30, 8320b57cec5SDimitry Andric UNW_SPARC_I7 = 31, 8330b57cec5SDimitry Andric }; 8340b57cec5SDimitry Andric 835*5ffd83dbSDimitry Andric // Hexagon register numbers 836*5ffd83dbSDimitry Andric enum { 837*5ffd83dbSDimitry Andric UNW_HEXAGON_R0, 838*5ffd83dbSDimitry Andric UNW_HEXAGON_R1, 839*5ffd83dbSDimitry Andric UNW_HEXAGON_R2, 840*5ffd83dbSDimitry Andric UNW_HEXAGON_R3, 841*5ffd83dbSDimitry Andric UNW_HEXAGON_R4, 842*5ffd83dbSDimitry Andric UNW_HEXAGON_R5, 843*5ffd83dbSDimitry Andric UNW_HEXAGON_R6, 844*5ffd83dbSDimitry Andric UNW_HEXAGON_R7, 845*5ffd83dbSDimitry Andric UNW_HEXAGON_R8, 846*5ffd83dbSDimitry Andric UNW_HEXAGON_R9, 847*5ffd83dbSDimitry Andric UNW_HEXAGON_R10, 848*5ffd83dbSDimitry Andric UNW_HEXAGON_R11, 849*5ffd83dbSDimitry Andric UNW_HEXAGON_R12, 850*5ffd83dbSDimitry Andric UNW_HEXAGON_R13, 851*5ffd83dbSDimitry Andric UNW_HEXAGON_R14, 852*5ffd83dbSDimitry Andric UNW_HEXAGON_R15, 853*5ffd83dbSDimitry Andric UNW_HEXAGON_R16, 854*5ffd83dbSDimitry Andric UNW_HEXAGON_R17, 855*5ffd83dbSDimitry Andric UNW_HEXAGON_R18, 856*5ffd83dbSDimitry Andric UNW_HEXAGON_R19, 857*5ffd83dbSDimitry Andric UNW_HEXAGON_R20, 858*5ffd83dbSDimitry Andric UNW_HEXAGON_R21, 859*5ffd83dbSDimitry Andric UNW_HEXAGON_R22, 860*5ffd83dbSDimitry Andric UNW_HEXAGON_R23, 861*5ffd83dbSDimitry Andric UNW_HEXAGON_R24, 862*5ffd83dbSDimitry Andric UNW_HEXAGON_R25, 863*5ffd83dbSDimitry Andric UNW_HEXAGON_R26, 864*5ffd83dbSDimitry Andric UNW_HEXAGON_R27, 865*5ffd83dbSDimitry Andric UNW_HEXAGON_R28, 866*5ffd83dbSDimitry Andric UNW_HEXAGON_R29, 867*5ffd83dbSDimitry Andric UNW_HEXAGON_R30, 868*5ffd83dbSDimitry Andric UNW_HEXAGON_R31, 869*5ffd83dbSDimitry Andric UNW_HEXAGON_P3_0, 870*5ffd83dbSDimitry Andric UNW_HEXAGON_PC, 871*5ffd83dbSDimitry Andric }; 872*5ffd83dbSDimitry Andric 873480093f4SDimitry Andric // RISC-V registers. These match the DWARF register numbers defined by section 874480093f4SDimitry Andric // 4 of the RISC-V ELF psABI specification, which can be found at: 875480093f4SDimitry Andric // 876480093f4SDimitry Andric // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md 877480093f4SDimitry Andric enum { 878480093f4SDimitry Andric UNW_RISCV_X0 = 0, 879480093f4SDimitry Andric UNW_RISCV_X1 = 1, 880480093f4SDimitry Andric UNW_RISCV_X2 = 2, 881480093f4SDimitry Andric UNW_RISCV_X3 = 3, 882480093f4SDimitry Andric UNW_RISCV_X4 = 4, 883480093f4SDimitry Andric UNW_RISCV_X5 = 5, 884480093f4SDimitry Andric UNW_RISCV_X6 = 6, 885480093f4SDimitry Andric UNW_RISCV_X7 = 7, 886480093f4SDimitry Andric UNW_RISCV_X8 = 8, 887480093f4SDimitry Andric UNW_RISCV_X9 = 9, 888480093f4SDimitry Andric UNW_RISCV_X10 = 10, 889480093f4SDimitry Andric UNW_RISCV_X11 = 11, 890480093f4SDimitry Andric UNW_RISCV_X12 = 12, 891480093f4SDimitry Andric UNW_RISCV_X13 = 13, 892480093f4SDimitry Andric UNW_RISCV_X14 = 14, 893480093f4SDimitry Andric UNW_RISCV_X15 = 15, 894480093f4SDimitry Andric UNW_RISCV_X16 = 16, 895480093f4SDimitry Andric UNW_RISCV_X17 = 17, 896480093f4SDimitry Andric UNW_RISCV_X18 = 18, 897480093f4SDimitry Andric UNW_RISCV_X19 = 19, 898480093f4SDimitry Andric UNW_RISCV_X20 = 20, 899480093f4SDimitry Andric UNW_RISCV_X21 = 21, 900480093f4SDimitry Andric UNW_RISCV_X22 = 22, 901480093f4SDimitry Andric UNW_RISCV_X23 = 23, 902480093f4SDimitry Andric UNW_RISCV_X24 = 24, 903480093f4SDimitry Andric UNW_RISCV_X25 = 25, 904480093f4SDimitry Andric UNW_RISCV_X26 = 26, 905480093f4SDimitry Andric UNW_RISCV_X27 = 27, 906480093f4SDimitry Andric UNW_RISCV_X28 = 28, 907480093f4SDimitry Andric UNW_RISCV_X29 = 29, 908480093f4SDimitry Andric UNW_RISCV_X30 = 30, 909480093f4SDimitry Andric UNW_RISCV_X31 = 31, 910480093f4SDimitry Andric UNW_RISCV_F0 = 32, 911480093f4SDimitry Andric UNW_RISCV_F1 = 33, 912480093f4SDimitry Andric UNW_RISCV_F2 = 34, 913480093f4SDimitry Andric UNW_RISCV_F3 = 35, 914480093f4SDimitry Andric UNW_RISCV_F4 = 36, 915480093f4SDimitry Andric UNW_RISCV_F5 = 37, 916480093f4SDimitry Andric UNW_RISCV_F6 = 38, 917480093f4SDimitry Andric UNW_RISCV_F7 = 39, 918480093f4SDimitry Andric UNW_RISCV_F8 = 40, 919480093f4SDimitry Andric UNW_RISCV_F9 = 41, 920480093f4SDimitry Andric UNW_RISCV_F10 = 42, 921480093f4SDimitry Andric UNW_RISCV_F11 = 43, 922480093f4SDimitry Andric UNW_RISCV_F12 = 44, 923480093f4SDimitry Andric UNW_RISCV_F13 = 45, 924480093f4SDimitry Andric UNW_RISCV_F14 = 46, 925480093f4SDimitry Andric UNW_RISCV_F15 = 47, 926480093f4SDimitry Andric UNW_RISCV_F16 = 48, 927480093f4SDimitry Andric UNW_RISCV_F17 = 49, 928480093f4SDimitry Andric UNW_RISCV_F18 = 50, 929480093f4SDimitry Andric UNW_RISCV_F19 = 51, 930480093f4SDimitry Andric UNW_RISCV_F20 = 52, 931480093f4SDimitry Andric UNW_RISCV_F21 = 53, 932480093f4SDimitry Andric UNW_RISCV_F22 = 54, 933480093f4SDimitry Andric UNW_RISCV_F23 = 55, 934480093f4SDimitry Andric UNW_RISCV_F24 = 56, 935480093f4SDimitry Andric UNW_RISCV_F25 = 57, 936480093f4SDimitry Andric UNW_RISCV_F26 = 58, 937480093f4SDimitry Andric UNW_RISCV_F27 = 59, 938480093f4SDimitry Andric UNW_RISCV_F28 = 60, 939480093f4SDimitry Andric UNW_RISCV_F29 = 61, 940480093f4SDimitry Andric UNW_RISCV_F30 = 62, 941480093f4SDimitry Andric UNW_RISCV_F31 = 63, 942480093f4SDimitry Andric }; 943480093f4SDimitry Andric 9440b57cec5SDimitry Andric #endif 945