xref: /freebsd/contrib/llvm-project/compiler-rt/lib/orc/macho_tlv.arm64.S (revision 19fae0f66023a97a9b464b3beeeabb2081f575b3) 
1//===-- macho_tlv.arm64.s ---------------------------------------*- ASM -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is a part of the ORC runtime support library.
10//
11//===----------------------------------------------------------------------===//
12
13// The content of this file is arm64-only
14#if defined(__arm64__) || defined(__aarch64__)
15
16#define REGISTER_SAVE_SPACE_SIZE     32 * 24
17
18        .text
19
20  // returns address of TLV in x0, all other registers preserved
21  .globl ___orc_rt_macho_tlv_get_addr
22___orc_rt_macho_tlv_get_addr:
23        sub  sp,  sp, #REGISTER_SAVE_SPACE_SIZE
24        stp x29, x30, [sp, #16 * 1]
25        stp x27, x28, [sp, #16 * 2]
26        stp x25, x26, [sp, #16 * 3]
27        stp x23, x24, [sp, #16 * 4]
28        stp x21, x22, [sp, #16 * 5]
29        stp x19, x20, [sp, #16 * 6]
30        stp x17, x18, [sp, #16 * 7]
31        stp x15, x16, [sp, #16 * 8]
32        stp x13, x14, [sp, #16 * 9]
33        stp x11, x12, [sp, #16 * 10]
34        stp  x9, x10, [sp, #16 * 11]
35        stp  x7,  x8, [sp, #16 * 12]
36        stp  x5,  x6, [sp, #16 * 13]
37        stp  x3,  x4, [sp, #16 * 14]
38        stp  x1,  x2, [sp, #16 * 15]
39        stp q30, q31, [sp, #32 * 8]
40        stp q28, q29, [sp, #32 * 9]
41        stp q26, q27, [sp, #32 * 10]
42        stp q24, q25, [sp, #32 * 11]
43        stp q22, q23, [sp, #32 * 12]
44        stp q20, q21, [sp, #32 * 13]
45        stp q18, q19, [sp, #32 * 14]
46        stp q16, q17, [sp, #32 * 15]
47        stp q14, q15, [sp, #32 * 16]
48        stp q12, q13, [sp, #32 * 17]
49        stp q10, q11, [sp, #32 * 18]
50        stp  q8,  q9, [sp, #32 * 19]
51        stp  q6,  q7, [sp, #32 * 20]
52        stp  q4,  q5, [sp, #32 * 21]
53        stp  q2,  q3, [sp, #32 * 22]
54        stp  q0,  q1, [sp, #32 * 23]
55
56        bl ___orc_rt_macho_tlv_get_addr_impl
57
58        ldp  q0,  q1, [sp, #32 * 23]
59        ldp  q2,  q3, [sp, #32 * 22]
60        ldp  q4,  q5, [sp, #32 * 21]
61        ldp  q6,  q7, [sp, #32 * 20]
62        ldp  q8,  q9, [sp, #32 * 19]
63        ldp q10, q11, [sp, #32 * 18]
64        ldp q12, q13, [sp, #32 * 17]
65        ldp q14, q15, [sp, #32 * 16]
66        ldp q16, q17, [sp, #32 * 15]
67        ldp q18, q19, [sp, #32 * 14]
68        ldp q20, q21, [sp, #32 * 13]
69        ldp q22, q23, [sp, #32 * 12]
70        ldp q24, q25, [sp, #32 * 11]
71        ldp q26, q27, [sp, #32 * 10]
72        ldp q28, q29, [sp, #32 * 9]
73        ldp q30, q31, [sp, #32 * 8]
74        ldp  x1,  x2, [sp, #16 * 15]
75        ldp  x3,  x4, [sp, #16 * 14]
76        ldp  x5,  x6, [sp, #16 * 13]
77        ldp  x7,  x8, [sp, #16 * 12]
78        ldp  x9, x10, [sp, #16 * 11]
79        ldp x11, x12, [sp, #16 * 10]
80        ldp x13, x14, [sp, #16 * 9]
81        ldp x15, x16, [sp, #16 * 8]
82        ldp x17, x18, [sp, #16 * 7]
83        ldp x19, x20, [sp, #16 * 6]
84        ldp x21, x22, [sp, #16 * 5]
85        ldp x23, x24, [sp, #16 * 4]
86        ldp x25, x26, [sp, #16 * 3]
87        ldp x27, x28, [sp, #16 * 2]
88        ldp x29, x30, [sp, #16 * 1]
89        add  sp,  sp, #REGISTER_SAVE_SPACE_SIZE
90        ret
91
92#endif // defined(__arm64__) || defined(__aarch64__)
93